Lines Matching refs:h
31 void (*submit_command)(struct ctlr_info *h,
33 void (*set_intr_mask)(struct ctlr_info *h, unsigned long val);
34 bool (*intr_pending)(struct ctlr_info *h);
35 unsigned long (*command_completed)(struct ctlr_info *h, u8 q);
420 static void SA5_submit_command(struct ctlr_info *h, in SA5_submit_command() argument
423 writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET); in SA5_submit_command()
424 (void) readl(h->vaddr + SA5_SCRATCHPAD_OFFSET); in SA5_submit_command()
427 static void SA5_submit_command_no_read(struct ctlr_info *h, in SA5_submit_command_no_read() argument
430 writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET); in SA5_submit_command_no_read()
433 static void SA5_submit_command_ioaccel2(struct ctlr_info *h, in SA5_submit_command_ioaccel2() argument
436 writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET); in SA5_submit_command_ioaccel2()
444 static void SA5_intr_mask(struct ctlr_info *h, unsigned long val) in SA5_intr_mask() argument
447 h->interrupts_enabled = 1; in SA5_intr_mask()
448 writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); in SA5_intr_mask()
449 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); in SA5_intr_mask()
451 h->interrupts_enabled = 0; in SA5_intr_mask()
453 h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); in SA5_intr_mask()
454 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); in SA5_intr_mask()
461 static void SA5B_intr_mask(struct ctlr_info *h, unsigned long val) in SA5B_intr_mask() argument
464 h->interrupts_enabled = 1; in SA5B_intr_mask()
465 writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); in SA5B_intr_mask()
466 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); in SA5B_intr_mask()
468 h->interrupts_enabled = 0; in SA5B_intr_mask()
470 h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); in SA5B_intr_mask()
471 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); in SA5B_intr_mask()
475 static void SA5_performant_intr_mask(struct ctlr_info *h, unsigned long val) in SA5_performant_intr_mask() argument
478 h->interrupts_enabled = 1; in SA5_performant_intr_mask()
479 writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); in SA5_performant_intr_mask()
480 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); in SA5_performant_intr_mask()
482 h->interrupts_enabled = 0; in SA5_performant_intr_mask()
484 h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); in SA5_performant_intr_mask()
485 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); in SA5_performant_intr_mask()
489 static unsigned long SA5_performant_completed(struct ctlr_info *h, u8 q) in SA5_performant_completed() argument
491 struct reply_queue_buffer *rq = &h->reply_queue[q]; in SA5_performant_completed()
495 if (unlikely(!(h->pdev->msi_enabled || h->msix_vectors))) { in SA5_performant_completed()
499 (void) readl(h->vaddr + SA5_OUTDB_STATUS); in SA5_performant_completed()
500 writel(SA5_OUTDB_CLEAR_PERF_BIT, h->vaddr + SA5_OUTDB_CLEAR); in SA5_performant_completed()
504 (void) readl(h->vaddr + SA5_OUTDB_STATUS); in SA5_performant_completed()
510 atomic_dec(&h->commands_outstanding); in SA5_performant_completed()
515 if (rq->current_entry == h->max_commands) { in SA5_performant_completed()
526 static unsigned long SA5_completed(struct ctlr_info *h, in SA5_completed() argument
530 = readl(h->vaddr + SA5_REPLY_PORT_OFFSET); in SA5_completed()
533 atomic_dec(&h->commands_outstanding); in SA5_completed()
537 dev_dbg(&h->pdev->dev, "Read %lx back from board\n", in SA5_completed()
540 dev_dbg(&h->pdev->dev, "FIFO Empty read\n"); in SA5_completed()
548 static bool SA5_intr_pending(struct ctlr_info *h) in SA5_intr_pending() argument
551 readl(h->vaddr + SA5_INTR_STATUS); in SA5_intr_pending()
555 static bool SA5_performant_intr_pending(struct ctlr_info *h) in SA5_performant_intr_pending() argument
557 unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS); in SA5_performant_intr_pending()
563 register_value = readl(h->vaddr + SA5_OUTDB_STATUS); in SA5_performant_intr_pending()
569 static bool SA5_ioaccel_mode1_intr_pending(struct ctlr_info *h) in SA5_ioaccel_mode1_intr_pending() argument
571 unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS); in SA5_ioaccel_mode1_intr_pending()
580 static bool SA5B_intr_pending(struct ctlr_info *h) in SA5B_intr_pending() argument
582 return readl(h->vaddr + SA5_INTR_STATUS) & SA5B_INTR_PENDING; in SA5B_intr_pending()
590 static unsigned long SA5_ioaccel_mode1_completed(struct ctlr_info *h, u8 q) in SA5_ioaccel_mode1_completed() argument
593 struct reply_queue_buffer *rq = &h->reply_queue[q]; in SA5_ioaccel_mode1_completed()
595 BUG_ON(q >= h->nreply_queues); in SA5_ioaccel_mode1_completed()
609 writel((q << 24) | rq->current_entry, h->vaddr + in SA5_ioaccel_mode1_completed()
611 atomic_dec(&h->commands_outstanding); in SA5_ioaccel_mode1_completed()