Lines Matching refs:tup
147 static void tegra_uart_start_next_tx(struct tegra_uart_port *tup);
148 static int tegra_uart_start_rx_dma(struct tegra_uart_port *tup);
149 static void tegra_uart_dma_channel_free(struct tegra_uart_port *tup,
152 static inline unsigned long tegra_uart_read(struct tegra_uart_port *tup, in tegra_uart_read() argument
155 return readl(tup->uport.membase + (reg << tup->uport.regshift)); in tegra_uart_read()
158 static inline void tegra_uart_write(struct tegra_uart_port *tup, unsigned val, in tegra_uart_write() argument
161 writel(val, tup->uport.membase + (reg << tup->uport.regshift)); in tegra_uart_write()
171 struct tegra_uart_port *tup = to_tegra_uport(u); in tegra_uart_get_mctrl() local
182 if (tup->enable_modem_interrupt) in tegra_uart_get_mctrl()
187 static void set_rts(struct tegra_uart_port *tup, bool active) in set_rts() argument
191 mcr = tup->mcr_shadow; in set_rts()
196 if (mcr != tup->mcr_shadow) { in set_rts()
197 tegra_uart_write(tup, mcr, UART_MCR); in set_rts()
198 tup->mcr_shadow = mcr; in set_rts()
202 static void set_dtr(struct tegra_uart_port *tup, bool active) in set_dtr() argument
206 mcr = tup->mcr_shadow; in set_dtr()
211 if (mcr != tup->mcr_shadow) { in set_dtr()
212 tegra_uart_write(tup, mcr, UART_MCR); in set_dtr()
213 tup->mcr_shadow = mcr; in set_dtr()
217 static void set_loopbk(struct tegra_uart_port *tup, bool active) in set_loopbk() argument
219 unsigned long mcr = tup->mcr_shadow; in set_loopbk()
226 if (mcr != tup->mcr_shadow) { in set_loopbk()
227 tegra_uart_write(tup, mcr, UART_MCR); in set_loopbk()
228 tup->mcr_shadow = mcr; in set_loopbk()
234 struct tegra_uart_port *tup = to_tegra_uport(u); in tegra_uart_set_mctrl() local
237 tup->rts_active = !!(mctrl & TIOCM_RTS); in tegra_uart_set_mctrl()
238 set_rts(tup, tup->rts_active); in tegra_uart_set_mctrl()
241 set_dtr(tup, enable); in tegra_uart_set_mctrl()
244 set_loopbk(tup, enable); in tegra_uart_set_mctrl()
249 struct tegra_uart_port *tup = to_tegra_uport(u); in tegra_uart_break_ctl() local
252 lcr = tup->lcr_shadow; in tegra_uart_break_ctl()
257 tegra_uart_write(tup, lcr, UART_LCR); in tegra_uart_break_ctl()
258 tup->lcr_shadow = lcr; in tegra_uart_break_ctl()
270 static void tegra_uart_wait_cycle_time(struct tegra_uart_port *tup, in tegra_uart_wait_cycle_time() argument
273 if (tup->current_baud) in tegra_uart_wait_cycle_time()
274 udelay(DIV_ROUND_UP(cycles * 1000000, tup->current_baud * 16)); in tegra_uart_wait_cycle_time()
278 static void tegra_uart_wait_sym_time(struct tegra_uart_port *tup, in tegra_uart_wait_sym_time() argument
281 if (tup->current_baud) in tegra_uart_wait_sym_time()
282 udelay(DIV_ROUND_UP(syms * tup->symb_bit * 1000000, in tegra_uart_wait_sym_time()
283 tup->current_baud)); in tegra_uart_wait_sym_time()
286 static int tegra_uart_wait_fifo_mode_enabled(struct tegra_uart_port *tup) in tegra_uart_wait_fifo_mode_enabled() argument
292 iir = tegra_uart_read(tup, UART_IIR); in tegra_uart_wait_fifo_mode_enabled()
301 static void tegra_uart_fifo_reset(struct tegra_uart_port *tup, u8 fcr_bits) in tegra_uart_fifo_reset() argument
303 unsigned long fcr = tup->fcr_shadow; in tegra_uart_fifo_reset()
306 if (tup->rts_active) in tegra_uart_fifo_reset()
307 set_rts(tup, false); in tegra_uart_fifo_reset()
309 if (tup->cdata->allow_txfifo_reset_fifo_mode) { in tegra_uart_fifo_reset()
311 tegra_uart_write(tup, fcr, UART_FCR); in tegra_uart_fifo_reset()
314 tegra_uart_write(tup, fcr, UART_FCR); in tegra_uart_fifo_reset()
317 tegra_uart_write(tup, fcr, UART_FCR); in tegra_uart_fifo_reset()
319 tegra_uart_write(tup, fcr, UART_FCR); in tegra_uart_fifo_reset()
320 if (tup->cdata->fifo_mode_enable_status) in tegra_uart_fifo_reset()
321 tegra_uart_wait_fifo_mode_enabled(tup); in tegra_uart_fifo_reset()
325 tegra_uart_read(tup, UART_SCR); in tegra_uart_fifo_reset()
332 tegra_uart_wait_cycle_time(tup, 32); in tegra_uart_fifo_reset()
335 lsr = tegra_uart_read(tup, UART_LSR); in tegra_uart_fifo_reset()
341 if (tup->rts_active) in tegra_uart_fifo_reset()
342 set_rts(tup, true); in tegra_uart_fifo_reset()
345 static long tegra_get_tolerance_rate(struct tegra_uart_port *tup, in tegra_get_tolerance_rate() argument
350 for (i = 0; i < tup->n_adjustable_baud_rates; ++i) { in tegra_get_tolerance_rate()
351 if (baud >= tup->baud_tolerance[i].lower_range_baud && in tegra_get_tolerance_rate()
352 baud <= tup->baud_tolerance[i].upper_range_baud) in tegra_get_tolerance_rate()
354 tup->baud_tolerance[i].tolerance) / 10000); in tegra_get_tolerance_rate()
360 static int tegra_check_rate_in_range(struct tegra_uart_port *tup) in tegra_check_rate_in_range() argument
364 diff = ((long)(tup->configured_rate - tup->required_rate) * 10000) in tegra_check_rate_in_range()
365 / tup->required_rate; in tegra_check_rate_in_range()
366 if (diff < (tup->cdata->error_tolerance_low_range * 100) || in tegra_check_rate_in_range()
367 diff > (tup->cdata->error_tolerance_high_range * 100)) { in tegra_check_rate_in_range()
368 dev_err(tup->uport.dev, in tegra_check_rate_in_range()
376 static int tegra_set_baudrate(struct tegra_uart_port *tup, unsigned int baud) in tegra_set_baudrate() argument
384 if (tup->current_baud == baud) in tegra_set_baudrate()
387 if (tup->cdata->support_clk_src_div) { in tegra_set_baudrate()
389 tup->required_rate = rate; in tegra_set_baudrate()
391 if (tup->n_adjustable_baud_rates) in tegra_set_baudrate()
392 rate = tegra_get_tolerance_rate(tup, baud, rate); in tegra_set_baudrate()
394 ret = clk_set_rate(tup->uart_clk, rate); in tegra_set_baudrate()
396 dev_err(tup->uport.dev, in tegra_set_baudrate()
400 tup->configured_rate = clk_get_rate(tup->uart_clk); in tegra_set_baudrate()
402 ret = tegra_check_rate_in_range(tup); in tegra_set_baudrate()
406 rate = clk_get_rate(tup->uart_clk); in tegra_set_baudrate()
410 spin_lock_irqsave(&tup->uport.lock, flags); in tegra_set_baudrate()
411 lcr = tup->lcr_shadow; in tegra_set_baudrate()
413 tegra_uart_write(tup, lcr, UART_LCR); in tegra_set_baudrate()
415 tegra_uart_write(tup, divisor & 0xFF, UART_TX); in tegra_set_baudrate()
416 tegra_uart_write(tup, ((divisor >> 8) & 0xFF), UART_IER); in tegra_set_baudrate()
419 tegra_uart_write(tup, lcr, UART_LCR); in tegra_set_baudrate()
422 tegra_uart_read(tup, UART_SCR); in tegra_set_baudrate()
423 spin_unlock_irqrestore(&tup->uport.lock, flags); in tegra_set_baudrate()
425 tup->current_baud = baud; in tegra_set_baudrate()
428 tegra_uart_wait_sym_time(tup, 2); in tegra_set_baudrate()
432 static char tegra_uart_decode_rx_error(struct tegra_uart_port *tup, in tegra_uart_decode_rx_error() argument
441 tup->uport.icount.overrun++; in tegra_uart_decode_rx_error()
442 dev_dbg(tup->uport.dev, "Got overrun errors\n"); in tegra_uart_decode_rx_error()
446 tup->uport.icount.parity++; in tegra_uart_decode_rx_error()
447 dev_dbg(tup->uport.dev, "Got Parity errors\n"); in tegra_uart_decode_rx_error()
450 tup->uport.icount.frame++; in tegra_uart_decode_rx_error()
451 dev_dbg(tup->uport.dev, "Got frame errors\n"); in tegra_uart_decode_rx_error()
458 tegra_uart_fifo_reset(tup, UART_FCR_CLEAR_RCVR); in tegra_uart_decode_rx_error()
459 if (tup->uport.ignore_status_mask & UART_LSR_BI) in tegra_uart_decode_rx_error()
462 tup->uport.icount.brk++; in tegra_uart_decode_rx_error()
463 dev_dbg(tup->uport.dev, "Got Break\n"); in tegra_uart_decode_rx_error()
465 uart_insert_char(&tup->uport, lsr, UART_LSR_OE, 0, flag); in tegra_uart_decode_rx_error()
481 static void tegra_uart_fill_tx_fifo(struct tegra_uart_port *tup, int max_bytes) in tegra_uart_fill_tx_fifo() argument
483 struct circ_buf *xmit = &tup->uport.state->xmit; in tegra_uart_fill_tx_fifo()
488 if (tup->cdata->tx_fifo_full_status) { in tegra_uart_fill_tx_fifo()
489 unsigned long lsr = tegra_uart_read(tup, UART_LSR); in tegra_uart_fill_tx_fifo()
493 tegra_uart_write(tup, xmit->buf[xmit->tail], UART_TX); in tegra_uart_fill_tx_fifo()
495 tup->uport.icount.tx++; in tegra_uart_fill_tx_fifo()
499 static void tegra_uart_start_pio_tx(struct tegra_uart_port *tup, in tegra_uart_start_pio_tx() argument
505 tup->tx_in_progress = TEGRA_UART_TX_PIO; in tegra_uart_start_pio_tx()
506 tup->tx_bytes = bytes; in tegra_uart_start_pio_tx()
507 tup->ier_shadow |= UART_IER_THRI; in tegra_uart_start_pio_tx()
508 tegra_uart_write(tup, tup->ier_shadow, UART_IER); in tegra_uart_start_pio_tx()
513 struct tegra_uart_port *tup = args; in tegra_uart_tx_dma_complete() local
514 struct circ_buf *xmit = &tup->uport.state->xmit; in tegra_uart_tx_dma_complete()
519 dmaengine_tx_status(tup->tx_dma_chan, tup->tx_cookie, &state); in tegra_uart_tx_dma_complete()
520 count = tup->tx_bytes_requested - state.residue; in tegra_uart_tx_dma_complete()
521 async_tx_ack(tup->tx_dma_desc); in tegra_uart_tx_dma_complete()
522 spin_lock_irqsave(&tup->uport.lock, flags); in tegra_uart_tx_dma_complete()
523 uart_xmit_advance(&tup->uport, count); in tegra_uart_tx_dma_complete()
524 tup->tx_in_progress = 0; in tegra_uart_tx_dma_complete()
526 uart_write_wakeup(&tup->uport); in tegra_uart_tx_dma_complete()
527 tegra_uart_start_next_tx(tup); in tegra_uart_tx_dma_complete()
528 spin_unlock_irqrestore(&tup->uport.lock, flags); in tegra_uart_tx_dma_complete()
531 static int tegra_uart_start_tx_dma(struct tegra_uart_port *tup, in tegra_uart_start_tx_dma() argument
534 struct circ_buf *xmit = &tup->uport.state->xmit; in tegra_uart_start_tx_dma()
537 tup->tx_bytes = count & ~(0xF); in tegra_uart_start_tx_dma()
538 tx_phys_addr = tup->tx_dma_buf_phys + xmit->tail; in tegra_uart_start_tx_dma()
540 dma_sync_single_for_device(tup->uport.dev, tx_phys_addr, in tegra_uart_start_tx_dma()
541 tup->tx_bytes, DMA_TO_DEVICE); in tegra_uart_start_tx_dma()
543 tup->tx_dma_desc = dmaengine_prep_slave_single(tup->tx_dma_chan, in tegra_uart_start_tx_dma()
544 tx_phys_addr, tup->tx_bytes, DMA_MEM_TO_DEV, in tegra_uart_start_tx_dma()
546 if (!tup->tx_dma_desc) { in tegra_uart_start_tx_dma()
547 dev_err(tup->uport.dev, "Not able to get desc for Tx\n"); in tegra_uart_start_tx_dma()
551 tup->tx_dma_desc->callback = tegra_uart_tx_dma_complete; in tegra_uart_start_tx_dma()
552 tup->tx_dma_desc->callback_param = tup; in tegra_uart_start_tx_dma()
553 tup->tx_in_progress = TEGRA_UART_TX_DMA; in tegra_uart_start_tx_dma()
554 tup->tx_bytes_requested = tup->tx_bytes; in tegra_uart_start_tx_dma()
555 tup->tx_cookie = dmaengine_submit(tup->tx_dma_desc); in tegra_uart_start_tx_dma()
556 dma_async_issue_pending(tup->tx_dma_chan); in tegra_uart_start_tx_dma()
560 static void tegra_uart_start_next_tx(struct tegra_uart_port *tup) in tegra_uart_start_next_tx() argument
564 struct circ_buf *xmit = &tup->uport.state->xmit; in tegra_uart_start_next_tx()
566 if (!tup->current_baud) in tegra_uart_start_next_tx()
574 if (tup->use_tx_pio || count < TEGRA_UART_MIN_DMA) in tegra_uart_start_next_tx()
575 tegra_uart_start_pio_tx(tup, count); in tegra_uart_start_next_tx()
577 tegra_uart_start_pio_tx(tup, BYTES_TO_ALIGN(tail)); in tegra_uart_start_next_tx()
579 tegra_uart_start_tx_dma(tup, count); in tegra_uart_start_next_tx()
585 struct tegra_uart_port *tup = to_tegra_uport(u); in tegra_uart_start_tx() local
588 if (!uart_circ_empty(xmit) && !tup->tx_in_progress) in tegra_uart_start_tx()
589 tegra_uart_start_next_tx(tup); in tegra_uart_start_tx()
594 struct tegra_uart_port *tup = to_tegra_uport(u); in tegra_uart_tx_empty() local
599 if (!tup->tx_in_progress) { in tegra_uart_tx_empty()
600 unsigned long lsr = tegra_uart_read(tup, UART_LSR); in tegra_uart_tx_empty()
610 struct tegra_uart_port *tup = to_tegra_uport(u); in tegra_uart_stop_tx() local
614 if (tup->tx_in_progress != TEGRA_UART_TX_DMA) in tegra_uart_stop_tx()
617 dmaengine_pause(tup->tx_dma_chan); in tegra_uart_stop_tx()
618 dmaengine_tx_status(tup->tx_dma_chan, tup->tx_cookie, &state); in tegra_uart_stop_tx()
619 dmaengine_terminate_all(tup->tx_dma_chan); in tegra_uart_stop_tx()
620 count = tup->tx_bytes_requested - state.residue; in tegra_uart_stop_tx()
621 async_tx_ack(tup->tx_dma_desc); in tegra_uart_stop_tx()
622 uart_xmit_advance(&tup->uport, count); in tegra_uart_stop_tx()
623 tup->tx_in_progress = 0; in tegra_uart_stop_tx()
626 static void tegra_uart_handle_tx_pio(struct tegra_uart_port *tup) in tegra_uart_handle_tx_pio() argument
628 struct circ_buf *xmit = &tup->uport.state->xmit; in tegra_uart_handle_tx_pio()
630 tegra_uart_fill_tx_fifo(tup, tup->tx_bytes); in tegra_uart_handle_tx_pio()
631 tup->tx_in_progress = 0; in tegra_uart_handle_tx_pio()
633 uart_write_wakeup(&tup->uport); in tegra_uart_handle_tx_pio()
634 tegra_uart_start_next_tx(tup); in tegra_uart_handle_tx_pio()
637 static void tegra_uart_handle_rx_pio(struct tegra_uart_port *tup, in tegra_uart_handle_rx_pio() argument
645 lsr = tegra_uart_read(tup, UART_LSR); in tegra_uart_handle_rx_pio()
649 flag = tegra_uart_decode_rx_error(tup, lsr); in tegra_uart_handle_rx_pio()
653 ch = (unsigned char) tegra_uart_read(tup, UART_RX); in tegra_uart_handle_rx_pio()
654 tup->uport.icount.rx++; in tegra_uart_handle_rx_pio()
656 if (uart_handle_sysrq_char(&tup->uport, ch)) in tegra_uart_handle_rx_pio()
659 if (tup->uport.ignore_status_mask & UART_LSR_DR) in tegra_uart_handle_rx_pio()
666 static void tegra_uart_copy_rx_to_tty(struct tegra_uart_port *tup, in tegra_uart_copy_rx_to_tty() argument
676 tup->uport.icount.rx += count; in tegra_uart_copy_rx_to_tty()
678 if (tup->uport.ignore_status_mask & UART_LSR_DR) in tegra_uart_copy_rx_to_tty()
681 dma_sync_single_for_cpu(tup->uport.dev, tup->rx_dma_buf_phys, in tegra_uart_copy_rx_to_tty()
684 ((unsigned char *)(tup->rx_dma_buf_virt)), count); in tegra_uart_copy_rx_to_tty()
687 dev_err(tup->uport.dev, "RxData copy to tty layer failed\n"); in tegra_uart_copy_rx_to_tty()
689 dma_sync_single_for_device(tup->uport.dev, tup->rx_dma_buf_phys, in tegra_uart_copy_rx_to_tty()
693 static void do_handle_rx_pio(struct tegra_uart_port *tup) in do_handle_rx_pio() argument
695 struct tty_struct *tty = tty_port_tty_get(&tup->uport.state->port); in do_handle_rx_pio()
696 struct tty_port *port = &tup->uport.state->port; in do_handle_rx_pio()
698 tegra_uart_handle_rx_pio(tup, port); in do_handle_rx_pio()
705 static void tegra_uart_rx_buffer_push(struct tegra_uart_port *tup, in tegra_uart_rx_buffer_push() argument
708 struct tty_port *port = &tup->uport.state->port; in tegra_uart_rx_buffer_push()
711 async_tx_ack(tup->rx_dma_desc); in tegra_uart_rx_buffer_push()
712 count = tup->rx_bytes_requested - residue; in tegra_uart_rx_buffer_push()
715 tegra_uart_copy_rx_to_tty(tup, port, count); in tegra_uart_rx_buffer_push()
717 do_handle_rx_pio(tup); in tegra_uart_rx_buffer_push()
722 struct tegra_uart_port *tup = args; in tegra_uart_rx_dma_complete() local
723 struct uart_port *u = &tup->uport; in tegra_uart_rx_dma_complete()
730 status = dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state); in tegra_uart_rx_dma_complete()
733 dev_dbg(tup->uport.dev, "RX DMA is in progress\n"); in tegra_uart_rx_dma_complete()
738 if (tup->rts_active) in tegra_uart_rx_dma_complete()
739 set_rts(tup, false); in tegra_uart_rx_dma_complete()
741 tup->rx_dma_active = false; in tegra_uart_rx_dma_complete()
742 tegra_uart_rx_buffer_push(tup, 0); in tegra_uart_rx_dma_complete()
743 tegra_uart_start_rx_dma(tup); in tegra_uart_rx_dma_complete()
746 if (tup->rts_active) in tegra_uart_rx_dma_complete()
747 set_rts(tup, true); in tegra_uart_rx_dma_complete()
753 static void tegra_uart_terminate_rx_dma(struct tegra_uart_port *tup) in tegra_uart_terminate_rx_dma() argument
757 if (!tup->rx_dma_active) { in tegra_uart_terminate_rx_dma()
758 do_handle_rx_pio(tup); in tegra_uart_terminate_rx_dma()
762 dmaengine_pause(tup->rx_dma_chan); in tegra_uart_terminate_rx_dma()
763 dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state); in tegra_uart_terminate_rx_dma()
764 dmaengine_terminate_all(tup->rx_dma_chan); in tegra_uart_terminate_rx_dma()
766 tegra_uart_rx_buffer_push(tup, state.residue); in tegra_uart_terminate_rx_dma()
767 tup->rx_dma_active = false; in tegra_uart_terminate_rx_dma()
770 static void tegra_uart_handle_rx_dma(struct tegra_uart_port *tup) in tegra_uart_handle_rx_dma() argument
773 if (tup->rts_active) in tegra_uart_handle_rx_dma()
774 set_rts(tup, false); in tegra_uart_handle_rx_dma()
776 tegra_uart_terminate_rx_dma(tup); in tegra_uart_handle_rx_dma()
778 if (tup->rts_active) in tegra_uart_handle_rx_dma()
779 set_rts(tup, true); in tegra_uart_handle_rx_dma()
782 static int tegra_uart_start_rx_dma(struct tegra_uart_port *tup) in tegra_uart_start_rx_dma() argument
786 if (tup->rx_dma_active) in tegra_uart_start_rx_dma()
789 tup->rx_dma_desc = dmaengine_prep_slave_single(tup->rx_dma_chan, in tegra_uart_start_rx_dma()
790 tup->rx_dma_buf_phys, count, DMA_DEV_TO_MEM, in tegra_uart_start_rx_dma()
792 if (!tup->rx_dma_desc) { in tegra_uart_start_rx_dma()
793 dev_err(tup->uport.dev, "Not able to get desc for Rx\n"); in tegra_uart_start_rx_dma()
797 tup->rx_dma_active = true; in tegra_uart_start_rx_dma()
798 tup->rx_dma_desc->callback = tegra_uart_rx_dma_complete; in tegra_uart_start_rx_dma()
799 tup->rx_dma_desc->callback_param = tup; in tegra_uart_start_rx_dma()
800 tup->rx_bytes_requested = count; in tegra_uart_start_rx_dma()
801 tup->rx_cookie = dmaengine_submit(tup->rx_dma_desc); in tegra_uart_start_rx_dma()
802 dma_async_issue_pending(tup->rx_dma_chan); in tegra_uart_start_rx_dma()
808 struct tegra_uart_port *tup = to_tegra_uport(u); in tegra_uart_handle_modem_signal_change() local
811 msr = tegra_uart_read(tup, UART_MSR); in tegra_uart_handle_modem_signal_change()
816 tup->uport.icount.rng++; in tegra_uart_handle_modem_signal_change()
818 tup->uport.icount.dsr++; in tegra_uart_handle_modem_signal_change()
821 uart_handle_dcd_change(&tup->uport, msr & UART_MSR_DCD); in tegra_uart_handle_modem_signal_change()
824 uart_handle_cts_change(&tup->uport, msr & UART_MSR_CTS); in tegra_uart_handle_modem_signal_change()
829 struct tegra_uart_port *tup = data; in tegra_uart_isr() local
830 struct uart_port *u = &tup->uport; in tegra_uart_isr()
839 iir = tegra_uart_read(tup, UART_IIR); in tegra_uart_isr()
841 if (!tup->use_rx_pio && is_rx_int) { in tegra_uart_isr()
842 tegra_uart_handle_rx_dma(tup); in tegra_uart_isr()
843 if (tup->rx_in_progress) { in tegra_uart_isr()
844 ier = tup->ier_shadow; in tegra_uart_isr()
847 tup->ier_shadow = ier; in tegra_uart_isr()
848 tegra_uart_write(tup, ier, UART_IER); in tegra_uart_isr()
851 tegra_uart_start_rx_dma(tup); in tegra_uart_isr()
863 tup->ier_shadow &= ~UART_IER_THRI; in tegra_uart_isr()
864 tegra_uart_write(tup, tup->ier_shadow, UART_IER); in tegra_uart_isr()
865 tegra_uart_handle_tx_pio(tup); in tegra_uart_isr()
870 if (!tup->use_rx_pio) { in tegra_uart_isr()
871 is_rx_int = tup->rx_in_progress; in tegra_uart_isr()
873 ier = tup->ier_shadow; in tegra_uart_isr()
876 tup->ier_shadow = ier; in tegra_uart_isr()
877 tegra_uart_write(tup, ier, UART_IER); in tegra_uart_isr()
882 if (!tup->use_rx_pio) { in tegra_uart_isr()
883 is_rx_start = tup->rx_in_progress; in tegra_uart_isr()
884 tup->ier_shadow &= ~UART_IER_RDI; in tegra_uart_isr()
885 tegra_uart_write(tup, tup->ier_shadow, in tegra_uart_isr()
888 do_handle_rx_pio(tup); in tegra_uart_isr()
893 tegra_uart_decode_rx_error(tup, in tegra_uart_isr()
894 tegra_uart_read(tup, UART_LSR)); in tegra_uart_isr()
906 struct tegra_uart_port *tup = to_tegra_uport(u); in tegra_uart_stop_rx() local
907 struct tty_port *port = &tup->uport.state->port; in tegra_uart_stop_rx()
910 if (tup->rts_active) in tegra_uart_stop_rx()
911 set_rts(tup, false); in tegra_uart_stop_rx()
913 if (!tup->rx_in_progress) in tegra_uart_stop_rx()
916 tegra_uart_wait_sym_time(tup, 1); /* wait one character interval */ in tegra_uart_stop_rx()
918 ier = tup->ier_shadow; in tegra_uart_stop_rx()
921 tup->ier_shadow = ier; in tegra_uart_stop_rx()
922 tegra_uart_write(tup, ier, UART_IER); in tegra_uart_stop_rx()
923 tup->rx_in_progress = 0; in tegra_uart_stop_rx()
925 if (!tup->use_rx_pio) in tegra_uart_stop_rx()
926 tegra_uart_terminate_rx_dma(tup); in tegra_uart_stop_rx()
928 tegra_uart_handle_rx_pio(tup, port); in tegra_uart_stop_rx()
931 static void tegra_uart_hw_deinit(struct tegra_uart_port *tup) in tegra_uart_hw_deinit() argument
934 unsigned long char_time = DIV_ROUND_UP(10000000, tup->current_baud); in tegra_uart_hw_deinit()
935 unsigned long fifo_empty_time = tup->uport.fifosize * char_time; in tegra_uart_hw_deinit()
942 tegra_uart_write(tup, 0, UART_IER); in tegra_uart_hw_deinit()
944 lsr = tegra_uart_read(tup, UART_LSR); in tegra_uart_hw_deinit()
946 msr = tegra_uart_read(tup, UART_MSR); in tegra_uart_hw_deinit()
947 mcr = tegra_uart_read(tup, UART_MCR); in tegra_uart_hw_deinit()
949 dev_err(tup->uport.dev, in tegra_uart_hw_deinit()
958 msr = tegra_uart_read(tup, UART_MSR); in tegra_uart_hw_deinit()
959 mcr = tegra_uart_read(tup, UART_MCR); in tegra_uart_hw_deinit()
962 dev_err(tup->uport.dev, in tegra_uart_hw_deinit()
966 lsr = tegra_uart_read(tup, UART_LSR); in tegra_uart_hw_deinit()
970 spin_lock_irqsave(&tup->uport.lock, flags); in tegra_uart_hw_deinit()
972 tegra_uart_fifo_reset(tup, UART_FCR_CLEAR_XMIT | UART_FCR_CLEAR_RCVR); in tegra_uart_hw_deinit()
973 tup->current_baud = 0; in tegra_uart_hw_deinit()
974 spin_unlock_irqrestore(&tup->uport.lock, flags); in tegra_uart_hw_deinit()
976 tup->rx_in_progress = 0; in tegra_uart_hw_deinit()
977 tup->tx_in_progress = 0; in tegra_uart_hw_deinit()
979 if (!tup->use_rx_pio) in tegra_uart_hw_deinit()
980 tegra_uart_dma_channel_free(tup, true); in tegra_uart_hw_deinit()
981 if (!tup->use_tx_pio) in tegra_uart_hw_deinit()
982 tegra_uart_dma_channel_free(tup, false); in tegra_uart_hw_deinit()
984 clk_disable_unprepare(tup->uart_clk); in tegra_uart_hw_deinit()
987 static int tegra_uart_hw_init(struct tegra_uart_port *tup) in tegra_uart_hw_init() argument
991 tup->fcr_shadow = 0; in tegra_uart_hw_init()
992 tup->mcr_shadow = 0; in tegra_uart_hw_init()
993 tup->lcr_shadow = 0; in tegra_uart_hw_init()
994 tup->ier_shadow = 0; in tegra_uart_hw_init()
995 tup->current_baud = 0; in tegra_uart_hw_init()
997 ret = clk_prepare_enable(tup->uart_clk); in tegra_uart_hw_init()
999 dev_err(tup->uport.dev, "could not enable clk\n"); in tegra_uart_hw_init()
1004 reset_control_assert(tup->rst); in tegra_uart_hw_init()
1006 reset_control_deassert(tup->rst); in tegra_uart_hw_init()
1008 tup->rx_in_progress = 0; in tegra_uart_hw_init()
1009 tup->tx_in_progress = 0; in tegra_uart_hw_init()
1029 tup->fcr_shadow = UART_FCR_ENABLE_FIFO; in tegra_uart_hw_init()
1031 if (tup->use_rx_pio) { in tegra_uart_hw_init()
1032 tup->fcr_shadow |= UART_FCR_R_TRIG_11; in tegra_uart_hw_init()
1034 if (tup->cdata->max_dma_burst_bytes == 8) in tegra_uart_hw_init()
1035 tup->fcr_shadow |= UART_FCR_R_TRIG_10; in tegra_uart_hw_init()
1037 tup->fcr_shadow |= UART_FCR_R_TRIG_01; in tegra_uart_hw_init()
1040 tup->fcr_shadow |= TEGRA_UART_TX_TRIG_16B; in tegra_uart_hw_init()
1041 tegra_uart_write(tup, tup->fcr_shadow, UART_FCR); in tegra_uart_hw_init()
1044 tegra_uart_read(tup, UART_SCR); in tegra_uart_hw_init()
1046 if (tup->cdata->fifo_mode_enable_status) { in tegra_uart_hw_init()
1047 ret = tegra_uart_wait_fifo_mode_enabled(tup); in tegra_uart_hw_init()
1049 dev_err(tup->uport.dev, in tegra_uart_hw_init()
1060 tegra_uart_wait_cycle_time(tup, 3); in tegra_uart_hw_init()
1068 ret = tegra_set_baudrate(tup, TEGRA_UART_DEFAULT_BAUD); in tegra_uart_hw_init()
1070 dev_err(tup->uport.dev, "Failed to set baud rate\n"); in tegra_uart_hw_init()
1073 if (!tup->use_rx_pio) { in tegra_uart_hw_init()
1074 tup->lcr_shadow = TEGRA_UART_DEFAULT_LSR; in tegra_uart_hw_init()
1075 tup->fcr_shadow |= UART_FCR_DMA_SELECT; in tegra_uart_hw_init()
1076 tegra_uart_write(tup, tup->fcr_shadow, UART_FCR); in tegra_uart_hw_init()
1078 tegra_uart_write(tup, tup->fcr_shadow, UART_FCR); in tegra_uart_hw_init()
1080 tup->rx_in_progress = 1; in tegra_uart_hw_init()
1096 tup->ier_shadow = UART_IER_RLSI | UART_IER_RTOIE | UART_IER_RDI; in tegra_uart_hw_init()
1102 if (!tup->use_rx_pio) in tegra_uart_hw_init()
1103 tup->ier_shadow |= TEGRA_UART_IER_EORD; in tegra_uart_hw_init()
1105 tegra_uart_write(tup, tup->ier_shadow, UART_IER); in tegra_uart_hw_init()
1109 static void tegra_uart_dma_channel_free(struct tegra_uart_port *tup, in tegra_uart_dma_channel_free() argument
1113 dmaengine_terminate_all(tup->rx_dma_chan); in tegra_uart_dma_channel_free()
1114 dma_release_channel(tup->rx_dma_chan); in tegra_uart_dma_channel_free()
1115 dma_free_coherent(tup->uport.dev, TEGRA_UART_RX_DMA_BUFFER_SIZE, in tegra_uart_dma_channel_free()
1116 tup->rx_dma_buf_virt, tup->rx_dma_buf_phys); in tegra_uart_dma_channel_free()
1117 tup->rx_dma_chan = NULL; in tegra_uart_dma_channel_free()
1118 tup->rx_dma_buf_phys = 0; in tegra_uart_dma_channel_free()
1119 tup->rx_dma_buf_virt = NULL; in tegra_uart_dma_channel_free()
1121 dmaengine_terminate_all(tup->tx_dma_chan); in tegra_uart_dma_channel_free()
1122 dma_release_channel(tup->tx_dma_chan); in tegra_uart_dma_channel_free()
1123 dma_unmap_single(tup->uport.dev, tup->tx_dma_buf_phys, in tegra_uart_dma_channel_free()
1125 tup->tx_dma_chan = NULL; in tegra_uart_dma_channel_free()
1126 tup->tx_dma_buf_phys = 0; in tegra_uart_dma_channel_free()
1127 tup->tx_dma_buf_virt = NULL; in tegra_uart_dma_channel_free()
1131 static int tegra_uart_dma_channel_allocate(struct tegra_uart_port *tup, in tegra_uart_dma_channel_allocate() argument
1140 dma_chan = dma_request_chan(tup->uport.dev, dma_to_memory ? "rx" : "tx"); in tegra_uart_dma_channel_allocate()
1143 dev_err(tup->uport.dev, in tegra_uart_dma_channel_allocate()
1149 dma_buf = dma_alloc_coherent(tup->uport.dev, in tegra_uart_dma_channel_allocate()
1153 dev_err(tup->uport.dev, in tegra_uart_dma_channel_allocate()
1158 dma_sync_single_for_device(tup->uport.dev, dma_phys, in tegra_uart_dma_channel_allocate()
1161 dma_sconfig.src_addr = tup->uport.mapbase; in tegra_uart_dma_channel_allocate()
1163 dma_sconfig.src_maxburst = tup->cdata->max_dma_burst_bytes; in tegra_uart_dma_channel_allocate()
1164 tup->rx_dma_chan = dma_chan; in tegra_uart_dma_channel_allocate()
1165 tup->rx_dma_buf_virt = dma_buf; in tegra_uart_dma_channel_allocate()
1166 tup->rx_dma_buf_phys = dma_phys; in tegra_uart_dma_channel_allocate()
1168 dma_phys = dma_map_single(tup->uport.dev, in tegra_uart_dma_channel_allocate()
1169 tup->uport.state->xmit.buf, UART_XMIT_SIZE, in tegra_uart_dma_channel_allocate()
1171 if (dma_mapping_error(tup->uport.dev, dma_phys)) { in tegra_uart_dma_channel_allocate()
1172 dev_err(tup->uport.dev, "dma_map_single tx failed\n"); in tegra_uart_dma_channel_allocate()
1176 dma_buf = tup->uport.state->xmit.buf; in tegra_uart_dma_channel_allocate()
1177 dma_sconfig.dst_addr = tup->uport.mapbase; in tegra_uart_dma_channel_allocate()
1180 tup->tx_dma_chan = dma_chan; in tegra_uart_dma_channel_allocate()
1181 tup->tx_dma_buf_virt = dma_buf; in tegra_uart_dma_channel_allocate()
1182 tup->tx_dma_buf_phys = dma_phys; in tegra_uart_dma_channel_allocate()
1187 dev_err(tup->uport.dev, in tegra_uart_dma_channel_allocate()
1189 tegra_uart_dma_channel_free(tup, dma_to_memory); in tegra_uart_dma_channel_allocate()
1198 struct tegra_uart_port *tup = to_tegra_uport(u); in tegra_uart_startup() local
1201 if (!tup->use_tx_pio) { in tegra_uart_startup()
1202 ret = tegra_uart_dma_channel_allocate(tup, false); in tegra_uart_startup()
1210 if (!tup->use_rx_pio) { in tegra_uart_startup()
1211 ret = tegra_uart_dma_channel_allocate(tup, true); in tegra_uart_startup()
1219 ret = tegra_uart_hw_init(tup); in tegra_uart_startup()
1226 dev_name(u->dev), tup); in tegra_uart_startup()
1234 if (!tup->use_rx_pio) in tegra_uart_startup()
1235 tegra_uart_dma_channel_free(tup, true); in tegra_uart_startup()
1237 if (!tup->use_tx_pio) in tegra_uart_startup()
1238 tegra_uart_dma_channel_free(tup, false); in tegra_uart_startup()
1248 struct tegra_uart_port *tup = to_tegra_uport(u); in tegra_uart_flush_buffer() local
1250 tup->tx_bytes = 0; in tegra_uart_flush_buffer()
1251 if (tup->tx_dma_chan) in tegra_uart_flush_buffer()
1252 dmaengine_terminate_all(tup->tx_dma_chan); in tegra_uart_flush_buffer()
1257 struct tegra_uart_port *tup = to_tegra_uport(u); in tegra_uart_shutdown() local
1259 tegra_uart_hw_deinit(tup); in tegra_uart_shutdown()
1260 free_irq(u->irq, tup); in tegra_uart_shutdown()
1265 struct tegra_uart_port *tup = to_tegra_uport(u); in tegra_uart_enable_ms() local
1267 if (tup->enable_modem_interrupt) { in tegra_uart_enable_ms()
1268 tup->ier_shadow |= UART_IER_MSI; in tegra_uart_enable_ms()
1269 tegra_uart_write(tup, tup->ier_shadow, UART_IER); in tegra_uart_enable_ms()
1276 struct tegra_uart_port *tup = to_tegra_uport(u); in tegra_uart_set_termios() local
1281 struct clk *parent_clk = clk_get_parent(tup->uart_clk); in tegra_uart_set_termios()
1283 int max_divider = (tup->cdata->support_clk_src_div) ? 0x7FFF : 0xFFFF; in tegra_uart_set_termios()
1290 if (tup->rts_active) in tegra_uart_set_termios()
1291 set_rts(tup, false); in tegra_uart_set_termios()
1294 tegra_uart_write(tup, tup->ier_shadow | UART_IER_RDI, UART_IER); in tegra_uart_set_termios()
1295 tegra_uart_read(tup, UART_IER); in tegra_uart_set_termios()
1296 tegra_uart_write(tup, 0, UART_IER); in tegra_uart_set_termios()
1297 tegra_uart_read(tup, UART_IER); in tegra_uart_set_termios()
1300 lcr = tup->lcr_shadow; in tegra_uart_set_termios()
1348 tegra_uart_write(tup, lcr, UART_LCR); in tegra_uart_set_termios()
1349 tup->lcr_shadow = lcr; in tegra_uart_set_termios()
1350 tup->symb_bit = symb_bit; in tegra_uart_set_termios()
1357 ret = tegra_set_baudrate(tup, baud); in tegra_uart_set_termios()
1359 dev_err(tup->uport.dev, "Failed to set baud rate\n"); in tegra_uart_set_termios()
1368 tup->mcr_shadow |= TEGRA_UART_MCR_CTS_EN; in tegra_uart_set_termios()
1369 tup->mcr_shadow &= ~TEGRA_UART_MCR_RTS_EN; in tegra_uart_set_termios()
1370 tegra_uart_write(tup, tup->mcr_shadow, UART_MCR); in tegra_uart_set_termios()
1372 if (tup->rts_active) in tegra_uart_set_termios()
1373 set_rts(tup, true); in tegra_uart_set_termios()
1375 tup->mcr_shadow &= ~TEGRA_UART_MCR_CTS_EN; in tegra_uart_set_termios()
1376 tup->mcr_shadow &= ~TEGRA_UART_MCR_RTS_EN; in tegra_uart_set_termios()
1377 tegra_uart_write(tup, tup->mcr_shadow, UART_MCR); in tegra_uart_set_termios()
1384 tegra_uart_read(tup, UART_IER); in tegra_uart_set_termios()
1387 tegra_uart_write(tup, tup->ier_shadow, UART_IER); in tegra_uart_set_termios()
1388 tegra_uart_read(tup, UART_IER); in tegra_uart_set_termios()
1390 tup->uport.ignore_status_mask = 0; in tegra_uart_set_termios()
1393 tup->uport.ignore_status_mask |= UART_LSR_DR; in tegra_uart_set_termios()
1395 tup->uport.ignore_status_mask |= UART_LSR_BI; in tegra_uart_set_termios()
1432 struct tegra_uart_port *tup) in tegra_uart_parse_dt() argument
1447 tup->uport.line = port; in tegra_uart_parse_dt()
1449 tup->enable_modem_interrupt = of_property_read_bool(np, in tegra_uart_parse_dt()
1454 tup->use_rx_pio = true; in tegra_uart_parse_dt()
1459 tup->use_tx_pio = true; in tegra_uart_parse_dt()
1465 tup->n_adjustable_baud_rates = n_entries / 3; in tegra_uart_parse_dt()
1466 tup->baud_tolerance = in tegra_uart_parse_dt()
1467 devm_kzalloc(&pdev->dev, (tup->n_adjustable_baud_rates) * in tegra_uart_parse_dt()
1468 sizeof(*tup->baud_tolerance), GFP_KERNEL); in tegra_uart_parse_dt()
1469 if (!tup->baud_tolerance) in tegra_uart_parse_dt()
1478 tup->baud_tolerance[index].lower_range_baud = in tegra_uart_parse_dt()
1485 tup->baud_tolerance[index].upper_range_baud = in tegra_uart_parse_dt()
1492 tup->baud_tolerance[index].tolerance = in tegra_uart_parse_dt()
1496 tup->n_adjustable_baud_rates = 0; in tegra_uart_parse_dt()
1566 struct tegra_uart_port *tup; in tegra_uart_probe() local
1580 tup = devm_kzalloc(&pdev->dev, sizeof(*tup), GFP_KERNEL); in tegra_uart_probe()
1581 if (!tup) { in tegra_uart_probe()
1586 ret = tegra_uart_parse_dt(pdev, tup); in tegra_uart_probe()
1590 u = &tup->uport; in tegra_uart_probe()
1595 tup->cdata = cdata; in tegra_uart_probe()
1597 platform_set_drvdata(pdev, tup); in tegra_uart_probe()
1609 tup->uart_clk = devm_clk_get(&pdev->dev, NULL); in tegra_uart_probe()
1610 if (IS_ERR(tup->uart_clk)) { in tegra_uart_probe()
1612 return PTR_ERR(tup->uart_clk); in tegra_uart_probe()
1615 tup->rst = devm_reset_control_get_exclusive(&pdev->dev, "serial"); in tegra_uart_probe()
1616 if (IS_ERR(tup->rst)) { in tegra_uart_probe()
1618 return PTR_ERR(tup->rst); in tegra_uart_probe()
1637 struct tegra_uart_port *tup = platform_get_drvdata(pdev); in tegra_uart_remove() local
1638 struct uart_port *u = &tup->uport; in tegra_uart_remove()
1647 struct tegra_uart_port *tup = dev_get_drvdata(dev); in tegra_uart_suspend() local
1648 struct uart_port *u = &tup->uport; in tegra_uart_suspend()
1655 struct tegra_uart_port *tup = dev_get_drvdata(dev); in tegra_uart_resume() local
1656 struct uart_port *u = &tup->uport; in tegra_uart_resume()