1# SPDX-License-Identifier: GPL-2.0-only 2menu "IRQ chip support" 3 4config IRQCHIP 5 def_bool y 6 depends on OF_IRQ 7 8config ARM_GIC 9 bool 10 select IRQ_DOMAIN_HIERARCHY 11 select GENERIC_IRQ_MULTI_HANDLER 12 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 13 14config ARM_GIC_PM 15 bool 16 depends on PM 17 select ARM_GIC 18 19config ARM_GIC_MAX_NR 20 int 21 depends on ARM_GIC 22 default 2 if ARCH_REALVIEW 23 default 1 24 25config ARM_GIC_V2M 26 bool 27 depends on PCI 28 select ARM_GIC 29 select PCI_MSI 30 31config GIC_NON_BANKED 32 bool 33 34config ARM_GIC_V3 35 bool 36 select GENERIC_IRQ_MULTI_HANDLER 37 select IRQ_DOMAIN_HIERARCHY 38 select PARTITION_PERCPU 39 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 40 41config ARM_GIC_V3_ITS 42 bool 43 select GENERIC_MSI_IRQ_DOMAIN 44 default ARM_GIC_V3 45 46config ARM_GIC_V3_ITS_PCI 47 bool 48 depends on ARM_GIC_V3_ITS 49 depends on PCI 50 depends on PCI_MSI 51 default ARM_GIC_V3_ITS 52 53config ARM_GIC_V3_ITS_FSL_MC 54 bool 55 depends on ARM_GIC_V3_ITS 56 depends on FSL_MC_BUS 57 default ARM_GIC_V3_ITS 58 59config ARM_NVIC 60 bool 61 select IRQ_DOMAIN_HIERARCHY 62 select GENERIC_IRQ_CHIP 63 64config ARM_VIC 65 bool 66 select IRQ_DOMAIN 67 select GENERIC_IRQ_MULTI_HANDLER 68 69config ARM_VIC_NR 70 int 71 default 4 if ARCH_S5PV210 72 default 2 73 depends on ARM_VIC 74 help 75 The maximum number of VICs available in the system, for 76 power management. 77 78config ARMADA_370_XP_IRQ 79 bool 80 select GENERIC_IRQ_CHIP 81 select PCI_MSI if PCI 82 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 83 84config ALPINE_MSI 85 bool 86 depends on PCI 87 select PCI_MSI 88 select GENERIC_IRQ_CHIP 89 90config AL_FIC 91 bool "Amazon's Annapurna Labs Fabric Interrupt Controller" 92 depends on OF || COMPILE_TEST 93 select GENERIC_IRQ_CHIP 94 select IRQ_DOMAIN 95 help 96 Support Amazon's Annapurna Labs Fabric Interrupt Controller. 97 98config ATMEL_AIC_IRQ 99 bool 100 select GENERIC_IRQ_CHIP 101 select IRQ_DOMAIN 102 select GENERIC_IRQ_MULTI_HANDLER 103 select SPARSE_IRQ 104 105config ATMEL_AIC5_IRQ 106 bool 107 select GENERIC_IRQ_CHIP 108 select IRQ_DOMAIN 109 select GENERIC_IRQ_MULTI_HANDLER 110 select SPARSE_IRQ 111 112config I8259 113 bool 114 select IRQ_DOMAIN 115 116config BCM6345_L1_IRQ 117 bool 118 select GENERIC_IRQ_CHIP 119 select IRQ_DOMAIN 120 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 121 122config BCM7038_L1_IRQ 123 bool 124 select GENERIC_IRQ_CHIP 125 select IRQ_DOMAIN 126 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 127 128config BCM7120_L2_IRQ 129 bool 130 select GENERIC_IRQ_CHIP 131 select IRQ_DOMAIN 132 133config BRCMSTB_L2_IRQ 134 bool 135 select GENERIC_IRQ_CHIP 136 select IRQ_DOMAIN 137 138config DAVINCI_AINTC 139 bool 140 select GENERIC_IRQ_CHIP 141 select IRQ_DOMAIN 142 143config DAVINCI_CP_INTC 144 bool 145 select GENERIC_IRQ_CHIP 146 select IRQ_DOMAIN 147 148config DW_APB_ICTL 149 bool 150 select GENERIC_IRQ_CHIP 151 select IRQ_DOMAIN_HIERARCHY 152 153config FARADAY_FTINTC010 154 bool 155 select IRQ_DOMAIN 156 select GENERIC_IRQ_MULTI_HANDLER 157 select SPARSE_IRQ 158 159config HISILICON_IRQ_MBIGEN 160 bool 161 select ARM_GIC_V3 162 select ARM_GIC_V3_ITS 163 164config IMGPDC_IRQ 165 bool 166 select GENERIC_IRQ_CHIP 167 select IRQ_DOMAIN 168 169config IXP4XX_IRQ 170 bool 171 select IRQ_DOMAIN 172 select GENERIC_IRQ_MULTI_HANDLER 173 select SPARSE_IRQ 174 175config MADERA_IRQ 176 tristate 177 178config IRQ_MIPS_CPU 179 bool 180 select GENERIC_IRQ_CHIP 181 select GENERIC_IRQ_IPI if SMP && SYS_SUPPORTS_MULTITHREADING 182 select IRQ_DOMAIN 183 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 184 185config CLPS711X_IRQCHIP 186 bool 187 depends on ARCH_CLPS711X 188 select IRQ_DOMAIN 189 select GENERIC_IRQ_MULTI_HANDLER 190 select SPARSE_IRQ 191 default y 192 193config OMPIC 194 bool 195 196config OR1K_PIC 197 bool 198 select IRQ_DOMAIN 199 200config OMAP_IRQCHIP 201 bool 202 select GENERIC_IRQ_CHIP 203 select IRQ_DOMAIN 204 205config ORION_IRQCHIP 206 bool 207 select IRQ_DOMAIN 208 select GENERIC_IRQ_MULTI_HANDLER 209 210config PIC32_EVIC 211 bool 212 select GENERIC_IRQ_CHIP 213 select IRQ_DOMAIN 214 215config JCORE_AIC 216 bool "J-Core integrated AIC" if COMPILE_TEST 217 depends on OF 218 select IRQ_DOMAIN 219 help 220 Support for the J-Core integrated AIC. 221 222config RDA_INTC 223 bool 224 select IRQ_DOMAIN 225 226config RENESAS_INTC_IRQPIN 227 bool "Renesas INTC External IRQ Pin Support" if COMPILE_TEST 228 select IRQ_DOMAIN 229 help 230 Enable support for the Renesas Interrupt Controller for external 231 interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs. 232 233config RENESAS_IRQC 234 bool "Renesas R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} IRQC support" if COMPILE_TEST 235 select GENERIC_IRQ_CHIP 236 select IRQ_DOMAIN 237 help 238 Enable support for the Renesas Interrupt Controller for external 239 devices, as found on R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} SoCs. 240 241config RENESAS_RZA1_IRQC 242 bool "Renesas RZ/A1 IRQC support" if COMPILE_TEST 243 select IRQ_DOMAIN_HIERARCHY 244 help 245 Enable support for the Renesas RZ/A1 Interrupt Controller, to use up 246 to 8 external interrupts with configurable sense select. 247 248config SL28CPLD_INTC 249 bool "Kontron sl28cpld IRQ controller" 250 depends on MFD_SL28CPLD=y || COMPILE_TEST 251 select REGMAP_IRQ 252 help 253 Interrupt controller driver for the board management controller 254 found on the Kontron sl28 CPLD. 255 256config ST_IRQCHIP 257 bool 258 select REGMAP 259 select MFD_SYSCON 260 help 261 Enables SysCfg Controlled IRQs on STi based platforms. 262 263config TANGO_IRQ 264 bool 265 select IRQ_DOMAIN 266 select GENERIC_IRQ_CHIP 267 268config TB10X_IRQC 269 bool 270 select IRQ_DOMAIN 271 select GENERIC_IRQ_CHIP 272 273config TS4800_IRQ 274 tristate "TS-4800 IRQ controller" 275 select IRQ_DOMAIN 276 depends on HAS_IOMEM 277 depends on SOC_IMX51 || COMPILE_TEST 278 help 279 Support for the TS-4800 FPGA IRQ controller 280 281config VERSATILE_FPGA_IRQ 282 bool 283 select IRQ_DOMAIN 284 285config VERSATILE_FPGA_IRQ_NR 286 int 287 default 4 288 depends on VERSATILE_FPGA_IRQ 289 290config XTENSA_MX 291 bool 292 select IRQ_DOMAIN 293 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 294 295config XILINX_INTC 296 bool 297 select IRQ_DOMAIN 298 299config IRQ_CROSSBAR 300 bool 301 help 302 Support for a CROSSBAR ip that precedes the main interrupt controller. 303 The primary irqchip invokes the crossbar's callback which inturn allocates 304 a free irq and configures the IP. Thus the peripheral interrupts are 305 routed to one of the free irqchip interrupt lines. 306 307config KEYSTONE_IRQ 308 tristate "Keystone 2 IRQ controller IP" 309 depends on ARCH_KEYSTONE 310 help 311 Support for Texas Instruments Keystone 2 IRQ controller IP which 312 is part of the Keystone 2 IPC mechanism 313 314config MIPS_GIC 315 bool 316 select GENERIC_IRQ_IPI if SMP 317 select IRQ_DOMAIN_HIERARCHY 318 select MIPS_CM 319 320config INGENIC_IRQ 321 bool 322 depends on MACH_INGENIC 323 default y 324 325config INGENIC_TCU_IRQ 326 bool "Ingenic JZ47xx TCU interrupt controller" 327 default MACH_INGENIC 328 depends on MIPS || COMPILE_TEST 329 select MFD_SYSCON 330 select GENERIC_IRQ_CHIP 331 help 332 Support for interrupts in the Timer/Counter Unit (TCU) of the Ingenic 333 JZ47xx SoCs. 334 335 If unsure, say N. 336 337config RENESAS_H8300H_INTC 338 bool 339 select IRQ_DOMAIN 340 341config RENESAS_H8S_INTC 342 bool "Renesas H8S Interrupt Controller Support" if COMPILE_TEST 343 select IRQ_DOMAIN 344 help 345 Enable support for the Renesas H8/300 Interrupt Controller, as found 346 on Renesas H8S SoCs. 347 348config IMX_GPCV2 349 bool 350 select IRQ_DOMAIN 351 help 352 Enables the wakeup IRQs for IMX platforms with GPCv2 block 353 354config IRQ_MXS 355 def_bool y if MACH_ASM9260 || ARCH_MXS 356 select IRQ_DOMAIN 357 select STMP_DEVICE 358 359config MSCC_OCELOT_IRQ 360 bool 361 select IRQ_DOMAIN 362 select GENERIC_IRQ_CHIP 363 364config MVEBU_GICP 365 bool 366 367config MVEBU_ICU 368 bool 369 370config MVEBU_ODMI 371 bool 372 select GENERIC_MSI_IRQ_DOMAIN 373 374config MVEBU_PIC 375 bool 376 377config MVEBU_SEI 378 bool 379 380config LS_EXTIRQ 381 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 382 select MFD_SYSCON 383 384config LS_SCFG_MSI 385 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 386 depends on PCI && PCI_MSI 387 388config PARTITION_PERCPU 389 bool 390 391config EZNPS_GIC 392 bool "NPS400 Global Interrupt Manager (GIM)" 393 depends on ARC || (COMPILE_TEST && !64BIT) 394 select IRQ_DOMAIN 395 help 396 Support the EZchip NPS400 global interrupt controller 397 398config STM32_EXTI 399 bool 400 select IRQ_DOMAIN 401 select GENERIC_IRQ_CHIP 402 403config QCOM_IRQ_COMBINER 404 bool "QCOM IRQ combiner support" 405 depends on ARCH_QCOM && ACPI 406 select IRQ_DOMAIN_HIERARCHY 407 help 408 Say yes here to add support for the IRQ combiner devices embedded 409 in Qualcomm Technologies chips. 410 411config IRQ_UNIPHIER_AIDET 412 bool "UniPhier AIDET support" if COMPILE_TEST 413 depends on ARCH_UNIPHIER || COMPILE_TEST 414 default ARCH_UNIPHIER 415 select IRQ_DOMAIN_HIERARCHY 416 help 417 Support for the UniPhier AIDET (ARM Interrupt Detector). 418 419config MESON_IRQ_GPIO 420 tristate "Meson GPIO Interrupt Multiplexer" 421 depends on ARCH_MESON || COMPILE_TEST 422 default ARCH_MESON 423 select IRQ_DOMAIN_HIERARCHY 424 help 425 Support Meson SoC Family GPIO Interrupt Multiplexer 426 427config GOLDFISH_PIC 428 bool "Goldfish programmable interrupt controller" 429 depends on MIPS && (GOLDFISH || COMPILE_TEST) 430 select GENERIC_IRQ_CHIP 431 select IRQ_DOMAIN 432 help 433 Say yes here to enable Goldfish interrupt controller driver used 434 for Goldfish based virtual platforms. 435 436config QCOM_PDC 437 tristate "QCOM PDC" 438 depends on ARCH_QCOM 439 depends on QCOM_SCM || !QCOM_SCM 440 select IRQ_DOMAIN_HIERARCHY 441 help 442 Power Domain Controller driver to manage and configure wakeup 443 IRQs for Qualcomm Technologies Inc (QTI) mobile chips. 444 445config CSKY_MPINTC 446 bool "C-SKY Multi Processor Interrupt Controller" 447 depends on CSKY 448 help 449 Say yes here to enable C-SKY SMP interrupt controller driver used 450 for C-SKY SMP system. 451 In fact it's not mmio map in hardware and it uses ld/st to visit the 452 controller's register inside CPU. 453 454config CSKY_APB_INTC 455 bool "C-SKY APB Interrupt Controller" 456 depends on CSKY 457 help 458 Say yes here to enable C-SKY APB interrupt controller driver used 459 by C-SKY single core SOC system. It uses mmio map apb-bus to visit 460 the controller's register. 461 462config IMX_IRQSTEER 463 bool "i.MX IRQSTEER support" 464 depends on ARCH_MXC || COMPILE_TEST 465 default ARCH_MXC 466 select IRQ_DOMAIN 467 help 468 Support for the i.MX IRQSTEER interrupt multiplexer/remapper. 469 470config IMX_INTMUX 471 bool "i.MX INTMUX support" if COMPILE_TEST 472 default y if ARCH_MXC 473 select IRQ_DOMAIN 474 help 475 Support for the i.MX INTMUX interrupt multiplexer. 476 477config LS1X_IRQ 478 bool "Loongson-1 Interrupt Controller" 479 depends on MACH_LOONGSON32 480 default y 481 select IRQ_DOMAIN 482 select GENERIC_IRQ_CHIP 483 help 484 Support for the Loongson-1 platform Interrupt Controller. 485 486config TI_SCI_INTR_IRQCHIP 487 bool 488 depends on TI_SCI_PROTOCOL 489 select IRQ_DOMAIN_HIERARCHY 490 help 491 This enables the irqchip driver support for K3 Interrupt router 492 over TI System Control Interface available on some new TI's SoCs. 493 If you wish to use interrupt router irq resources managed by the 494 TI System Controller, say Y here. Otherwise, say N. 495 496config TI_SCI_INTA_IRQCHIP 497 bool 498 depends on TI_SCI_PROTOCOL 499 select IRQ_DOMAIN_HIERARCHY 500 select TI_SCI_INTA_MSI_DOMAIN 501 help 502 This enables the irqchip driver support for K3 Interrupt aggregator 503 over TI System Control Interface available on some new TI's SoCs. 504 If you wish to use interrupt aggregator irq resources managed by the 505 TI System Controller, say Y here. Otherwise, say N. 506 507config TI_PRUSS_INTC 508 tristate "TI PRU-ICSS Interrupt Controller" 509 depends on ARCH_DAVINCI || SOC_AM33XX || SOC_AM43XX || SOC_DRA7XX || ARCH_KEYSTONE || ARCH_K3 510 select IRQ_DOMAIN 511 help 512 This enables support for the PRU-ICSS Local Interrupt Controller 513 present within a PRU-ICSS subsystem present on various TI SoCs. 514 The PRUSS INTC enables various interrupts to be routed to multiple 515 different processors within the SoC. 516 517config RISCV_INTC 518 bool "RISC-V Local Interrupt Controller" 519 depends on RISCV 520 default y 521 help 522 This enables support for the per-HART local interrupt controller 523 found in standard RISC-V systems. The per-HART local interrupt 524 controller handles timer interrupts, software interrupts, and 525 hardware interrupts. Without a per-HART local interrupt controller, 526 a RISC-V system will be unable to handle any interrupts. 527 528 If you don't know what to do here, say Y. 529 530config SIFIVE_PLIC 531 bool "SiFive Platform-Level Interrupt Controller" 532 depends on RISCV 533 select IRQ_DOMAIN_HIERARCHY 534 help 535 This enables support for the PLIC chip found in SiFive (and 536 potentially other) RISC-V systems. The PLIC controls devices 537 interrupts and connects them to each core's local interrupt 538 controller. Aside from timer and software interrupts, all other 539 interrupt sources are subordinate to the PLIC. 540 541 If you don't know what to do here, say Y. 542 543config EXYNOS_IRQ_COMBINER 544 bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST 545 depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST 546 help 547 Say yes here to add support for the IRQ combiner devices embedded 548 in Samsung Exynos chips. 549 550config LOONGSON_LIOINTC 551 bool "Loongson Local I/O Interrupt Controller" 552 depends on MACH_LOONGSON64 553 default y 554 select IRQ_DOMAIN 555 select GENERIC_IRQ_CHIP 556 help 557 Support for the Loongson Local I/O Interrupt Controller. 558 559config LOONGSON_HTPIC 560 bool "Loongson3 HyperTransport PIC Controller" 561 depends on MACH_LOONGSON64 562 default y 563 select IRQ_DOMAIN 564 select GENERIC_IRQ_CHIP 565 help 566 Support for the Loongson-3 HyperTransport PIC Controller. 567 568config LOONGSON_HTVEC 569 bool "Loongson3 HyperTransport Interrupt Vector Controller" 570 depends on MACH_LOONGSON64 571 default MACH_LOONGSON64 572 select IRQ_DOMAIN_HIERARCHY 573 help 574 Support for the Loongson3 HyperTransport Interrupt Vector Controller. 575 576config LOONGSON_PCH_PIC 577 bool "Loongson PCH PIC Controller" 578 depends on MACH_LOONGSON64 || COMPILE_TEST 579 default MACH_LOONGSON64 580 select IRQ_DOMAIN_HIERARCHY 581 select IRQ_FASTEOI_HIERARCHY_HANDLERS 582 help 583 Support for the Loongson PCH PIC Controller. 584 585config LOONGSON_PCH_MSI 586 bool "Loongson PCH MSI Controller" 587 depends on MACH_LOONGSON64 || COMPILE_TEST 588 depends on PCI 589 default MACH_LOONGSON64 590 select IRQ_DOMAIN_HIERARCHY 591 select PCI_MSI 592 help 593 Support for the Loongson PCH MSI Controller. 594 595config MST_IRQ 596 bool "MStar Interrupt Controller" 597 depends on ARCH_MEDIATEK || ARCH_MSTARV7 || COMPILE_TEST 598 default ARCH_MEDIATEK 599 select IRQ_DOMAIN 600 select IRQ_DOMAIN_HIERARCHY 601 help 602 Support MStar Interrupt Controller. 603 604endmenu 605