1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (C) 2010 - 2012 Samsung Electronics Co., Ltd.
4 */
5
6 #ifndef FIMC_CORE_H_
7 #define FIMC_CORE_H_
8
9 /*#define DEBUG*/
10
11 #include <linux/platform_device.h>
12 #include <linux/regmap.h>
13 #include <linux/sched.h>
14 #include <linux/spinlock.h>
15 #include <linux/mfd/syscon.h>
16 #include <linux/types.h>
17 #include <linux/videodev2.h>
18 #include <linux/io.h>
19 #include <linux/sizes.h>
20
21 #include <media/media-entity.h>
22 #include <media/videobuf2-v4l2.h>
23 #include <media/v4l2-ctrls.h>
24 #include <media/v4l2-device.h>
25 #include <media/v4l2-mem2mem.h>
26 #include <media/v4l2-mediabus.h>
27 #include <media/drv-intf/exynos-fimc.h>
28
29 #define dbg(fmt, args...) \
30 pr_debug("%s:%d: " fmt "\n", __func__, __LINE__, ##args)
31
32 /* Time to wait for next frame VSYNC interrupt while stopping operation. */
33 #define FIMC_SHUTDOWN_TIMEOUT ((100*HZ)/1000)
34 #define MAX_FIMC_CLOCKS 2
35 #define FIMC_DRIVER_NAME "exynos4-fimc"
36 #define FIMC_MAX_DEVS 4
37 #define FIMC_MAX_OUT_BUFS 4
38 #define SCALER_MAX_HRATIO 64
39 #define SCALER_MAX_VRATIO 64
40 #define DMA_MIN_SIZE 8
41 #define FIMC_CAMIF_MAX_HEIGHT 0x2000
42 #define FIMC_MAX_JPEG_BUF_SIZE (10 * SZ_1M)
43 #define FIMC_MAX_PLANES 3
44 #define FIMC_PIX_LIMITS_MAX 4
45 #define FIMC_DEF_MIN_SIZE 16
46 #define FIMC_DEF_HEIGHT_ALIGN 2
47 #define FIMC_DEF_HOR_OFFS_ALIGN 1
48 #define FIMC_DEFAULT_WIDTH 640
49 #define FIMC_DEFAULT_HEIGHT 480
50
51 /* indices to the clocks array */
52 enum {
53 CLK_BUS,
54 CLK_GATE,
55 };
56
57 enum fimc_dev_flags {
58 ST_LPM,
59 /* m2m node */
60 ST_M2M_RUN,
61 ST_M2M_PEND,
62 ST_M2M_SUSPENDING,
63 ST_M2M_SUSPENDED,
64 /* capture node */
65 ST_CAPT_PEND,
66 ST_CAPT_RUN,
67 ST_CAPT_STREAM,
68 ST_CAPT_ISP_STREAM,
69 ST_CAPT_SUSPENDED,
70 ST_CAPT_SHUT,
71 ST_CAPT_BUSY,
72 ST_CAPT_APPLY_CFG,
73 ST_CAPT_JPEG,
74 };
75
76 #define fimc_m2m_active(dev) test_bit(ST_M2M_RUN, &(dev)->state)
77 #define fimc_m2m_pending(dev) test_bit(ST_M2M_PEND, &(dev)->state)
78
79 #define fimc_capture_running(dev) test_bit(ST_CAPT_RUN, &(dev)->state)
80 #define fimc_capture_pending(dev) test_bit(ST_CAPT_PEND, &(dev)->state)
81 #define fimc_capture_busy(dev) test_bit(ST_CAPT_BUSY, &(dev)->state)
82
83 enum fimc_datapath {
84 FIMC_IO_NONE,
85 FIMC_IO_CAMERA,
86 FIMC_IO_DMA,
87 FIMC_IO_LCDFIFO,
88 FIMC_IO_WRITEBACK,
89 FIMC_IO_ISP,
90 };
91
92 enum fimc_color_fmt {
93 FIMC_FMT_RGB444 = 0x10,
94 FIMC_FMT_RGB555,
95 FIMC_FMT_RGB565,
96 FIMC_FMT_RGB666,
97 FIMC_FMT_RGB888,
98 FIMC_FMT_RGB30_LOCAL,
99 FIMC_FMT_YCBCR420 = 0x20,
100 FIMC_FMT_YCBYCR422,
101 FIMC_FMT_YCRYCB422,
102 FIMC_FMT_CBYCRY422,
103 FIMC_FMT_CRYCBY422,
104 FIMC_FMT_YCBCR444_LOCAL,
105 FIMC_FMT_RAW8 = 0x40,
106 FIMC_FMT_RAW10,
107 FIMC_FMT_RAW12,
108 FIMC_FMT_JPEG = 0x80,
109 FIMC_FMT_YUYV_JPEG = 0x100,
110 };
111
112 #define fimc_fmt_is_user_defined(x) (!!((x) & 0x180))
113 #define fimc_fmt_is_rgb(x) (!!((x) & 0x10))
114
115 #define IS_M2M(__strt) ((__strt) == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE || \
116 __strt == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
117
118 /* The hardware context state. */
119 #define FIMC_PARAMS (1 << 0)
120 #define FIMC_COMPOSE (1 << 1)
121 #define FIMC_CTX_M2M (1 << 16)
122 #define FIMC_CTX_CAP (1 << 17)
123 #define FIMC_CTX_SHUT (1 << 18)
124
125 /* Image conversion flags */
126 #define FIMC_IN_DMA_ACCESS_TILED (1 << 0)
127 #define FIMC_IN_DMA_ACCESS_LINEAR (0 << 0)
128 #define FIMC_OUT_DMA_ACCESS_TILED (1 << 1)
129 #define FIMC_OUT_DMA_ACCESS_LINEAR (0 << 1)
130 #define FIMC_SCAN_MODE_PROGRESSIVE (0 << 2)
131 #define FIMC_SCAN_MODE_INTERLACED (1 << 2)
132 /*
133 * YCbCr data dynamic range for RGB-YUV color conversion.
134 * Y/Cb/Cr: (0 ~ 255) */
135 #define FIMC_COLOR_RANGE_WIDE (0 << 3)
136 /* Y (16 ~ 235), Cb/Cr (16 ~ 240) */
137 #define FIMC_COLOR_RANGE_NARROW (1 << 3)
138
139 /**
140 * struct fimc_dma_offset - pixel offset information for DMA
141 * @y_h: y value horizontal offset
142 * @y_v: y value vertical offset
143 * @cb_h: cb value horizontal offset
144 * @cb_v: cb value vertical offset
145 * @cr_h: cr value horizontal offset
146 * @cr_v: cr value vertical offset
147 */
148 struct fimc_dma_offset {
149 int y_h;
150 int y_v;
151 int cb_h;
152 int cb_v;
153 int cr_h;
154 int cr_v;
155 };
156
157 /**
158 * struct fimc_effect - color effect information
159 * @type: effect type
160 * @pat_cb: cr value when type is "arbitrary"
161 * @pat_cr: cr value when type is "arbitrary"
162 */
163 struct fimc_effect {
164 u32 type;
165 u8 pat_cb;
166 u8 pat_cr;
167 };
168
169 /**
170 * struct fimc_scaler - the configuration data for FIMC inetrnal scaler
171 * @scaleup_h: flag indicating scaling up horizontally
172 * @scaleup_v: flag indicating scaling up vertically
173 * @copy_mode: flag indicating transparent DMA transfer (no scaling
174 * and color format conversion)
175 * @enabled: flag indicating if the scaler is used
176 * @hfactor: horizontal shift factor
177 * @vfactor: vertical shift factor
178 * @pre_hratio: horizontal ratio of the prescaler
179 * @pre_vratio: vertical ratio of the prescaler
180 * @pre_dst_width: the prescaler's destination width
181 * @pre_dst_height: the prescaler's destination height
182 * @main_hratio: the main scaler's horizontal ratio
183 * @main_vratio: the main scaler's vertical ratio
184 * @real_width: source pixel (width - offset)
185 * @real_height: source pixel (height - offset)
186 */
187 struct fimc_scaler {
188 unsigned int scaleup_h:1;
189 unsigned int scaleup_v:1;
190 unsigned int copy_mode:1;
191 unsigned int enabled:1;
192 u32 hfactor;
193 u32 vfactor;
194 u32 pre_hratio;
195 u32 pre_vratio;
196 u32 pre_dst_width;
197 u32 pre_dst_height;
198 u32 main_hratio;
199 u32 main_vratio;
200 u32 real_width;
201 u32 real_height;
202 };
203
204 /**
205 * struct fimc_addr - the FIMC physical address set for DMA
206 * @y: luminance plane physical address
207 * @cb: Cb plane physical address
208 * @cr: Cr plane physical address
209 */
210 struct fimc_addr {
211 u32 y;
212 u32 cb;
213 u32 cr;
214 };
215
216 /**
217 * struct fimc_vid_buffer - the driver's video buffer
218 * @vb: v4l videobuf buffer
219 * @list: linked list structure for buffer queue
220 * @paddr: precalculated physical address set
221 * @index: buffer index for the output DMA engine
222 */
223 struct fimc_vid_buffer {
224 struct vb2_v4l2_buffer vb;
225 struct list_head list;
226 struct fimc_addr paddr;
227 int index;
228 };
229
230 /**
231 * struct fimc_frame - source/target frame properties
232 * @f_width: image full width (virtual screen size)
233 * @f_height: image full height (virtual screen size)
234 * @o_width: original image width as set by S_FMT
235 * @o_height: original image height as set by S_FMT
236 * @offs_h: image horizontal pixel offset
237 * @offs_v: image vertical pixel offset
238 * @width: image pixel width
239 * @height: image pixel weight
240 * @payload: image size in bytes (w x h x bpp)
241 * @bytesperline: bytesperline value for each plane
242 * @paddr: image frame buffer physical addresses
243 * @dma_offset: DMA offset in bytes
244 * @fmt: fimc color format pointer
245 */
246 struct fimc_frame {
247 u32 f_width;
248 u32 f_height;
249 u32 o_width;
250 u32 o_height;
251 u32 offs_h;
252 u32 offs_v;
253 u32 width;
254 u32 height;
255 unsigned int payload[VIDEO_MAX_PLANES];
256 unsigned int bytesperline[VIDEO_MAX_PLANES];
257 struct fimc_addr paddr;
258 struct fimc_dma_offset dma_offset;
259 struct fimc_fmt *fmt;
260 u8 alpha;
261 };
262
263 /**
264 * struct fimc_m2m_device - v4l2 memory-to-memory device data
265 * @vfd: the video device node for v4l2 m2m mode
266 * @m2m_dev: v4l2 memory-to-memory device data
267 * @ctx: hardware context data
268 * @refcnt: the reference counter
269 */
270 struct fimc_m2m_device {
271 struct video_device vfd;
272 struct v4l2_m2m_dev *m2m_dev;
273 struct fimc_ctx *ctx;
274 int refcnt;
275 };
276
277 #define FIMC_SD_PAD_SINK_CAM 0
278 #define FIMC_SD_PAD_SINK_FIFO 1
279 #define FIMC_SD_PAD_SOURCE 2
280 #define FIMC_SD_PADS_NUM 3
281
282 /**
283 * struct fimc_vid_cap - camera capture device information
284 * @ctx: hardware context data
285 * @subdev: subdev exposing the FIMC processing block
286 * @ve: exynos video device entity structure
287 * @vd_pad: fimc video capture node pad
288 * @sd_pads: fimc video processing block pads
289 * @ci_fmt: image format at the FIMC camera input (and the scaler output)
290 * @wb_fmt: image format at the FIMC ISP Writeback input
291 * @source_config: external image source related configuration structure
292 * @pending_buf_q: the pending buffer queue head
293 * @active_buf_q: the queue head of buffers scheduled in hardware
294 * @vbq: the capture am video buffer queue
295 * @active_buf_cnt: number of video buffers scheduled in hardware
296 * @buf_index: index for managing the output DMA buffers
297 * @frame_count: the frame counter for statistics
298 * @reqbufs_count: the number of buffers requested in REQBUFS ioctl
299 * @input: capture input type, grp_id of the attached subdev
300 * @user_subdev_api: true if subdevs are not configured by the host driver
301 */
302 struct fimc_vid_cap {
303 struct fimc_ctx *ctx;
304 struct v4l2_subdev subdev;
305 struct exynos_video_entity ve;
306 struct media_pad vd_pad;
307 struct media_pad sd_pads[FIMC_SD_PADS_NUM];
308 struct v4l2_mbus_framefmt ci_fmt;
309 struct v4l2_mbus_framefmt wb_fmt;
310 struct fimc_source_info source_config;
311 struct list_head pending_buf_q;
312 struct list_head active_buf_q;
313 struct vb2_queue vbq;
314 int active_buf_cnt;
315 int buf_index;
316 unsigned int frame_count;
317 unsigned int reqbufs_count;
318 bool streaming;
319 u32 input;
320 bool user_subdev_api;
321 };
322
323 /**
324 * struct fimc_pix_limit - image pixel size limits in various IP configurations
325 *
326 * @scaler_en_w: max input pixel width when the scaler is enabled
327 * @scaler_dis_w: max input pixel width when the scaler is disabled
328 * @in_rot_en_h: max input width with the input rotator is on
329 * @in_rot_dis_w: max input width with the input rotator is off
330 * @out_rot_en_w: max output width with the output rotator on
331 * @out_rot_dis_w: max output width with the output rotator off
332 */
333 struct fimc_pix_limit {
334 u16 scaler_en_w;
335 u16 scaler_dis_w;
336 u16 in_rot_en_h;
337 u16 in_rot_dis_w;
338 u16 out_rot_en_w;
339 u16 out_rot_dis_w;
340 };
341
342 /**
343 * struct fimc_variant - FIMC device variant information
344 * @has_inp_rot: set if has input rotator
345 * @has_out_rot: set if has output rotator
346 * @has_mainscaler_ext: 1 if extended mainscaler ratios in CIEXTEN register
347 * are present in this IP revision
348 * @has_cam_if: set if this instance has a camera input interface
349 * @has_isp_wb: set if this instance has ISP writeback input
350 * @pix_limit: pixel size constraints for the scaler
351 * @min_inp_pixsize: minimum input pixel size
352 * @min_out_pixsize: minimum output pixel size
353 * @hor_offs_align: horizontal pixel offset alignment
354 * @min_vsize_align: minimum vertical pixel size alignment
355 */
356 struct fimc_variant {
357 unsigned int has_inp_rot:1;
358 unsigned int has_out_rot:1;
359 unsigned int has_mainscaler_ext:1;
360 unsigned int has_cam_if:1;
361 unsigned int has_isp_wb:1;
362 const struct fimc_pix_limit *pix_limit;
363 u16 min_inp_pixsize;
364 u16 min_out_pixsize;
365 u16 hor_offs_align;
366 u16 min_vsize_align;
367 };
368
369 /**
370 * struct fimc_drvdata - per device type driver data
371 * @variant: variant information for this device
372 * @num_entities: number of fimc instances available in a SoC
373 * @lclk_frequency: local bus clock frequency
374 * @cistatus2: 1 if the FIMC IPs have CISTATUS2 register
375 * @dma_pix_hoff: the horizontal DMA offset unit: 1 - pixels, 0 - bytes
376 * @alpha_color: 1 if alpha color component is supported
377 * @out_buf_count: maximum number of output DMA buffers supported
378 */
379 struct fimc_drvdata {
380 const struct fimc_variant *variant[FIMC_MAX_DEVS];
381 int num_entities;
382 unsigned long lclk_frequency;
383 /* Fields common to all FIMC IP instances */
384 u8 cistatus2;
385 u8 dma_pix_hoff;
386 u8 alpha_color;
387 u8 out_buf_count;
388 };
389
390 #define fimc_get_drvdata(_pdev) \
391 ((struct fimc_drvdata *) platform_get_device_id(_pdev)->driver_data)
392
393 struct fimc_ctx;
394
395 /**
396 * struct fimc_dev - abstraction for FIMC entity
397 * @slock: the spinlock protecting this data structure
398 * @lock: the mutex protecting this data structure
399 * @pdev: pointer to the FIMC platform device
400 * @pdata: pointer to the device platform data
401 * @sysreg: pointer to the SYSREG regmap
402 * @variant: the IP variant information
403 * @id: FIMC device index (0..FIMC_MAX_DEVS)
404 * @clock: clocks required for FIMC operation
405 * @regs: the mapped hardware registers
406 * @irq_queue: interrupt handler waitqueue
407 * @v4l2_dev: root v4l2_device
408 * @m2m: memory-to-memory V4L2 device information
409 * @vid_cap: camera capture device information
410 * @state: flags used to synchronize m2m and capture mode operation
411 * @pipeline: fimc video capture pipeline data structure
412 */
413 struct fimc_dev {
414 spinlock_t slock;
415 struct mutex lock;
416 struct platform_device *pdev;
417 struct s5p_platform_fimc *pdata;
418 struct regmap *sysreg;
419 const struct fimc_variant *variant;
420 const struct fimc_drvdata *drv_data;
421 int id;
422 struct clk *clock[MAX_FIMC_CLOCKS];
423 void __iomem *regs;
424 wait_queue_head_t irq_queue;
425 struct v4l2_device *v4l2_dev;
426 struct fimc_m2m_device m2m;
427 struct fimc_vid_cap vid_cap;
428 unsigned long state;
429 };
430
431 /**
432 * struct fimc_ctrls - v4l2 controls structure
433 * @handler: the control handler
434 * @colorfx: image effect control
435 * @colorfx_cbcr: Cb/Cr coefficients control
436 * @rotate: image rotation control
437 * @hflip: horizontal flip control
438 * @vflip: vertical flip control
439 * @alpha: RGB alpha control
440 * @ready: true if @handler is initialized
441 */
442 struct fimc_ctrls {
443 struct v4l2_ctrl_handler handler;
444 struct {
445 struct v4l2_ctrl *colorfx;
446 struct v4l2_ctrl *colorfx_cbcr;
447 };
448 struct v4l2_ctrl *rotate;
449 struct v4l2_ctrl *hflip;
450 struct v4l2_ctrl *vflip;
451 struct v4l2_ctrl *alpha;
452 bool ready;
453 };
454
455 /**
456 * fimc_ctx - the device context data
457 * @s_frame: source frame properties
458 * @d_frame: destination frame properties
459 * @out_order_1p: output 1-plane YCBCR order
460 * @out_order_2p: output 2-plane YCBCR order
461 * @in_order_1p input 1-plane YCBCR order
462 * @in_order_2p: input 2-plane YCBCR order
463 * @in_path: input mode (DMA or camera)
464 * @out_path: output mode (DMA or FIFO)
465 * @scaler: image scaler properties
466 * @effect: image effect
467 * @rotation: image clockwise rotation in degrees
468 * @hflip: indicates image horizontal flip if set
469 * @vflip: indicates image vertical flip if set
470 * @flags: additional flags for image conversion
471 * @state: flags to keep track of user configuration
472 * @fimc_dev: the FIMC device this context applies to
473 * @fh: v4l2 file handle
474 * @ctrls: v4l2 controls structure
475 */
476 struct fimc_ctx {
477 struct fimc_frame s_frame;
478 struct fimc_frame d_frame;
479 u32 out_order_1p;
480 u32 out_order_2p;
481 u32 in_order_1p;
482 u32 in_order_2p;
483 enum fimc_datapath in_path;
484 enum fimc_datapath out_path;
485 struct fimc_scaler scaler;
486 struct fimc_effect effect;
487 int rotation;
488 unsigned int hflip:1;
489 unsigned int vflip:1;
490 u32 flags;
491 u32 state;
492 struct fimc_dev *fimc_dev;
493 struct v4l2_fh fh;
494 struct fimc_ctrls ctrls;
495 };
496
497 #define fh_to_ctx(__fh) container_of(__fh, struct fimc_ctx, fh)
498
set_frame_bounds(struct fimc_frame * f,u32 width,u32 height)499 static inline void set_frame_bounds(struct fimc_frame *f, u32 width, u32 height)
500 {
501 f->o_width = width;
502 f->o_height = height;
503 f->f_width = width;
504 f->f_height = height;
505 }
506
set_frame_crop(struct fimc_frame * f,u32 left,u32 top,u32 width,u32 height)507 static inline void set_frame_crop(struct fimc_frame *f,
508 u32 left, u32 top, u32 width, u32 height)
509 {
510 f->offs_h = left;
511 f->offs_v = top;
512 f->width = width;
513 f->height = height;
514 }
515
fimc_get_format_depth(struct fimc_fmt * ff)516 static inline u32 fimc_get_format_depth(struct fimc_fmt *ff)
517 {
518 u32 i, depth = 0;
519
520 if (ff != NULL)
521 for (i = 0; i < ff->colplanes; i++)
522 depth += ff->depth[i];
523 return depth;
524 }
525
fimc_capture_active(struct fimc_dev * fimc)526 static inline bool fimc_capture_active(struct fimc_dev *fimc)
527 {
528 unsigned long flags;
529 bool ret;
530
531 spin_lock_irqsave(&fimc->slock, flags);
532 ret = !!(fimc->state & (1 << ST_CAPT_RUN) ||
533 fimc->state & (1 << ST_CAPT_PEND));
534 spin_unlock_irqrestore(&fimc->slock, flags);
535 return ret;
536 }
537
fimc_ctx_state_set(u32 state,struct fimc_ctx * ctx)538 static inline void fimc_ctx_state_set(u32 state, struct fimc_ctx *ctx)
539 {
540 unsigned long flags;
541
542 spin_lock_irqsave(&ctx->fimc_dev->slock, flags);
543 ctx->state |= state;
544 spin_unlock_irqrestore(&ctx->fimc_dev->slock, flags);
545 }
546
fimc_ctx_state_is_set(u32 mask,struct fimc_ctx * ctx)547 static inline bool fimc_ctx_state_is_set(u32 mask, struct fimc_ctx *ctx)
548 {
549 unsigned long flags;
550 bool ret;
551
552 spin_lock_irqsave(&ctx->fimc_dev->slock, flags);
553 ret = (ctx->state & mask) == mask;
554 spin_unlock_irqrestore(&ctx->fimc_dev->slock, flags);
555 return ret;
556 }
557
tiled_fmt(struct fimc_fmt * fmt)558 static inline int tiled_fmt(struct fimc_fmt *fmt)
559 {
560 return fmt->fourcc == V4L2_PIX_FMT_NV12MT;
561 }
562
fimc_jpeg_fourcc(u32 pixelformat)563 static inline bool fimc_jpeg_fourcc(u32 pixelformat)
564 {
565 return (pixelformat == V4L2_PIX_FMT_JPEG ||
566 pixelformat == V4L2_PIX_FMT_S5C_UYVY_JPG);
567 }
568
fimc_user_defined_mbus_fmt(u32 code)569 static inline bool fimc_user_defined_mbus_fmt(u32 code)
570 {
571 return (code == MEDIA_BUS_FMT_JPEG_1X8 ||
572 code == MEDIA_BUS_FMT_S5C_UYVY_JPEG_1X8);
573 }
574
575 /* Return the alpha component bit mask */
fimc_get_alpha_mask(struct fimc_fmt * fmt)576 static inline int fimc_get_alpha_mask(struct fimc_fmt *fmt)
577 {
578 switch (fmt->color) {
579 case FIMC_FMT_RGB444: return 0x0f;
580 case FIMC_FMT_RGB555: return 0x01;
581 case FIMC_FMT_RGB888: return 0xff;
582 default: return 0;
583 };
584 }
585
ctx_get_frame(struct fimc_ctx * ctx,enum v4l2_buf_type type)586 static inline struct fimc_frame *ctx_get_frame(struct fimc_ctx *ctx,
587 enum v4l2_buf_type type)
588 {
589 struct fimc_frame *frame;
590
591 if (type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE ||
592 type == V4L2_BUF_TYPE_VIDEO_OUTPUT) {
593 if (fimc_ctx_state_is_set(FIMC_CTX_M2M, ctx))
594 frame = &ctx->s_frame;
595 else
596 return ERR_PTR(-EINVAL);
597 } else if (type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE ||
598 type == V4L2_BUF_TYPE_VIDEO_CAPTURE) {
599 frame = &ctx->d_frame;
600 } else {
601 v4l2_err(ctx->fimc_dev->v4l2_dev,
602 "Wrong buffer/video queue type (%d)\n", type);
603 return ERR_PTR(-EINVAL);
604 }
605
606 return frame;
607 }
608
609 /* -----------------------------------------------------*/
610 /* fimc-core.c */
611 int fimc_vidioc_enum_fmt_mplane(struct file *file, void *priv,
612 struct v4l2_fmtdesc *f);
613 int fimc_ctrls_create(struct fimc_ctx *ctx);
614 void fimc_ctrls_delete(struct fimc_ctx *ctx);
615 void fimc_ctrls_activate(struct fimc_ctx *ctx, bool active);
616 void fimc_alpha_ctrl_update(struct fimc_ctx *ctx);
617 void __fimc_get_format(struct fimc_frame *frame, struct v4l2_format *f);
618 void fimc_adjust_mplane_format(struct fimc_fmt *fmt, u32 width, u32 height,
619 struct v4l2_pix_format_mplane *pix);
620 struct fimc_fmt *fimc_find_format(const u32 *pixelformat, const u32 *mbus_code,
621 unsigned int mask, int index);
622 struct fimc_fmt *fimc_get_format(unsigned int index);
623
624 int fimc_check_scaler_ratio(struct fimc_ctx *ctx, int sw, int sh,
625 int dw, int dh, int rotation);
626 int fimc_set_scaler_info(struct fimc_ctx *ctx);
627 int fimc_prepare_config(struct fimc_ctx *ctx, u32 flags);
628 int fimc_prepare_addr(struct fimc_ctx *ctx, struct vb2_buffer *vb,
629 struct fimc_frame *frame, struct fimc_addr *paddr);
630 void fimc_prepare_dma_offset(struct fimc_ctx *ctx, struct fimc_frame *f);
631 void fimc_set_yuv_order(struct fimc_ctx *ctx);
632 void fimc_capture_irq_handler(struct fimc_dev *fimc, int deq_buf);
633
634 int fimc_register_m2m_device(struct fimc_dev *fimc,
635 struct v4l2_device *v4l2_dev);
636 void fimc_unregister_m2m_device(struct fimc_dev *fimc);
637 int fimc_register_driver(void);
638 void fimc_unregister_driver(void);
639
640 #ifdef CONFIG_MFD_SYSCON
fimc_get_sysreg_regmap(struct device_node * node)641 static inline struct regmap * fimc_get_sysreg_regmap(struct device_node *node)
642 {
643 return syscon_regmap_lookup_by_phandle(node, "samsung,sysreg");
644 }
645 #else
646 #define fimc_get_sysreg_regmap(node) (NULL)
647 #endif
648
649 /* -----------------------------------------------------*/
650 /* fimc-m2m.c */
651 void fimc_m2m_job_finish(struct fimc_ctx *ctx, int vb_state);
652
653 /* -----------------------------------------------------*/
654 /* fimc-capture.c */
655 int fimc_initialize_capture_subdev(struct fimc_dev *fimc);
656 void fimc_unregister_capture_subdev(struct fimc_dev *fimc);
657 int fimc_capture_ctrls_create(struct fimc_dev *fimc);
658 void fimc_sensor_notify(struct v4l2_subdev *sd, unsigned int notification,
659 void *arg);
660 int fimc_capture_suspend(struct fimc_dev *fimc);
661 int fimc_capture_resume(struct fimc_dev *fimc);
662
663 /*
664 * Buffer list manipulation functions. Must be called with fimc.slock held.
665 */
666
667 /**
668 * fimc_active_queue_add - add buffer to the capture active buffers queue
669 * @buf: buffer to add to the active buffers list
670 */
fimc_active_queue_add(struct fimc_vid_cap * vid_cap,struct fimc_vid_buffer * buf)671 static inline void fimc_active_queue_add(struct fimc_vid_cap *vid_cap,
672 struct fimc_vid_buffer *buf)
673 {
674 list_add_tail(&buf->list, &vid_cap->active_buf_q);
675 vid_cap->active_buf_cnt++;
676 }
677
678 /**
679 * fimc_active_queue_pop - pop buffer from the capture active buffers queue
680 *
681 * The caller must assure the active_buf_q list is not empty.
682 */
fimc_active_queue_pop(struct fimc_vid_cap * vid_cap)683 static inline struct fimc_vid_buffer *fimc_active_queue_pop(
684 struct fimc_vid_cap *vid_cap)
685 {
686 struct fimc_vid_buffer *buf;
687 buf = list_entry(vid_cap->active_buf_q.next,
688 struct fimc_vid_buffer, list);
689 list_del(&buf->list);
690 vid_cap->active_buf_cnt--;
691 return buf;
692 }
693
694 /**
695 * fimc_pending_queue_add - add buffer to the capture pending buffers queue
696 * @buf: buffer to add to the pending buffers list
697 */
fimc_pending_queue_add(struct fimc_vid_cap * vid_cap,struct fimc_vid_buffer * buf)698 static inline void fimc_pending_queue_add(struct fimc_vid_cap *vid_cap,
699 struct fimc_vid_buffer *buf)
700 {
701 list_add_tail(&buf->list, &vid_cap->pending_buf_q);
702 }
703
704 /**
705 * fimc_pending_queue_pop - pop buffer from the capture pending buffers queue
706 *
707 * The caller must assure the pending_buf_q list is not empty.
708 */
fimc_pending_queue_pop(struct fimc_vid_cap * vid_cap)709 static inline struct fimc_vid_buffer *fimc_pending_queue_pop(
710 struct fimc_vid_cap *vid_cap)
711 {
712 struct fimc_vid_buffer *buf;
713 buf = list_entry(vid_cap->pending_buf_q.next,
714 struct fimc_vid_buffer, list);
715 list_del(&buf->list);
716 return buf;
717 }
718
719 #endif /* FIMC_CORE_H_ */
720