1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Support for Intel Camera Imaging ISP subsystem. 4 * Copyright (c) 2015, Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 */ 15 16 #ifndef _IA_CSS_ACC_TYPES_H 17 #define _IA_CSS_ACC_TYPES_H 18 19 /* @file 20 * This file contains types used for acceleration 21 */ 22 23 #include <system_local.h> /* HAS_IRQ_MAP_VERSION_# */ 24 #include <type_support.h> 25 #include <platform_support.h> 26 #include <debug_global.h> 27 28 #include "ia_css_types.h" 29 #include "ia_css_frame_format.h" 30 31 /* Should be included without the path. 32 However, that requires adding the path to numerous makefiles 33 that have nothing to do with isp parameters. 34 */ 35 #include "runtime/isp_param/interface/ia_css_isp_param_types.h" 36 37 /* Types for the acceleration API. 38 * These should be moved to sh_css_internal.h once the old acceleration 39 * argument handling has been completed. 40 * After that, interpretation of these structures is no longer needed 41 * in the kernel and HAL. 42 */ 43 44 /* Type of acceleration. 45 */ 46 enum ia_css_acc_type { 47 IA_CSS_ACC_NONE, /** Normal binary */ 48 IA_CSS_ACC_OUTPUT, /** Accelerator stage on output frame */ 49 IA_CSS_ACC_VIEWFINDER, /** Accelerator stage on viewfinder frame */ 50 IA_CSS_ACC_STANDALONE, /** Stand-alone acceleration */ 51 }; 52 53 /* Cells types 54 */ 55 enum ia_css_cell_type { 56 IA_CSS_SP0 = 0, 57 IA_CSS_SP1, 58 IA_CSS_ISP, 59 MAX_NUM_OF_CELLS 60 }; 61 62 /* Firmware types. 63 */ 64 enum ia_css_fw_type { 65 ia_css_sp_firmware, /** Firmware for the SP */ 66 ia_css_isp_firmware, /** Firmware for the ISP */ 67 ia_css_bootloader_firmware, /** Firmware for the BootLoader */ 68 ia_css_acc_firmware /** Firmware for accelrations */ 69 }; 70 71 struct ia_css_blob_descr; 72 73 /* Blob descriptor. 74 * This structure describes an SP or ISP blob. 75 * It describes the test, data and bss sections as well as position in a 76 * firmware file. 77 * For convenience, it contains dynamic data after loading. 78 */ 79 struct ia_css_blob_info { 80 /** Static blob data */ 81 u32 offset; /** Blob offset in fw file */ 82 struct ia_css_isp_param_memory_offsets 83 memory_offsets; /** offset wrt hdr in bytes */ 84 u32 prog_name_offset; /** offset wrt hdr in bytes */ 85 u32 size; /** Size of blob */ 86 u32 padding_size; /** total cummulative of bytes added due to section alignment */ 87 u32 icache_source; /** Position of icache in blob */ 88 u32 icache_size; /** Size of icache section */ 89 u32 icache_padding;/** bytes added due to icache section alignment */ 90 u32 text_source; /** Position of text in blob */ 91 u32 text_size; /** Size of text section */ 92 u32 text_padding; /** bytes added due to text section alignment */ 93 u32 data_source; /** Position of data in blob */ 94 u32 data_target; /** Start of data in SP dmem */ 95 u32 data_size; /** Size of text section */ 96 u32 data_padding; /** bytes added due to data section alignment */ 97 u32 bss_target; /** Start position of bss in SP dmem */ 98 u32 bss_size; /** Size of bss section */ 99 /** Dynamic data filled by loader */ 100 CSS_ALIGN(const void *code, 101 8); /** Code section absolute pointer within fw, code = icache + text */ 102 CSS_ALIGN(const void *data, 103 8); /** Data section absolute pointer within fw, data = data + bss */ 104 }; 105 106 struct ia_css_binary_input_info { 107 u32 min_width; 108 u32 min_height; 109 u32 max_width; 110 u32 max_height; 111 u32 source; /* memory, sensor, variable */ 112 }; 113 114 struct ia_css_binary_output_info { 115 u32 min_width; 116 u32 min_height; 117 u32 max_width; 118 u32 max_height; 119 u32 num_chunks; 120 u32 variable_format; 121 }; 122 123 struct ia_css_binary_internal_info { 124 u32 max_width; 125 u32 max_height; 126 }; 127 128 struct ia_css_binary_bds_info { 129 u32 supported_bds_factors; 130 }; 131 132 struct ia_css_binary_dvs_info { 133 u32 max_envelope_width; 134 u32 max_envelope_height; 135 }; 136 137 struct ia_css_binary_vf_dec_info { 138 u32 is_variable; 139 u32 max_log_downscale; 140 }; 141 142 struct ia_css_binary_s3a_info { 143 u32 s3atbl_use_dmem; 144 u32 fixed_s3a_deci_log; 145 }; 146 147 /* DPC related binary info */ 148 struct ia_css_binary_dpc_info { 149 u32 bnr_lite; /** bnr lite enable flag */ 150 }; 151 152 struct ia_css_binary_iterator_info { 153 u32 num_stripes; 154 u32 row_stripes_height; 155 u32 row_stripes_overlap_lines; 156 }; 157 158 struct ia_css_binary_address_info { 159 u32 isp_addresses; /* Address in ISP dmem */ 160 u32 main_entry; /* Address of entry fct */ 161 u32 in_frame; /* Address in ISP dmem */ 162 u32 out_frame; /* Address in ISP dmem */ 163 u32 in_data; /* Address in ISP dmem */ 164 u32 out_data; /* Address in ISP dmem */ 165 u32 sh_dma_cmd_ptr; /* In ISP dmem */ 166 }; 167 168 struct ia_css_binary_uds_info { 169 u16 bpp; 170 u16 use_bci; 171 u16 use_str; 172 u16 woix; 173 u16 woiy; 174 u16 extra_out_vecs; 175 u16 vectors_per_line_in; 176 u16 vectors_per_line_out; 177 u16 vectors_c_per_line_in; 178 u16 vectors_c_per_line_out; 179 u16 vmem_gdc_in_block_height_y; 180 u16 vmem_gdc_in_block_height_c; 181 /* uint16_t padding; */ 182 }; 183 184 struct ia_css_binary_pipeline_info { 185 u32 mode; 186 u32 isp_pipe_version; 187 u32 pipelining; 188 u32 c_subsampling; 189 u32 top_cropping; 190 u32 left_cropping; 191 u32 variable_resolution; 192 }; 193 194 struct ia_css_binary_block_info { 195 u32 block_width; 196 u32 block_height; 197 u32 output_block_height; 198 }; 199 200 /* Structure describing an ISP binary. 201 * It describes the capabilities of a binary, like the maximum resolution, 202 * support features, dma channels, uds features, etc. 203 * This part is to be used by the SP. 204 * Future refactoring should move binary properties to ia_css_binary_xinfo, 205 * thereby making the SP code more binary independent. 206 */ 207 struct ia_css_binary_info { 208 CSS_ALIGN(u32 id, 8); /* IA_CSS_BINARY_ID_* */ 209 struct ia_css_binary_pipeline_info pipeline; 210 struct ia_css_binary_input_info input; 211 struct ia_css_binary_output_info output; 212 struct ia_css_binary_internal_info internal; 213 struct ia_css_binary_bds_info bds; 214 struct ia_css_binary_dvs_info dvs; 215 struct ia_css_binary_vf_dec_info vf_dec; 216 struct ia_css_binary_s3a_info s3a; 217 struct ia_css_binary_dpc_info dpc_bnr; /** DPC related binary info */ 218 struct ia_css_binary_iterator_info iterator; 219 struct ia_css_binary_address_info addresses; 220 struct ia_css_binary_uds_info uds; 221 struct ia_css_binary_block_info block; 222 struct ia_css_isp_param_isp_segments mem_initializers; 223 /* MW: Packing (related) bools in an integer ?? */ 224 struct { 225 /* ISP2401 */ 226 u8 luma_only; 227 u8 input_yuv; 228 u8 input_raw; 229 230 u8 reduced_pipe; 231 u8 vf_veceven; 232 u8 dis; 233 u8 dvs_envelope; 234 u8 uds; 235 u8 dvs_6axis; 236 u8 block_output; 237 u8 streaming_dma; 238 u8 ds; 239 u8 bayer_fir_6db; 240 u8 raw_binning; 241 u8 continuous; 242 u8 s3a; 243 u8 fpnr; 244 u8 sc; 245 u8 macc; 246 u8 output; 247 u8 ref_frame; 248 u8 tnr; 249 u8 xnr; 250 u8 params; 251 u8 ca_gdc; 252 u8 isp_addresses; 253 u8 in_frame; 254 u8 out_frame; 255 u8 high_speed; 256 u8 dpc; 257 u8 padding[2]; 258 } enable; 259 struct { 260 /* DMA channel ID: [0,...,HIVE_ISP_NUM_DMA_CHANNELS> */ 261 u8 ref_y_channel; 262 u8 ref_c_channel; 263 u8 tnr_channel; 264 u8 tnr_out_channel; 265 u8 dvs_coords_channel; 266 u8 output_channel; 267 u8 c_channel; 268 u8 vfout_channel; 269 u8 vfout_c_channel; 270 u8 vfdec_bits_per_pixel; 271 u8 claimed_by_isp; 272 u8 padding[2]; 273 } dma; 274 }; 275 276 /* Structure describing an ISP binary. 277 * It describes the capabilities of a binary, like the maximum resolution, 278 * support features, dma channels, uds features, etc. 279 */ 280 struct ia_css_binary_xinfo { 281 /* Part that is of interest to the SP. */ 282 struct ia_css_binary_info sp; 283 284 /* Rest of the binary info, only interesting to the host. */ 285 enum ia_css_acc_type type; 286 287 CSS_ALIGN(s32 num_output_formats, 8); 288 enum ia_css_frame_format output_formats[IA_CSS_FRAME_FORMAT_NUM]; 289 290 CSS_ALIGN(s32 num_vf_formats, 8); /** number of supported vf formats */ 291 enum ia_css_frame_format 292 vf_formats[IA_CSS_FRAME_FORMAT_NUM]; /** types of supported vf formats */ 293 u8 num_output_pins; 294 ia_css_ptr xmem_addr; 295 296 CSS_ALIGN(const struct ia_css_blob_descr *blob, 8); 297 CSS_ALIGN(u32 blob_index, 8); 298 CSS_ALIGN(union ia_css_all_memory_offsets mem_offsets, 8); 299 CSS_ALIGN(struct ia_css_binary_xinfo *next, 8); 300 }; 301 302 /* Structure describing the Bootloader (an ISP binary). 303 * It contains several address, either in ddr, isp_dmem or 304 * the entry function in icache. 305 */ 306 struct ia_css_bl_info { 307 u32 num_dma_cmds; /** Number of cmds sent by CSS */ 308 u32 dma_cmd_list; /** Dma command list sent by CSS */ 309 u32 sw_state; /** Polled from css */ 310 /* Entry functions */ 311 u32 bl_entry; /** The SP entry function */ 312 }; 313 314 /* Structure describing the SP binary. 315 * It contains several address, either in ddr, sp_dmem or 316 * the entry function in pmem. 317 */ 318 struct ia_css_sp_info { 319 u32 init_dmem_data; /** data sect config, stored to dmem */ 320 u32 per_frame_data; /** Per frame data, stored to dmem */ 321 u32 group; /** Per pipeline data, loaded by dma */ 322 u32 output; /** SP output data, loaded by dmem */ 323 u32 host_sp_queue; /** Host <-> SP queues */ 324 u32 host_sp_com;/** Host <-> SP commands */ 325 u32 isp_started; /** Polled from sensor thread, csim only */ 326 u32 sw_state; /** Polled from css */ 327 u32 host_sp_queues_initialized; /** Polled from the SP */ 328 u32 sleep_mode; /** different mode to halt SP */ 329 u32 invalidate_tlb; /** inform SP to invalidate mmu TLB */ 330 331 /* ISP2400 */ 332 u32 stop_copy_preview; /** suspend copy and preview pipe when capture */ 333 334 u32 debug_buffer_ddr_address; /** inform SP the address 335 of DDR debug queue */ 336 u32 perf_counter_input_system_error; /** input system perf 337 counter array */ 338 #ifdef HAS_WATCHDOG_SP_THREAD_DEBUG 339 u32 debug_wait; /** thread/pipe post mortem debug */ 340 u32 debug_stage; /** thread/pipe post mortem debug */ 341 u32 debug_stripe; /** thread/pipe post mortem debug */ 342 #endif 343 u32 threads_stack; /** sp thread's stack pointers */ 344 u32 threads_stack_size; /** sp thread's stack sizes */ 345 u32 curr_binary_id; /** current binary id */ 346 u32 raw_copy_line_count; /** raw copy line counter */ 347 u32 ddr_parameter_address; /** acc param ddrptr, sp dmem */ 348 u32 ddr_parameter_size; /** acc param size, sp dmem */ 349 /* Entry functions */ 350 u32 sp_entry; /** The SP entry function */ 351 u32 tagger_frames_addr; /** Base address of tagger state */ 352 }; 353 354 /* The following #if is there because this header file is also included 355 by SP and ISP code but they do not need this data and HIVECC has alignment 356 issue with the firmware struct/union's. 357 More permanent solution will be to refactor this include. 358 */ 359 360 /* Accelerator firmware information. 361 */ 362 struct ia_css_acc_info { 363 u32 per_frame_data; /** Dummy for now */ 364 }; 365 366 /* Firmware information. 367 */ 368 union ia_css_fw_union { 369 struct ia_css_binary_xinfo isp; /** ISP info */ 370 struct ia_css_sp_info sp; /** SP info */ 371 struct ia_css_bl_info bl; /** Bootloader info */ 372 struct ia_css_acc_info acc; /** Accelerator info */ 373 }; 374 375 /* Firmware information. 376 */ 377 struct ia_css_fw_info { 378 size_t header_size; /** size of fw header */ 379 380 CSS_ALIGN(u32 type, 8); 381 union ia_css_fw_union info; /** Binary info */ 382 struct ia_css_blob_info blob; /** Blob info */ 383 /* Dynamic part */ 384 struct ia_css_fw_info *next; 385 386 CSS_ALIGN(u32 loaded, 8); /** Firmware has been loaded */ 387 CSS_ALIGN(const u8 *isp_code, 8); /** ISP pointer to code */ 388 /** Firmware handle between user space and kernel */ 389 CSS_ALIGN(u32 handle, 8); 390 /** Sections to copy from/to ISP */ 391 struct ia_css_isp_param_css_segments mem_initializers; 392 /** Initializer for local ISP memories */ 393 }; 394 395 struct ia_css_blob_descr { 396 const unsigned char *blob; 397 struct ia_css_fw_info header; 398 const char *name; 399 union ia_css_all_memory_offsets mem_offsets; 400 }; 401 402 struct ia_css_acc_fw; 403 404 /* Structure describing the SP binary of a stand-alone accelerator. 405 */ 406 struct ia_css_acc_sp { 407 void (*init)(struct ia_css_acc_fw *); /** init for crun */ 408 u32 sp_prog_name_offset; /** program name offset wrt hdr in bytes */ 409 u32 sp_blob_offset; /** blob offset wrt hdr in bytes */ 410 void *entry; /** Address of sp entry point */ 411 u32 *css_abort; /** SP dmem abort flag */ 412 void *isp_code; /** SP dmem address holding xmem 413 address of isp code */ 414 struct ia_css_fw_info fw; /** SP fw descriptor */ 415 const u8 *code; /** ISP pointer of allocated SP code */ 416 }; 417 418 /* Acceleration firmware descriptor. 419 * This descriptor descibes either SP code (stand-alone), or 420 * ISP code (a separate pipeline stage). 421 */ 422 struct ia_css_acc_fw_hdr { 423 enum ia_css_acc_type type; /** Type of accelerator */ 424 u32 isp_prog_name_offset; /** program name offset wrt 425 header in bytes */ 426 u32 isp_blob_offset; /** blob offset wrt header 427 in bytes */ 428 u32 isp_size; /** Size of isp blob */ 429 const u8 *isp_code; /** ISP pointer to code */ 430 struct ia_css_acc_sp sp; /** Standalone sp code */ 431 /** Firmware handle between user space and kernel */ 432 u32 handle; 433 struct ia_css_data parameters; /** Current SP parameters */ 434 }; 435 436 /* Firmware structure. 437 * This contains the header and actual blobs. 438 * For standalone, it contains SP and ISP blob. 439 * For a pipeline stage accelerator, it contains ISP code only. 440 * Since its members are variable size, their offsets are described in the 441 * header and computed using the access macros below. 442 */ 443 struct ia_css_acc_fw { 444 struct ia_css_acc_fw_hdr header; /** firmware header */ 445 /* 446 int8_t isp_progname[]; **< ISP program name 447 int8_t sp_progname[]; **< SP program name, stand-alone only 448 uint8_t sp_code[]; **< SP blob, stand-alone only 449 uint8_t isp_code[]; **< ISP blob 450 */ 451 }; 452 453 /* Access macros for firmware */ 454 #define IA_CSS_ACC_OFFSET(t, f, n) ((t)((uint8_t *)(f) + (f->header.n))) 455 #define IA_CSS_ACC_SP_PROG_NAME(f) IA_CSS_ACC_OFFSET(const char *, f, \ 456 sp.sp_prog_name_offset) 457 #define IA_CSS_ACC_ISP_PROG_NAME(f) IA_CSS_ACC_OFFSET(const char *, f, \ 458 isp_prog_name_offset) 459 #define IA_CSS_ACC_SP_CODE(f) IA_CSS_ACC_OFFSET(uint8_t *, f, \ 460 sp.sp_blob_offset) 461 #define IA_CSS_ACC_SP_DATA(f) (IA_CSS_ACC_SP_CODE(f) + \ 462 (f)->header.sp.fw.blob.data_source) 463 #define IA_CSS_ACC_ISP_CODE(f) IA_CSS_ACC_OFFSET(uint8_t*, f,\ 464 isp_blob_offset) 465 #define IA_CSS_ACC_ISP_SIZE(f) ((f)->header.isp_size) 466 467 /* Binary name follows header immediately */ 468 #define IA_CSS_EXT_ISP_PROG_NAME(f) ((const char *)(f) + (f)->blob.prog_name_offset) 469 #define IA_CSS_EXT_ISP_MEM_OFFSETS(f) \ 470 ((const struct ia_css_memory_offsets *)((const char *)(f) + (f)->blob.mem_offsets)) 471 472 enum ia_css_sp_sleep_mode { 473 SP_DISABLE_SLEEP_MODE = 0, 474 SP_SLEEP_AFTER_FRAME = 1 << 0, 475 SP_SLEEP_AFTER_IRQ = 1 << 1 476 }; 477 #endif /* _IA_CSS_ACC_TYPES_H */ 478