1 /* 2 * Copyright © 2016-2019 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 */ 23 24 /* 25 * Please use intel_vbt_defs.h for VBT private data, to hide and abstract away 26 * the VBT from the rest of the driver. Add the parsed, clean data to struct 27 * intel_vbt_data within struct drm_i915_private. 28 */ 29 30 #ifndef _INTEL_BIOS_H_ 31 #define _INTEL_BIOS_H_ 32 33 #include <linux/types.h> 34 35 struct drm_i915_private; 36 struct intel_crtc_state; 37 struct intel_encoder; 38 enum port; 39 40 enum intel_backlight_type { 41 INTEL_BACKLIGHT_PMIC, 42 INTEL_BACKLIGHT_LPSS, 43 INTEL_BACKLIGHT_DISPLAY_DDI, 44 INTEL_BACKLIGHT_DSI_DCS, 45 INTEL_BACKLIGHT_PANEL_DRIVER_INTERFACE, 46 INTEL_BACKLIGHT_VESA_EDP_AUX_INTERFACE, 47 }; 48 49 struct edp_power_seq { 50 u16 t1_t3; 51 u16 t8; 52 u16 t9; 53 u16 t10; 54 u16 t11_t12; 55 } __packed; 56 57 /* 58 * MIPI Sequence Block definitions 59 * 60 * Note the VBT spec has AssertReset / DeassertReset swapped from their 61 * usual naming, we use the proper names here to avoid confusion when 62 * reading the code. 63 */ 64 enum mipi_seq { 65 MIPI_SEQ_END = 0, 66 MIPI_SEQ_DEASSERT_RESET, /* Spec says MipiAssertResetPin */ 67 MIPI_SEQ_INIT_OTP, 68 MIPI_SEQ_DISPLAY_ON, 69 MIPI_SEQ_DISPLAY_OFF, 70 MIPI_SEQ_ASSERT_RESET, /* Spec says MipiDeassertResetPin */ 71 MIPI_SEQ_BACKLIGHT_ON, /* sequence block v2+ */ 72 MIPI_SEQ_BACKLIGHT_OFF, /* sequence block v2+ */ 73 MIPI_SEQ_TEAR_ON, /* sequence block v2+ */ 74 MIPI_SEQ_TEAR_OFF, /* sequence block v3+ */ 75 MIPI_SEQ_POWER_ON, /* sequence block v3+ */ 76 MIPI_SEQ_POWER_OFF, /* sequence block v3+ */ 77 MIPI_SEQ_MAX 78 }; 79 80 enum mipi_seq_element { 81 MIPI_SEQ_ELEM_END = 0, 82 MIPI_SEQ_ELEM_SEND_PKT, 83 MIPI_SEQ_ELEM_DELAY, 84 MIPI_SEQ_ELEM_GPIO, 85 MIPI_SEQ_ELEM_I2C, /* sequence block v2+ */ 86 MIPI_SEQ_ELEM_SPI, /* sequence block v3+ */ 87 MIPI_SEQ_ELEM_PMIC, /* sequence block v3+ */ 88 MIPI_SEQ_ELEM_MAX 89 }; 90 91 #define MIPI_DSI_UNDEFINED_PANEL_ID 0 92 #define MIPI_DSI_GENERIC_PANEL_ID 1 93 94 struct mipi_config { 95 u16 panel_id; 96 97 /* General Params */ 98 u32 enable_dithering:1; 99 u32 rsvd1:1; 100 u32 is_bridge:1; 101 102 u32 panel_arch_type:2; 103 u32 is_cmd_mode:1; 104 105 #define NON_BURST_SYNC_PULSE 0x1 106 #define NON_BURST_SYNC_EVENTS 0x2 107 #define BURST_MODE 0x3 108 u32 video_transfer_mode:2; 109 110 u32 cabc_supported:1; 111 #define PPS_BLC_PMIC 0 112 #define PPS_BLC_SOC 1 113 u32 pwm_blc:1; 114 115 /* Bit 13:10 */ 116 #define PIXEL_FORMAT_RGB565 0x1 117 #define PIXEL_FORMAT_RGB666 0x2 118 #define PIXEL_FORMAT_RGB666_LOOSELY_PACKED 0x3 119 #define PIXEL_FORMAT_RGB888 0x4 120 u32 videomode_color_format:4; 121 122 /* Bit 15:14 */ 123 #define ENABLE_ROTATION_0 0x0 124 #define ENABLE_ROTATION_90 0x1 125 #define ENABLE_ROTATION_180 0x2 126 #define ENABLE_ROTATION_270 0x3 127 u32 rotation:2; 128 u32 bta_enabled:1; 129 u32 rsvd2:15; 130 131 /* 2 byte Port Description */ 132 #define DUAL_LINK_NOT_SUPPORTED 0 133 #define DUAL_LINK_FRONT_BACK 1 134 #define DUAL_LINK_PIXEL_ALT 2 135 u16 dual_link:2; 136 u16 lane_cnt:2; 137 u16 pixel_overlap:3; 138 u16 rgb_flip:1; 139 #define DL_DCS_PORT_A 0x00 140 #define DL_DCS_PORT_C 0x01 141 #define DL_DCS_PORT_A_AND_C 0x02 142 u16 dl_dcs_cabc_ports:2; 143 u16 dl_dcs_backlight_ports:2; 144 u16 rsvd3:4; 145 146 u16 rsvd4; 147 148 u8 rsvd5; 149 u32 target_burst_mode_freq; 150 u32 dsi_ddr_clk; 151 u32 bridge_ref_clk; 152 153 #define BYTE_CLK_SEL_20MHZ 0 154 #define BYTE_CLK_SEL_10MHZ 1 155 #define BYTE_CLK_SEL_5MHZ 2 156 u8 byte_clk_sel:2; 157 158 u8 rsvd6:6; 159 160 /* DPHY Flags */ 161 u16 dphy_param_valid:1; 162 u16 eot_pkt_disabled:1; 163 u16 enable_clk_stop:1; 164 u16 rsvd7:13; 165 166 u32 hs_tx_timeout; 167 u32 lp_rx_timeout; 168 u32 turn_around_timeout; 169 u32 device_reset_timer; 170 u32 master_init_timer; 171 u32 dbi_bw_timer; 172 u32 lp_byte_clk_val; 173 174 /* 4 byte Dphy Params */ 175 u32 prepare_cnt:6; 176 u32 rsvd8:2; 177 u32 clk_zero_cnt:8; 178 u32 trail_cnt:5; 179 u32 rsvd9:3; 180 u32 exit_zero_cnt:6; 181 u32 rsvd10:2; 182 183 u32 clk_lane_switch_cnt; 184 u32 hl_switch_cnt; 185 186 u32 rsvd11[6]; 187 188 /* timings based on dphy spec */ 189 u8 tclk_miss; 190 u8 tclk_post; 191 u8 rsvd12; 192 u8 tclk_pre; 193 u8 tclk_prepare; 194 u8 tclk_settle; 195 u8 tclk_term_enable; 196 u8 tclk_trail; 197 u16 tclk_prepare_clkzero; 198 u8 rsvd13; 199 u8 td_term_enable; 200 u8 teot; 201 u8 ths_exit; 202 u8 ths_prepare; 203 u16 ths_prepare_hszero; 204 u8 rsvd14; 205 u8 ths_settle; 206 u8 ths_skip; 207 u8 ths_trail; 208 u8 tinit; 209 u8 tlpx; 210 u8 rsvd15[3]; 211 212 /* GPIOs */ 213 u8 panel_enable; 214 u8 bl_enable; 215 u8 pwm_enable; 216 u8 reset_r_n; 217 u8 pwr_down_r; 218 u8 stdby_r_n; 219 220 } __packed; 221 222 /* all delays have a unit of 100us */ 223 struct mipi_pps_data { 224 u16 panel_on_delay; 225 u16 bl_enable_delay; 226 u16 bl_disable_delay; 227 u16 panel_off_delay; 228 u16 panel_power_cycle_delay; 229 } __packed; 230 231 void intel_bios_init(struct drm_i915_private *dev_priv); 232 void intel_bios_driver_remove(struct drm_i915_private *dev_priv); 233 bool intel_bios_is_valid_vbt(const void *buf, size_t size); 234 bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv); 235 bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin); 236 bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port); 237 bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port); 238 bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv, enum port port); 239 bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, enum port *port); 240 bool intel_bios_is_port_hpd_inverted(const struct drm_i915_private *i915, 241 enum port port); 242 bool intel_bios_is_lspcon_present(const struct drm_i915_private *i915, 243 enum port port); 244 enum aux_ch intel_bios_port_aux_ch(struct drm_i915_private *dev_priv, enum port port); 245 bool intel_bios_get_dsc_params(struct intel_encoder *encoder, 246 struct intel_crtc_state *crtc_state, 247 int dsc_max_bpc); 248 int intel_bios_max_tmds_clock(struct intel_encoder *encoder); 249 int intel_bios_hdmi_level_shift(struct intel_encoder *encoder); 250 int intel_bios_dp_boost_level(struct intel_encoder *encoder); 251 int intel_bios_hdmi_boost_level(struct intel_encoder *encoder); 252 int intel_bios_dp_max_link_rate(struct intel_encoder *encoder); 253 int intel_bios_alternate_ddc_pin(struct intel_encoder *encoder); 254 bool intel_bios_port_supports_dvi(struct drm_i915_private *i915, enum port port); 255 bool intel_bios_port_supports_hdmi(struct drm_i915_private *i915, enum port port); 256 bool intel_bios_port_supports_dp(struct drm_i915_private *i915, enum port port); 257 bool intel_bios_port_supports_typec_usb(struct drm_i915_private *i915, enum port port); 258 bool intel_bios_port_supports_tbt(struct drm_i915_private *i915, enum port port); 259 260 #endif /* _INTEL_BIOS_H_ */ 261