1 /*
2 * SPDX-License-Identifier: MIT
3 *
4 * Copyright � 2003-2018 Intel Corporation
5 */
6
7 #ifndef _INTEL_GPU_COMMANDS_H_
8 #define _INTEL_GPU_COMMANDS_H_
9
10 #include <linux/bitops.h>
11
12 /*
13 * Target address alignments required for GPU access e.g.
14 * MI_STORE_DWORD_IMM.
15 */
16 #define alignof_dword 4
17 #define alignof_qword 8
18
19 /*
20 * Instruction field definitions used by the command parser
21 */
22 #define INSTR_CLIENT_SHIFT 29
23 #define INSTR_MI_CLIENT 0x0
24 #define INSTR_BC_CLIENT 0x2
25 #define INSTR_RC_CLIENT 0x3
26 #define INSTR_SUBCLIENT_SHIFT 27
27 #define INSTR_SUBCLIENT_MASK 0x18000000
28 #define INSTR_MEDIA_SUBCLIENT 0x2
29 #define INSTR_26_TO_24_MASK 0x7000000
30 #define INSTR_26_TO_24_SHIFT 24
31
32 /*
33 * Memory interface instructions used by the kernel
34 */
35 #define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
36 /* Many MI commands use bit 22 of the header dword for GGTT vs PPGTT */
37 #define MI_GLOBAL_GTT (1<<22)
38
39 #define MI_NOOP MI_INSTR(0, 0)
40 #define MI_USER_INTERRUPT MI_INSTR(0x02, 0)
41 #define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0)
42 #define MI_WAIT_FOR_OVERLAY_FLIP (1<<16)
43 #define MI_WAIT_FOR_PLANE_B_FLIP (1<<6)
44 #define MI_WAIT_FOR_PLANE_A_FLIP (1<<2)
45 #define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
46 #define MI_FLUSH MI_INSTR(0x04, 0)
47 #define MI_READ_FLUSH (1 << 0)
48 #define MI_EXE_FLUSH (1 << 1)
49 #define MI_NO_WRITE_FLUSH (1 << 2)
50 #define MI_SCENE_COUNT (1 << 3) /* just increment scene count */
51 #define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */
52 #define MI_INVALIDATE_ISP (1 << 5) /* invalidate indirect state pointers */
53 #define MI_REPORT_HEAD MI_INSTR(0x07, 0)
54 #define MI_ARB_ON_OFF MI_INSTR(0x08, 0)
55 #define MI_ARB_ENABLE (1<<0)
56 #define MI_ARB_DISABLE (0<<0)
57 #define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0)
58 #define MI_SUSPEND_FLUSH MI_INSTR(0x0b, 0)
59 #define MI_SUSPEND_FLUSH_EN (1<<0)
60 #define MI_SET_APPID MI_INSTR(0x0e, 0)
61 #define MI_OVERLAY_FLIP MI_INSTR(0x11, 0)
62 #define MI_OVERLAY_CONTINUE (0x0<<21)
63 #define MI_OVERLAY_ON (0x1<<21)
64 #define MI_OVERLAY_OFF (0x2<<21)
65 #define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0)
66 #define MI_DISPLAY_FLIP MI_INSTR(0x14, 2)
67 #define MI_DISPLAY_FLIP_I915 MI_INSTR(0x14, 1)
68 #define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20)
69 /* IVB has funny definitions for which plane to flip. */
70 #define MI_DISPLAY_FLIP_IVB_PLANE_A (0 << 19)
71 #define MI_DISPLAY_FLIP_IVB_PLANE_B (1 << 19)
72 #define MI_DISPLAY_FLIP_IVB_SPRITE_A (2 << 19)
73 #define MI_DISPLAY_FLIP_IVB_SPRITE_B (3 << 19)
74 #define MI_DISPLAY_FLIP_IVB_PLANE_C (4 << 19)
75 #define MI_DISPLAY_FLIP_IVB_SPRITE_C (5 << 19)
76 /* SKL ones */
77 #define MI_DISPLAY_FLIP_SKL_PLANE_1_A (0 << 8)
78 #define MI_DISPLAY_FLIP_SKL_PLANE_1_B (1 << 8)
79 #define MI_DISPLAY_FLIP_SKL_PLANE_1_C (2 << 8)
80 #define MI_DISPLAY_FLIP_SKL_PLANE_2_A (4 << 8)
81 #define MI_DISPLAY_FLIP_SKL_PLANE_2_B (5 << 8)
82 #define MI_DISPLAY_FLIP_SKL_PLANE_2_C (6 << 8)
83 #define MI_DISPLAY_FLIP_SKL_PLANE_3_A (7 << 8)
84 #define MI_DISPLAY_FLIP_SKL_PLANE_3_B (8 << 8)
85 #define MI_DISPLAY_FLIP_SKL_PLANE_3_C (9 << 8)
86 #define MI_SEMAPHORE_MBOX MI_INSTR(0x16, 1) /* gen6, gen7 */
87 #define MI_SEMAPHORE_GLOBAL_GTT (1<<22)
88 #define MI_SEMAPHORE_UPDATE (1<<21)
89 #define MI_SEMAPHORE_COMPARE (1<<20)
90 #define MI_SEMAPHORE_REGISTER (1<<18)
91 #define MI_SEMAPHORE_SYNC_VR (0<<16) /* RCS wait for VCS (RVSYNC) */
92 #define MI_SEMAPHORE_SYNC_VER (1<<16) /* RCS wait for VECS (RVESYNC) */
93 #define MI_SEMAPHORE_SYNC_BR (2<<16) /* RCS wait for BCS (RBSYNC) */
94 #define MI_SEMAPHORE_SYNC_BV (0<<16) /* VCS wait for BCS (VBSYNC) */
95 #define MI_SEMAPHORE_SYNC_VEV (1<<16) /* VCS wait for VECS (VVESYNC) */
96 #define MI_SEMAPHORE_SYNC_RV (2<<16) /* VCS wait for RCS (VRSYNC) */
97 #define MI_SEMAPHORE_SYNC_RB (0<<16) /* BCS wait for RCS (BRSYNC) */
98 #define MI_SEMAPHORE_SYNC_VEB (1<<16) /* BCS wait for VECS (BVESYNC) */
99 #define MI_SEMAPHORE_SYNC_VB (2<<16) /* BCS wait for VCS (BVSYNC) */
100 #define MI_SEMAPHORE_SYNC_BVE (0<<16) /* VECS wait for BCS (VEBSYNC) */
101 #define MI_SEMAPHORE_SYNC_VVE (1<<16) /* VECS wait for VCS (VEVSYNC) */
102 #define MI_SEMAPHORE_SYNC_RVE (2<<16) /* VECS wait for RCS (VERSYNC) */
103 #define MI_SEMAPHORE_SYNC_INVALID (3<<16)
104 #define MI_SEMAPHORE_SYNC_MASK (3<<16)
105 #define MI_SET_CONTEXT MI_INSTR(0x18, 0)
106 #define MI_MM_SPACE_GTT (1<<8)
107 #define MI_MM_SPACE_PHYSICAL (0<<8)
108 #define MI_SAVE_EXT_STATE_EN (1<<3)
109 #define MI_RESTORE_EXT_STATE_EN (1<<2)
110 #define MI_FORCE_RESTORE (1<<1)
111 #define MI_RESTORE_INHIBIT (1<<0)
112 #define HSW_MI_RS_SAVE_STATE_EN (1<<3)
113 #define HSW_MI_RS_RESTORE_STATE_EN (1<<2)
114 #define MI_SEMAPHORE_SIGNAL MI_INSTR(0x1b, 0) /* GEN8+ */
115 #define MI_SEMAPHORE_TARGET(engine) ((engine)<<15)
116 #define MI_SEMAPHORE_WAIT MI_INSTR(0x1c, 2) /* GEN8+ */
117 #define MI_SEMAPHORE_WAIT_TOKEN MI_INSTR(0x1c, 3) /* GEN12+ */
118 #define MI_SEMAPHORE_POLL (1 << 15)
119 #define MI_SEMAPHORE_SAD_GT_SDD (0 << 12)
120 #define MI_SEMAPHORE_SAD_GTE_SDD (1 << 12)
121 #define MI_SEMAPHORE_SAD_LT_SDD (2 << 12)
122 #define MI_SEMAPHORE_SAD_LTE_SDD (3 << 12)
123 #define MI_SEMAPHORE_SAD_EQ_SDD (4 << 12)
124 #define MI_SEMAPHORE_SAD_NEQ_SDD (5 << 12)
125 #define MI_SEMAPHORE_TOKEN_MASK REG_GENMASK(9, 5)
126 #define MI_SEMAPHORE_TOKEN_SHIFT 5
127 #define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1)
128 #define MI_STORE_DWORD_IMM_GEN4 MI_INSTR(0x20, 2)
129 #define MI_MEM_VIRTUAL (1 << 22) /* 945,g33,965 */
130 #define MI_USE_GGTT (1 << 22) /* g4x+ */
131 #define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1)
132 /*
133 * Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM:
134 * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw
135 * simply ignores the register load under certain conditions.
136 * - One can actually load arbitrary many arbitrary registers: Simply issue x
137 * address/value pairs. Don't overdue it, though, x <= 2^4 must hold!
138 */
139 #define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*(x)-1)
140 /* Gen11+. addr = base + (ctx_restore ? offset & GENMASK(12,2) : offset) */
141 #define MI_LRI_LRM_CS_MMIO REG_BIT(19)
142 #define MI_LRI_FORCE_POSTED (1<<12)
143 #define MI_LOAD_REGISTER_IMM_MAX_REGS (126)
144 #define MI_STORE_REGISTER_MEM MI_INSTR(0x24, 1)
145 #define MI_STORE_REGISTER_MEM_GEN8 MI_INSTR(0x24, 2)
146 #define MI_SRM_LRM_GLOBAL_GTT (1<<22)
147 #define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */
148 #define MI_FLUSH_DW_STORE_INDEX (1<<21)
149 #define MI_INVALIDATE_TLB (1<<18)
150 #define MI_FLUSH_DW_OP_STOREDW (1<<14)
151 #define MI_FLUSH_DW_OP_MASK (3<<14)
152 #define MI_FLUSH_DW_NOTIFY (1<<8)
153 #define MI_INVALIDATE_BSD (1<<7)
154 #define MI_FLUSH_DW_USE_GTT (1<<2)
155 #define MI_FLUSH_DW_USE_PPGTT (0<<2)
156 #define MI_LOAD_REGISTER_MEM MI_INSTR(0x29, 1)
157 #define MI_LOAD_REGISTER_MEM_GEN8 MI_INSTR(0x29, 2)
158 #define MI_LOAD_REGISTER_REG MI_INSTR(0x2A, 1)
159 #define MI_LRR_SOURCE_CS_MMIO REG_BIT(18)
160 #define MI_BATCH_BUFFER MI_INSTR(0x30, 1)
161 #define MI_BATCH_NON_SECURE (1)
162 /* for snb/ivb/vlv this also means "batch in ppgtt" when ppgtt is enabled. */
163 #define MI_BATCH_NON_SECURE_I965 (1<<8)
164 #define MI_BATCH_PPGTT_HSW (1<<8)
165 #define MI_BATCH_NON_SECURE_HSW (1<<13)
166 #define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0)
167 #define MI_BATCH_GTT (2<<6) /* aliased with (1<<7) on gen4 */
168 #define MI_BATCH_BUFFER_START_GEN8 MI_INSTR(0x31, 1)
169 #define MI_BATCH_RESOURCE_STREAMER REG_BIT(10)
170 #define MI_BATCH_PREDICATE REG_BIT(15) /* HSW+ on RCS only*/
171
172 /*
173 * 3D instructions used by the kernel
174 */
175 #define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags))
176
177 #define GEN9_MEDIA_POOL_STATE ((0x3 << 29) | (0x2 << 27) | (0x5 << 16) | 4)
178 #define GEN9_MEDIA_POOL_ENABLE (1 << 31)
179 #define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24))
180 #define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19))
181 #define SC_UPDATE_SCISSOR (0x1<<1)
182 #define SC_ENABLE_MASK (0x1<<0)
183 #define SC_ENABLE (0x1<<0)
184 #define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16))
185 #define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
186 #define SCI_YMIN_MASK (0xffff<<16)
187 #define SCI_XMIN_MASK (0xffff<<0)
188 #define SCI_YMAX_MASK (0xffff<<16)
189 #define SCI_XMAX_MASK (0xffff<<0)
190 #define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19))
191 #define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
192 #define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
193 #define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16))
194 #define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4)
195 #define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
196 #define GFX_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
197 #define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
198 #define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2)
199
200 #define COLOR_BLT_CMD (2 << 29 | 0x40 << 22 | (5 - 2))
201 #define XY_COLOR_BLT_CMD (2 << 29 | 0x50 << 22)
202 #define SRC_COPY_BLT_CMD (2 << 29 | 0x43 << 22)
203 #define GEN9_XY_FAST_COPY_BLT_CMD (2 << 29 | 0x42 << 22)
204 #define XY_SRC_COPY_BLT_CMD (2 << 29 | 0x53 << 22)
205 #define XY_MONO_SRC_COPY_IMM_BLT (2 << 29 | 0x71 << 22 | 5)
206 #define BLT_WRITE_A (2<<20)
207 #define BLT_WRITE_RGB (1<<20)
208 #define BLT_WRITE_RGBA (BLT_WRITE_RGB | BLT_WRITE_A)
209 #define BLT_DEPTH_8 (0<<24)
210 #define BLT_DEPTH_16_565 (1<<24)
211 #define BLT_DEPTH_16_1555 (2<<24)
212 #define BLT_DEPTH_32 (3<<24)
213 #define BLT_ROP_SRC_COPY (0xcc<<16)
214 #define BLT_ROP_COLOR_COPY (0xf0<<16)
215 #define XY_SRC_COPY_BLT_SRC_TILED (1<<15) /* 965+ only */
216 #define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */
217 #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
218 #define ASYNC_FLIP (1<<22)
219 #define DISPLAY_PLANE_A (0<<20)
220 #define DISPLAY_PLANE_B (1<<20)
221 #define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|((len)-2))
222 #define PIPE_CONTROL_COMMAND_CACHE_INVALIDATE (1<<29) /* gen11+ */
223 #define PIPE_CONTROL_TILE_CACHE_FLUSH (1<<28) /* gen11+ */
224 #define PIPE_CONTROL_FLUSH_L3 (1<<27)
225 #define PIPE_CONTROL_GLOBAL_GTT_IVB (1<<24) /* gen7+ */
226 #define PIPE_CONTROL_MMIO_WRITE (1<<23)
227 #define PIPE_CONTROL_STORE_DATA_INDEX (1<<21)
228 #define PIPE_CONTROL_CS_STALL (1<<20)
229 #define PIPE_CONTROL_TLB_INVALIDATE (1<<18)
230 #define PIPE_CONTROL_MEDIA_STATE_CLEAR (1<<16)
231 #define PIPE_CONTROL_WRITE_TIMESTAMP (3<<14)
232 #define PIPE_CONTROL_QW_WRITE (1<<14)
233 #define PIPE_CONTROL_POST_SYNC_OP_MASK (3<<14)
234 #define PIPE_CONTROL_DEPTH_STALL (1<<13)
235 #define PIPE_CONTROL_WRITE_FLUSH (1<<12)
236 #define PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH (1<<12) /* gen6+ */
237 #define PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE (1<<11) /* MBZ on ILK */
238 #define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (1<<10) /* GM45+ only */
239 #define PIPE_CONTROL_INDIRECT_STATE_DISABLE (1<<9)
240 #define PIPE_CONTROL0_HDC_PIPELINE_FLUSH REG_BIT(9) /* gen12 */
241 #define PIPE_CONTROL_NOTIFY (1<<8)
242 #define PIPE_CONTROL_FLUSH_ENABLE (1<<7) /* gen7+ */
243 #define PIPE_CONTROL_DC_FLUSH_ENABLE (1<<5)
244 #define PIPE_CONTROL_VF_CACHE_INVALIDATE (1<<4)
245 #define PIPE_CONTROL_CONST_CACHE_INVALIDATE (1<<3)
246 #define PIPE_CONTROL_STATE_CACHE_INVALIDATE (1<<2)
247 #define PIPE_CONTROL_STALL_AT_SCOREBOARD (1<<1)
248 #define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0)
249 #define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
250
251 #define MI_MATH(x) MI_INSTR(0x1a, (x) - 1)
252 #define MI_MATH_INSTR(opcode, op1, op2) ((opcode) << 20 | (op1) << 10 | (op2))
253 /* Opcodes for MI_MATH_INSTR */
254 #define MI_MATH_NOOP MI_MATH_INSTR(0x000, 0x0, 0x0)
255 #define MI_MATH_LOAD(op1, op2) MI_MATH_INSTR(0x080, op1, op2)
256 #define MI_MATH_LOADINV(op1, op2) MI_MATH_INSTR(0x480, op1, op2)
257 #define MI_MATH_LOAD0(op1) MI_MATH_INSTR(0x081, op1)
258 #define MI_MATH_LOAD1(op1) MI_MATH_INSTR(0x481, op1)
259 #define MI_MATH_ADD MI_MATH_INSTR(0x100, 0x0, 0x0)
260 #define MI_MATH_SUB MI_MATH_INSTR(0x101, 0x0, 0x0)
261 #define MI_MATH_AND MI_MATH_INSTR(0x102, 0x0, 0x0)
262 #define MI_MATH_OR MI_MATH_INSTR(0x103, 0x0, 0x0)
263 #define MI_MATH_XOR MI_MATH_INSTR(0x104, 0x0, 0x0)
264 #define MI_MATH_STORE(op1, op2) MI_MATH_INSTR(0x180, op1, op2)
265 #define MI_MATH_STOREINV(op1, op2) MI_MATH_INSTR(0x580, op1, op2)
266 /* Registers used as operands in MI_MATH_INSTR */
267 #define MI_MATH_REG(x) (x)
268 #define MI_MATH_REG_SRCA 0x20
269 #define MI_MATH_REG_SRCB 0x21
270 #define MI_MATH_REG_ACCU 0x31
271 #define MI_MATH_REG_ZF 0x32
272 #define MI_MATH_REG_CF 0x33
273
274 /*
275 * Commands used only by the command parser
276 */
277 #define MI_SET_PREDICATE MI_INSTR(0x01, 0)
278 #define MI_ARB_CHECK MI_INSTR(0x05, 0)
279 #define MI_RS_CONTROL MI_INSTR(0x06, 0)
280 #define MI_URB_ATOMIC_ALLOC MI_INSTR(0x09, 0)
281 #define MI_PREDICATE MI_INSTR(0x0C, 0)
282 #define MI_RS_CONTEXT MI_INSTR(0x0F, 0)
283 #define MI_TOPOLOGY_FILTER MI_INSTR(0x0D, 0)
284 #define MI_LOAD_SCAN_LINES_EXCL MI_INSTR(0x13, 0)
285 #define MI_URB_CLEAR MI_INSTR(0x19, 0)
286 #define MI_UPDATE_GTT MI_INSTR(0x23, 0)
287 #define MI_CLFLUSH MI_INSTR(0x27, 0)
288 #define MI_REPORT_PERF_COUNT MI_INSTR(0x28, 0)
289 #define MI_REPORT_PERF_COUNT_GGTT (1<<0)
290 #define MI_RS_STORE_DATA_IMM MI_INSTR(0x2B, 0)
291 #define MI_LOAD_URB_MEM MI_INSTR(0x2C, 0)
292 #define MI_STORE_URB_MEM MI_INSTR(0x2D, 0)
293 #define MI_CONDITIONAL_BATCH_BUFFER_END MI_INSTR(0x36, 0)
294
295 #define STATE_BASE_ADDRESS \
296 ((0x3 << 29) | (0x0 << 27) | (0x1 << 24) | (0x1 << 16))
297 #define BASE_ADDRESS_MODIFY REG_BIT(0)
298 #define PIPELINE_SELECT \
299 ((0x3 << 29) | (0x1 << 27) | (0x1 << 24) | (0x4 << 16))
300 #define PIPELINE_SELECT_MEDIA REG_BIT(0)
301 #define GFX_OP_3DSTATE_VF_STATISTICS \
302 ((0x3 << 29) | (0x1 << 27) | (0x0 << 24) | (0xB << 16))
303 #define MEDIA_VFE_STATE \
304 ((0x3 << 29) | (0x2 << 27) | (0x0 << 24) | (0x0 << 16))
305 #define MEDIA_VFE_STATE_MMIO_ACCESS_MASK (0x18)
306 #define MEDIA_INTERFACE_DESCRIPTOR_LOAD \
307 ((0x3 << 29) | (0x2 << 27) | (0x0 << 24) | (0x2 << 16))
308 #define MEDIA_OBJECT \
309 ((0x3 << 29) | (0x2 << 27) | (0x1 << 24) | (0x0 << 16))
310 #define GPGPU_OBJECT ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x4<<16))
311 #define GPGPU_WALKER ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x5<<16))
312 #define GFX_OP_3DSTATE_DX9_CONSTANTF_VS \
313 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x39<<16))
314 #define GFX_OP_3DSTATE_DX9_CONSTANTF_PS \
315 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x3A<<16))
316 #define GFX_OP_3DSTATE_SO_DECL_LIST \
317 ((0x3<<29)|(0x3<<27)|(0x1<<24)|(0x17<<16))
318
319 #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_VS \
320 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x43<<16))
321 #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_GS \
322 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x44<<16))
323 #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_HS \
324 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x45<<16))
325 #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_DS \
326 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x46<<16))
327 #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_PS \
328 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x47<<16))
329
330 #define MFX_WAIT ((0x3<<29)|(0x1<<27)|(0x0<<16))
331
332 #define COLOR_BLT ((0x2<<29)|(0x40<<22))
333 #define SRC_COPY_BLT ((0x2<<29)|(0x43<<22))
334
335 /*
336 * Used to convert any address to canonical form.
337 * Starting from gen8, some commands (e.g. STATE_BASE_ADDRESS,
338 * MI_LOAD_REGISTER_MEM and others, see Broadwell PRM Vol2a) require the
339 * addresses to be in a canonical form:
340 * "GraphicsAddress[63:48] are ignored by the HW and assumed to be in correct
341 * canonical form [63:48] == [47]."
342 */
343 #define GEN8_HIGH_ADDRESS_BIT 47
gen8_canonical_addr(u64 address)344 static inline u64 gen8_canonical_addr(u64 address)
345 {
346 return sign_extend64(address, GEN8_HIGH_ADDRESS_BIT);
347 }
348
gen8_noncanonical_addr(u64 address)349 static inline u64 gen8_noncanonical_addr(u64 address)
350 {
351 return address & GENMASK_ULL(GEN8_HIGH_ADDRESS_BIT, 0);
352 }
353
__gen6_emit_bb_start(u32 * cs,u32 addr,unsigned int flags)354 static inline u32 *__gen6_emit_bb_start(u32 *cs, u32 addr, unsigned int flags)
355 {
356 *cs++ = MI_BATCH_BUFFER_START | flags;
357 *cs++ = addr;
358
359 return cs;
360 }
361
362 #endif /* _INTEL_GPU_COMMANDS_H_ */
363