1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * linux/drivers/video/omap2/dss/dss.h
4 *
5 * Copyright (C) 2009 Nokia Corporation
6 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
7 *
8 * Some code and ideas taken from drivers/video/omap/ driver
9 * by Imre Deak.
10 */
11
12 #ifndef __OMAP2_DSS_H
13 #define __OMAP2_DSS_H
14
15 #include <linux/interrupt.h>
16
17 #ifdef pr_fmt
18 #undef pr_fmt
19 #endif
20
21 #ifdef DSS_SUBSYS_NAME
22 #define pr_fmt(fmt) DSS_SUBSYS_NAME ": " fmt
23 #else
24 #define pr_fmt(fmt) fmt
25 #endif
26
27 #define DSSDBG(format, ...) \
28 pr_debug(format, ## __VA_ARGS__)
29
30 #ifdef DSS_SUBSYS_NAME
31 #define DSSERR(format, ...) \
32 printk(KERN_ERR "omapdss " DSS_SUBSYS_NAME " error: " format, \
33 ## __VA_ARGS__)
34 #else
35 #define DSSERR(format, ...) \
36 printk(KERN_ERR "omapdss error: " format, ## __VA_ARGS__)
37 #endif
38
39 #ifdef DSS_SUBSYS_NAME
40 #define DSSINFO(format, ...) \
41 printk(KERN_INFO "omapdss " DSS_SUBSYS_NAME ": " format, \
42 ## __VA_ARGS__)
43 #else
44 #define DSSINFO(format, ...) \
45 printk(KERN_INFO "omapdss: " format, ## __VA_ARGS__)
46 #endif
47
48 #ifdef DSS_SUBSYS_NAME
49 #define DSSWARN(format, ...) \
50 printk(KERN_WARNING "omapdss " DSS_SUBSYS_NAME ": " format, \
51 ## __VA_ARGS__)
52 #else
53 #define DSSWARN(format, ...) \
54 printk(KERN_WARNING "omapdss: " format, ## __VA_ARGS__)
55 #endif
56
57 /* OMAP TRM gives bitfields as start:end, where start is the higher bit
58 number. For example 7:0 */
59 #define FLD_MASK(start, end) (((1 << ((start) - (end) + 1)) - 1) << (end))
60 #define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end))
61 #define FLD_GET(val, start, end) (((val) & FLD_MASK(start, end)) >> (end))
62 #define FLD_MOD(orig, val, start, end) \
63 (((orig) & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end))
64
65 enum omap_dss_clk_source {
66 OMAP_DSS_CLK_SRC_FCK = 0, /* OMAP2/3: DSS1_ALWON_FCLK
67 * OMAP4: DSS_FCLK */
68 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC, /* OMAP3: DSI1_PLL_FCLK
69 * OMAP4: PLL1_CLK1 */
70 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI, /* OMAP3: DSI2_PLL_FCLK
71 * OMAP4: PLL1_CLK2 */
72 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC, /* OMAP4: PLL2_CLK1 */
73 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI, /* OMAP4: PLL2_CLK2 */
74 };
75
76 enum dss_io_pad_mode {
77 DSS_IO_PAD_MODE_RESET,
78 DSS_IO_PAD_MODE_RFBI,
79 DSS_IO_PAD_MODE_BYPASS,
80 };
81
82 enum dss_hdmi_venc_clk_source_select {
83 DSS_VENC_TV_CLK = 0,
84 DSS_HDMI_M_PCLK = 1,
85 };
86
87 enum dss_dsi_content_type {
88 DSS_DSI_CONTENT_DCS,
89 DSS_DSI_CONTENT_GENERIC,
90 };
91
92 enum dss_pll_id {
93 DSS_PLL_DSI1,
94 DSS_PLL_DSI2,
95 DSS_PLL_HDMI,
96 DSS_PLL_VIDEO1,
97 DSS_PLL_VIDEO2,
98 };
99
100 struct dss_pll;
101
102 #define DSS_PLL_MAX_HSDIVS 4
103
104 /*
105 * Type-A PLLs: clkout[]/mX[] refer to hsdiv outputs m4, m5, m6, m7.
106 * Type-B PLLs: clkout[0] refers to m2.
107 */
108 struct dss_pll_clock_info {
109 /* rates that we get with dividers below */
110 unsigned long fint;
111 unsigned long clkdco;
112 unsigned long clkout[DSS_PLL_MAX_HSDIVS];
113
114 /* dividers */
115 u16 n;
116 u16 m;
117 u32 mf;
118 u16 mX[DSS_PLL_MAX_HSDIVS];
119 u16 sd;
120 };
121
122 struct dss_pll_ops {
123 int (*enable)(struct dss_pll *pll);
124 void (*disable)(struct dss_pll *pll);
125 int (*set_config)(struct dss_pll *pll,
126 const struct dss_pll_clock_info *cinfo);
127 };
128
129 struct dss_pll_hw {
130 unsigned n_max;
131 unsigned m_min;
132 unsigned m_max;
133 unsigned mX_max;
134
135 unsigned long fint_min, fint_max;
136 unsigned long clkdco_min, clkdco_low, clkdco_max;
137
138 u8 n_msb, n_lsb;
139 u8 m_msb, m_lsb;
140 u8 mX_msb[DSS_PLL_MAX_HSDIVS], mX_lsb[DSS_PLL_MAX_HSDIVS];
141
142 bool has_stopmode;
143 bool has_freqsel;
144 bool has_selfreqdco;
145 bool has_refsel;
146 };
147
148 struct dss_pll {
149 const char *name;
150 enum dss_pll_id id;
151
152 struct clk *clkin;
153 struct regulator *regulator;
154
155 void __iomem *base;
156
157 const struct dss_pll_hw *hw;
158
159 const struct dss_pll_ops *ops;
160
161 struct dss_pll_clock_info cinfo;
162 };
163
164 struct dispc_clock_info {
165 /* rates that we get with dividers below */
166 unsigned long lck;
167 unsigned long pck;
168
169 /* dividers */
170 u16 lck_div;
171 u16 pck_div;
172 };
173
174 struct dss_lcd_mgr_config {
175 enum dss_io_pad_mode io_pad_mode;
176
177 bool stallmode;
178 bool fifohandcheck;
179
180 struct dispc_clock_info clock_info;
181
182 int video_port_width;
183
184 int lcden_sig_polarity;
185 };
186
187 struct seq_file;
188 struct platform_device;
189
190 /* core */
191 struct platform_device *dss_get_core_pdev(void);
192 int dss_dsi_enable_pads(int dsi_id, unsigned lane_mask);
193 void dss_dsi_disable_pads(int dsi_id, unsigned lane_mask);
194 int dss_set_min_bus_tput(struct device *dev, unsigned long tput);
195 void dss_debugfs_create_file(const char *name, void (*write)(struct seq_file *));
196
197 /* display */
198 int dss_suspend_all_devices(void);
199 int dss_resume_all_devices(void);
200 void dss_disable_all_devices(void);
201
202 int display_init_sysfs(struct platform_device *pdev);
203 void display_uninit_sysfs(struct platform_device *pdev);
204
205 /* manager */
206 int dss_init_overlay_managers(void);
207 void dss_uninit_overlay_managers(void);
208 int dss_init_overlay_managers_sysfs(struct platform_device *pdev);
209 void dss_uninit_overlay_managers_sysfs(struct platform_device *pdev);
210 int dss_mgr_simple_check(struct omap_overlay_manager *mgr,
211 const struct omap_overlay_manager_info *info);
212 int dss_mgr_check_timings(struct omap_overlay_manager *mgr,
213 const struct omap_video_timings *timings);
214 int dss_mgr_check(struct omap_overlay_manager *mgr,
215 struct omap_overlay_manager_info *info,
216 const struct omap_video_timings *mgr_timings,
217 const struct dss_lcd_mgr_config *config,
218 struct omap_overlay_info **overlay_infos);
219
dss_mgr_is_lcd(enum omap_channel id)220 static inline bool dss_mgr_is_lcd(enum omap_channel id)
221 {
222 if (id == OMAP_DSS_CHANNEL_LCD || id == OMAP_DSS_CHANNEL_LCD2 ||
223 id == OMAP_DSS_CHANNEL_LCD3)
224 return true;
225 else
226 return false;
227 }
228
229 int dss_manager_kobj_init(struct omap_overlay_manager *mgr,
230 struct platform_device *pdev);
231 void dss_manager_kobj_uninit(struct omap_overlay_manager *mgr);
232
233 /* overlay */
234 void dss_init_overlays(struct platform_device *pdev);
235 void dss_uninit_overlays(struct platform_device *pdev);
236 void dss_overlay_setup_dispc_manager(struct omap_overlay_manager *mgr);
237 int dss_ovl_simple_check(struct omap_overlay *ovl,
238 const struct omap_overlay_info *info);
239 int dss_ovl_check(struct omap_overlay *ovl, struct omap_overlay_info *info,
240 const struct omap_video_timings *mgr_timings);
241 bool dss_ovl_use_replication(struct dss_lcd_mgr_config config,
242 enum omap_color_mode mode);
243 int dss_overlay_kobj_init(struct omap_overlay *ovl,
244 struct platform_device *pdev);
245 void dss_overlay_kobj_uninit(struct omap_overlay *ovl);
246
247 /* DSS */
248 int dss_init_platform_driver(void) __init;
249 void dss_uninit_platform_driver(void);
250
251 int dss_runtime_get(void);
252 void dss_runtime_put(void);
253
254 unsigned long dss_get_dispc_clk_rate(void);
255 int dss_dpi_select_source(int port, enum omap_channel channel);
256 void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select);
257 enum dss_hdmi_venc_clk_source_select dss_get_hdmi_venc_clk_source(void);
258 const char *dss_get_generic_clk_source_name(enum omap_dss_clk_source clk_src);
259 void dss_dump_clocks(struct seq_file *s);
260
261 /* DSS VIDEO PLL */
262 struct dss_pll *dss_video_pll_init(struct platform_device *pdev, int id,
263 struct regulator *regulator);
264 void dss_video_pll_uninit(struct dss_pll *pll);
265
266 /* dss-of */
267 struct device_node *dss_of_port_get_parent_device(struct device_node *port);
268 u32 dss_of_port_get_port_number(struct device_node *port);
269
270 #if defined(CONFIG_FB_OMAP2_DSS_DEBUGFS)
271 void dss_debug_dump_clocks(struct seq_file *s);
272 #endif
273
274 void dss_ctrl_pll_enable(enum dss_pll_id pll_id, bool enable);
275 void dss_ctrl_pll_set_control_mux(enum dss_pll_id pll_id,
276 enum omap_channel channel);
277
278 void dss_sdi_init(int datapairs);
279 int dss_sdi_enable(void);
280 void dss_sdi_disable(void);
281
282 void dss_select_dsi_clk_source(int dsi_module,
283 enum omap_dss_clk_source clk_src);
284 void dss_select_lcd_clk_source(enum omap_channel channel,
285 enum omap_dss_clk_source clk_src);
286 enum omap_dss_clk_source dss_get_dispc_clk_source(void);
287 enum omap_dss_clk_source dss_get_dsi_clk_source(int dsi_module);
288 enum omap_dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel);
289
290 void dss_set_venc_output(enum omap_dss_venc_type type);
291 void dss_set_dac_pwrdn_bgz(bool enable);
292
293 int dss_set_fck_rate(unsigned long rate);
294
295 typedef bool (*dss_div_calc_func)(unsigned long fck, void *data);
296 bool dss_div_calc(unsigned long pck, unsigned long fck_min,
297 dss_div_calc_func func, void *data);
298
299 /* SDI */
300 int sdi_init_platform_driver(void) __init;
301 void sdi_uninit_platform_driver(void);
302
303 #ifdef CONFIG_FB_OMAP2_DSS_SDI
304 int sdi_init_port(struct platform_device *pdev, struct device_node *port);
305 void sdi_uninit_port(struct device_node *port);
306 #else
sdi_init_port(struct platform_device * pdev,struct device_node * port)307 static inline int sdi_init_port(struct platform_device *pdev,
308 struct device_node *port)
309 {
310 return 0;
311 }
sdi_uninit_port(struct device_node * port)312 static inline void sdi_uninit_port(struct device_node *port)
313 {
314 }
315 #endif
316
317 /* DSI */
318
319 #ifdef CONFIG_FB_OMAP2_DSS_DSI
320
321 struct dentry;
322 struct file_operations;
323
324 int dsi_init_platform_driver(void) __init;
325 void dsi_uninit_platform_driver(void);
326
327 void dsi_dump_clocks(struct seq_file *s);
328
329 void dsi_irq_handler(void);
330 u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt);
331
332 #else
dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt)333 static inline u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt)
334 {
335 WARN(1, "%s: DSI not compiled in, returning pixel_size as 0\n",
336 __func__);
337 return 0;
338 }
339 #endif
340
341 /* DPI */
342 int dpi_init_platform_driver(void) __init;
343 void dpi_uninit_platform_driver(void);
344
345 #ifdef CONFIG_FB_OMAP2_DSS_DPI
346 int dpi_init_port(struct platform_device *pdev, struct device_node *port);
347 void dpi_uninit_port(struct device_node *port);
348 #else
dpi_init_port(struct platform_device * pdev,struct device_node * port)349 static inline int dpi_init_port(struct platform_device *pdev,
350 struct device_node *port)
351 {
352 return 0;
353 }
dpi_uninit_port(struct device_node * port)354 static inline void dpi_uninit_port(struct device_node *port)
355 {
356 }
357 #endif
358
359 /* DISPC */
360 int dispc_init_platform_driver(void) __init;
361 void dispc_uninit_platform_driver(void);
362 void dispc_dump_clocks(struct seq_file *s);
363
364 void dispc_enable_sidle(void);
365 void dispc_disable_sidle(void);
366
367 void dispc_lcd_enable_signal(bool enable);
368 void dispc_pck_free_enable(bool enable);
369 void dispc_enable_fifomerge(bool enable);
370 void dispc_enable_gamma_table(bool enable);
371
372 typedef bool (*dispc_div_calc_func)(int lckd, int pckd, unsigned long lck,
373 unsigned long pck, void *data);
374 bool dispc_div_calc(unsigned long dispc,
375 unsigned long pck_min, unsigned long pck_max,
376 dispc_div_calc_func func, void *data);
377
378 bool dispc_mgr_timings_ok(enum omap_channel channel,
379 const struct omap_video_timings *timings);
380 int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
381 struct dispc_clock_info *cinfo);
382
383
384 void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high);
385 void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
386 u32 *fifo_low, u32 *fifo_high, bool use_fifomerge,
387 bool manual_update);
388
389 void dispc_mgr_set_clock_div(enum omap_channel channel,
390 const struct dispc_clock_info *cinfo);
391 int dispc_mgr_get_clock_div(enum omap_channel channel,
392 struct dispc_clock_info *cinfo);
393 void dispc_set_tv_pclk(unsigned long pclk);
394
395 u32 dispc_read_irqstatus(void);
396 void dispc_clear_irqstatus(u32 mask);
397 u32 dispc_read_irqenable(void);
398 void dispc_write_irqenable(u32 mask);
399
400 int dispc_request_irq(irq_handler_t handler, void *dev_id);
401 void dispc_free_irq(void *dev_id);
402
403 int dispc_runtime_get(void);
404 void dispc_runtime_put(void);
405
406 void dispc_mgr_enable(enum omap_channel channel, bool enable);
407 bool dispc_mgr_is_enabled(enum omap_channel channel);
408 u32 dispc_mgr_get_vsync_irq(enum omap_channel channel);
409 u32 dispc_mgr_get_framedone_irq(enum omap_channel channel);
410 u32 dispc_mgr_get_sync_lost_irq(enum omap_channel channel);
411 bool dispc_mgr_go_busy(enum omap_channel channel);
412 void dispc_mgr_go(enum omap_channel channel);
413 void dispc_mgr_set_lcd_config(enum omap_channel channel,
414 const struct dss_lcd_mgr_config *config);
415 void dispc_mgr_set_timings(enum omap_channel channel,
416 const struct omap_video_timings *timings);
417 void dispc_mgr_setup(enum omap_channel channel,
418 const struct omap_overlay_manager_info *info);
419
420 int dispc_ovl_check(enum omap_plane plane, enum omap_channel channel,
421 const struct omap_overlay_info *oi,
422 const struct omap_video_timings *timings,
423 int *x_predecim, int *y_predecim);
424
425 int dispc_ovl_enable(enum omap_plane plane, bool enable);
426 bool dispc_ovl_enabled(enum omap_plane plane);
427 void dispc_ovl_set_channel_out(enum omap_plane plane,
428 enum omap_channel channel);
429 int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi,
430 bool replication, const struct omap_video_timings *mgr_timings,
431 bool mem_to_mem);
432
433 /* VENC */
434 int venc_init_platform_driver(void) __init;
435 void venc_uninit_platform_driver(void);
436
437 /* HDMI */
438 int hdmi4_init_platform_driver(void) __init;
439 void hdmi4_uninit_platform_driver(void);
440
441 int hdmi5_init_platform_driver(void) __init;
442 void hdmi5_uninit_platform_driver(void);
443
444
445 #ifdef CONFIG_FB_OMAP2_DSS_COLLECT_IRQ_STATS
dss_collect_irq_stats(u32 irqstatus,unsigned * irq_arr)446 static inline void dss_collect_irq_stats(u32 irqstatus, unsigned *irq_arr)
447 {
448 int b;
449 for (b = 0; b < 32; ++b) {
450 if (irqstatus & (1 << b))
451 irq_arr[b]++;
452 }
453 }
454 #endif
455
456 /* PLL */
457 typedef bool (*dss_pll_calc_func)(int n, int m, unsigned long fint,
458 unsigned long clkdco, void *data);
459 typedef bool (*dss_hsdiv_calc_func)(int m_dispc, unsigned long dispc,
460 void *data);
461
462 int dss_pll_register(struct dss_pll *pll);
463 void dss_pll_unregister(struct dss_pll *pll);
464 struct dss_pll *dss_pll_find(const char *name);
465 int dss_pll_enable(struct dss_pll *pll);
466 void dss_pll_disable(struct dss_pll *pll);
467 int dss_pll_set_config(struct dss_pll *pll,
468 const struct dss_pll_clock_info *cinfo);
469
470 bool dss_pll_hsdiv_calc(const struct dss_pll *pll, unsigned long clkdco,
471 unsigned long out_min, unsigned long out_max,
472 dss_hsdiv_calc_func func, void *data);
473 bool dss_pll_calc(const struct dss_pll *pll, unsigned long clkin,
474 unsigned long pll_min, unsigned long pll_max,
475 dss_pll_calc_func func, void *data);
476 int dss_pll_write_config_type_a(struct dss_pll *pll,
477 const struct dss_pll_clock_info *cinfo);
478 int dss_pll_write_config_type_b(struct dss_pll *pll,
479 const struct dss_pll_clock_info *cinfo);
480 int dss_pll_wait_reset_done(struct dss_pll *pll);
481
482 /* compat */
483
484 struct dss_mgr_ops {
485 int (*connect)(struct omap_overlay_manager *mgr,
486 struct omap_dss_device *dst);
487 void (*disconnect)(struct omap_overlay_manager *mgr,
488 struct omap_dss_device *dst);
489
490 void (*start_update)(struct omap_overlay_manager *mgr);
491 int (*enable)(struct omap_overlay_manager *mgr);
492 void (*disable)(struct omap_overlay_manager *mgr);
493 void (*set_timings)(struct omap_overlay_manager *mgr,
494 const struct omap_video_timings *timings);
495 void (*set_lcd_config)(struct omap_overlay_manager *mgr,
496 const struct dss_lcd_mgr_config *config);
497 int (*register_framedone_handler)(struct omap_overlay_manager *mgr,
498 void (*handler)(void *), void *data);
499 void (*unregister_framedone_handler)(struct omap_overlay_manager *mgr,
500 void (*handler)(void *), void *data);
501 };
502
503 int dss_install_mgr_ops(const struct dss_mgr_ops *mgr_ops);
504 void dss_uninstall_mgr_ops(void);
505
506 int dss_mgr_connect(struct omap_overlay_manager *mgr,
507 struct omap_dss_device *dst);
508 void dss_mgr_disconnect(struct omap_overlay_manager *mgr,
509 struct omap_dss_device *dst);
510 void dss_mgr_set_timings(struct omap_overlay_manager *mgr,
511 const struct omap_video_timings *timings);
512 void dss_mgr_set_lcd_config(struct omap_overlay_manager *mgr,
513 const struct dss_lcd_mgr_config *config);
514 int dss_mgr_enable(struct omap_overlay_manager *mgr);
515 void dss_mgr_disable(struct omap_overlay_manager *mgr);
516 void dss_mgr_start_update(struct omap_overlay_manager *mgr);
517 int dss_mgr_register_framedone_handler(struct omap_overlay_manager *mgr,
518 void (*handler)(void *), void *data);
519 void dss_mgr_unregister_framedone_handler(struct omap_overlay_manager *mgr,
520 void (*handler)(void *), void *data);
521
522 #endif
523