1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __DAL_TIMING_GENERATOR_TYPES_H__ 27 #define __DAL_TIMING_GENERATOR_TYPES_H__ 28 29 #include "hw_shared.h" 30 31 struct dc_bios; 32 33 /* Contains CRTC vertical/horizontal pixel counters */ 34 struct crtc_position { 35 int32_t vertical_count; 36 int32_t horizontal_count; 37 int32_t nominal_vcount; 38 }; 39 40 struct dcp_gsl_params { 41 int gsl_group; 42 int gsl_master; 43 }; 44 45 struct gsl_params { 46 int gsl0_en; 47 int gsl1_en; 48 int gsl2_en; 49 int gsl_master_en; 50 int gsl_master_mode; 51 int master_update_lock_gsl_en; 52 int gsl_window_start_x; 53 int gsl_window_end_x; 54 int gsl_window_start_y; 55 int gsl_window_end_y; 56 }; 57 58 /* define the structure of Dynamic Refresh Mode */ 59 struct drr_params { 60 uint32_t vertical_total_min; 61 uint32_t vertical_total_max; 62 uint32_t vertical_total_mid; 63 uint32_t vertical_total_mid_frame_num; 64 bool immediate_flip; 65 }; 66 67 #define LEFT_EYE_3D_PRIMARY_SURFACE 1 68 #define RIGHT_EYE_3D_PRIMARY_SURFACE 0 69 70 enum crtc_state { 71 CRTC_STATE_VBLANK = 0, 72 CRTC_STATE_VACTIVE 73 }; 74 75 struct vupdate_keepout_params { 76 int start_offset; 77 int end_offset; 78 int enable; 79 }; 80 81 struct crtc_stereo_flags { 82 uint8_t PROGRAM_STEREO : 1; 83 uint8_t PROGRAM_POLARITY : 1; 84 uint8_t RIGHT_EYE_POLARITY : 1; 85 uint8_t FRAME_PACKED : 1; 86 uint8_t DISABLE_STEREO_DP_SYNC : 1; 87 }; 88 89 enum crc_selection { 90 /* Order must match values expected by hardware */ 91 UNION_WINDOW_A_B = 0, 92 UNION_WINDOW_A_NOT_B, 93 UNION_WINDOW_NOT_A_B, 94 UNION_WINDOW_NOT_A_NOT_B, 95 INTERSECT_WINDOW_A_B, 96 INTERSECT_WINDOW_A_NOT_B, 97 INTERSECT_WINDOW_NOT_A_B, 98 INTERSECT_WINDOW_NOT_A_NOT_B, 99 }; 100 101 #ifdef CONFIG_DRM_AMD_DC_DCN3_0 102 enum otg_out_mux_dest { 103 OUT_MUX_DIO = 0, 104 }; 105 #endif 106 107 enum h_timing_div_mode { 108 H_TIMING_NO_DIV, 109 H_TIMING_DIV_BY2, 110 #if defined(CONFIG_DRM_AMD_DC_DCN3_0) 111 H_TIMING_RESERVED, 112 H_TIMING_DIV_BY4, 113 #endif 114 }; 115 116 struct crc_params { 117 /* Regions used to calculate CRC*/ 118 uint16_t windowa_x_start; 119 uint16_t windowa_x_end; 120 uint16_t windowa_y_start; 121 uint16_t windowa_y_end; 122 123 uint16_t windowb_x_start; 124 uint16_t windowb_x_end; 125 uint16_t windowb_y_start; 126 uint16_t windowb_y_end; 127 128 enum crc_selection selection; 129 130 uint8_t dsc_mode; 131 uint8_t odm_mode; 132 133 bool continuous_mode; 134 bool enable; 135 }; 136 137 struct timing_generator { 138 const struct timing_generator_funcs *funcs; 139 struct dc_bios *bp; 140 struct dc_context *ctx; 141 int inst; 142 }; 143 144 struct dc_crtc_timing; 145 146 struct drr_params; 147 148 149 struct timing_generator_funcs { 150 bool (*validate_timing)(struct timing_generator *tg, 151 const struct dc_crtc_timing *timing); 152 void (*program_timing)(struct timing_generator *tg, 153 const struct dc_crtc_timing *timing, 154 int vready_offset, 155 int vstartup_start, 156 int vupdate_offset, 157 int vupdate_width, 158 const enum signal_type signal, 159 bool use_vbios 160 ); 161 void (*setup_vertical_interrupt0)( 162 struct timing_generator *optc, 163 uint32_t start_line, 164 uint32_t end_line); 165 void (*setup_vertical_interrupt1)( 166 struct timing_generator *optc, 167 uint32_t start_line); 168 void (*setup_vertical_interrupt2)( 169 struct timing_generator *optc, 170 uint32_t start_line); 171 172 bool (*enable_crtc)(struct timing_generator *tg); 173 bool (*disable_crtc)(struct timing_generator *tg); 174 bool (*is_counter_moving)(struct timing_generator *tg); 175 void (*get_position)(struct timing_generator *tg, 176 struct crtc_position *position); 177 178 uint32_t (*get_frame_count)(struct timing_generator *tg); 179 void (*get_scanoutpos)( 180 struct timing_generator *tg, 181 uint32_t *v_blank_start, 182 uint32_t *v_blank_end, 183 uint32_t *h_position, 184 uint32_t *v_position); 185 bool (*get_otg_active_size)(struct timing_generator *optc, 186 uint32_t *otg_active_width, 187 uint32_t *otg_active_height); 188 bool (*is_matching_timing)(struct timing_generator *tg, 189 const struct dc_crtc_timing *otg_timing); 190 void (*set_early_control)(struct timing_generator *tg, 191 uint32_t early_cntl); 192 void (*wait_for_state)(struct timing_generator *tg, 193 enum crtc_state state); 194 void (*set_blank)(struct timing_generator *tg, 195 bool enable_blanking); 196 bool (*is_blanked)(struct timing_generator *tg); 197 void (*set_overscan_blank_color) (struct timing_generator *tg, const struct tg_color *color); 198 void (*set_blank_color)(struct timing_generator *tg, const struct tg_color *color); 199 void (*set_colors)(struct timing_generator *tg, 200 const struct tg_color *blank_color, 201 const struct tg_color *overscan_color); 202 203 void (*disable_vga)(struct timing_generator *tg); 204 bool (*did_triggered_reset_occur)(struct timing_generator *tg); 205 void (*setup_global_swap_lock)(struct timing_generator *tg, 206 const struct dcp_gsl_params *gsl_params); 207 void (*unlock)(struct timing_generator *tg); 208 void (*lock)(struct timing_generator *tg); 209 void (*lock_doublebuffer_disable)(struct timing_generator *tg); 210 void (*lock_doublebuffer_enable)(struct timing_generator *tg); 211 void(*triplebuffer_unlock)(struct timing_generator *tg); 212 void(*triplebuffer_lock)(struct timing_generator *tg); 213 void (*enable_reset_trigger)(struct timing_generator *tg, 214 int source_tg_inst); 215 void (*enable_crtc_reset)(struct timing_generator *tg, 216 int source_tg_inst, 217 struct crtc_trigger_info *crtc_tp); 218 void (*disable_reset_trigger)(struct timing_generator *tg); 219 void (*tear_down_global_swap_lock)(struct timing_generator *tg); 220 void (*enable_advanced_request)(struct timing_generator *tg, 221 bool enable, const struct dc_crtc_timing *timing); 222 void (*set_drr)(struct timing_generator *tg, const struct drr_params *params); 223 void (*set_static_screen_control)(struct timing_generator *tg, 224 uint32_t event_triggers, 225 uint32_t num_frames); 226 void (*set_test_pattern)( 227 struct timing_generator *tg, 228 enum controller_dp_test_pattern test_pattern, 229 enum dc_color_depth color_depth); 230 231 bool (*arm_vert_intr)(struct timing_generator *tg, uint8_t width); 232 233 void (*program_global_sync)(struct timing_generator *tg, 234 int vready_offset, 235 int vstartup_start, 236 int vupdate_offset, 237 int vupdate_width); 238 void (*enable_optc_clock)(struct timing_generator *tg, bool enable); 239 void (*program_stereo)(struct timing_generator *tg, 240 const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags); 241 bool (*is_stereo_left_eye)(struct timing_generator *tg); 242 243 void (*set_blank_data_double_buffer)(struct timing_generator *tg, bool enable); 244 245 void (*tg_init)(struct timing_generator *tg); 246 bool (*is_tg_enabled)(struct timing_generator *tg); 247 bool (*is_optc_underflow_occurred)(struct timing_generator *tg); 248 void (*clear_optc_underflow)(struct timing_generator *tg); 249 250 void (*set_dwb_source)(struct timing_generator *optc, 251 uint32_t dwb_pipe_inst); 252 253 void (*get_optc_source)(struct timing_generator *optc, 254 uint32_t *num_of_input_segments, 255 uint32_t *seg0_src_sel, 256 uint32_t *seg1_src_sel); 257 258 /** 259 * Configure CRCs for the given timing generator. Return false if TG is 260 * not on. 261 */ 262 bool (*configure_crc)(struct timing_generator *tg, 263 const struct crc_params *params); 264 265 /** 266 * Get CRCs for the given timing generator. Return false if CRCs are 267 * not enabled (via configure_crc). 268 */ 269 bool (*get_crc)(struct timing_generator *tg, 270 uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb); 271 272 void (*program_manual_trigger)(struct timing_generator *optc); 273 void (*setup_manual_trigger)(struct timing_generator *optc); 274 bool (*get_hw_timing)(struct timing_generator *optc, 275 struct dc_crtc_timing *hw_crtc_timing); 276 277 void (*set_vtg_params)(struct timing_generator *optc, 278 const struct dc_crtc_timing *dc_crtc_timing); 279 280 void (*set_dsc_config)(struct timing_generator *optc, 281 enum optc_dsc_mode dsc_mode, 282 uint32_t dsc_bytes_per_pixel, 283 uint32_t dsc_slice_width); 284 void (*set_odm_bypass)(struct timing_generator *optc, const struct dc_crtc_timing *dc_crtc_timing); 285 void (*set_odm_combine)(struct timing_generator *optc, int *opp_id, int opp_cnt, 286 struct dc_crtc_timing *timing); 287 void (*set_gsl)(struct timing_generator *optc, const struct gsl_params *params); 288 void (*set_gsl_source_select)(struct timing_generator *optc, 289 int group_idx, 290 uint32_t gsl_ready_signal); 291 #if defined(CONFIG_DRM_AMD_DC_DCN3_0) 292 void (*set_out_mux)(struct timing_generator *tg, enum otg_out_mux_dest dest); 293 void (*set_vrr_m_const)(struct timing_generator *optc, 294 double vtotal_avg); 295 void (*set_drr_trigger_window)(struct timing_generator *optc, 296 uint32_t window_start, uint32_t window_end); 297 void (*set_vtotal_change_limit)(struct timing_generator *optc, 298 uint32_t limit); 299 #endif 300 }; 301 302 #endif 303