1 /* SPDX-License-Identifier: GPL-2.0+ 2 * 3 * Copyright (c) 2016 Linaro Limited. 4 * Copyright (c) 2014-2016 Hisilicon Limited. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 */ 11 #ifndef __KIRIN_DPE_REG_H__ 12 #define __KIRIN_DPE_REG_H__ 13 14 #define BIT_MMU_IRPT_NS BIT(28) 15 #define BIT_ITF0_INTS BIT(16) 16 #define BIT_DPP_INTS BIT(15) 17 #define BIT_VACTIVE0_END BIT(8) 18 #define BIT_VACTIVE0_START BIT(7) 19 #define BIT_VSYNC BIT(4) 20 #define BIT_LDI_UNFLOW BIT(2) 21 22 #define DFS_TIME (80) 23 #define DFS_TIME_MIN (50) 24 #define DFS_TIME_MIN_4K (10) 25 #define DBUF0_DEPTH (1408) 26 #define DBUF_WIDTH_BIT (144) 27 #define PERRSTDIS3 (0x088) 28 29 #define DPE_GLB0_OFFSET (0x12000) 30 #define DPE_DBG_OFFSET (0x11000) 31 #define DPE_CMDLIST_OFFSET (0x02000) 32 #define DPE_SMMU_OFFSET (0x08000) 33 #define DPE_MIF_OFFSET (0x0A000) 34 #define DPE_MCTRL_SYS_OFFSET (0x10000) 35 #define DPE_MCTRL_CTL0_OFFSET (0x10800) 36 #define DPE_RCH_VG0_DMA_OFFSET (0x20000) 37 #define DPE_RCH_VG0_SCL_OFFSET (0x20200) 38 #define DPE_RCH_VG0_ARSR_OFFSET (0x20300) 39 #define DPE_RCH_VG1_DMA_OFFSET (0x28000) 40 #define DPE_RCH_VG1_SCL_OFFSET (0x28200) 41 #define DPE_RCH_VG2_DMA_OFFSET (0x30000) 42 #define DPE_RCH_VG2_SCL_OFFSET (0x30200) 43 #define DPE_RCH_G0_DMA_OFFSET (0x38000) 44 #define DPE_RCH_G0_SCL_OFFSET (0x38200) 45 #define DPE_RCH_G1_DMA_OFFSET (0x40000) 46 #define DPE_RCH_G1_SCL_OFFSET (0x40200) 47 #define DPE_RCH_D2_DMA_OFFSET (0x50000) 48 #define DPE_RCH_D3_DMA_OFFSET (0x51000) 49 #define DPE_RCH_D0_DMA_OFFSET (0x52000) 50 #define DPE_RCH_D0_DFC_OFFSET (0x52100) 51 #define DPE_RCH_D1_DMA_OFFSET (0x53000) 52 #define DPE_WCH0_DMA_OFFSET (0x5A000) 53 #define DPE_WCH1_DMA_OFFSET (0x5C000) 54 #define DPE_WCH2_DMA_OFFSET (0x5E000) 55 #define DPE_WCH2_DFC_OFFSET (0x5E100) 56 #define DPE_OVL0_OFFSET (0x60000) 57 #define DPE_DBUF0_OFFSET (0x6D000) 58 #define DPE_DPP_OFFSET (0x70000) 59 #define DPE_DPP_DITHER_OFFSET (0x70200) 60 #define DPE_LDI0_OFFSET (0x7D000) 61 #define DPE_IFBC_OFFSET (0x7D800) 62 #define DPE_DSC_OFFSET (0x7DC00) 63 64 #define GLB_CPU_PDP_INTS (DPE_GLB0_OFFSET + 0x224) 65 #define GLB_CPU_PDP_INT_MSK (DPE_GLB0_OFFSET + 0x228) 66 #define GLB_CPU_SDP_INTS (DPE_GLB0_OFFSET + 0x22C) 67 #define GLB_CPU_SDP_INT_MSK (DPE_GLB0_OFFSET + 0x230) 68 69 #define DBG_MCTL_INTS (0x023C) 70 #define DBG_MCTL_INT_MSK (0x0240) 71 #define DBG_WCH0_INTS (0x0244) 72 #define DBG_WCH0_INT_MSK (0x0248) 73 #define DBG_WCH1_INTS (0x024C) 74 #define DBG_WCH1_INT_MSK (0x0250) 75 #define DBG_RCH0_INTS (0x0254) 76 #define DBG_RCH0_INT_MSK (0x0258) 77 #define DBG_RCH1_INTS (0x025C) 78 #define DBG_RCH1_INT_MSK (0x0260) 79 #define DBG_RCH2_INTS (0x0264) 80 #define DBG_RCH2_INT_MSK (0x0268) 81 #define DBG_RCH3_INTS (0x026C) 82 #define DBG_RCH3_INT_MSK (0x0270) 83 #define DBG_RCH4_INTS (0x0274) 84 #define DBG_RCH4_INT_MSK (0x0278) 85 #define DBG_RCH5_INTS (0x027C) 86 #define DBG_RCH5_INT_MSK (0x0280) 87 #define DBG_RCH6_INTS (0x0284) 88 #define DBG_RCH6_INT_MSK (0x0288) 89 #define DBG_RCH7_INTS (0x028C) 90 #define DBG_RCH7_INT_MSK (0x0290) 91 #define DBG_DPE_GLB_INTS (0x0294) 92 #define DBG_DPE_GLB_INT_MSK (0x0298) 93 94 #define AIF0_CH0_OFFSET (0x7000) 95 #define AIF0_CH0_ADD_OFFSET (0x7004) 96 97 #define MIF_ENABLE (0x0000) 98 #define MIF_MEM_CTRL (0x0004) 99 #define MIF_CTRL0 (0x0000) 100 #define MIF_CTRL1 (0x0004) 101 #define MIF_CTRL2 (0x0008) 102 #define MIF_CTRL3 (0x000C) 103 #define MIF_CTRL4 (0x0010) 104 #define MIF_CTRL5 (0x0014) 105 #define MIF_CTRL_OFFSET (0x0020) 106 #define MIF_CH0_OFFSET (DPE_MIF_OFFSET + MIF_CTRL_OFFSET * 1) 107 108 #define SMMU_SCR (0x0000) 109 #define SMMU_MEMCTRL (0x0004) 110 #define SMMU_LP_CTRL (0x0008) 111 #define SMMU_INTMASK_NS (0x0010) 112 #define SMMU_INTRAW_NS (0x0014) 113 #define SMMU_INTSTAT_NS (0x0018) 114 #define SMMU_INTCLR_NS (0x001C) 115 #define SMMU_SMRx_NS (0x0020) 116 117 #define DMA_OFT_X0 (0x0000) 118 #define DMA_OFT_Y0 (0x0004) 119 #define DMA_OFT_X1 (0x0008) 120 #define DMA_OFT_Y1 (0x000C) 121 #define DMA_MASK0 (0x0010) 122 #define DMA_MASK1 (0x0014) 123 #define DMA_STRETCH_SIZE_VRT (0x0018) 124 #define DMA_CTRL (0x001C) 125 #define DMA_TILE_SCRAM (0x0020) 126 #define DMA_PULSE (0x0028) 127 #define DMA_CORE_GT (0x002C) 128 #define DMA_DATA_ADDR0 (0x0060) 129 #define DMA_STRIDE0 (0x0064) 130 #define DMA_STRETCH_STRIDE0 (0x0068) 131 #define DMA_DATA_NUM0 (0x006C) 132 #define DMA_CH_CTL (0x00D4) 133 #define DMA_CH_REG_DEFAULT (0x0A00) 134 #define DMA_ALIGN_BYTES (128 / BITS_PER_BYTE) 135 #define DMA_ADDR_ALIGN (128 / BITS_PER_BYTE) 136 #define DMA_STRIDE_ALIGN (128 / BITS_PER_BYTE) 137 138 #define DFC_DISP_SIZE (0x0000) 139 #define DFC_PIX_IN_NUM (0x0004) 140 #define DFC_GLB_ALPHA (0x0008) 141 #define DFC_DISP_FMT (0x000C) 142 #define DFC_CLIP_CTL_HRZ (0x0010) 143 #define DFC_CLIP_CTL_VRZ (0x0014) 144 #define DFC_CTL_CLIP_EN (0x0018) 145 #define DFC_ICG_MODULE (0x001C) 146 #define DFC_DITHER_ENABLE (0x0020) 147 #define DFC_PADDING_CTL (0x0024) 148 149 #define MCTL_CTL_EN (0x0000) 150 #define MCTL_CTL_MUTEX (0x0004) 151 #define MCTL_CTL_MUTEX_STATUS (0x0008) 152 #define MCTL_CTL_MUTEX_ITF (0x000C) 153 #define MCTL_CTL_MUTEX_DBUF (0x0010) 154 #define MCTL_CTL_MUTEX_SCF (0x0014) 155 #define MCTL_CTL_MUTEX_OV (0x0018) 156 #define MCTL_CTL_MUTEX_WCH0 (0x0020) 157 #define MCTL_CTL_MUTEX_RCH0 (0x0030) 158 #define MCTL_CTL_TOP (0x0050) 159 #define MCTL_CTL_DBG (0x00E0) 160 #define MCTL_RCH0_FLUSH_EN (0x0100) 161 #define MCTL_OV0_FLUSH_EN (0x0128) 162 #define MCTL_RCH0_OV_OEN (0x0160) 163 #define MCTL_RCH_OV0_SEL (0x0180) 164 165 #define OVL_SIZE (0x0000) 166 #define OVL_BG_COLOR (0x0004) 167 #define OVL_DST_STARTPOS (0x0008) 168 #define OVL_DST_ENDPOS (0x000C) 169 #define OVL_GCFG (0x0010) 170 #define OVL_LAYER0_POS (0x0014) 171 #define OVL_LAYER0_SIZE (0x0018) 172 #define OVL_LAYER0_ALPHA (0x0030) 173 #define OVL_LAYER0_CFG (0x0034) 174 #define OVL6_REG_DEFAULT (0x01A8) 175 176 #define DBUF_FRM_SIZE (0x0000) 177 #define DBUF_FRM_HSIZE (0x0004) 178 #define DBUF_SRAM_VALID_NUM (0x0008) 179 #define DBUF_WBE_EN (0x000C) 180 #define DBUF_THD_FILL_LEV0 (0x0010) 181 #define DBUF_DFS_FILL_LEV1 (0x0014) 182 #define DBUF_THD_RQOS (0x0018) 183 #define DBUF_THD_WQOS (0x001C) 184 #define DBUF_THD_CG (0x0020) 185 #define DBUF_THD_OTHER (0x0024) 186 #define DBUF_ONLINE_FILL_LEVEL (0x003C) 187 #define DBUF_WB_FILL_LEVEL (0x0040) 188 #define DBUF_DFS_STATUS (0x0044) 189 #define DBUF_THD_FLUX_REQ_BEF (0x0048) 190 #define DBUF_DFS_LP_CTRL (0x004C) 191 #define DBUF_RD_SHADOW_SEL (0x0050) 192 #define DBUF_MEM_CTRL (0x0054) 193 #define DBUF_THD_FLUX_REQ_AFT (0x0064) 194 #define DBUF_THD_DFS_OK (0x0068) 195 #define DBUF_FLUX_REQ_CTRL (0x006C) 196 #define DBUF_REG_DEFAULT (0x00A4) 197 198 #define DPP_IMG_SIZE_BEF_SR (0x000C) 199 #define DPP_IMG_SIZE_AFT_SR (0x0010) 200 #define DPP_INTS (0x0040) 201 #define DPP_INT_MSK (0x0044) 202 203 #define SCF_COEF_MEM_CTRL (0x0018) 204 #define IFBC_MEM_CTRL (0x001C) 205 #define DITHER_MEM_CTRL (0x002C) 206 #define DSC_MEM_CTRL (0x0084) 207 #define ARSR2P_LB_MEM_CTRL (0x0084) 208 #define SCF_LB_MEM_CTRL (0x0090) 209 #define ROT_MEM_CTRL (0x0538) 210 #define VPP_MEM_CTRL (0x0704) 211 #define CMD_MEM_CTRL (0x073C) 212 #define DMA_BUF_MEM_CTRL (0x0854) 213 #define AFBCD_MEM_CTRL (0x093C) 214 #define AFBCE_MEM_CTRL (0x0924) 215 216 #define LDI_DPI0_HRZ_CTRL0 (0x0000) 217 #define LDI_DPI0_HRZ_CTRL1 (0x0004) 218 #define LDI_DPI0_HRZ_CTRL2 (0x0008) 219 #define LDI_VRT_CTRL0 (0x000C) 220 #define LDI_VRT_CTRL1 (0x0010) 221 #define LDI_VRT_CTRL2 (0x0014) 222 #define LDI_PLR_CTRL (0x0018) 223 #define LDI_CTRL (0x0024) 224 #define LDI_WORK_MODE (0x0028) 225 #define LDI_DSI_CMD_MOD_CTRL (0x0030) 226 #define LDI_VINACT_MSK_LEN (0x0050) 227 #define LDI_CMD_EVENT_SEL (0x0060) 228 #define LDI_MEM_CTRL (0x0100) 229 #define LDI_PXL0_DIV2_GT_EN (0x0210) 230 #define LDI_PXL0_DIV4_GT_EN (0x0214) 231 #define LDI_PXL0_GT_EN (0x0218) 232 #define LDI_PXL0_DSI_GT_EN (0x021C) 233 #define LDI_PXL0_DIVXCFG (0x0220) 234 #define LDI_VESA_CLK_SEL (0x0228) 235 #define LDI_CPU_ITF_INTS (0x0248) 236 #define LDI_CPU_ITF_INT_MSK (0x024C) 237 238 #define MIPIDSI_VERSION_OFFSET (0x0000) 239 #define MIPIDSI_PWR_UP_OFFSET (0x0004) 240 #define MIPIDSI_CLKMGR_CFG_OFFSET (0x0008) 241 #define MIPIDSI_DPI_VCID_OFFSET (0x000c) 242 #define MIPIDSI_DPI_COLOR_CODING_OFFSET (0x0010) 243 #define MIPIDSI_DPI_CFG_POL_OFFSET (0x0014) 244 #define MIPIDSI_DPI_LP_CMD_TIM_OFFSET (0x0018) 245 #define MIPIDSI_PCKHDL_CFG_OFFSET (0x002c) 246 #define MIPIDSI_GEN_VCID_OFFSET (0x0030) 247 #define MIPIDSI_MODE_CFG_OFFSET (0x0034) 248 #define MIPIDSI_VID_MODE_CFG_OFFSET (0x0038) 249 #define MIPIDSI_VID_PKT_SIZE_OFFSET (0x003c) 250 #define MIPIDSI_VID_NUM_CHUNKS_OFFSET (0x0040) 251 #define MIPIDSI_VID_NULL_SIZE_OFFSET (0x0044) 252 #define MIPIDSI_VID_HSA_TIME_OFFSET (0x0048) 253 #define MIPIDSI_VID_HBP_TIME_OFFSET (0x004c) 254 #define MIPIDSI_VID_HLINE_TIME_OFFSET (0x0050) 255 #define MIPIDSI_VID_VSA_LINES_OFFSET (0x0054) 256 #define MIPIDSI_VID_VBP_LINES_OFFSET (0x0058) 257 #define MIPIDSI_VID_VFP_LINES_OFFSET (0x005c) 258 #define MIPIDSI_VID_VACTIVE_LINES_OFFSET (0x0060) 259 #define MIPIDSI_EDPI_CMD_SIZE_OFFSET (0x0064) 260 #define MIPIDSI_CMD_MODE_CFG_OFFSET (0x0068) 261 #define MIPIDSI_GEN_HDR_OFFSET (0x006c) 262 #define MIPIDSI_GEN_PLD_DATA_OFFSET (0x0070) 263 #define MIPIDSI_CMD_PKT_STATUS_OFFSET (0x0074) 264 #define MIPIDSI_TO_CNT_CFG_OFFSET (0x0078) 265 #define MIPIDSI_BTA_TO_CNT_OFFSET (0x008C) 266 #define MIPIDSI_SDF_3D_OFFSET (0x0090) 267 #define MIPIDSI_LPCLK_CTRL_OFFSET (0x0094) 268 #define MIPIDSI_PHY_TMR_LPCLK_CFG_OFFSET (0x0098) 269 #define MIPIDSI_PHY_TMR_CFG_OFFSET (0x009c) 270 #define MIPIDSI_PHY_RSTZ_OFFSET (0x00a0) 271 #define MIPIDSI_PHY_IF_CFG_OFFSET (0x00a4) 272 #define MIPIDSI_PHY_ULPS_CTRL_OFFSET (0x00a8) 273 #define MIPIDSI_PHY_TX_TRIGGERS_OFFSET (0x00ac) 274 #define MIPIDSI_PHY_STATUS_OFFSET (0x00b0) 275 #define MIPIDSI_PHY_TST_CTRL0_OFFSET (0x00b4) 276 #define MIPIDSI_PHY_TST_CTRL1_OFFSET (0x00b8) 277 #define MIPIDSI_PHY_TMR_RD_CFG_OFFSET (0x00f4) 278 279 enum XRES_DIV { 280 XRES_DIV_1 = 1, 281 XRES_DIV_2, 282 }; 283 284 enum YRES_DIV { 285 YRES_DIV_1 = 1, 286 YRES_DIV_2, 287 }; 288 289 enum PXL0_DIVCFG { 290 PXL0_DIVCFG_0 = 0, 291 PXL0_DIVCFG_1, 292 }; 293 294 enum PXL0_DIV2_GT_EN { 295 PXL0_DIV2_GT_EN_CLOSE = 0, 296 PXL0_DIV2_GT_EN_OPEN, 297 }; 298 299 enum PXL0_DIV4_GT_EN { 300 PXL0_DIV4_GT_EN_CLOSE = 0, 301 PXL0_DIV4_GT_EN_OPEN, 302 }; 303 304 enum PXL0_DSI_GT_EN { 305 PXL0_DSI_GT_EN_0 = 0, 306 PXL0_DSI_GT_EN_1, 307 }; 308 309 enum lcd_format { 310 LCD_RGB888 = 0, 311 LCD_RGB101010, 312 LCD_RGB565, 313 }; 314 315 enum lcd_rgb_order { 316 LCD_RGB = 0, 317 LCD_BGR, 318 }; 319 320 enum dpe_dfc_format { 321 DFC_PIXEL_FORMAT_RGB_565 = 0, 322 DFC_PIXEL_FORMAT_XRGB_4444, 323 DFC_PIXEL_FORMAT_ARGB_4444, 324 DFC_PIXEL_FORMAT_XRGB_5551, 325 DFC_PIXEL_FORMAT_ARGB_5551, 326 DFC_PIXEL_FORMAT_XRGB_8888, 327 DFC_PIXEL_FORMAT_ARGB_8888, 328 DFC_PIXEL_FORMAT_BGR_565, 329 DFC_PIXEL_FORMAT_XBGR_4444, 330 DFC_PIXEL_FORMAT_ABGR_4444, 331 DFC_PIXEL_FORMAT_XBGR_5551, 332 DFC_PIXEL_FORMAT_ABGR_5551, 333 DFC_PIXEL_FORMAT_XBGR_8888, 334 DFC_PIXEL_FORMAT_ABGR_8888, 335 DFC_PIXEL_FORMAT_YUV444, 336 DFC_PIXEL_FORMAT_YVU444, 337 DFC_PIXEL_FORMAT_YUYV422, 338 DFC_PIXEL_FORMAT_YVYU422, 339 DFC_PIXEL_FORMAT_VYUY422, 340 DFC_PIXEL_FORMAT_UYVY422, 341 }; 342 343 enum dpe_dma_format { 344 DMA_PIXEL_FORMAT_RGB_565 = 0, 345 DMA_PIXEL_FORMAT_ARGB_4444, 346 DMA_PIXEL_FORMAT_XRGB_4444, 347 DMA_PIXEL_FORMAT_ARGB_5551, 348 DMA_PIXEL_FORMAT_XRGB_5551, 349 DMA_PIXEL_FORMAT_ARGB_8888, 350 DMA_PIXEL_FORMAT_XRGB_8888, 351 DMA_PIXEL_FORMAT_RESERVED0, 352 DMA_PIXEL_FORMAT_YUYV_422_Pkg, 353 DMA_PIXEL_FORMAT_YUV_420_SP_HP, 354 DMA_PIXEL_FORMAT_YUV_420_P_HP, 355 DMA_PIXEL_FORMAT_YUV_422_SP_HP, 356 DMA_PIXEL_FORMAT_YUV_422_P_HP, 357 DMA_PIXEL_FORMAT_AYUV_4444, 358 }; 359 360 enum dpe_fb_format { 361 DPE_RGB_565 = 0, 362 DPE_RGBX_4444, 363 DPE_RGBA_4444, 364 DPE_RGBX_5551, 365 DPE_RGBA_5551, 366 DPE_RGBX_8888, 367 DPE_RGBA_8888, 368 DPE_BGR_565, 369 DPE_BGRX_4444, 370 DPE_BGRA_4444, 371 DPE_BGRX_5551, 372 DPE_BGRA_5551, 373 DPE_BGRX_8888, 374 DPE_BGRA_8888, 375 DPE_YUV_422_I, 376 /* YUV Semi-planar */ 377 DPE_YCbCr_422_SP, 378 DPE_YCrCb_422_SP, 379 DPE_YCbCr_420_SP, 380 DPE_YCrCb_420_SP, 381 /* YUV Planar */ 382 DPE_YCbCr_422_P, 383 DPE_YCrCb_422_P, 384 DPE_YCbCr_420_P, 385 DPE_YCrCb_420_P, 386 /* YUV Package */ 387 DPE_YUYV_422_Pkg, 388 DPE_UYVY_422_Pkg, 389 DPE_YVYU_422_Pkg, 390 DPE_VYUY_422_Pkg, 391 }; 392 393 #endif 394