1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #ifndef __SMU_V11_0_H__ 24 #define __SMU_V11_0_H__ 25 26 #include "amdgpu_smu.h" 27 28 #define SMU11_DRIVER_IF_VERSION_INV 0xFFFFFFFF 29 #define SMU11_DRIVER_IF_VERSION_ARCT 0x17 30 #define SMU11_DRIVER_IF_VERSION_NV10 0x36 31 #define SMU11_DRIVER_IF_VERSION_NV12 0x36 32 #define SMU11_DRIVER_IF_VERSION_NV14 0x36 33 #define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x39 34 #define SMU11_DRIVER_IF_VERSION_Navy_Flounder 0x5 35 36 /* MP Apertures */ 37 #define MP0_Public 0x03800000 38 #define MP0_SRAM 0x03900000 39 #define MP1_Public 0x03b00000 40 #define MP1_SRAM 0x03c00004 41 42 /* address block */ 43 #define smnMP1_FIRMWARE_FLAGS 0x3010024 44 #define smnMP0_FW_INTF 0x30101c0 45 #define smnMP1_PUB_CTRL 0x3010b14 46 47 #define TEMP_RANGE_MIN (0) 48 #define TEMP_RANGE_MAX (80 * 1000) 49 50 #define SMU11_TOOL_SIZE 0x19000 51 52 #define MAX_DPM_LEVELS 16 53 #define MAX_PCIE_CONF 2 54 55 #define CTF_OFFSET_EDGE 5 56 #define CTF_OFFSET_HOTSPOT 5 57 #define CTF_OFFSET_MEM 5 58 59 static const struct smu_temperature_range smu11_thermal_policy[] = 60 { 61 {-273150, 99000, 99000, -273150, 99000, 99000, -273150, 99000, 99000}, 62 { 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000}, 63 }; 64 65 struct smu_11_0_max_sustainable_clocks { 66 uint32_t display_clock; 67 uint32_t phy_clock; 68 uint32_t pixel_clock; 69 uint32_t uclock; 70 uint32_t dcef_clock; 71 uint32_t soc_clock; 72 }; 73 74 struct smu_11_0_dpm_clk_level { 75 bool enabled; 76 uint32_t value; 77 }; 78 79 struct smu_11_0_dpm_table { 80 uint32_t min; /* MHz */ 81 uint32_t max; /* MHz */ 82 uint32_t count; 83 bool is_fine_grained; 84 struct smu_11_0_dpm_clk_level dpm_levels[MAX_DPM_LEVELS]; 85 }; 86 87 struct smu_11_0_pcie_table { 88 uint8_t pcie_gen[MAX_PCIE_CONF]; 89 uint8_t pcie_lane[MAX_PCIE_CONF]; 90 }; 91 92 struct smu_11_0_dpm_tables { 93 struct smu_11_0_dpm_table soc_table; 94 struct smu_11_0_dpm_table gfx_table; 95 struct smu_11_0_dpm_table uclk_table; 96 struct smu_11_0_dpm_table eclk_table; 97 struct smu_11_0_dpm_table vclk_table; 98 struct smu_11_0_dpm_table vclk1_table; 99 struct smu_11_0_dpm_table dclk_table; 100 struct smu_11_0_dpm_table dclk1_table; 101 struct smu_11_0_dpm_table dcef_table; 102 struct smu_11_0_dpm_table pixel_table; 103 struct smu_11_0_dpm_table display_table; 104 struct smu_11_0_dpm_table phy_table; 105 struct smu_11_0_dpm_table fclk_table; 106 struct smu_11_0_pcie_table pcie_table; 107 }; 108 109 struct smu_11_0_dpm_context { 110 struct smu_11_0_dpm_tables dpm_tables; 111 uint32_t workload_policy_mask; 112 uint32_t dcef_min_ds_clk; 113 }; 114 115 enum smu_11_0_power_state { 116 SMU_11_0_POWER_STATE__D0 = 0, 117 SMU_11_0_POWER_STATE__D1, 118 SMU_11_0_POWER_STATE__D3, /* Sleep*/ 119 SMU_11_0_POWER_STATE__D4, /* Hibernate*/ 120 SMU_11_0_POWER_STATE__D5, /* Power off*/ 121 }; 122 123 struct smu_11_0_power_context { 124 uint32_t power_source; 125 uint8_t in_power_limit_boost_mode; 126 enum smu_11_0_power_state power_state; 127 }; 128 129 enum smu_v11_0_baco_seq { 130 BACO_SEQ_BACO = 0, 131 BACO_SEQ_MSR, 132 BACO_SEQ_BAMACO, 133 BACO_SEQ_ULPS, 134 BACO_SEQ_COUNT, 135 }; 136 137 #if defined(SWSMU_CODE_LAYER_L2) || defined(SWSMU_CODE_LAYER_L3) 138 139 int smu_v11_0_init_microcode(struct smu_context *smu); 140 141 void smu_v11_0_fini_microcode(struct smu_context *smu); 142 143 int smu_v11_0_load_microcode(struct smu_context *smu); 144 145 int smu_v11_0_init_smc_tables(struct smu_context *smu); 146 147 int smu_v11_0_fini_smc_tables(struct smu_context *smu); 148 149 int smu_v11_0_init_power(struct smu_context *smu); 150 151 int smu_v11_0_fini_power(struct smu_context *smu); 152 153 int smu_v11_0_check_fw_status(struct smu_context *smu); 154 155 int smu_v11_0_setup_pptable(struct smu_context *smu); 156 157 int smu_v11_0_get_vbios_bootup_values(struct smu_context *smu); 158 159 int smu_v11_0_check_fw_version(struct smu_context *smu); 160 161 int smu_v11_0_set_driver_table_location(struct smu_context *smu); 162 163 int smu_v11_0_set_tool_table_location(struct smu_context *smu); 164 165 int smu_v11_0_notify_memory_pool_location(struct smu_context *smu); 166 167 int smu_v11_0_system_features_control(struct smu_context *smu, 168 bool en); 169 170 int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count); 171 172 int smu_v11_0_set_allowed_mask(struct smu_context *smu); 173 174 int smu_v11_0_notify_display_change(struct smu_context *smu); 175 176 int smu_v11_0_get_current_power_limit(struct smu_context *smu, 177 uint32_t *power_limit); 178 179 int smu_v11_0_set_power_limit(struct smu_context *smu, uint32_t n); 180 181 int smu_v11_0_init_max_sustainable_clocks(struct smu_context *smu); 182 183 int smu_v11_0_enable_thermal_alert(struct smu_context *smu); 184 185 int smu_v11_0_disable_thermal_alert(struct smu_context *smu); 186 187 int smu_v11_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value); 188 189 int smu_v11_0_set_min_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk); 190 191 int 192 smu_v11_0_display_clock_voltage_request(struct smu_context *smu, 193 struct pp_display_clock_request 194 *clock_req); 195 196 uint32_t 197 smu_v11_0_get_fan_control_mode(struct smu_context *smu); 198 199 int 200 smu_v11_0_set_fan_control_mode(struct smu_context *smu, 201 uint32_t mode); 202 203 int 204 smu_v11_0_set_fan_speed_percent(struct smu_context *smu, uint32_t speed); 205 206 int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu, 207 uint32_t speed); 208 209 int smu_v11_0_get_fan_speed_rpm(struct smu_context *smu, 210 uint32_t *speed); 211 212 int smu_v11_0_set_xgmi_pstate(struct smu_context *smu, 213 uint32_t pstate); 214 215 int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable); 216 217 int smu_v11_0_register_irq_handler(struct smu_context *smu); 218 219 int smu_v11_0_set_azalia_d3_pme(struct smu_context *smu); 220 221 int smu_v11_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu, 222 struct pp_smu_nv_clock_table *max_clocks); 223 224 bool smu_v11_0_baco_is_support(struct smu_context *smu); 225 226 enum smu_baco_state smu_v11_0_baco_get_state(struct smu_context *smu); 227 228 int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state); 229 230 int smu_v11_0_baco_enter(struct smu_context *smu); 231 int smu_v11_0_baco_exit(struct smu_context *smu); 232 233 int smu_v11_0_mode1_reset(struct smu_context *smu); 234 235 int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type, 236 uint32_t *min, uint32_t *max); 237 238 int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type, 239 uint32_t min, uint32_t max); 240 241 int smu_v11_0_set_hard_freq_limited_range(struct smu_context *smu, 242 enum smu_clk_type clk_type, 243 uint32_t min, 244 uint32_t max); 245 246 int smu_v11_0_set_performance_level(struct smu_context *smu, 247 enum amd_dpm_forced_level level); 248 249 int smu_v11_0_set_power_source(struct smu_context *smu, 250 enum smu_power_src_type power_src); 251 252 int smu_v11_0_get_dpm_freq_by_index(struct smu_context *smu, 253 enum smu_clk_type clk_type, 254 uint16_t level, 255 uint32_t *value); 256 257 int smu_v11_0_get_dpm_level_count(struct smu_context *smu, 258 enum smu_clk_type clk_type, 259 uint32_t *value); 260 261 int smu_v11_0_set_single_dpm_table(struct smu_context *smu, 262 enum smu_clk_type clk_type, 263 struct smu_11_0_dpm_table *single_dpm_table); 264 265 int smu_v11_0_get_dpm_level_range(struct smu_context *smu, 266 enum smu_clk_type clk_type, 267 uint32_t *min_value, 268 uint32_t *max_value); 269 270 int smu_v11_0_get_current_pcie_link_width_level(struct smu_context *smu); 271 272 int smu_v11_0_get_current_pcie_link_width(struct smu_context *smu); 273 274 int smu_v11_0_get_current_pcie_link_speed_level(struct smu_context *smu); 275 276 int smu_v11_0_get_current_pcie_link_speed(struct smu_context *smu); 277 278 void smu_v11_0_init_gpu_metrics_v1_0(struct gpu_metrics_v1_0 *gpu_metrics); 279 280 int smu_v11_0_gfx_ulv_control(struct smu_context *smu, 281 bool enablement); 282 283 int smu_v11_0_deep_sleep_control(struct smu_context *smu, 284 bool enablement); 285 286 void smu_v11_0_interrupt_work(struct smu_context *smu); 287 288 #endif 289 #endif 290