1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Marvell OcteonTx2 RVU Admin Function driver 3 * 4 * Copyright (C) 2018 Marvell International Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #ifndef NPC_H 12 #define NPC_H 13 14 enum NPC_LID_E { 15 NPC_LID_LA = 0, 16 NPC_LID_LB, 17 NPC_LID_LC, 18 NPC_LID_LD, 19 NPC_LID_LE, 20 NPC_LID_LF, 21 NPC_LID_LG, 22 NPC_LID_LH, 23 }; 24 25 #define NPC_LT_NA 0 26 27 enum npc_kpu_la_ltype { 28 NPC_LT_LA_8023 = 1, 29 NPC_LT_LA_ETHER, 30 NPC_LT_LA_IH_NIX_ETHER, 31 NPC_LT_LA_IH_8_ETHER, 32 NPC_LT_LA_IH_4_ETHER, 33 NPC_LT_LA_IH_2_ETHER, 34 NPC_LT_LA_HIGIG2_ETHER, 35 NPC_LT_LA_IH_NIX_HIGIG2_ETHER, 36 NPC_LT_LA_CUSTOM0 = 0xE, 37 NPC_LT_LA_CUSTOM1 = 0xF, 38 }; 39 40 enum npc_kpu_lb_ltype { 41 NPC_LT_LB_ETAG = 1, 42 NPC_LT_LB_CTAG, 43 NPC_LT_LB_STAG_QINQ, 44 NPC_LT_LB_BTAG, 45 NPC_LT_LB_ITAG, 46 NPC_LT_LB_DSA, 47 NPC_LT_LB_DSA_VLAN, 48 NPC_LT_LB_EDSA, 49 NPC_LT_LB_EDSA_VLAN, 50 NPC_LT_LB_EXDSA, 51 NPC_LT_LB_EXDSA_VLAN, 52 NPC_LT_LB_FDSA, 53 NPC_LT_LB_CUSTOM0 = 0xE, 54 NPC_LT_LB_CUSTOM1 = 0xF, 55 }; 56 57 enum npc_kpu_lc_ltype { 58 NPC_LT_LC_IP = 1, 59 NPC_LT_LC_IP_OPT, 60 NPC_LT_LC_IP6, 61 NPC_LT_LC_IP6_EXT, 62 NPC_LT_LC_ARP, 63 NPC_LT_LC_RARP, 64 NPC_LT_LC_MPLS, 65 NPC_LT_LC_NSH, 66 NPC_LT_LC_PTP, 67 NPC_LT_LC_FCOE, 68 NPC_LT_LC_CUSTOM0 = 0xE, 69 NPC_LT_LC_CUSTOM1 = 0xF, 70 }; 71 72 /* Don't modify Ltypes upto SCTP, otherwise it will 73 * effect flow tag calculation and thus RSS. 74 */ 75 enum npc_kpu_ld_ltype { 76 NPC_LT_LD_TCP = 1, 77 NPC_LT_LD_UDP, 78 NPC_LT_LD_ICMP, 79 NPC_LT_LD_SCTP, 80 NPC_LT_LD_ICMP6, 81 NPC_LT_LD_CUSTOM0, 82 NPC_LT_LD_CUSTOM1, 83 NPC_LT_LD_IGMP = 8, 84 NPC_LT_LD_AH, 85 NPC_LT_LD_GRE, 86 NPC_LT_LD_NVGRE, 87 NPC_LT_LD_NSH, 88 NPC_LT_LD_TU_MPLS_IN_NSH, 89 NPC_LT_LD_TU_MPLS_IN_IP, 90 }; 91 92 enum npc_kpu_le_ltype { 93 NPC_LT_LE_VXLAN = 1, 94 NPC_LT_LE_GENEVE, 95 NPC_LT_LE_ESP, 96 NPC_LT_LE_GTPU = 4, 97 NPC_LT_LE_VXLANGPE, 98 NPC_LT_LE_GTPC, 99 NPC_LT_LE_NSH, 100 NPC_LT_LE_TU_MPLS_IN_GRE, 101 NPC_LT_LE_TU_NSH_IN_GRE, 102 NPC_LT_LE_TU_MPLS_IN_UDP, 103 NPC_LT_LE_CUSTOM0 = 0xE, 104 NPC_LT_LE_CUSTOM1 = 0xF, 105 }; 106 107 enum npc_kpu_lf_ltype { 108 NPC_LT_LF_TU_ETHER = 1, 109 NPC_LT_LF_TU_PPP, 110 NPC_LT_LF_TU_MPLS_IN_VXLANGPE, 111 NPC_LT_LF_TU_NSH_IN_VXLANGPE, 112 NPC_LT_LF_TU_MPLS_IN_NSH, 113 NPC_LT_LF_TU_3RD_NSH, 114 NPC_LT_LF_CUSTOM0 = 0xE, 115 NPC_LT_LF_CUSTOM1 = 0xF, 116 }; 117 118 enum npc_kpu_lg_ltype { 119 NPC_LT_LG_TU_IP = 1, 120 NPC_LT_LG_TU_IP6, 121 NPC_LT_LG_TU_ARP, 122 NPC_LT_LG_TU_ETHER_IN_NSH, 123 NPC_LT_LG_CUSTOM0 = 0xE, 124 NPC_LT_LG_CUSTOM1 = 0xF, 125 }; 126 127 /* Don't modify Ltypes upto SCTP, otherwise it will 128 * effect flow tag calculation and thus RSS. 129 */ 130 enum npc_kpu_lh_ltype { 131 NPC_LT_LH_TU_TCP = 1, 132 NPC_LT_LH_TU_UDP, 133 NPC_LT_LH_TU_ICMP, 134 NPC_LT_LH_TU_SCTP, 135 NPC_LT_LH_TU_ICMP6, 136 NPC_LT_LH_TU_IGMP = 8, 137 NPC_LT_LH_TU_ESP, 138 NPC_LT_LH_TU_AH, 139 NPC_LT_LH_CUSTOM0 = 0xE, 140 NPC_LT_LH_CUSTOM1 = 0xF, 141 }; 142 143 /* NPC port kind defines how the incoming or outgoing packets 144 * are processed. NPC accepts packets from up to 64 pkinds. 145 * Software assigns pkind for each incoming port such as CGX 146 * Ethernet interfaces, LBK interfaces, etc. 147 */ 148 enum npc_pkind_type { 149 NPC_TX_DEF_PKIND = 63ULL, /* NIX-TX PKIND */ 150 }; 151 152 struct npc_kpu_profile_cam { 153 u8 state; 154 u8 state_mask; 155 u16 dp0; 156 u16 dp0_mask; 157 u16 dp1; 158 u16 dp1_mask; 159 u16 dp2; 160 u16 dp2_mask; 161 }; 162 163 struct npc_kpu_profile_action { 164 u8 errlev; 165 u8 errcode; 166 u8 dp0_offset; 167 u8 dp1_offset; 168 u8 dp2_offset; 169 u8 bypass_count; 170 u8 parse_done; 171 u8 next_state; 172 u8 ptr_advance; 173 u8 cap_ena; 174 u8 lid; 175 u8 ltype; 176 u8 flags; 177 u8 offset; 178 u8 mask; 179 u8 right; 180 u8 shift; 181 }; 182 183 struct npc_kpu_profile { 184 int cam_entries; 185 int action_entries; 186 const struct npc_kpu_profile_cam *cam; 187 const struct npc_kpu_profile_action *action; 188 }; 189 190 /* NPC KPU register formats */ 191 struct npc_kpu_cam { 192 #if defined(__BIG_ENDIAN_BITFIELD) 193 u64 rsvd_63_56 : 8; 194 u64 state : 8; 195 u64 dp2_data : 16; 196 u64 dp1_data : 16; 197 u64 dp0_data : 16; 198 #else 199 u64 dp0_data : 16; 200 u64 dp1_data : 16; 201 u64 dp2_data : 16; 202 u64 state : 8; 203 u64 rsvd_63_56 : 8; 204 #endif 205 }; 206 207 struct npc_kpu_action0 { 208 #if defined(__BIG_ENDIAN_BITFIELD) 209 u64 rsvd_63_57 : 7; 210 u64 byp_count : 3; 211 u64 capture_ena : 1; 212 u64 parse_done : 1; 213 u64 next_state : 8; 214 u64 rsvd_43 : 1; 215 u64 capture_lid : 3; 216 u64 capture_ltype : 4; 217 u64 capture_flags : 8; 218 u64 ptr_advance : 8; 219 u64 var_len_offset : 8; 220 u64 var_len_mask : 8; 221 u64 var_len_right : 1; 222 u64 var_len_shift : 3; 223 #else 224 u64 var_len_shift : 3; 225 u64 var_len_right : 1; 226 u64 var_len_mask : 8; 227 u64 var_len_offset : 8; 228 u64 ptr_advance : 8; 229 u64 capture_flags : 8; 230 u64 capture_ltype : 4; 231 u64 capture_lid : 3; 232 u64 rsvd_43 : 1; 233 u64 next_state : 8; 234 u64 parse_done : 1; 235 u64 capture_ena : 1; 236 u64 byp_count : 3; 237 u64 rsvd_63_57 : 7; 238 #endif 239 }; 240 241 struct npc_kpu_action1 { 242 #if defined(__BIG_ENDIAN_BITFIELD) 243 u64 rsvd_63_36 : 28; 244 u64 errlev : 4; 245 u64 errcode : 8; 246 u64 dp2_offset : 8; 247 u64 dp1_offset : 8; 248 u64 dp0_offset : 8; 249 #else 250 u64 dp0_offset : 8; 251 u64 dp1_offset : 8; 252 u64 dp2_offset : 8; 253 u64 errcode : 8; 254 u64 errlev : 4; 255 u64 rsvd_63_36 : 28; 256 #endif 257 }; 258 259 struct npc_kpu_pkind_cpi_def { 260 #if defined(__BIG_ENDIAN_BITFIELD) 261 u64 ena : 1; 262 u64 rsvd_62_59 : 4; 263 u64 lid : 3; 264 u64 ltype_match : 4; 265 u64 ltype_mask : 4; 266 u64 flags_match : 8; 267 u64 flags_mask : 8; 268 u64 add_offset : 8; 269 u64 add_mask : 8; 270 u64 rsvd_15 : 1; 271 u64 add_shift : 3; 272 u64 rsvd_11_10 : 2; 273 u64 cpi_base : 10; 274 #else 275 u64 cpi_base : 10; 276 u64 rsvd_11_10 : 2; 277 u64 add_shift : 3; 278 u64 rsvd_15 : 1; 279 u64 add_mask : 8; 280 u64 add_offset : 8; 281 u64 flags_mask : 8; 282 u64 flags_match : 8; 283 u64 ltype_mask : 4; 284 u64 ltype_match : 4; 285 u64 lid : 3; 286 u64 rsvd_62_59 : 4; 287 u64 ena : 1; 288 #endif 289 }; 290 291 struct nix_rx_action { 292 #if defined(__BIG_ENDIAN_BITFIELD) 293 u64 rsvd_63_61 :3; 294 u64 flow_key_alg :5; 295 u64 match_id :16; 296 u64 index :20; 297 u64 pf_func :16; 298 u64 op :4; 299 #else 300 u64 op :4; 301 u64 pf_func :16; 302 u64 index :20; 303 u64 match_id :16; 304 u64 flow_key_alg :5; 305 u64 rsvd_63_61 :3; 306 #endif 307 }; 308 309 /* NPC_AF_INTFX_KEX_CFG field masks */ 310 #define NPC_PARSE_NIBBLE GENMASK_ULL(30, 0) 311 312 /* NPC_PARSE_KEX_S nibble definitions for each field */ 313 #define NPC_PARSE_NIBBLE_CHAN GENMASK_ULL(2, 0) 314 #define NPC_PARSE_NIBBLE_ERRLEV BIT_ULL(3) 315 #define NPC_PARSE_NIBBLE_ERRCODE GENMASK_ULL(5, 4) 316 #define NPC_PARSE_NIBBLE_L2L3_BCAST BIT_ULL(6) 317 #define NPC_PARSE_NIBBLE_LA_FLAGS GENMASK_ULL(8, 7) 318 #define NPC_PARSE_NIBBLE_LA_LTYPE BIT_ULL(9) 319 #define NPC_PARSE_NIBBLE_LB_FLAGS GENMASK_ULL(11, 10) 320 #define NPC_PARSE_NIBBLE_LB_LTYPE BIT_ULL(12) 321 #define NPC_PARSE_NIBBLE_LC_FLAGS GENMASK_ULL(14, 13) 322 #define NPC_PARSE_NIBBLE_LC_LTYPE BIT_ULL(15) 323 #define NPC_PARSE_NIBBLE_LD_FLAGS GENMASK_ULL(17, 16) 324 #define NPC_PARSE_NIBBLE_LD_LTYPE BIT_ULL(18) 325 #define NPC_PARSE_NIBBLE_LE_FLAGS GENMASK_ULL(20, 19) 326 #define NPC_PARSE_NIBBLE_LE_LTYPE BIT_ULL(21) 327 #define NPC_PARSE_NIBBLE_LF_FLAGS GENMASK_ULL(23, 22) 328 #define NPC_PARSE_NIBBLE_LF_LTYPE BIT_ULL(24) 329 #define NPC_PARSE_NIBBLE_LG_FLAGS GENMASK_ULL(26, 25) 330 #define NPC_PARSE_NIBBLE_LG_LTYPE BIT_ULL(27) 331 #define NPC_PARSE_NIBBLE_LH_FLAGS GENMASK_ULL(29, 28) 332 #define NPC_PARSE_NIBBLE_LH_LTYPE BIT_ULL(30) 333 334 /* NIX Receive Vtag Action Structure */ 335 #define VTAG0_VALID_BIT BIT_ULL(15) 336 #define VTAG0_TYPE_MASK GENMASK_ULL(14, 12) 337 #define VTAG0_LID_MASK GENMASK_ULL(10, 8) 338 #define VTAG0_RELPTR_MASK GENMASK_ULL(7, 0) 339 340 struct npc_mcam_kex { 341 /* MKEX Profle Header */ 342 u64 mkex_sign; /* "mcam-kex-profile" (8 bytes/ASCII characters) */ 343 u8 name[MKEX_NAME_LEN]; /* MKEX Profile name */ 344 u64 cpu_model; /* Format as profiled by CPU hardware */ 345 u64 kpu_version; /* KPU firmware/profile version */ 346 u64 reserved; /* Reserved for extension */ 347 348 /* MKEX Profle Data */ 349 u64 keyx_cfg[NPC_MAX_INTF]; /* NPC_AF_INTF(0..1)_KEX_CFG */ 350 /* NPC_AF_KEX_LDATA(0..1)_FLAGS_CFG */ 351 u64 kex_ld_flags[NPC_MAX_LD]; 352 /* NPC_AF_INTF(0..1)_LID(0..7)_LT(0..15)_LD(0..1)_CFG */ 353 u64 intf_lid_lt_ld[NPC_MAX_INTF][NPC_MAX_LID][NPC_MAX_LT][NPC_MAX_LD]; 354 /* NPC_AF_INTF(0..1)_LDATA(0..1)_FLAGS(0..15)_CFG */ 355 u64 intf_ld_flags[NPC_MAX_INTF][NPC_MAX_LD][NPC_MAX_LFL]; 356 } __packed; 357 358 struct npc_lt_def { 359 u8 ltype_mask; 360 u8 ltype_match; 361 u8 lid; 362 } __packed; 363 364 struct npc_lt_def_ipsec { 365 u8 ltype_mask; 366 u8 ltype_match; 367 u8 lid; 368 u8 spi_offset; 369 u8 spi_nz; 370 } __packed; 371 372 struct npc_lt_def_cfg { 373 struct npc_lt_def rx_ol2; 374 struct npc_lt_def rx_oip4; 375 struct npc_lt_def rx_iip4; 376 struct npc_lt_def rx_oip6; 377 struct npc_lt_def rx_iip6; 378 struct npc_lt_def rx_otcp; 379 struct npc_lt_def rx_itcp; 380 struct npc_lt_def rx_oudp; 381 struct npc_lt_def rx_iudp; 382 struct npc_lt_def rx_osctp; 383 struct npc_lt_def rx_isctp; 384 struct npc_lt_def_ipsec rx_ipsec[2]; 385 struct npc_lt_def pck_ol2; 386 struct npc_lt_def pck_oip4; 387 struct npc_lt_def pck_oip6; 388 struct npc_lt_def pck_iip4; 389 }; 390 391 #endif /* NPC_H */ 392