1 // SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only)
2 /* Copyright(c) 2014 - 2020 Intel Corporation */
3 #include "adf_accel_devices.h"
4 #include "adf_common_drv.h"
5 #include "adf_transport_internal.h"
6
7 #define ADF_ARB_NUM 4
8 #define ADF_ARB_REG_SIZE 0x4
9 #define ADF_ARB_WTR_SIZE 0x20
10 #define ADF_ARB_OFFSET 0x30000
11 #define ADF_ARB_REG_SLOT 0x1000
12 #define ADF_ARB_WTR_OFFSET 0x010
13 #define ADF_ARB_RO_EN_OFFSET 0x090
14 #define ADF_ARB_WQCFG_OFFSET 0x100
15 #define ADF_ARB_WRK_2_SER_MAP_OFFSET 0x180
16 #define ADF_ARB_RINGSRVARBEN_OFFSET 0x19C
17
18 #define WRITE_CSR_ARB_RINGSRVARBEN(csr_addr, index, value) \
19 ADF_CSR_WR(csr_addr, ADF_ARB_RINGSRVARBEN_OFFSET + \
20 (ADF_ARB_REG_SLOT * index), value)
21
22 #define WRITE_CSR_ARB_SARCONFIG(csr_addr, index, value) \
23 ADF_CSR_WR(csr_addr, ADF_ARB_OFFSET + \
24 (ADF_ARB_REG_SIZE * index), value)
25
26 #define WRITE_CSR_ARB_WRK_2_SER_MAP(csr_addr, index, value) \
27 ADF_CSR_WR(csr_addr, (ADF_ARB_OFFSET + \
28 ADF_ARB_WRK_2_SER_MAP_OFFSET) + \
29 (ADF_ARB_REG_SIZE * index), value)
30
31 #define WRITE_CSR_ARB_WQCFG(csr_addr, index, value) \
32 ADF_CSR_WR(csr_addr, (ADF_ARB_OFFSET + \
33 ADF_ARB_WQCFG_OFFSET) + (ADF_ARB_REG_SIZE * index), value)
34
adf_init_arb(struct adf_accel_dev * accel_dev)35 int adf_init_arb(struct adf_accel_dev *accel_dev)
36 {
37 struct adf_hw_device_data *hw_data = accel_dev->hw_device;
38 void __iomem *csr = accel_dev->transport->banks[0].csr_addr;
39 u32 arb_cfg = 0x1 << 31 | 0x4 << 4 | 0x1;
40 u32 arb, i;
41 const u32 *thd_2_arb_cfg;
42
43 /* Service arb configured for 32 bytes responses and
44 * ring flow control check enabled. */
45 for (arb = 0; arb < ADF_ARB_NUM; arb++)
46 WRITE_CSR_ARB_SARCONFIG(csr, arb, arb_cfg);
47
48 /* Setup worker queue registers */
49 for (i = 0; i < hw_data->num_engines; i++)
50 WRITE_CSR_ARB_WQCFG(csr, i, i);
51
52 /* Map worker threads to service arbiters */
53 hw_data->get_arb_mapping(accel_dev, &thd_2_arb_cfg);
54
55 if (!thd_2_arb_cfg)
56 return -EFAULT;
57
58 for (i = 0; i < hw_data->num_engines; i++)
59 WRITE_CSR_ARB_WRK_2_SER_MAP(csr, i, *(thd_2_arb_cfg + i));
60
61 return 0;
62 }
63 EXPORT_SYMBOL_GPL(adf_init_arb);
64
adf_update_ring_arb(struct adf_etr_ring_data * ring)65 void adf_update_ring_arb(struct adf_etr_ring_data *ring)
66 {
67 WRITE_CSR_ARB_RINGSRVARBEN(ring->bank->csr_addr,
68 ring->bank->bank_number,
69 ring->bank->ring_mask & 0xFF);
70 }
71
adf_exit_arb(struct adf_accel_dev * accel_dev)72 void adf_exit_arb(struct adf_accel_dev *accel_dev)
73 {
74 struct adf_hw_device_data *hw_data = accel_dev->hw_device;
75 void __iomem *csr;
76 unsigned int i;
77
78 if (!accel_dev->transport)
79 return;
80
81 csr = accel_dev->transport->banks[0].csr_addr;
82
83 /* Reset arbiter configuration */
84 for (i = 0; i < ADF_ARB_NUM; i++)
85 WRITE_CSR_ARB_SARCONFIG(csr, i, 0);
86
87 /* Shutdown work queue */
88 for (i = 0; i < hw_data->num_engines; i++)
89 WRITE_CSR_ARB_WQCFG(csr, i, 0);
90
91 /* Unmap worker threads to service arbiters */
92 for (i = 0; i < hw_data->num_engines; i++)
93 WRITE_CSR_ARB_WRK_2_SER_MAP(csr, i, 0);
94
95 /* Disable arbitration on all rings */
96 for (i = 0; i < GET_MAX_BANKS(accel_dev); i++)
97 WRITE_CSR_ARB_RINGSRVARBEN(csr, i, 0);
98 }
99 EXPORT_SYMBOL_GPL(adf_exit_arb);
100