1 /*
2 * Copyright 2018 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 *
23 */
24 #include <linux/list.h>
25 #include "amdgpu.h"
26 #include "amdgpu_xgmi.h"
27 #include "amdgpu_smu.h"
28 #include "amdgpu_ras.h"
29 #include "soc15.h"
30 #include "df/df_3_6_offset.h"
31 #include "xgmi/xgmi_4_0_0_smn.h"
32 #include "xgmi/xgmi_4_0_0_sh_mask.h"
33 #include "wafl/wafl2_4_0_0_smn.h"
34 #include "wafl/wafl2_4_0_0_sh_mask.h"
35
36 static DEFINE_MUTEX(xgmi_mutex);
37
38 #define AMDGPU_MAX_XGMI_DEVICE_PER_HIVE 4
39
40 static LIST_HEAD(xgmi_hive_list);
41
42 static const int xgmi_pcs_err_status_reg_vg20[] = {
43 smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS,
44 smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x100000,
45 };
46
47 static const int wafl_pcs_err_status_reg_vg20[] = {
48 smnPCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS,
49 smnPCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS + 0x100000,
50 };
51
52 static const int xgmi_pcs_err_status_reg_arct[] = {
53 smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS,
54 smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x100000,
55 smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x500000,
56 smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x600000,
57 smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x700000,
58 smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x800000,
59 };
60
61 /* same as vg20*/
62 static const int wafl_pcs_err_status_reg_arct[] = {
63 smnPCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS,
64 smnPCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS + 0x100000,
65 };
66
67 static const struct amdgpu_pcs_ras_field xgmi_pcs_ras_fields[] = {
68 {"XGMI PCS DataLossErr",
69 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, DataLossErr)},
70 {"XGMI PCS TrainingErr",
71 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, TrainingErr)},
72 {"XGMI PCS CRCErr",
73 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, CRCErr)},
74 {"XGMI PCS BERExceededErr",
75 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, BERExceededErr)},
76 {"XGMI PCS TxMetaDataErr",
77 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, TxMetaDataErr)},
78 {"XGMI PCS ReplayBufParityErr",
79 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ReplayBufParityErr)},
80 {"XGMI PCS DataParityErr",
81 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, DataParityErr)},
82 {"XGMI PCS ReplayFifoOverflowErr",
83 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ReplayFifoOverflowErr)},
84 {"XGMI PCS ReplayFifoUnderflowErr",
85 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ReplayFifoUnderflowErr)},
86 {"XGMI PCS ElasticFifoOverflowErr",
87 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ElasticFifoOverflowErr)},
88 {"XGMI PCS DeskewErr",
89 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, DeskewErr)},
90 {"XGMI PCS DataStartupLimitErr",
91 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, DataStartupLimitErr)},
92 {"XGMI PCS FCInitTimeoutErr",
93 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, FCInitTimeoutErr)},
94 {"XGMI PCS RecoveryTimeoutErr",
95 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, RecoveryTimeoutErr)},
96 {"XGMI PCS ReadySerialTimeoutErr",
97 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ReadySerialTimeoutErr)},
98 {"XGMI PCS ReadySerialAttemptErr",
99 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ReadySerialAttemptErr)},
100 {"XGMI PCS RecoveryAttemptErr",
101 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, RecoveryAttemptErr)},
102 {"XGMI PCS RecoveryRelockAttemptErr",
103 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, RecoveryRelockAttemptErr)},
104 };
105
106 static const struct amdgpu_pcs_ras_field wafl_pcs_ras_fields[] = {
107 {"WAFL PCS DataLossErr",
108 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, DataLossErr)},
109 {"WAFL PCS TrainingErr",
110 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, TrainingErr)},
111 {"WAFL PCS CRCErr",
112 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, CRCErr)},
113 {"WAFL PCS BERExceededErr",
114 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, BERExceededErr)},
115 {"WAFL PCS TxMetaDataErr",
116 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, TxMetaDataErr)},
117 {"WAFL PCS ReplayBufParityErr",
118 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ReplayBufParityErr)},
119 {"WAFL PCS DataParityErr",
120 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, DataParityErr)},
121 {"WAFL PCS ReplayFifoOverflowErr",
122 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ReplayFifoOverflowErr)},
123 {"WAFL PCS ReplayFifoUnderflowErr",
124 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ReplayFifoUnderflowErr)},
125 {"WAFL PCS ElasticFifoOverflowErr",
126 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ElasticFifoOverflowErr)},
127 {"WAFL PCS DeskewErr",
128 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, DeskewErr)},
129 {"WAFL PCS DataStartupLimitErr",
130 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, DataStartupLimitErr)},
131 {"WAFL PCS FCInitTimeoutErr",
132 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, FCInitTimeoutErr)},
133 {"WAFL PCS RecoveryTimeoutErr",
134 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, RecoveryTimeoutErr)},
135 {"WAFL PCS ReadySerialTimeoutErr",
136 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ReadySerialTimeoutErr)},
137 {"WAFL PCS ReadySerialAttemptErr",
138 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ReadySerialAttemptErr)},
139 {"WAFL PCS RecoveryAttemptErr",
140 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, RecoveryAttemptErr)},
141 {"WAFL PCS RecoveryRelockAttemptErr",
142 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, RecoveryRelockAttemptErr)},
143 };
144
145 /**
146 * DOC: AMDGPU XGMI Support
147 *
148 * XGMI is a high speed interconnect that joins multiple GPU cards
149 * into a homogeneous memory space that is organized by a collective
150 * hive ID and individual node IDs, both of which are 64-bit numbers.
151 *
152 * The file xgmi_device_id contains the unique per GPU device ID and
153 * is stored in the /sys/class/drm/card${cardno}/device/ directory.
154 *
155 * Inside the device directory a sub-directory 'xgmi_hive_info' is
156 * created which contains the hive ID and the list of nodes.
157 *
158 * The hive ID is stored in:
159 * /sys/class/drm/card${cardno}/device/xgmi_hive_info/xgmi_hive_id
160 *
161 * The node information is stored in numbered directories:
162 * /sys/class/drm/card${cardno}/device/xgmi_hive_info/node${nodeno}/xgmi_device_id
163 *
164 * Each device has their own xgmi_hive_info direction with a mirror
165 * set of node sub-directories.
166 *
167 * The XGMI memory space is built by contiguously adding the power of
168 * two padded VRAM space from each node to each other.
169 *
170 */
171
172 static struct attribute amdgpu_xgmi_hive_id = {
173 .name = "xgmi_hive_id",
174 .mode = S_IRUGO
175 };
176
177 static struct attribute *amdgpu_xgmi_hive_attrs[] = {
178 &amdgpu_xgmi_hive_id,
179 NULL
180 };
181
amdgpu_xgmi_show_attrs(struct kobject * kobj,struct attribute * attr,char * buf)182 static ssize_t amdgpu_xgmi_show_attrs(struct kobject *kobj,
183 struct attribute *attr, char *buf)
184 {
185 struct amdgpu_hive_info *hive = container_of(
186 kobj, struct amdgpu_hive_info, kobj);
187
188 if (attr == &amdgpu_xgmi_hive_id)
189 return snprintf(buf, PAGE_SIZE, "%llu\n", hive->hive_id);
190
191 return 0;
192 }
193
amdgpu_xgmi_hive_release(struct kobject * kobj)194 static void amdgpu_xgmi_hive_release(struct kobject *kobj)
195 {
196 struct amdgpu_hive_info *hive = container_of(
197 kobj, struct amdgpu_hive_info, kobj);
198
199 mutex_destroy(&hive->hive_lock);
200 kfree(hive);
201 }
202
203 static const struct sysfs_ops amdgpu_xgmi_hive_ops = {
204 .show = amdgpu_xgmi_show_attrs,
205 };
206
207 struct kobj_type amdgpu_xgmi_hive_type = {
208 .release = amdgpu_xgmi_hive_release,
209 .sysfs_ops = &amdgpu_xgmi_hive_ops,
210 .default_attrs = amdgpu_xgmi_hive_attrs,
211 };
212
amdgpu_xgmi_show_device_id(struct device * dev,struct device_attribute * attr,char * buf)213 static ssize_t amdgpu_xgmi_show_device_id(struct device *dev,
214 struct device_attribute *attr,
215 char *buf)
216 {
217 struct drm_device *ddev = dev_get_drvdata(dev);
218 struct amdgpu_device *adev = drm_to_adev(ddev);
219
220 return snprintf(buf, PAGE_SIZE, "%llu\n", adev->gmc.xgmi.node_id);
221
222 }
223
224 #define AMDGPU_XGMI_SET_FICAA(o) ((o) | 0x456801)
amdgpu_xgmi_show_error(struct device * dev,struct device_attribute * attr,char * buf)225 static ssize_t amdgpu_xgmi_show_error(struct device *dev,
226 struct device_attribute *attr,
227 char *buf)
228 {
229 struct drm_device *ddev = dev_get_drvdata(dev);
230 struct amdgpu_device *adev = drm_to_adev(ddev);
231 uint32_t ficaa_pie_ctl_in, ficaa_pie_status_in;
232 uint64_t fica_out;
233 unsigned int error_count = 0;
234
235 ficaa_pie_ctl_in = AMDGPU_XGMI_SET_FICAA(0x200);
236 ficaa_pie_status_in = AMDGPU_XGMI_SET_FICAA(0x208);
237
238 fica_out = adev->df.funcs->get_fica(adev, ficaa_pie_ctl_in);
239 if (fica_out != 0x1f)
240 pr_err("xGMI error counters not enabled!\n");
241
242 fica_out = adev->df.funcs->get_fica(adev, ficaa_pie_status_in);
243
244 if ((fica_out & 0xffff) == 2)
245 error_count = ((fica_out >> 62) & 0x1) + (fica_out >> 63);
246
247 adev->df.funcs->set_fica(adev, ficaa_pie_status_in, 0, 0);
248
249 return snprintf(buf, PAGE_SIZE, "%d\n", error_count);
250 }
251
252
253 static DEVICE_ATTR(xgmi_device_id, S_IRUGO, amdgpu_xgmi_show_device_id, NULL);
254 static DEVICE_ATTR(xgmi_error, S_IRUGO, amdgpu_xgmi_show_error, NULL);
255
amdgpu_xgmi_sysfs_add_dev_info(struct amdgpu_device * adev,struct amdgpu_hive_info * hive)256 static int amdgpu_xgmi_sysfs_add_dev_info(struct amdgpu_device *adev,
257 struct amdgpu_hive_info *hive)
258 {
259 int ret = 0;
260 char node[10] = { 0 };
261
262 /* Create xgmi device id file */
263 ret = device_create_file(adev->dev, &dev_attr_xgmi_device_id);
264 if (ret) {
265 dev_err(adev->dev, "XGMI: Failed to create device file xgmi_device_id\n");
266 return ret;
267 }
268
269 /* Create xgmi error file */
270 ret = device_create_file(adev->dev, &dev_attr_xgmi_error);
271 if (ret)
272 pr_err("failed to create xgmi_error\n");
273
274
275 /* Create sysfs link to hive info folder on the first device */
276 if (hive->kobj.parent != (&adev->dev->kobj)) {
277 ret = sysfs_create_link(&adev->dev->kobj, &hive->kobj,
278 "xgmi_hive_info");
279 if (ret) {
280 dev_err(adev->dev, "XGMI: Failed to create link to hive info");
281 goto remove_file;
282 }
283 }
284
285 sprintf(node, "node%d", atomic_read(&hive->number_devices));
286 /* Create sysfs link form the hive folder to yourself */
287 ret = sysfs_create_link(&hive->kobj, &adev->dev->kobj, node);
288 if (ret) {
289 dev_err(adev->dev, "XGMI: Failed to create link from hive info");
290 goto remove_link;
291 }
292
293 goto success;
294
295
296 remove_link:
297 sysfs_remove_link(&adev->dev->kobj, adev_to_drm(adev)->unique);
298
299 remove_file:
300 device_remove_file(adev->dev, &dev_attr_xgmi_device_id);
301
302 success:
303 return ret;
304 }
305
amdgpu_xgmi_sysfs_rem_dev_info(struct amdgpu_device * adev,struct amdgpu_hive_info * hive)306 static void amdgpu_xgmi_sysfs_rem_dev_info(struct amdgpu_device *adev,
307 struct amdgpu_hive_info *hive)
308 {
309 char node[10];
310 memset(node, 0, sizeof(node));
311
312 device_remove_file(adev->dev, &dev_attr_xgmi_device_id);
313 device_remove_file(adev->dev, &dev_attr_xgmi_error);
314
315 if (hive->kobj.parent != (&adev->dev->kobj))
316 sysfs_remove_link(&adev->dev->kobj,"xgmi_hive_info");
317
318 sprintf(node, "node%d", atomic_read(&hive->number_devices));
319 sysfs_remove_link(&hive->kobj, node);
320
321 }
322
323
324
amdgpu_get_xgmi_hive(struct amdgpu_device * adev)325 struct amdgpu_hive_info *amdgpu_get_xgmi_hive(struct amdgpu_device *adev)
326 {
327 struct amdgpu_hive_info *hive = NULL, *tmp = NULL;
328 int ret;
329
330 if (!adev->gmc.xgmi.hive_id)
331 return NULL;
332
333 if (adev->hive) {
334 kobject_get(&adev->hive->kobj);
335 return adev->hive;
336 }
337
338 mutex_lock(&xgmi_mutex);
339
340 if (!list_empty(&xgmi_hive_list)) {
341 list_for_each_entry_safe(hive, tmp, &xgmi_hive_list, node) {
342 if (hive->hive_id == adev->gmc.xgmi.hive_id)
343 goto pro_end;
344 }
345 }
346
347 hive = kzalloc(sizeof(*hive), GFP_KERNEL);
348 if (!hive) {
349 dev_err(adev->dev, "XGMI: allocation failed\n");
350 hive = NULL;
351 goto pro_end;
352 }
353
354 /* initialize new hive if not exist */
355 ret = kobject_init_and_add(&hive->kobj,
356 &amdgpu_xgmi_hive_type,
357 &adev->dev->kobj,
358 "%s", "xgmi_hive_info");
359 if (ret) {
360 dev_err(adev->dev, "XGMI: failed initializing kobject for xgmi hive\n");
361 kobject_put(&hive->kobj);
362 kfree(hive);
363 hive = NULL;
364 goto pro_end;
365 }
366
367 hive->hive_id = adev->gmc.xgmi.hive_id;
368 INIT_LIST_HEAD(&hive->device_list);
369 INIT_LIST_HEAD(&hive->node);
370 mutex_init(&hive->hive_lock);
371 atomic_set(&hive->in_reset, 0);
372 atomic_set(&hive->number_devices, 0);
373 task_barrier_init(&hive->tb);
374 hive->pstate = AMDGPU_XGMI_PSTATE_UNKNOWN;
375 hive->hi_req_gpu = NULL;
376 /*
377 * hive pstate on boot is high in vega20 so we have to go to low
378 * pstate on after boot.
379 */
380 hive->hi_req_count = AMDGPU_MAX_XGMI_DEVICE_PER_HIVE;
381 list_add_tail(&hive->node, &xgmi_hive_list);
382
383 pro_end:
384 if (hive)
385 kobject_get(&hive->kobj);
386 mutex_unlock(&xgmi_mutex);
387 return hive;
388 }
389
amdgpu_put_xgmi_hive(struct amdgpu_hive_info * hive)390 void amdgpu_put_xgmi_hive(struct amdgpu_hive_info *hive)
391 {
392 if (hive)
393 kobject_put(&hive->kobj);
394 }
395
amdgpu_xgmi_set_pstate(struct amdgpu_device * adev,int pstate)396 int amdgpu_xgmi_set_pstate(struct amdgpu_device *adev, int pstate)
397 {
398 int ret = 0;
399 struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev);
400 struct amdgpu_device *request_adev = hive->hi_req_gpu ?
401 hive->hi_req_gpu : adev;
402 bool is_hi_req = pstate == AMDGPU_XGMI_PSTATE_MAX_VEGA20;
403 bool init_low = hive->pstate == AMDGPU_XGMI_PSTATE_UNKNOWN;
404
405 amdgpu_put_xgmi_hive(hive);
406 /* fw bug so temporarily disable pstate switching */
407 return 0;
408
409 if (!hive || adev->asic_type != CHIP_VEGA20)
410 return 0;
411
412 mutex_lock(&hive->hive_lock);
413
414 if (is_hi_req)
415 hive->hi_req_count++;
416 else
417 hive->hi_req_count--;
418
419 /*
420 * Vega20 only needs single peer to request pstate high for the hive to
421 * go high but all peers must request pstate low for the hive to go low
422 */
423 if (hive->pstate == pstate ||
424 (!is_hi_req && hive->hi_req_count && !init_low))
425 goto out;
426
427 dev_dbg(request_adev->dev, "Set xgmi pstate %d.\n", pstate);
428
429 ret = amdgpu_dpm_set_xgmi_pstate(request_adev, pstate);
430 if (ret) {
431 dev_err(request_adev->dev,
432 "XGMI: Set pstate failure on device %llx, hive %llx, ret %d",
433 request_adev->gmc.xgmi.node_id,
434 request_adev->gmc.xgmi.hive_id, ret);
435 goto out;
436 }
437
438 if (init_low)
439 hive->pstate = hive->hi_req_count ?
440 hive->pstate : AMDGPU_XGMI_PSTATE_MIN;
441 else {
442 hive->pstate = pstate;
443 hive->hi_req_gpu = pstate != AMDGPU_XGMI_PSTATE_MIN ?
444 adev : NULL;
445 }
446 out:
447 mutex_unlock(&hive->hive_lock);
448 return ret;
449 }
450
amdgpu_xgmi_update_topology(struct amdgpu_hive_info * hive,struct amdgpu_device * adev)451 int amdgpu_xgmi_update_topology(struct amdgpu_hive_info *hive, struct amdgpu_device *adev)
452 {
453 int ret;
454
455 /* Each psp need to set the latest topology */
456 ret = psp_xgmi_set_topology_info(&adev->psp,
457 atomic_read(&hive->number_devices),
458 &adev->psp.xgmi_context.top_info);
459 if (ret)
460 dev_err(adev->dev,
461 "XGMI: Set topology failure on device %llx, hive %llx, ret %d",
462 adev->gmc.xgmi.node_id,
463 adev->gmc.xgmi.hive_id, ret);
464
465 return ret;
466 }
467
468
469 /*
470 * NOTE psp_xgmi_node_info.num_hops layout is as follows:
471 * num_hops[7:6] = link type (0 = xGMI2, 1 = xGMI3, 2/3 = reserved)
472 * num_hops[5:3] = reserved
473 * num_hops[2:0] = number of hops
474 */
amdgpu_xgmi_get_hops_count(struct amdgpu_device * adev,struct amdgpu_device * peer_adev)475 int amdgpu_xgmi_get_hops_count(struct amdgpu_device *adev,
476 struct amdgpu_device *peer_adev)
477 {
478 struct psp_xgmi_topology_info *top = &adev->psp.xgmi_context.top_info;
479 uint8_t num_hops_mask = 0x7;
480 int i;
481
482 for (i = 0 ; i < top->num_nodes; ++i)
483 if (top->nodes[i].node_id == peer_adev->gmc.xgmi.node_id)
484 return top->nodes[i].num_hops & num_hops_mask;
485 return -EINVAL;
486 }
487
amdgpu_xgmi_add_device(struct amdgpu_device * adev)488 int amdgpu_xgmi_add_device(struct amdgpu_device *adev)
489 {
490 struct psp_xgmi_topology_info *top_info;
491 struct amdgpu_hive_info *hive;
492 struct amdgpu_xgmi *entry;
493 struct amdgpu_device *tmp_adev = NULL;
494
495 int count = 0, ret = 0;
496
497 if (!adev->gmc.xgmi.supported)
498 return 0;
499
500 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP)) {
501 ret = psp_xgmi_initialize(&adev->psp);
502 if (ret) {
503 dev_err(adev->dev,
504 "XGMI: Failed to initialize xgmi session\n");
505 return ret;
506 }
507
508 ret = psp_xgmi_get_hive_id(&adev->psp, &adev->gmc.xgmi.hive_id);
509 if (ret) {
510 dev_err(adev->dev,
511 "XGMI: Failed to get hive id\n");
512 return ret;
513 }
514
515 ret = psp_xgmi_get_node_id(&adev->psp, &adev->gmc.xgmi.node_id);
516 if (ret) {
517 dev_err(adev->dev,
518 "XGMI: Failed to get node id\n");
519 return ret;
520 }
521 } else {
522 adev->gmc.xgmi.hive_id = 16;
523 adev->gmc.xgmi.node_id = adev->gmc.xgmi.physical_node_id + 16;
524 }
525
526 hive = amdgpu_get_xgmi_hive(adev);
527 if (!hive) {
528 ret = -EINVAL;
529 dev_err(adev->dev,
530 "XGMI: node 0x%llx, can not match hive 0x%llx in the hive list.\n",
531 adev->gmc.xgmi.node_id, adev->gmc.xgmi.hive_id);
532 goto exit;
533 }
534 mutex_lock(&hive->hive_lock);
535
536 top_info = &adev->psp.xgmi_context.top_info;
537
538 list_add_tail(&adev->gmc.xgmi.head, &hive->device_list);
539 list_for_each_entry(entry, &hive->device_list, head)
540 top_info->nodes[count++].node_id = entry->node_id;
541 top_info->num_nodes = count;
542 atomic_set(&hive->number_devices, count);
543
544 task_barrier_add_task(&hive->tb);
545
546 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP)) {
547 list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) {
548 /* update node list for other device in the hive */
549 if (tmp_adev != adev) {
550 top_info = &tmp_adev->psp.xgmi_context.top_info;
551 top_info->nodes[count - 1].node_id =
552 adev->gmc.xgmi.node_id;
553 top_info->num_nodes = count;
554 }
555 ret = amdgpu_xgmi_update_topology(hive, tmp_adev);
556 if (ret)
557 goto exit_unlock;
558 }
559
560 /* get latest topology info for each device from psp */
561 list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) {
562 ret = psp_xgmi_get_topology_info(&tmp_adev->psp, count,
563 &tmp_adev->psp.xgmi_context.top_info);
564 if (ret) {
565 dev_err(tmp_adev->dev,
566 "XGMI: Get topology failure on device %llx, hive %llx, ret %d",
567 tmp_adev->gmc.xgmi.node_id,
568 tmp_adev->gmc.xgmi.hive_id, ret);
569 /* To do : continue with some node failed or disable the whole hive */
570 goto exit_unlock;
571 }
572 }
573 }
574
575 if (!ret)
576 ret = amdgpu_xgmi_sysfs_add_dev_info(adev, hive);
577
578 exit_unlock:
579 mutex_unlock(&hive->hive_lock);
580 exit:
581 if (!ret) {
582 adev->hive = hive;
583 dev_info(adev->dev, "XGMI: Add node %d, hive 0x%llx.\n",
584 adev->gmc.xgmi.physical_node_id, adev->gmc.xgmi.hive_id);
585 } else {
586 amdgpu_put_xgmi_hive(hive);
587 dev_err(adev->dev, "XGMI: Failed to add node %d, hive 0x%llx ret: %d\n",
588 adev->gmc.xgmi.physical_node_id, adev->gmc.xgmi.hive_id,
589 ret);
590 }
591
592 return ret;
593 }
594
amdgpu_xgmi_remove_device(struct amdgpu_device * adev)595 int amdgpu_xgmi_remove_device(struct amdgpu_device *adev)
596 {
597 struct amdgpu_hive_info *hive = adev->hive;
598
599 if (!adev->gmc.xgmi.supported)
600 return -EINVAL;
601
602 if (!hive)
603 return -EINVAL;
604
605 mutex_lock(&hive->hive_lock);
606 task_barrier_rem_task(&hive->tb);
607 amdgpu_xgmi_sysfs_rem_dev_info(adev, hive);
608 if (hive->hi_req_gpu == adev)
609 hive->hi_req_gpu = NULL;
610 list_del(&adev->gmc.xgmi.head);
611 mutex_unlock(&hive->hive_lock);
612
613 amdgpu_put_xgmi_hive(hive);
614 adev->hive = NULL;
615
616 if (atomic_dec_return(&hive->number_devices) == 0) {
617 /* Remove the hive from global hive list */
618 mutex_lock(&xgmi_mutex);
619 list_del(&hive->node);
620 mutex_unlock(&xgmi_mutex);
621
622 amdgpu_put_xgmi_hive(hive);
623 }
624
625 return 0;
626 }
627
amdgpu_xgmi_ras_late_init(struct amdgpu_device * adev)628 int amdgpu_xgmi_ras_late_init(struct amdgpu_device *adev)
629 {
630 int r;
631 struct ras_ih_if ih_info = {
632 .cb = NULL,
633 };
634 struct ras_fs_if fs_info = {
635 .sysfs_name = "xgmi_wafl_err_count",
636 };
637
638 if (!adev->gmc.xgmi.supported ||
639 adev->gmc.xgmi.num_physical_nodes == 0)
640 return 0;
641
642 amdgpu_xgmi_reset_ras_error_count(adev);
643
644 if (!adev->gmc.xgmi.ras_if) {
645 adev->gmc.xgmi.ras_if = kmalloc(sizeof(struct ras_common_if), GFP_KERNEL);
646 if (!adev->gmc.xgmi.ras_if)
647 return -ENOMEM;
648 adev->gmc.xgmi.ras_if->block = AMDGPU_RAS_BLOCK__XGMI_WAFL;
649 adev->gmc.xgmi.ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
650 adev->gmc.xgmi.ras_if->sub_block_index = 0;
651 strcpy(adev->gmc.xgmi.ras_if->name, "xgmi_wafl");
652 }
653 ih_info.head = fs_info.head = *adev->gmc.xgmi.ras_if;
654 r = amdgpu_ras_late_init(adev, adev->gmc.xgmi.ras_if,
655 &fs_info, &ih_info);
656 if (r || !amdgpu_ras_is_supported(adev, adev->gmc.xgmi.ras_if->block)) {
657 kfree(adev->gmc.xgmi.ras_if);
658 adev->gmc.xgmi.ras_if = NULL;
659 }
660
661 return r;
662 }
663
amdgpu_xgmi_ras_fini(struct amdgpu_device * adev)664 void amdgpu_xgmi_ras_fini(struct amdgpu_device *adev)
665 {
666 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__XGMI_WAFL) &&
667 adev->gmc.xgmi.ras_if) {
668 struct ras_common_if *ras_if = adev->gmc.xgmi.ras_if;
669 struct ras_ih_if ih_info = {
670 .cb = NULL,
671 };
672
673 amdgpu_ras_late_fini(adev, ras_if, &ih_info);
674 kfree(ras_if);
675 }
676 }
677
amdgpu_xgmi_get_relative_phy_addr(struct amdgpu_device * adev,uint64_t addr)678 uint64_t amdgpu_xgmi_get_relative_phy_addr(struct amdgpu_device *adev,
679 uint64_t addr)
680 {
681 struct amdgpu_xgmi *xgmi = &adev->gmc.xgmi;
682 return (addr + xgmi->physical_node_id * xgmi->node_segment_size);
683 }
684
pcs_clear_status(struct amdgpu_device * adev,uint32_t pcs_status_reg)685 static void pcs_clear_status(struct amdgpu_device *adev, uint32_t pcs_status_reg)
686 {
687 WREG32_PCIE(pcs_status_reg, 0xFFFFFFFF);
688 WREG32_PCIE(pcs_status_reg, 0);
689 }
690
amdgpu_xgmi_reset_ras_error_count(struct amdgpu_device * adev)691 void amdgpu_xgmi_reset_ras_error_count(struct amdgpu_device *adev)
692 {
693 uint32_t i;
694
695 switch (adev->asic_type) {
696 case CHIP_ARCTURUS:
697 for (i = 0; i < ARRAY_SIZE(xgmi_pcs_err_status_reg_arct); i++)
698 pcs_clear_status(adev,
699 xgmi_pcs_err_status_reg_arct[i]);
700 break;
701 case CHIP_VEGA20:
702 for (i = 0; i < ARRAY_SIZE(xgmi_pcs_err_status_reg_vg20); i++)
703 pcs_clear_status(adev,
704 xgmi_pcs_err_status_reg_vg20[i]);
705 break;
706 default:
707 break;
708 }
709 }
710
amdgpu_xgmi_query_pcs_error_status(struct amdgpu_device * adev,uint32_t value,uint32_t * ue_count,uint32_t * ce_count,bool is_xgmi_pcs)711 static int amdgpu_xgmi_query_pcs_error_status(struct amdgpu_device *adev,
712 uint32_t value,
713 uint32_t *ue_count,
714 uint32_t *ce_count,
715 bool is_xgmi_pcs)
716 {
717 int i;
718 int ue_cnt;
719
720 if (is_xgmi_pcs) {
721 /* query xgmi pcs error status,
722 * only ue is supported */
723 for (i = 0; i < ARRAY_SIZE(xgmi_pcs_ras_fields); i ++) {
724 ue_cnt = (value &
725 xgmi_pcs_ras_fields[i].pcs_err_mask) >>
726 xgmi_pcs_ras_fields[i].pcs_err_shift;
727 if (ue_cnt) {
728 dev_info(adev->dev, "%s detected\n",
729 xgmi_pcs_ras_fields[i].err_name);
730 *ue_count += ue_cnt;
731 }
732 }
733 } else {
734 /* query wafl pcs error status,
735 * only ue is supported */
736 for (i = 0; i < ARRAY_SIZE(wafl_pcs_ras_fields); i++) {
737 ue_cnt = (value &
738 wafl_pcs_ras_fields[i].pcs_err_mask) >>
739 wafl_pcs_ras_fields[i].pcs_err_shift;
740 if (ue_cnt) {
741 dev_info(adev->dev, "%s detected\n",
742 wafl_pcs_ras_fields[i].err_name);
743 *ue_count += ue_cnt;
744 }
745 }
746 }
747
748 return 0;
749 }
750
amdgpu_xgmi_query_ras_error_count(struct amdgpu_device * adev,void * ras_error_status)751 int amdgpu_xgmi_query_ras_error_count(struct amdgpu_device *adev,
752 void *ras_error_status)
753 {
754 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
755 int i;
756 uint32_t data;
757 uint32_t ue_cnt = 0, ce_cnt = 0;
758
759 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__XGMI_WAFL))
760 return -EINVAL;
761
762 err_data->ue_count = 0;
763 err_data->ce_count = 0;
764
765 switch (adev->asic_type) {
766 case CHIP_ARCTURUS:
767 /* check xgmi pcs error */
768 for (i = 0; i < ARRAY_SIZE(xgmi_pcs_err_status_reg_arct); i++) {
769 data = RREG32_PCIE(xgmi_pcs_err_status_reg_arct[i]);
770 if (data)
771 amdgpu_xgmi_query_pcs_error_status(adev,
772 data, &ue_cnt, &ce_cnt, true);
773 }
774 /* check wafl pcs error */
775 for (i = 0; i < ARRAY_SIZE(wafl_pcs_err_status_reg_arct); i++) {
776 data = RREG32_PCIE(wafl_pcs_err_status_reg_arct[i]);
777 if (data)
778 amdgpu_xgmi_query_pcs_error_status(adev,
779 data, &ue_cnt, &ce_cnt, false);
780 }
781 break;
782 case CHIP_VEGA20:
783 default:
784 /* check xgmi pcs error */
785 for (i = 0; i < ARRAY_SIZE(xgmi_pcs_err_status_reg_vg20); i++) {
786 data = RREG32_PCIE(xgmi_pcs_err_status_reg_vg20[i]);
787 if (data)
788 amdgpu_xgmi_query_pcs_error_status(adev,
789 data, &ue_cnt, &ce_cnt, true);
790 }
791 /* check wafl pcs error */
792 for (i = 0; i < ARRAY_SIZE(wafl_pcs_err_status_reg_vg20); i++) {
793 data = RREG32_PCIE(wafl_pcs_err_status_reg_vg20[i]);
794 if (data)
795 amdgpu_xgmi_query_pcs_error_status(adev,
796 data, &ue_cnt, &ce_cnt, false);
797 }
798 break;
799 }
800
801 amdgpu_xgmi_reset_ras_error_count(adev);
802
803 err_data->ue_count += ue_cnt;
804 err_data->ce_count += ce_cnt;
805
806 return 0;
807 }
808