1 /*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #define SWSMU_CODE_LAYER_L2
25
26 #include <linux/firmware.h>
27 #include "amdgpu.h"
28 #include "amdgpu_smu.h"
29 #include "atomfirmware.h"
30 #include "amdgpu_atomfirmware.h"
31 #include "amdgpu_atombios.h"
32 #include "smu_v11_0.h"
33 #include "smu11_driver_if_arcturus.h"
34 #include "soc15_common.h"
35 #include "atom.h"
36 #include "power_state.h"
37 #include "arcturus_ppt.h"
38 #include "smu_v11_0_pptable.h"
39 #include "arcturus_ppsmc.h"
40 #include "nbio/nbio_7_4_offset.h"
41 #include "nbio/nbio_7_4_sh_mask.h"
42 #include "thm/thm_11_0_2_offset.h"
43 #include "thm/thm_11_0_2_sh_mask.h"
44 #include "amdgpu_xgmi.h"
45 #include <linux/i2c.h>
46 #include <linux/pci.h>
47 #include "amdgpu_ras.h"
48 #include "smu_cmn.h"
49
50 /*
51 * DO NOT use these for err/warn/info/debug messages.
52 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
53 * They are more MGPU friendly.
54 */
55 #undef pr_err
56 #undef pr_warn
57 #undef pr_info
58 #undef pr_debug
59
60 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c))
61
62 #define ARCTURUS_FEA_MAP(smu_feature, arcturus_feature) \
63 [smu_feature] = {1, (arcturus_feature)}
64
65 #define SMU_FEATURES_LOW_MASK 0x00000000FFFFFFFF
66 #define SMU_FEATURES_LOW_SHIFT 0
67 #define SMU_FEATURES_HIGH_MASK 0xFFFFFFFF00000000
68 #define SMU_FEATURES_HIGH_SHIFT 32
69
70 #define SMC_DPM_FEATURE ( \
71 FEATURE_DPM_PREFETCHER_MASK | \
72 FEATURE_DPM_GFXCLK_MASK | \
73 FEATURE_DPM_UCLK_MASK | \
74 FEATURE_DPM_SOCCLK_MASK | \
75 FEATURE_DPM_MP0CLK_MASK | \
76 FEATURE_DPM_FCLK_MASK | \
77 FEATURE_DPM_XGMI_MASK)
78
79 /* possible frequency drift (1Mhz) */
80 #define EPSILON 1
81
82 #define smnPCIE_ESM_CTRL 0x111003D0
83
84 static const struct cmn2asic_msg_mapping arcturus_message_map[SMU_MSG_MAX_COUNT] = {
85 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 0),
86 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1),
87 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1),
88 MSG_MAP(SetAllowedFeaturesMaskLow, PPSMC_MSG_SetAllowedFeaturesMaskLow, 0),
89 MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh, 0),
90 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0),
91 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0),
92 MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow, 1),
93 MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh, 1),
94 MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow, 0),
95 MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh, 0),
96 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetEnabledSmuFeaturesLow, 0),
97 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetEnabledSmuFeaturesHigh, 0),
98 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1),
99 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1),
100 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0),
101 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0),
102 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1),
103 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0),
104 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable, 0),
105 MSG_MAP(UseBackupPPTable, PPSMC_MSG_UseBackupPPTable, 0),
106 MSG_MAP(SetSystemVirtualDramAddrHigh, PPSMC_MSG_SetSystemVirtualDramAddrHigh, 0),
107 MSG_MAP(SetSystemVirtualDramAddrLow, PPSMC_MSG_SetSystemVirtualDramAddrLow, 0),
108 MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco, 0),
109 MSG_MAP(ExitBaco, PPSMC_MSG_ExitBaco, 0),
110 MSG_MAP(ArmD3, PPSMC_MSG_ArmD3, 0),
111 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 0),
112 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 0),
113 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq, 0),
114 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq, 0),
115 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 0),
116 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 0),
117 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1),
118 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask, 1),
119 MSG_MAP(SetDfSwitchType, PPSMC_MSG_SetDfSwitchType, 0),
120 MSG_MAP(GetVoltageByDpm, PPSMC_MSG_GetVoltageByDpm, 0),
121 MSG_MAP(GetVoltageByDpmOverdrive, PPSMC_MSG_GetVoltageByDpmOverdrive, 0),
122 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0),
123 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 1),
124 MSG_MAP(PowerUpVcn0, PPSMC_MSG_PowerUpVcn0, 0),
125 MSG_MAP(PowerDownVcn0, PPSMC_MSG_PowerDownVcn0, 0),
126 MSG_MAP(PowerUpVcn1, PPSMC_MSG_PowerUpVcn1, 0),
127 MSG_MAP(PowerDownVcn1, PPSMC_MSG_PowerDownVcn1, 0),
128 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 0),
129 MSG_MAP(PrepareMp1ForReset, PPSMC_MSG_PrepareMp1ForReset, 0),
130 MSG_MAP(PrepareMp1ForShutdown, PPSMC_MSG_PrepareMp1ForShutdown, 0),
131 MSG_MAP(SoftReset, PPSMC_MSG_SoftReset, 0),
132 MSG_MAP(RunAfllBtc, PPSMC_MSG_RunAfllBtc, 0),
133 MSG_MAP(RunDcBtc, PPSMC_MSG_RunDcBtc, 0),
134 MSG_MAP(DramLogSetDramAddrHigh, PPSMC_MSG_DramLogSetDramAddrHigh, 0),
135 MSG_MAP(DramLogSetDramAddrLow, PPSMC_MSG_DramLogSetDramAddrLow, 0),
136 MSG_MAP(DramLogSetDramSize, PPSMC_MSG_DramLogSetDramSize, 0),
137 MSG_MAP(GetDebugData, PPSMC_MSG_GetDebugData, 0),
138 MSG_MAP(WaflTest, PPSMC_MSG_WaflTest, 0),
139 MSG_MAP(SetXgmiMode, PPSMC_MSG_SetXgmiMode, 0),
140 MSG_MAP(SetMemoryChannelEnable, PPSMC_MSG_SetMemoryChannelEnable, 0),
141 MSG_MAP(DFCstateControl, PPSMC_MSG_DFCstateControl, 0),
142 MSG_MAP(GmiPwrDnControl, PPSMC_MSG_GmiPwrDnControl, 0),
143 MSG_MAP(ReadSerialNumTop32, PPSMC_MSG_ReadSerialNumTop32, 1),
144 MSG_MAP(ReadSerialNumBottom32, PPSMC_MSG_ReadSerialNumBottom32, 1),
145 };
146
147 static const struct cmn2asic_mapping arcturus_clk_map[SMU_CLK_COUNT] = {
148 CLK_MAP(GFXCLK, PPCLK_GFXCLK),
149 CLK_MAP(SCLK, PPCLK_GFXCLK),
150 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
151 CLK_MAP(FCLK, PPCLK_FCLK),
152 CLK_MAP(UCLK, PPCLK_UCLK),
153 CLK_MAP(MCLK, PPCLK_UCLK),
154 CLK_MAP(DCLK, PPCLK_DCLK),
155 CLK_MAP(VCLK, PPCLK_VCLK),
156 };
157
158 static const struct cmn2asic_mapping arcturus_feature_mask_map[SMU_FEATURE_COUNT] = {
159 FEA_MAP(DPM_PREFETCHER),
160 FEA_MAP(DPM_GFXCLK),
161 FEA_MAP(DPM_UCLK),
162 FEA_MAP(DPM_SOCCLK),
163 FEA_MAP(DPM_FCLK),
164 FEA_MAP(DPM_MP0CLK),
165 ARCTURUS_FEA_MAP(SMU_FEATURE_XGMI_BIT, FEATURE_DPM_XGMI_BIT),
166 FEA_MAP(DS_GFXCLK),
167 FEA_MAP(DS_SOCCLK),
168 FEA_MAP(DS_LCLK),
169 FEA_MAP(DS_FCLK),
170 FEA_MAP(DS_UCLK),
171 FEA_MAP(GFX_ULV),
172 ARCTURUS_FEA_MAP(SMU_FEATURE_VCN_PG_BIT, FEATURE_DPM_VCN_BIT),
173 FEA_MAP(RSMU_SMN_CG),
174 FEA_MAP(WAFL_CG),
175 FEA_MAP(PPT),
176 FEA_MAP(TDC),
177 FEA_MAP(APCC_PLUS),
178 FEA_MAP(VR0HOT),
179 FEA_MAP(VR1HOT),
180 FEA_MAP(FW_CTF),
181 FEA_MAP(FAN_CONTROL),
182 FEA_MAP(THERMAL),
183 FEA_MAP(OUT_OF_BAND_MONITOR),
184 FEA_MAP(TEMP_DEPENDENT_VMIN),
185 };
186
187 static const struct cmn2asic_mapping arcturus_table_map[SMU_TABLE_COUNT] = {
188 TAB_MAP(PPTABLE),
189 TAB_MAP(AVFS),
190 TAB_MAP(AVFS_PSM_DEBUG),
191 TAB_MAP(AVFS_FUSE_OVERRIDE),
192 TAB_MAP(PMSTATUSLOG),
193 TAB_MAP(SMU_METRICS),
194 TAB_MAP(DRIVER_SMU_CONFIG),
195 TAB_MAP(OVERDRIVE),
196 TAB_MAP(I2C_COMMANDS),
197 TAB_MAP(ACTIVITY_MONITOR_COEFF),
198 };
199
200 static const struct cmn2asic_mapping arcturus_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
201 PWR_MAP(AC),
202 PWR_MAP(DC),
203 };
204
205 static const struct cmn2asic_mapping arcturus_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
206 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT),
207 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT),
208 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT),
209 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT),
210 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT),
211 };
212
arcturus_tables_init(struct smu_context * smu)213 static int arcturus_tables_init(struct smu_context *smu)
214 {
215 struct smu_table_context *smu_table = &smu->smu_table;
216 struct smu_table *tables = smu_table->tables;
217
218 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
219 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
220
221 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
222 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
223
224 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
225 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
226
227 SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
228 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
229
230 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
231 sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE,
232 AMDGPU_GEM_DOMAIN_VRAM);
233
234 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
235 if (!smu_table->metrics_table)
236 return -ENOMEM;
237 smu_table->metrics_time = 0;
238
239 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_0);
240 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
241 if (!smu_table->gpu_metrics_table) {
242 kfree(smu_table->metrics_table);
243 return -ENOMEM;
244 }
245
246 return 0;
247 }
248
arcturus_allocate_dpm_context(struct smu_context * smu)249 static int arcturus_allocate_dpm_context(struct smu_context *smu)
250 {
251 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
252
253 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
254 GFP_KERNEL);
255 if (!smu_dpm->dpm_context)
256 return -ENOMEM;
257 smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
258
259 smu_dpm->dpm_current_power_state = kzalloc(sizeof(struct smu_power_state),
260 GFP_KERNEL);
261 if (!smu_dpm->dpm_current_power_state)
262 return -ENOMEM;
263
264 smu_dpm->dpm_request_power_state = kzalloc(sizeof(struct smu_power_state),
265 GFP_KERNEL);
266 if (!smu_dpm->dpm_request_power_state)
267 return -ENOMEM;
268
269 return 0;
270 }
271
arcturus_init_smc_tables(struct smu_context * smu)272 static int arcturus_init_smc_tables(struct smu_context *smu)
273 {
274 int ret = 0;
275
276 ret = arcturus_tables_init(smu);
277 if (ret)
278 return ret;
279
280 ret = arcturus_allocate_dpm_context(smu);
281 if (ret)
282 return ret;
283
284 return smu_v11_0_init_smc_tables(smu);
285 }
286
287 static int
arcturus_get_allowed_feature_mask(struct smu_context * smu,uint32_t * feature_mask,uint32_t num)288 arcturus_get_allowed_feature_mask(struct smu_context *smu,
289 uint32_t *feature_mask, uint32_t num)
290 {
291 if (num > 2)
292 return -EINVAL;
293
294 /* pptable will handle the features to enable */
295 memset(feature_mask, 0xFF, sizeof(uint32_t) * num);
296
297 return 0;
298 }
299
arcturus_set_default_dpm_table(struct smu_context * smu)300 static int arcturus_set_default_dpm_table(struct smu_context *smu)
301 {
302 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
303 PPTable_t *driver_ppt = smu->smu_table.driver_pptable;
304 struct smu_11_0_dpm_table *dpm_table = NULL;
305 int ret = 0;
306
307 /* socclk dpm table setup */
308 dpm_table = &dpm_context->dpm_tables.soc_table;
309 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
310 ret = smu_v11_0_set_single_dpm_table(smu,
311 SMU_SOCCLK,
312 dpm_table);
313 if (ret)
314 return ret;
315 dpm_table->is_fine_grained =
316 !driver_ppt->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete;
317 } else {
318 dpm_table->count = 1;
319 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
320 dpm_table->dpm_levels[0].enabled = true;
321 dpm_table->min = dpm_table->dpm_levels[0].value;
322 dpm_table->max = dpm_table->dpm_levels[0].value;
323 }
324
325 /* gfxclk dpm table setup */
326 dpm_table = &dpm_context->dpm_tables.gfx_table;
327 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
328 ret = smu_v11_0_set_single_dpm_table(smu,
329 SMU_GFXCLK,
330 dpm_table);
331 if (ret)
332 return ret;
333 dpm_table->is_fine_grained =
334 !driver_ppt->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete;
335 } else {
336 dpm_table->count = 1;
337 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
338 dpm_table->dpm_levels[0].enabled = true;
339 dpm_table->min = dpm_table->dpm_levels[0].value;
340 dpm_table->max = dpm_table->dpm_levels[0].value;
341 }
342
343 /* memclk dpm table setup */
344 dpm_table = &dpm_context->dpm_tables.uclk_table;
345 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
346 ret = smu_v11_0_set_single_dpm_table(smu,
347 SMU_UCLK,
348 dpm_table);
349 if (ret)
350 return ret;
351 dpm_table->is_fine_grained =
352 !driver_ppt->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete;
353 } else {
354 dpm_table->count = 1;
355 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
356 dpm_table->dpm_levels[0].enabled = true;
357 dpm_table->min = dpm_table->dpm_levels[0].value;
358 dpm_table->max = dpm_table->dpm_levels[0].value;
359 }
360
361 /* fclk dpm table setup */
362 dpm_table = &dpm_context->dpm_tables.fclk_table;
363 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
364 ret = smu_v11_0_set_single_dpm_table(smu,
365 SMU_FCLK,
366 dpm_table);
367 if (ret)
368 return ret;
369 dpm_table->is_fine_grained =
370 !driver_ppt->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete;
371 } else {
372 dpm_table->count = 1;
373 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
374 dpm_table->dpm_levels[0].enabled = true;
375 dpm_table->min = dpm_table->dpm_levels[0].value;
376 dpm_table->max = dpm_table->dpm_levels[0].value;
377 }
378
379 return 0;
380 }
381
arcturus_check_bxco_support(struct smu_context * smu)382 static void arcturus_check_bxco_support(struct smu_context *smu)
383 {
384 struct smu_table_context *table_context = &smu->smu_table;
385 struct smu_11_0_powerplay_table *powerplay_table =
386 table_context->power_play_table;
387 struct smu_baco_context *smu_baco = &smu->smu_baco;
388 struct amdgpu_device *adev = smu->adev;
389 uint32_t val;
390
391 if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_BACO ||
392 powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_MACO) {
393 val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
394 smu_baco->platform_support =
395 (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true :
396 false;
397 }
398 }
399
arcturus_check_powerplay_table(struct smu_context * smu)400 static int arcturus_check_powerplay_table(struct smu_context *smu)
401 {
402 struct smu_table_context *table_context = &smu->smu_table;
403 struct smu_11_0_powerplay_table *powerplay_table =
404 table_context->power_play_table;
405
406 arcturus_check_bxco_support(smu);
407
408 table_context->thermal_controller_type =
409 powerplay_table->thermal_controller_type;
410
411 return 0;
412 }
413
arcturus_store_powerplay_table(struct smu_context * smu)414 static int arcturus_store_powerplay_table(struct smu_context *smu)
415 {
416 struct smu_table_context *table_context = &smu->smu_table;
417 struct smu_11_0_powerplay_table *powerplay_table =
418 table_context->power_play_table;
419
420 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
421 sizeof(PPTable_t));
422
423 return 0;
424 }
425
arcturus_append_powerplay_table(struct smu_context * smu)426 static int arcturus_append_powerplay_table(struct smu_context *smu)
427 {
428 struct smu_table_context *table_context = &smu->smu_table;
429 PPTable_t *smc_pptable = table_context->driver_pptable;
430 struct atom_smc_dpm_info_v4_6 *smc_dpm_table;
431 int index, ret;
432
433 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
434 smc_dpm_info);
435
436 ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL,
437 (uint8_t **)&smc_dpm_table);
438 if (ret)
439 return ret;
440
441 dev_info(smu->adev->dev, "smc_dpm_info table revision(format.content): %d.%d\n",
442 smc_dpm_table->table_header.format_revision,
443 smc_dpm_table->table_header.content_revision);
444
445 if ((smc_dpm_table->table_header.format_revision == 4) &&
446 (smc_dpm_table->table_header.content_revision == 6))
447 memcpy(&smc_pptable->MaxVoltageStepGfx,
448 &smc_dpm_table->maxvoltagestepgfx,
449 sizeof(*smc_dpm_table) - offsetof(struct atom_smc_dpm_info_v4_6, maxvoltagestepgfx));
450
451 return 0;
452 }
453
arcturus_setup_pptable(struct smu_context * smu)454 static int arcturus_setup_pptable(struct smu_context *smu)
455 {
456 int ret = 0;
457
458 ret = smu_v11_0_setup_pptable(smu);
459 if (ret)
460 return ret;
461
462 ret = arcturus_store_powerplay_table(smu);
463 if (ret)
464 return ret;
465
466 ret = arcturus_append_powerplay_table(smu);
467 if (ret)
468 return ret;
469
470 ret = arcturus_check_powerplay_table(smu);
471 if (ret)
472 return ret;
473
474 return ret;
475 }
476
arcturus_run_btc(struct smu_context * smu)477 static int arcturus_run_btc(struct smu_context *smu)
478 {
479 int ret = 0;
480
481 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_RunAfllBtc, NULL);
482 if (ret) {
483 dev_err(smu->adev->dev, "RunAfllBtc failed!\n");
484 return ret;
485 }
486
487 return smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
488 }
489
arcturus_populate_umd_state_clk(struct smu_context * smu)490 static int arcturus_populate_umd_state_clk(struct smu_context *smu)
491 {
492 struct smu_11_0_dpm_context *dpm_context =
493 smu->smu_dpm.dpm_context;
494 struct smu_11_0_dpm_table *gfx_table =
495 &dpm_context->dpm_tables.gfx_table;
496 struct smu_11_0_dpm_table *mem_table =
497 &dpm_context->dpm_tables.uclk_table;
498 struct smu_11_0_dpm_table *soc_table =
499 &dpm_context->dpm_tables.soc_table;
500 struct smu_umd_pstate_table *pstate_table =
501 &smu->pstate_table;
502
503 pstate_table->gfxclk_pstate.min = gfx_table->min;
504 pstate_table->gfxclk_pstate.peak = gfx_table->max;
505
506 pstate_table->uclk_pstate.min = mem_table->min;
507 pstate_table->uclk_pstate.peak = mem_table->max;
508
509 pstate_table->socclk_pstate.min = soc_table->min;
510 pstate_table->socclk_pstate.peak = soc_table->max;
511
512 if (gfx_table->count > ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL &&
513 mem_table->count > ARCTURUS_UMD_PSTATE_MCLK_LEVEL &&
514 soc_table->count > ARCTURUS_UMD_PSTATE_SOCCLK_LEVEL) {
515 pstate_table->gfxclk_pstate.standard =
516 gfx_table->dpm_levels[ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL].value;
517 pstate_table->uclk_pstate.standard =
518 mem_table->dpm_levels[ARCTURUS_UMD_PSTATE_MCLK_LEVEL].value;
519 pstate_table->socclk_pstate.standard =
520 soc_table->dpm_levels[ARCTURUS_UMD_PSTATE_SOCCLK_LEVEL].value;
521 } else {
522 pstate_table->gfxclk_pstate.standard =
523 pstate_table->gfxclk_pstate.min;
524 pstate_table->uclk_pstate.standard =
525 pstate_table->uclk_pstate.min;
526 pstate_table->socclk_pstate.standard =
527 pstate_table->socclk_pstate.min;
528 }
529
530 return 0;
531 }
532
arcturus_get_clk_table(struct smu_context * smu,struct pp_clock_levels_with_latency * clocks,struct smu_11_0_dpm_table * dpm_table)533 static int arcturus_get_clk_table(struct smu_context *smu,
534 struct pp_clock_levels_with_latency *clocks,
535 struct smu_11_0_dpm_table *dpm_table)
536 {
537 int i, count;
538
539 count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
540 clocks->num_levels = count;
541
542 for (i = 0; i < count; i++) {
543 clocks->data[i].clocks_in_khz =
544 dpm_table->dpm_levels[i].value * 1000;
545 clocks->data[i].latency_in_us = 0;
546 }
547
548 return 0;
549 }
550
arcturus_freqs_in_same_level(int32_t frequency1,int32_t frequency2)551 static int arcturus_freqs_in_same_level(int32_t frequency1,
552 int32_t frequency2)
553 {
554 return (abs(frequency1 - frequency2) <= EPSILON);
555 }
556
arcturus_get_smu_metrics_data(struct smu_context * smu,MetricsMember_t member,uint32_t * value)557 static int arcturus_get_smu_metrics_data(struct smu_context *smu,
558 MetricsMember_t member,
559 uint32_t *value)
560 {
561 struct smu_table_context *smu_table= &smu->smu_table;
562 SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table;
563 int ret = 0;
564
565 mutex_lock(&smu->metrics_lock);
566
567 ret = smu_cmn_get_metrics_table_locked(smu,
568 NULL,
569 false);
570 if (ret) {
571 mutex_unlock(&smu->metrics_lock);
572 return ret;
573 }
574
575 switch (member) {
576 case METRICS_CURR_GFXCLK:
577 *value = metrics->CurrClock[PPCLK_GFXCLK];
578 break;
579 case METRICS_CURR_SOCCLK:
580 *value = metrics->CurrClock[PPCLK_SOCCLK];
581 break;
582 case METRICS_CURR_UCLK:
583 *value = metrics->CurrClock[PPCLK_UCLK];
584 break;
585 case METRICS_CURR_VCLK:
586 *value = metrics->CurrClock[PPCLK_VCLK];
587 break;
588 case METRICS_CURR_DCLK:
589 *value = metrics->CurrClock[PPCLK_DCLK];
590 break;
591 case METRICS_CURR_FCLK:
592 *value = metrics->CurrClock[PPCLK_FCLK];
593 break;
594 case METRICS_AVERAGE_GFXCLK:
595 *value = metrics->AverageGfxclkFrequency;
596 break;
597 case METRICS_AVERAGE_SOCCLK:
598 *value = metrics->AverageSocclkFrequency;
599 break;
600 case METRICS_AVERAGE_UCLK:
601 *value = metrics->AverageUclkFrequency;
602 break;
603 case METRICS_AVERAGE_VCLK:
604 *value = metrics->AverageVclkFrequency;
605 break;
606 case METRICS_AVERAGE_DCLK:
607 *value = metrics->AverageDclkFrequency;
608 break;
609 case METRICS_AVERAGE_GFXACTIVITY:
610 *value = metrics->AverageGfxActivity;
611 break;
612 case METRICS_AVERAGE_MEMACTIVITY:
613 *value = metrics->AverageUclkActivity;
614 break;
615 case METRICS_AVERAGE_VCNACTIVITY:
616 *value = metrics->VcnActivityPercentage;
617 break;
618 case METRICS_AVERAGE_SOCKETPOWER:
619 *value = metrics->AverageSocketPower << 8;
620 break;
621 case METRICS_TEMPERATURE_EDGE:
622 *value = metrics->TemperatureEdge *
623 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
624 break;
625 case METRICS_TEMPERATURE_HOTSPOT:
626 *value = metrics->TemperatureHotspot *
627 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
628 break;
629 case METRICS_TEMPERATURE_MEM:
630 *value = metrics->TemperatureHBM *
631 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
632 break;
633 case METRICS_TEMPERATURE_VRGFX:
634 *value = metrics->TemperatureVrGfx *
635 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
636 break;
637 case METRICS_TEMPERATURE_VRSOC:
638 *value = metrics->TemperatureVrSoc *
639 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
640 break;
641 case METRICS_TEMPERATURE_VRMEM:
642 *value = metrics->TemperatureVrMem *
643 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
644 break;
645 case METRICS_THROTTLER_STATUS:
646 *value = metrics->ThrottlerStatus;
647 break;
648 case METRICS_CURR_FANSPEED:
649 *value = metrics->CurrFanSpeed;
650 break;
651 default:
652 *value = UINT_MAX;
653 break;
654 }
655
656 mutex_unlock(&smu->metrics_lock);
657
658 return ret;
659 }
660
arcturus_get_current_clk_freq_by_table(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * value)661 static int arcturus_get_current_clk_freq_by_table(struct smu_context *smu,
662 enum smu_clk_type clk_type,
663 uint32_t *value)
664 {
665 MetricsMember_t member_type;
666 int clk_id = 0;
667
668 if (!value)
669 return -EINVAL;
670
671 clk_id = smu_cmn_to_asic_specific_index(smu,
672 CMN2ASIC_MAPPING_CLK,
673 clk_type);
674 if (clk_id < 0)
675 return -EINVAL;
676
677 switch (clk_id) {
678 case PPCLK_GFXCLK:
679 /*
680 * CurrClock[clk_id] can provide accurate
681 * output only when the dpm feature is enabled.
682 * We can use Average_* for dpm disabled case.
683 * But this is available for gfxclk/uclk/socclk/vclk/dclk.
684 */
685 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT))
686 member_type = METRICS_CURR_GFXCLK;
687 else
688 member_type = METRICS_AVERAGE_GFXCLK;
689 break;
690 case PPCLK_UCLK:
691 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT))
692 member_type = METRICS_CURR_UCLK;
693 else
694 member_type = METRICS_AVERAGE_UCLK;
695 break;
696 case PPCLK_SOCCLK:
697 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT))
698 member_type = METRICS_CURR_SOCCLK;
699 else
700 member_type = METRICS_AVERAGE_SOCCLK;
701 break;
702 case PPCLK_VCLK:
703 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT))
704 member_type = METRICS_CURR_VCLK;
705 else
706 member_type = METRICS_AVERAGE_VCLK;
707 break;
708 case PPCLK_DCLK:
709 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT))
710 member_type = METRICS_CURR_DCLK;
711 else
712 member_type = METRICS_AVERAGE_DCLK;
713 break;
714 case PPCLK_FCLK:
715 member_type = METRICS_CURR_FCLK;
716 break;
717 default:
718 return -EINVAL;
719 }
720
721 return arcturus_get_smu_metrics_data(smu,
722 member_type,
723 value);
724 }
725
arcturus_print_clk_levels(struct smu_context * smu,enum smu_clk_type type,char * buf)726 static int arcturus_print_clk_levels(struct smu_context *smu,
727 enum smu_clk_type type, char *buf)
728 {
729 int i, now, size = 0;
730 int ret = 0;
731 struct pp_clock_levels_with_latency clocks;
732 struct smu_11_0_dpm_table *single_dpm_table;
733 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
734 struct smu_11_0_dpm_context *dpm_context = NULL;
735
736 if (amdgpu_ras_intr_triggered())
737 return snprintf(buf, PAGE_SIZE, "unavailable\n");
738
739 dpm_context = smu_dpm->dpm_context;
740
741 switch (type) {
742 case SMU_SCLK:
743 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_GFXCLK, &now);
744 if (ret) {
745 dev_err(smu->adev->dev, "Attempt to get current gfx clk Failed!");
746 return ret;
747 }
748
749 single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
750 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
751 if (ret) {
752 dev_err(smu->adev->dev, "Attempt to get gfx clk levels Failed!");
753 return ret;
754 }
755
756 /*
757 * For DPM disabled case, there will be only one clock level.
758 * And it's safe to assume that is always the current clock.
759 */
760 for (i = 0; i < clocks.num_levels; i++)
761 size += sprintf(buf + size, "%d: %uMhz %s\n", i,
762 clocks.data[i].clocks_in_khz / 1000,
763 (clocks.num_levels == 1) ? "*" :
764 (arcturus_freqs_in_same_level(
765 clocks.data[i].clocks_in_khz / 1000,
766 now) ? "*" : ""));
767 break;
768
769 case SMU_MCLK:
770 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_UCLK, &now);
771 if (ret) {
772 dev_err(smu->adev->dev, "Attempt to get current mclk Failed!");
773 return ret;
774 }
775
776 single_dpm_table = &(dpm_context->dpm_tables.uclk_table);
777 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
778 if (ret) {
779 dev_err(smu->adev->dev, "Attempt to get memory clk levels Failed!");
780 return ret;
781 }
782
783 for (i = 0; i < clocks.num_levels; i++)
784 size += sprintf(buf + size, "%d: %uMhz %s\n",
785 i, clocks.data[i].clocks_in_khz / 1000,
786 (clocks.num_levels == 1) ? "*" :
787 (arcturus_freqs_in_same_level(
788 clocks.data[i].clocks_in_khz / 1000,
789 now) ? "*" : ""));
790 break;
791
792 case SMU_SOCCLK:
793 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_SOCCLK, &now);
794 if (ret) {
795 dev_err(smu->adev->dev, "Attempt to get current socclk Failed!");
796 return ret;
797 }
798
799 single_dpm_table = &(dpm_context->dpm_tables.soc_table);
800 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
801 if (ret) {
802 dev_err(smu->adev->dev, "Attempt to get socclk levels Failed!");
803 return ret;
804 }
805
806 for (i = 0; i < clocks.num_levels; i++)
807 size += sprintf(buf + size, "%d: %uMhz %s\n",
808 i, clocks.data[i].clocks_in_khz / 1000,
809 (clocks.num_levels == 1) ? "*" :
810 (arcturus_freqs_in_same_level(
811 clocks.data[i].clocks_in_khz / 1000,
812 now) ? "*" : ""));
813 break;
814
815 case SMU_FCLK:
816 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_FCLK, &now);
817 if (ret) {
818 dev_err(smu->adev->dev, "Attempt to get current fclk Failed!");
819 return ret;
820 }
821
822 single_dpm_table = &(dpm_context->dpm_tables.fclk_table);
823 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
824 if (ret) {
825 dev_err(smu->adev->dev, "Attempt to get fclk levels Failed!");
826 return ret;
827 }
828
829 for (i = 0; i < single_dpm_table->count; i++)
830 size += sprintf(buf + size, "%d: %uMhz %s\n",
831 i, single_dpm_table->dpm_levels[i].value,
832 (clocks.num_levels == 1) ? "*" :
833 (arcturus_freqs_in_same_level(
834 clocks.data[i].clocks_in_khz / 1000,
835 now) ? "*" : ""));
836 break;
837
838 default:
839 break;
840 }
841
842 return size;
843 }
844
arcturus_upload_dpm_level(struct smu_context * smu,bool max,uint32_t feature_mask,uint32_t level)845 static int arcturus_upload_dpm_level(struct smu_context *smu,
846 bool max,
847 uint32_t feature_mask,
848 uint32_t level)
849 {
850 struct smu_11_0_dpm_context *dpm_context =
851 smu->smu_dpm.dpm_context;
852 uint32_t freq;
853 int ret = 0;
854
855 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) &&
856 (feature_mask & FEATURE_DPM_GFXCLK_MASK)) {
857 freq = dpm_context->dpm_tables.gfx_table.dpm_levels[level].value;
858 ret = smu_cmn_send_smc_msg_with_param(smu,
859 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
860 (PPCLK_GFXCLK << 16) | (freq & 0xffff),
861 NULL);
862 if (ret) {
863 dev_err(smu->adev->dev, "Failed to set soft %s gfxclk !\n",
864 max ? "max" : "min");
865 return ret;
866 }
867 }
868
869 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
870 (feature_mask & FEATURE_DPM_UCLK_MASK)) {
871 freq = dpm_context->dpm_tables.uclk_table.dpm_levels[level].value;
872 ret = smu_cmn_send_smc_msg_with_param(smu,
873 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
874 (PPCLK_UCLK << 16) | (freq & 0xffff),
875 NULL);
876 if (ret) {
877 dev_err(smu->adev->dev, "Failed to set soft %s memclk !\n",
878 max ? "max" : "min");
879 return ret;
880 }
881 }
882
883 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT) &&
884 (feature_mask & FEATURE_DPM_SOCCLK_MASK)) {
885 freq = dpm_context->dpm_tables.soc_table.dpm_levels[level].value;
886 ret = smu_cmn_send_smc_msg_with_param(smu,
887 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
888 (PPCLK_SOCCLK << 16) | (freq & 0xffff),
889 NULL);
890 if (ret) {
891 dev_err(smu->adev->dev, "Failed to set soft %s socclk !\n",
892 max ? "max" : "min");
893 return ret;
894 }
895 }
896
897 return ret;
898 }
899
arcturus_force_clk_levels(struct smu_context * smu,enum smu_clk_type type,uint32_t mask)900 static int arcturus_force_clk_levels(struct smu_context *smu,
901 enum smu_clk_type type, uint32_t mask)
902 {
903 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
904 struct smu_11_0_dpm_table *single_dpm_table = NULL;
905 uint32_t soft_min_level, soft_max_level;
906 uint32_t smu_version;
907 int ret = 0;
908
909 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
910 if (ret) {
911 dev_err(smu->adev->dev, "Failed to get smu version!\n");
912 return ret;
913 }
914
915 if ((smu_version >= 0x361200) &&
916 (smu_version <= 0x361a00)) {
917 dev_err(smu->adev->dev, "Forcing clock level is not supported with "
918 "54.18 - 54.26(included) SMU firmwares\n");
919 return -EOPNOTSUPP;
920 }
921
922 soft_min_level = mask ? (ffs(mask) - 1) : 0;
923 soft_max_level = mask ? (fls(mask) - 1) : 0;
924
925 switch (type) {
926 case SMU_SCLK:
927 single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
928 if (soft_max_level >= single_dpm_table->count) {
929 dev_err(smu->adev->dev, "Clock level specified %d is over max allowed %d\n",
930 soft_max_level, single_dpm_table->count - 1);
931 ret = -EINVAL;
932 break;
933 }
934
935 ret = arcturus_upload_dpm_level(smu,
936 false,
937 FEATURE_DPM_GFXCLK_MASK,
938 soft_min_level);
939 if (ret) {
940 dev_err(smu->adev->dev, "Failed to upload boot level to lowest!\n");
941 break;
942 }
943
944 ret = arcturus_upload_dpm_level(smu,
945 true,
946 FEATURE_DPM_GFXCLK_MASK,
947 soft_max_level);
948 if (ret)
949 dev_err(smu->adev->dev, "Failed to upload dpm max level to highest!\n");
950
951 break;
952
953 case SMU_MCLK:
954 case SMU_SOCCLK:
955 case SMU_FCLK:
956 /*
957 * Should not arrive here since Arcturus does not
958 * support mclk/socclk/fclk softmin/softmax settings
959 */
960 ret = -EINVAL;
961 break;
962
963 default:
964 break;
965 }
966
967 return ret;
968 }
969
arcturus_get_thermal_temperature_range(struct smu_context * smu,struct smu_temperature_range * range)970 static int arcturus_get_thermal_temperature_range(struct smu_context *smu,
971 struct smu_temperature_range *range)
972 {
973 struct smu_table_context *table_context = &smu->smu_table;
974 struct smu_11_0_powerplay_table *powerplay_table =
975 table_context->power_play_table;
976 PPTable_t *pptable = smu->smu_table.driver_pptable;
977
978 if (!range)
979 return -EINVAL;
980
981 memcpy(range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range));
982
983 range->max = pptable->TedgeLimit *
984 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
985 range->edge_emergency_max = (pptable->TedgeLimit + CTF_OFFSET_EDGE) *
986 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
987 range->hotspot_crit_max = pptable->ThotspotLimit *
988 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
989 range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT) *
990 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
991 range->mem_crit_max = pptable->TmemLimit *
992 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
993 range->mem_emergency_max = (pptable->TmemLimit + CTF_OFFSET_MEM)*
994 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
995 range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
996
997 return 0;
998 }
999
arcturus_get_current_activity_percent(struct smu_context * smu,enum amd_pp_sensors sensor,uint32_t * value)1000 static int arcturus_get_current_activity_percent(struct smu_context *smu,
1001 enum amd_pp_sensors sensor,
1002 uint32_t *value)
1003 {
1004 int ret = 0;
1005
1006 if (!value)
1007 return -EINVAL;
1008
1009 switch (sensor) {
1010 case AMDGPU_PP_SENSOR_GPU_LOAD:
1011 ret = arcturus_get_smu_metrics_data(smu,
1012 METRICS_AVERAGE_GFXACTIVITY,
1013 value);
1014 break;
1015 case AMDGPU_PP_SENSOR_MEM_LOAD:
1016 ret = arcturus_get_smu_metrics_data(smu,
1017 METRICS_AVERAGE_MEMACTIVITY,
1018 value);
1019 break;
1020 default:
1021 dev_err(smu->adev->dev, "Invalid sensor for retrieving clock activity\n");
1022 return -EINVAL;
1023 }
1024
1025 return ret;
1026 }
1027
arcturus_get_gpu_power(struct smu_context * smu,uint32_t * value)1028 static int arcturus_get_gpu_power(struct smu_context *smu, uint32_t *value)
1029 {
1030 if (!value)
1031 return -EINVAL;
1032
1033 return arcturus_get_smu_metrics_data(smu,
1034 METRICS_AVERAGE_SOCKETPOWER,
1035 value);
1036 }
1037
arcturus_thermal_get_temperature(struct smu_context * smu,enum amd_pp_sensors sensor,uint32_t * value)1038 static int arcturus_thermal_get_temperature(struct smu_context *smu,
1039 enum amd_pp_sensors sensor,
1040 uint32_t *value)
1041 {
1042 int ret = 0;
1043
1044 if (!value)
1045 return -EINVAL;
1046
1047 switch (sensor) {
1048 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1049 ret = arcturus_get_smu_metrics_data(smu,
1050 METRICS_TEMPERATURE_HOTSPOT,
1051 value);
1052 break;
1053 case AMDGPU_PP_SENSOR_EDGE_TEMP:
1054 ret = arcturus_get_smu_metrics_data(smu,
1055 METRICS_TEMPERATURE_EDGE,
1056 value);
1057 break;
1058 case AMDGPU_PP_SENSOR_MEM_TEMP:
1059 ret = arcturus_get_smu_metrics_data(smu,
1060 METRICS_TEMPERATURE_MEM,
1061 value);
1062 break;
1063 default:
1064 dev_err(smu->adev->dev, "Invalid sensor for retrieving temp\n");
1065 return -EINVAL;
1066 }
1067
1068 return ret;
1069 }
1070
arcturus_read_sensor(struct smu_context * smu,enum amd_pp_sensors sensor,void * data,uint32_t * size)1071 static int arcturus_read_sensor(struct smu_context *smu,
1072 enum amd_pp_sensors sensor,
1073 void *data, uint32_t *size)
1074 {
1075 struct smu_table_context *table_context = &smu->smu_table;
1076 PPTable_t *pptable = table_context->driver_pptable;
1077 int ret = 0;
1078
1079 if (amdgpu_ras_intr_triggered())
1080 return 0;
1081
1082 if (!data || !size)
1083 return -EINVAL;
1084
1085 mutex_lock(&smu->sensor_lock);
1086 switch (sensor) {
1087 case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
1088 *(uint32_t *)data = pptable->FanMaximumRpm;
1089 *size = 4;
1090 break;
1091 case AMDGPU_PP_SENSOR_MEM_LOAD:
1092 case AMDGPU_PP_SENSOR_GPU_LOAD:
1093 ret = arcturus_get_current_activity_percent(smu,
1094 sensor,
1095 (uint32_t *)data);
1096 *size = 4;
1097 break;
1098 case AMDGPU_PP_SENSOR_GPU_POWER:
1099 ret = arcturus_get_gpu_power(smu, (uint32_t *)data);
1100 *size = 4;
1101 break;
1102 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1103 case AMDGPU_PP_SENSOR_EDGE_TEMP:
1104 case AMDGPU_PP_SENSOR_MEM_TEMP:
1105 ret = arcturus_thermal_get_temperature(smu, sensor,
1106 (uint32_t *)data);
1107 *size = 4;
1108 break;
1109 case AMDGPU_PP_SENSOR_GFX_MCLK:
1110 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data);
1111 /* the output clock frequency in 10K unit */
1112 *(uint32_t *)data *= 100;
1113 *size = 4;
1114 break;
1115 case AMDGPU_PP_SENSOR_GFX_SCLK:
1116 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_GFXCLK, (uint32_t *)data);
1117 *(uint32_t *)data *= 100;
1118 *size = 4;
1119 break;
1120 case AMDGPU_PP_SENSOR_VDDGFX:
1121 ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);
1122 *size = 4;
1123 break;
1124 default:
1125 ret = -EOPNOTSUPP;
1126 break;
1127 }
1128 mutex_unlock(&smu->sensor_lock);
1129
1130 return ret;
1131 }
1132
arcturus_get_fan_speed_rpm(struct smu_context * smu,uint32_t * speed)1133 static int arcturus_get_fan_speed_rpm(struct smu_context *smu,
1134 uint32_t *speed)
1135 {
1136 if (!speed)
1137 return -EINVAL;
1138
1139 switch (smu_v11_0_get_fan_control_mode(smu)) {
1140 case AMD_FAN_CTRL_AUTO:
1141 return arcturus_get_smu_metrics_data(smu,
1142 METRICS_CURR_FANSPEED,
1143 speed);
1144 default:
1145 return smu_v11_0_get_fan_speed_rpm(smu, speed);
1146 }
1147 }
1148
arcturus_get_fan_parameters(struct smu_context * smu)1149 static int arcturus_get_fan_parameters(struct smu_context *smu)
1150 {
1151 PPTable_t *pptable = smu->smu_table.driver_pptable;
1152
1153 smu->fan_max_rpm = pptable->FanMaximumRpm;
1154
1155 return 0;
1156 }
1157
arcturus_get_power_limit(struct smu_context * smu)1158 static int arcturus_get_power_limit(struct smu_context *smu)
1159 {
1160 struct smu_11_0_powerplay_table *powerplay_table =
1161 (struct smu_11_0_powerplay_table *)smu->smu_table.power_play_table;
1162 PPTable_t *pptable = smu->smu_table.driver_pptable;
1163 uint32_t power_limit, od_percent;
1164
1165 if (smu_v11_0_get_current_power_limit(smu, &power_limit)) {
1166 /* the last hope to figure out the ppt limit */
1167 if (!pptable) {
1168 dev_err(smu->adev->dev, "Cannot get PPT limit due to pptable missing!");
1169 return -EINVAL;
1170 }
1171 power_limit =
1172 pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
1173 }
1174 smu->current_power_limit = power_limit;
1175
1176 if (smu->od_enabled) {
1177 od_percent = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_ODSETTING_POWERPERCENTAGE]);
1178
1179 dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_percent, power_limit);
1180
1181 power_limit *= (100 + od_percent);
1182 power_limit /= 100;
1183 }
1184 smu->max_power_limit = power_limit;
1185
1186 return 0;
1187 }
1188
arcturus_get_power_profile_mode(struct smu_context * smu,char * buf)1189 static int arcturus_get_power_profile_mode(struct smu_context *smu,
1190 char *buf)
1191 {
1192 DpmActivityMonitorCoeffInt_t activity_monitor;
1193 static const char *profile_name[] = {
1194 "BOOTUP_DEFAULT",
1195 "3D_FULL_SCREEN",
1196 "POWER_SAVING",
1197 "VIDEO",
1198 "VR",
1199 "COMPUTE",
1200 "CUSTOM"};
1201 static const char *title[] = {
1202 "PROFILE_INDEX(NAME)",
1203 "CLOCK_TYPE(NAME)",
1204 "FPS",
1205 "UseRlcBusy",
1206 "MinActiveFreqType",
1207 "MinActiveFreq",
1208 "BoosterFreqType",
1209 "BoosterFreq",
1210 "PD_Data_limit_c",
1211 "PD_Data_error_coeff",
1212 "PD_Data_error_rate_coeff"};
1213 uint32_t i, size = 0;
1214 int16_t workload_type = 0;
1215 int result = 0;
1216 uint32_t smu_version;
1217
1218 if (!buf)
1219 return -EINVAL;
1220
1221 result = smu_cmn_get_smc_version(smu, NULL, &smu_version);
1222 if (result)
1223 return result;
1224
1225 if (smu_version >= 0x360d00)
1226 size += sprintf(buf + size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
1227 title[0], title[1], title[2], title[3], title[4], title[5],
1228 title[6], title[7], title[8], title[9], title[10]);
1229 else
1230 size += sprintf(buf + size, "%16s\n",
1231 title[0]);
1232
1233 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1234 /*
1235 * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT
1236 * Not all profile modes are supported on arcturus.
1237 */
1238 workload_type = smu_cmn_to_asic_specific_index(smu,
1239 CMN2ASIC_MAPPING_WORKLOAD,
1240 i);
1241 if (workload_type < 0)
1242 continue;
1243
1244 if (smu_version >= 0x360d00) {
1245 result = smu_cmn_update_table(smu,
1246 SMU_TABLE_ACTIVITY_MONITOR_COEFF,
1247 workload_type,
1248 (void *)(&activity_monitor),
1249 false);
1250 if (result) {
1251 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1252 return result;
1253 }
1254 }
1255
1256 size += sprintf(buf + size, "%2d %14s%s\n",
1257 i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1258
1259 if (smu_version >= 0x360d00) {
1260 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1261 " ",
1262 0,
1263 "GFXCLK",
1264 activity_monitor.Gfx_FPS,
1265 activity_monitor.Gfx_UseRlcBusy,
1266 activity_monitor.Gfx_MinActiveFreqType,
1267 activity_monitor.Gfx_MinActiveFreq,
1268 activity_monitor.Gfx_BoosterFreqType,
1269 activity_monitor.Gfx_BoosterFreq,
1270 activity_monitor.Gfx_PD_Data_limit_c,
1271 activity_monitor.Gfx_PD_Data_error_coeff,
1272 activity_monitor.Gfx_PD_Data_error_rate_coeff);
1273
1274 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1275 " ",
1276 1,
1277 "UCLK",
1278 activity_monitor.Mem_FPS,
1279 activity_monitor.Mem_UseRlcBusy,
1280 activity_monitor.Mem_MinActiveFreqType,
1281 activity_monitor.Mem_MinActiveFreq,
1282 activity_monitor.Mem_BoosterFreqType,
1283 activity_monitor.Mem_BoosterFreq,
1284 activity_monitor.Mem_PD_Data_limit_c,
1285 activity_monitor.Mem_PD_Data_error_coeff,
1286 activity_monitor.Mem_PD_Data_error_rate_coeff);
1287 }
1288 }
1289
1290 return size;
1291 }
1292
arcturus_set_power_profile_mode(struct smu_context * smu,long * input,uint32_t size)1293 static int arcturus_set_power_profile_mode(struct smu_context *smu,
1294 long *input,
1295 uint32_t size)
1296 {
1297 DpmActivityMonitorCoeffInt_t activity_monitor;
1298 int workload_type = 0;
1299 uint32_t profile_mode = input[size];
1300 int ret = 0;
1301 uint32_t smu_version;
1302
1303 if (profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
1304 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", profile_mode);
1305 return -EINVAL;
1306 }
1307
1308 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
1309 if (ret)
1310 return ret;
1311
1312 if ((profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) &&
1313 (smu_version >=0x360d00)) {
1314 ret = smu_cmn_update_table(smu,
1315 SMU_TABLE_ACTIVITY_MONITOR_COEFF,
1316 WORKLOAD_PPLIB_CUSTOM_BIT,
1317 (void *)(&activity_monitor),
1318 false);
1319 if (ret) {
1320 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1321 return ret;
1322 }
1323
1324 switch (input[0]) {
1325 case 0: /* Gfxclk */
1326 activity_monitor.Gfx_FPS = input[1];
1327 activity_monitor.Gfx_UseRlcBusy = input[2];
1328 activity_monitor.Gfx_MinActiveFreqType = input[3];
1329 activity_monitor.Gfx_MinActiveFreq = input[4];
1330 activity_monitor.Gfx_BoosterFreqType = input[5];
1331 activity_monitor.Gfx_BoosterFreq = input[6];
1332 activity_monitor.Gfx_PD_Data_limit_c = input[7];
1333 activity_monitor.Gfx_PD_Data_error_coeff = input[8];
1334 activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9];
1335 break;
1336 case 1: /* Uclk */
1337 activity_monitor.Mem_FPS = input[1];
1338 activity_monitor.Mem_UseRlcBusy = input[2];
1339 activity_monitor.Mem_MinActiveFreqType = input[3];
1340 activity_monitor.Mem_MinActiveFreq = input[4];
1341 activity_monitor.Mem_BoosterFreqType = input[5];
1342 activity_monitor.Mem_BoosterFreq = input[6];
1343 activity_monitor.Mem_PD_Data_limit_c = input[7];
1344 activity_monitor.Mem_PD_Data_error_coeff = input[8];
1345 activity_monitor.Mem_PD_Data_error_rate_coeff = input[9];
1346 break;
1347 }
1348
1349 ret = smu_cmn_update_table(smu,
1350 SMU_TABLE_ACTIVITY_MONITOR_COEFF,
1351 WORKLOAD_PPLIB_CUSTOM_BIT,
1352 (void *)(&activity_monitor),
1353 true);
1354 if (ret) {
1355 dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__);
1356 return ret;
1357 }
1358 }
1359
1360 /*
1361 * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT
1362 * Not all profile modes are supported on arcturus.
1363 */
1364 workload_type = smu_cmn_to_asic_specific_index(smu,
1365 CMN2ASIC_MAPPING_WORKLOAD,
1366 profile_mode);
1367 if (workload_type < 0) {
1368 dev_err(smu->adev->dev, "Unsupported power profile mode %d on arcturus\n", profile_mode);
1369 return -EINVAL;
1370 }
1371
1372 ret = smu_cmn_send_smc_msg_with_param(smu,
1373 SMU_MSG_SetWorkloadMask,
1374 1 << workload_type,
1375 NULL);
1376 if (ret) {
1377 dev_err(smu->adev->dev, "Fail to set workload type %d\n", workload_type);
1378 return ret;
1379 }
1380
1381 smu->power_profile_mode = profile_mode;
1382
1383 return 0;
1384 }
1385
arcturus_set_performance_level(struct smu_context * smu,enum amd_dpm_forced_level level)1386 static int arcturus_set_performance_level(struct smu_context *smu,
1387 enum amd_dpm_forced_level level)
1388 {
1389 uint32_t smu_version;
1390 int ret;
1391
1392 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
1393 if (ret) {
1394 dev_err(smu->adev->dev, "Failed to get smu version!\n");
1395 return ret;
1396 }
1397
1398 switch (level) {
1399 case AMD_DPM_FORCED_LEVEL_HIGH:
1400 case AMD_DPM_FORCED_LEVEL_LOW:
1401 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1402 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1403 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1404 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1405 if ((smu_version >= 0x361200) &&
1406 (smu_version <= 0x361a00)) {
1407 dev_err(smu->adev->dev, "Forcing clock level is not supported with "
1408 "54.18 - 54.26(included) SMU firmwares\n");
1409 return -EOPNOTSUPP;
1410 }
1411 break;
1412 default:
1413 break;
1414 }
1415
1416 return smu_v11_0_set_performance_level(smu, level);
1417 }
1418
arcturus_dump_pptable(struct smu_context * smu)1419 static void arcturus_dump_pptable(struct smu_context *smu)
1420 {
1421 struct smu_table_context *table_context = &smu->smu_table;
1422 PPTable_t *pptable = table_context->driver_pptable;
1423 int i;
1424
1425 dev_info(smu->adev->dev, "Dumped PPTable:\n");
1426
1427 dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version);
1428
1429 dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
1430 dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
1431
1432 for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
1433 dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = %d\n", i, pptable->SocketPowerLimitAc[i]);
1434 dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = %d\n", i, pptable->SocketPowerLimitAcTau[i]);
1435 }
1436
1437 dev_info(smu->adev->dev, "TdcLimitSoc = %d\n", pptable->TdcLimitSoc);
1438 dev_info(smu->adev->dev, "TdcLimitSocTau = %d\n", pptable->TdcLimitSocTau);
1439 dev_info(smu->adev->dev, "TdcLimitGfx = %d\n", pptable->TdcLimitGfx);
1440 dev_info(smu->adev->dev, "TdcLimitGfxTau = %d\n", pptable->TdcLimitGfxTau);
1441
1442 dev_info(smu->adev->dev, "TedgeLimit = %d\n", pptable->TedgeLimit);
1443 dev_info(smu->adev->dev, "ThotspotLimit = %d\n", pptable->ThotspotLimit);
1444 dev_info(smu->adev->dev, "TmemLimit = %d\n", pptable->TmemLimit);
1445 dev_info(smu->adev->dev, "Tvr_gfxLimit = %d\n", pptable->Tvr_gfxLimit);
1446 dev_info(smu->adev->dev, "Tvr_memLimit = %d\n", pptable->Tvr_memLimit);
1447 dev_info(smu->adev->dev, "Tvr_socLimit = %d\n", pptable->Tvr_socLimit);
1448 dev_info(smu->adev->dev, "FitLimit = %d\n", pptable->FitLimit);
1449
1450 dev_info(smu->adev->dev, "PpmPowerLimit = %d\n", pptable->PpmPowerLimit);
1451 dev_info(smu->adev->dev, "PpmTemperatureThreshold = %d\n", pptable->PpmTemperatureThreshold);
1452
1453 dev_info(smu->adev->dev, "ThrottlerControlMask = %d\n", pptable->ThrottlerControlMask);
1454
1455 dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = %d\n", pptable->UlvVoltageOffsetGfx);
1456 dev_info(smu->adev->dev, "UlvPadding = 0x%08x\n", pptable->UlvPadding);
1457
1458 dev_info(smu->adev->dev, "UlvGfxclkBypass = %d\n", pptable->UlvGfxclkBypass);
1459 dev_info(smu->adev->dev, "Padding234[0] = 0x%02x\n", pptable->Padding234[0]);
1460 dev_info(smu->adev->dev, "Padding234[1] = 0x%02x\n", pptable->Padding234[1]);
1461 dev_info(smu->adev->dev, "Padding234[2] = 0x%02x\n", pptable->Padding234[2]);
1462
1463 dev_info(smu->adev->dev, "MinVoltageGfx = %d\n", pptable->MinVoltageGfx);
1464 dev_info(smu->adev->dev, "MinVoltageSoc = %d\n", pptable->MinVoltageSoc);
1465 dev_info(smu->adev->dev, "MaxVoltageGfx = %d\n", pptable->MaxVoltageGfx);
1466 dev_info(smu->adev->dev, "MaxVoltageSoc = %d\n", pptable->MaxVoltageSoc);
1467
1468 dev_info(smu->adev->dev, "LoadLineResistanceGfx = %d\n", pptable->LoadLineResistanceGfx);
1469 dev_info(smu->adev->dev, "LoadLineResistanceSoc = %d\n", pptable->LoadLineResistanceSoc);
1470
1471 dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n"
1472 " .VoltageMode = 0x%02x\n"
1473 " .SnapToDiscrete = 0x%02x\n"
1474 " .NumDiscreteLevels = 0x%02x\n"
1475 " .padding = 0x%02x\n"
1476 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1477 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1478 " .SsFmin = 0x%04x\n"
1479 " .Padding_16 = 0x%04x\n",
1480 pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
1481 pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
1482 pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
1483 pptable->DpmDescriptor[PPCLK_GFXCLK].padding,
1484 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
1485 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
1486 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
1487 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
1488 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
1489 pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
1490 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
1491
1492 dev_info(smu->adev->dev, "[PPCLK_VCLK]\n"
1493 " .VoltageMode = 0x%02x\n"
1494 " .SnapToDiscrete = 0x%02x\n"
1495 " .NumDiscreteLevels = 0x%02x\n"
1496 " .padding = 0x%02x\n"
1497 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1498 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1499 " .SsFmin = 0x%04x\n"
1500 " .Padding_16 = 0x%04x\n",
1501 pptable->DpmDescriptor[PPCLK_VCLK].VoltageMode,
1502 pptable->DpmDescriptor[PPCLK_VCLK].SnapToDiscrete,
1503 pptable->DpmDescriptor[PPCLK_VCLK].NumDiscreteLevels,
1504 pptable->DpmDescriptor[PPCLK_VCLK].padding,
1505 pptable->DpmDescriptor[PPCLK_VCLK].ConversionToAvfsClk.m,
1506 pptable->DpmDescriptor[PPCLK_VCLK].ConversionToAvfsClk.b,
1507 pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.a,
1508 pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.b,
1509 pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.c,
1510 pptable->DpmDescriptor[PPCLK_VCLK].SsFmin,
1511 pptable->DpmDescriptor[PPCLK_VCLK].Padding16);
1512
1513 dev_info(smu->adev->dev, "[PPCLK_DCLK]\n"
1514 " .VoltageMode = 0x%02x\n"
1515 " .SnapToDiscrete = 0x%02x\n"
1516 " .NumDiscreteLevels = 0x%02x\n"
1517 " .padding = 0x%02x\n"
1518 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1519 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1520 " .SsFmin = 0x%04x\n"
1521 " .Padding_16 = 0x%04x\n",
1522 pptable->DpmDescriptor[PPCLK_DCLK].VoltageMode,
1523 pptable->DpmDescriptor[PPCLK_DCLK].SnapToDiscrete,
1524 pptable->DpmDescriptor[PPCLK_DCLK].NumDiscreteLevels,
1525 pptable->DpmDescriptor[PPCLK_DCLK].padding,
1526 pptable->DpmDescriptor[PPCLK_DCLK].ConversionToAvfsClk.m,
1527 pptable->DpmDescriptor[PPCLK_DCLK].ConversionToAvfsClk.b,
1528 pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.a,
1529 pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.b,
1530 pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.c,
1531 pptable->DpmDescriptor[PPCLK_DCLK].SsFmin,
1532 pptable->DpmDescriptor[PPCLK_DCLK].Padding16);
1533
1534 dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n"
1535 " .VoltageMode = 0x%02x\n"
1536 " .SnapToDiscrete = 0x%02x\n"
1537 " .NumDiscreteLevels = 0x%02x\n"
1538 " .padding = 0x%02x\n"
1539 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1540 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1541 " .SsFmin = 0x%04x\n"
1542 " .Padding_16 = 0x%04x\n",
1543 pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
1544 pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
1545 pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
1546 pptable->DpmDescriptor[PPCLK_SOCCLK].padding,
1547 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
1548 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
1549 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
1550 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
1551 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
1552 pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
1553 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
1554
1555 dev_info(smu->adev->dev, "[PPCLK_UCLK]\n"
1556 " .VoltageMode = 0x%02x\n"
1557 " .SnapToDiscrete = 0x%02x\n"
1558 " .NumDiscreteLevels = 0x%02x\n"
1559 " .padding = 0x%02x\n"
1560 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1561 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1562 " .SsFmin = 0x%04x\n"
1563 " .Padding_16 = 0x%04x\n",
1564 pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
1565 pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
1566 pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
1567 pptable->DpmDescriptor[PPCLK_UCLK].padding,
1568 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
1569 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
1570 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
1571 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
1572 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
1573 pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
1574 pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
1575
1576 dev_info(smu->adev->dev, "[PPCLK_FCLK]\n"
1577 " .VoltageMode = 0x%02x\n"
1578 " .SnapToDiscrete = 0x%02x\n"
1579 " .NumDiscreteLevels = 0x%02x\n"
1580 " .padding = 0x%02x\n"
1581 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1582 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1583 " .SsFmin = 0x%04x\n"
1584 " .Padding_16 = 0x%04x\n",
1585 pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
1586 pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
1587 pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
1588 pptable->DpmDescriptor[PPCLK_FCLK].padding,
1589 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
1590 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
1591 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
1592 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
1593 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
1594 pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
1595 pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
1596
1597
1598 dev_info(smu->adev->dev, "FreqTableGfx\n");
1599 for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
1600 dev_info(smu->adev->dev, " .[%02d] = %d\n", i, pptable->FreqTableGfx[i]);
1601
1602 dev_info(smu->adev->dev, "FreqTableVclk\n");
1603 for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
1604 dev_info(smu->adev->dev, " .[%02d] = %d\n", i, pptable->FreqTableVclk[i]);
1605
1606 dev_info(smu->adev->dev, "FreqTableDclk\n");
1607 for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
1608 dev_info(smu->adev->dev, " .[%02d] = %d\n", i, pptable->FreqTableDclk[i]);
1609
1610 dev_info(smu->adev->dev, "FreqTableSocclk\n");
1611 for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
1612 dev_info(smu->adev->dev, " .[%02d] = %d\n", i, pptable->FreqTableSocclk[i]);
1613
1614 dev_info(smu->adev->dev, "FreqTableUclk\n");
1615 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
1616 dev_info(smu->adev->dev, " .[%02d] = %d\n", i, pptable->FreqTableUclk[i]);
1617
1618 dev_info(smu->adev->dev, "FreqTableFclk\n");
1619 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
1620 dev_info(smu->adev->dev, " .[%02d] = %d\n", i, pptable->FreqTableFclk[i]);
1621
1622 dev_info(smu->adev->dev, "Mp0clkFreq\n");
1623 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
1624 dev_info(smu->adev->dev, " .[%d] = %d\n", i, pptable->Mp0clkFreq[i]);
1625
1626 dev_info(smu->adev->dev, "Mp0DpmVoltage\n");
1627 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
1628 dev_info(smu->adev->dev, " .[%d] = %d\n", i, pptable->Mp0DpmVoltage[i]);
1629
1630 dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
1631 dev_info(smu->adev->dev, "GfxclkSlewRate = 0x%x\n", pptable->GfxclkSlewRate);
1632 dev_info(smu->adev->dev, "Padding567[0] = 0x%x\n", pptable->Padding567[0]);
1633 dev_info(smu->adev->dev, "Padding567[1] = 0x%x\n", pptable->Padding567[1]);
1634 dev_info(smu->adev->dev, "Padding567[2] = 0x%x\n", pptable->Padding567[2]);
1635 dev_info(smu->adev->dev, "Padding567[3] = 0x%x\n", pptable->Padding567[3]);
1636 dev_info(smu->adev->dev, "GfxclkDsMaxFreq = %d\n", pptable->GfxclkDsMaxFreq);
1637 dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource);
1638 dev_info(smu->adev->dev, "Padding456 = 0x%x\n", pptable->Padding456);
1639
1640 dev_info(smu->adev->dev, "EnableTdpm = %d\n", pptable->EnableTdpm);
1641 dev_info(smu->adev->dev, "TdpmHighHystTemperature = %d\n", pptable->TdpmHighHystTemperature);
1642 dev_info(smu->adev->dev, "TdpmLowHystTemperature = %d\n", pptable->TdpmLowHystTemperature);
1643 dev_info(smu->adev->dev, "GfxclkFreqHighTempLimit = %d\n", pptable->GfxclkFreqHighTempLimit);
1644
1645 dev_info(smu->adev->dev, "FanStopTemp = %d\n", pptable->FanStopTemp);
1646 dev_info(smu->adev->dev, "FanStartTemp = %d\n", pptable->FanStartTemp);
1647
1648 dev_info(smu->adev->dev, "FanGainEdge = %d\n", pptable->FanGainEdge);
1649 dev_info(smu->adev->dev, "FanGainHotspot = %d\n", pptable->FanGainHotspot);
1650 dev_info(smu->adev->dev, "FanGainVrGfx = %d\n", pptable->FanGainVrGfx);
1651 dev_info(smu->adev->dev, "FanGainVrSoc = %d\n", pptable->FanGainVrSoc);
1652 dev_info(smu->adev->dev, "FanGainVrMem = %d\n", pptable->FanGainVrMem);
1653 dev_info(smu->adev->dev, "FanGainHbm = %d\n", pptable->FanGainHbm);
1654
1655 dev_info(smu->adev->dev, "FanPwmMin = %d\n", pptable->FanPwmMin);
1656 dev_info(smu->adev->dev, "FanAcousticLimitRpm = %d\n", pptable->FanAcousticLimitRpm);
1657 dev_info(smu->adev->dev, "FanThrottlingRpm = %d\n", pptable->FanThrottlingRpm);
1658 dev_info(smu->adev->dev, "FanMaximumRpm = %d\n", pptable->FanMaximumRpm);
1659 dev_info(smu->adev->dev, "FanTargetTemperature = %d\n", pptable->FanTargetTemperature);
1660 dev_info(smu->adev->dev, "FanTargetGfxclk = %d\n", pptable->FanTargetGfxclk);
1661 dev_info(smu->adev->dev, "FanZeroRpmEnable = %d\n", pptable->FanZeroRpmEnable);
1662 dev_info(smu->adev->dev, "FanTachEdgePerRev = %d\n", pptable->FanTachEdgePerRev);
1663 dev_info(smu->adev->dev, "FanTempInputSelect = %d\n", pptable->FanTempInputSelect);
1664
1665 dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = %d\n", pptable->FuzzyFan_ErrorSetDelta);
1666 dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = %d\n", pptable->FuzzyFan_ErrorRateSetDelta);
1667 dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = %d\n", pptable->FuzzyFan_PwmSetDelta);
1668 dev_info(smu->adev->dev, "FuzzyFan_Reserved = %d\n", pptable->FuzzyFan_Reserved);
1669
1670 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
1671 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
1672 dev_info(smu->adev->dev, "Padding8_Avfs[0] = %d\n", pptable->Padding8_Avfs[0]);
1673 dev_info(smu->adev->dev, "Padding8_Avfs[1] = %d\n", pptable->Padding8_Avfs[1]);
1674
1675 dev_info(smu->adev->dev, "dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
1676 pptable->dBtcGbGfxPll.a,
1677 pptable->dBtcGbGfxPll.b,
1678 pptable->dBtcGbGfxPll.c);
1679 dev_info(smu->adev->dev, "dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
1680 pptable->dBtcGbGfxAfll.a,
1681 pptable->dBtcGbGfxAfll.b,
1682 pptable->dBtcGbGfxAfll.c);
1683 dev_info(smu->adev->dev, "dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
1684 pptable->dBtcGbSoc.a,
1685 pptable->dBtcGbSoc.b,
1686 pptable->dBtcGbSoc.c);
1687
1688 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
1689 pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
1690 pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
1691 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
1692 pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
1693 pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
1694
1695 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
1696 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
1697 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
1698 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
1699 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
1700 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
1701 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
1702 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
1703
1704 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
1705 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
1706
1707 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
1708 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
1709 dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
1710 dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
1711
1712 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
1713 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
1714 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
1715 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
1716
1717 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
1718 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
1719
1720 dev_info(smu->adev->dev, "XgmiDpmPstates\n");
1721 for (i = 0; i < NUM_XGMI_LEVELS; i++)
1722 dev_info(smu->adev->dev, " .[%d] = %d\n", i, pptable->XgmiDpmPstates[i]);
1723 dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
1724 dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
1725
1726 dev_info(smu->adev->dev, "VDDGFX_TVmin = %d\n", pptable->VDDGFX_TVmin);
1727 dev_info(smu->adev->dev, "VDDSOC_TVmin = %d\n", pptable->VDDSOC_TVmin);
1728 dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = %d\n", pptable->VDDGFX_Vmin_HiTemp);
1729 dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = %d\n", pptable->VDDGFX_Vmin_LoTemp);
1730 dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = %d\n", pptable->VDDSOC_Vmin_HiTemp);
1731 dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = %d\n", pptable->VDDSOC_Vmin_LoTemp);
1732 dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = %d\n", pptable->VDDGFX_TVminHystersis);
1733 dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = %d\n", pptable->VDDSOC_TVminHystersis);
1734
1735 dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides);
1736 dev_info(smu->adev->dev, "ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
1737 pptable->ReservedEquation0.a,
1738 pptable->ReservedEquation0.b,
1739 pptable->ReservedEquation0.c);
1740 dev_info(smu->adev->dev, "ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
1741 pptable->ReservedEquation1.a,
1742 pptable->ReservedEquation1.b,
1743 pptable->ReservedEquation1.c);
1744 dev_info(smu->adev->dev, "ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
1745 pptable->ReservedEquation2.a,
1746 pptable->ReservedEquation2.b,
1747 pptable->ReservedEquation2.c);
1748 dev_info(smu->adev->dev, "ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
1749 pptable->ReservedEquation3.a,
1750 pptable->ReservedEquation3.b,
1751 pptable->ReservedEquation3.c);
1752
1753 dev_info(smu->adev->dev, "MinVoltageUlvGfx = %d\n", pptable->MinVoltageUlvGfx);
1754 dev_info(smu->adev->dev, "PaddingUlv = %d\n", pptable->PaddingUlv);
1755
1756 dev_info(smu->adev->dev, "TotalPowerConfig = %d\n", pptable->TotalPowerConfig);
1757 dev_info(smu->adev->dev, "TotalPowerSpare1 = %d\n", pptable->TotalPowerSpare1);
1758 dev_info(smu->adev->dev, "TotalPowerSpare2 = %d\n", pptable->TotalPowerSpare2);
1759
1760 dev_info(smu->adev->dev, "PccThresholdLow = %d\n", pptable->PccThresholdLow);
1761 dev_info(smu->adev->dev, "PccThresholdHigh = %d\n", pptable->PccThresholdHigh);
1762
1763 dev_info(smu->adev->dev, "Board Parameters:\n");
1764 dev_info(smu->adev->dev, "MaxVoltageStepGfx = 0x%x\n", pptable->MaxVoltageStepGfx);
1765 dev_info(smu->adev->dev, "MaxVoltageStepSoc = 0x%x\n", pptable->MaxVoltageStepSoc);
1766
1767 dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
1768 dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
1769 dev_info(smu->adev->dev, "VddMemVrMapping = 0x%x\n", pptable->VddMemVrMapping);
1770 dev_info(smu->adev->dev, "BoardVrMapping = 0x%x\n", pptable->BoardVrMapping);
1771
1772 dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
1773 dev_info(smu->adev->dev, "ExternalSensorPresent = 0x%x\n", pptable->ExternalSensorPresent);
1774
1775 dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
1776 dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset);
1777 dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
1778
1779 dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
1780 dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset);
1781 dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
1782
1783 dev_info(smu->adev->dev, "MemMaxCurrent = 0x%x\n", pptable->MemMaxCurrent);
1784 dev_info(smu->adev->dev, "MemOffset = 0x%x\n", pptable->MemOffset);
1785 dev_info(smu->adev->dev, "Padding_TelemetryMem = 0x%x\n", pptable->Padding_TelemetryMem);
1786
1787 dev_info(smu->adev->dev, "BoardMaxCurrent = 0x%x\n", pptable->BoardMaxCurrent);
1788 dev_info(smu->adev->dev, "BoardOffset = 0x%x\n", pptable->BoardOffset);
1789 dev_info(smu->adev->dev, "Padding_TelemetryBoardInput = 0x%x\n", pptable->Padding_TelemetryBoardInput);
1790
1791 dev_info(smu->adev->dev, "VR0HotGpio = %d\n", pptable->VR0HotGpio);
1792 dev_info(smu->adev->dev, "VR0HotPolarity = %d\n", pptable->VR0HotPolarity);
1793 dev_info(smu->adev->dev, "VR1HotGpio = %d\n", pptable->VR1HotGpio);
1794 dev_info(smu->adev->dev, "VR1HotPolarity = %d\n", pptable->VR1HotPolarity);
1795
1796 dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = %d\n", pptable->PllGfxclkSpreadEnabled);
1797 dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = %d\n", pptable->PllGfxclkSpreadPercent);
1798 dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = %d\n", pptable->PllGfxclkSpreadFreq);
1799
1800 dev_info(smu->adev->dev, "UclkSpreadEnabled = %d\n", pptable->UclkSpreadEnabled);
1801 dev_info(smu->adev->dev, "UclkSpreadPercent = %d\n", pptable->UclkSpreadPercent);
1802 dev_info(smu->adev->dev, "UclkSpreadFreq = %d\n", pptable->UclkSpreadFreq);
1803
1804 dev_info(smu->adev->dev, "FclkSpreadEnabled = %d\n", pptable->FclkSpreadEnabled);
1805 dev_info(smu->adev->dev, "FclkSpreadPercent = %d\n", pptable->FclkSpreadPercent);
1806 dev_info(smu->adev->dev, "FclkSpreadFreq = %d\n", pptable->FclkSpreadFreq);
1807
1808 dev_info(smu->adev->dev, "FllGfxclkSpreadEnabled = %d\n", pptable->FllGfxclkSpreadEnabled);
1809 dev_info(smu->adev->dev, "FllGfxclkSpreadPercent = %d\n", pptable->FllGfxclkSpreadPercent);
1810 dev_info(smu->adev->dev, "FllGfxclkSpreadFreq = %d\n", pptable->FllGfxclkSpreadFreq);
1811
1812 for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
1813 dev_info(smu->adev->dev, "I2cControllers[%d]:\n", i);
1814 dev_info(smu->adev->dev, " .Enabled = %d\n",
1815 pptable->I2cControllers[i].Enabled);
1816 dev_info(smu->adev->dev, " .SlaveAddress = 0x%x\n",
1817 pptable->I2cControllers[i].SlaveAddress);
1818 dev_info(smu->adev->dev, " .ControllerPort = %d\n",
1819 pptable->I2cControllers[i].ControllerPort);
1820 dev_info(smu->adev->dev, " .ControllerName = %d\n",
1821 pptable->I2cControllers[i].ControllerName);
1822 dev_info(smu->adev->dev, " .ThermalThrottler = %d\n",
1823 pptable->I2cControllers[i].ThermalThrotter);
1824 dev_info(smu->adev->dev, " .I2cProtocol = %d\n",
1825 pptable->I2cControllers[i].I2cProtocol);
1826 dev_info(smu->adev->dev, " .Speed = %d\n",
1827 pptable->I2cControllers[i].Speed);
1828 }
1829
1830 dev_info(smu->adev->dev, "MemoryChannelEnabled = %d\n", pptable->MemoryChannelEnabled);
1831 dev_info(smu->adev->dev, "DramBitWidth = %d\n", pptable->DramBitWidth);
1832
1833 dev_info(smu->adev->dev, "TotalBoardPower = %d\n", pptable->TotalBoardPower);
1834
1835 dev_info(smu->adev->dev, "XgmiLinkSpeed\n");
1836 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
1837 dev_info(smu->adev->dev, " .[%d] = %d\n", i, pptable->XgmiLinkSpeed[i]);
1838 dev_info(smu->adev->dev, "XgmiLinkWidth\n");
1839 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
1840 dev_info(smu->adev->dev, " .[%d] = %d\n", i, pptable->XgmiLinkWidth[i]);
1841 dev_info(smu->adev->dev, "XgmiFclkFreq\n");
1842 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
1843 dev_info(smu->adev->dev, " .[%d] = %d\n", i, pptable->XgmiFclkFreq[i]);
1844 dev_info(smu->adev->dev, "XgmiSocVoltage\n");
1845 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
1846 dev_info(smu->adev->dev, " .[%d] = %d\n", i, pptable->XgmiSocVoltage[i]);
1847
1848 }
1849
arcturus_is_dpm_running(struct smu_context * smu)1850 static bool arcturus_is_dpm_running(struct smu_context *smu)
1851 {
1852 int ret = 0;
1853 uint32_t feature_mask[2];
1854 uint64_t feature_enabled;
1855
1856 ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
1857 if (ret)
1858 return false;
1859
1860 feature_enabled = (uint64_t)feature_mask[1] << 32 | feature_mask[0];
1861
1862 return !!(feature_enabled & SMC_DPM_FEATURE);
1863 }
1864
arcturus_dpm_set_vcn_enable(struct smu_context * smu,bool enable)1865 static int arcturus_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
1866 {
1867 int ret = 0;
1868
1869 if (enable) {
1870 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
1871 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_VCN_PG_BIT, 1);
1872 if (ret) {
1873 dev_err(smu->adev->dev, "[EnableVCNDPM] failed!\n");
1874 return ret;
1875 }
1876 }
1877 } else {
1878 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
1879 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_VCN_PG_BIT, 0);
1880 if (ret) {
1881 dev_err(smu->adev->dev, "[DisableVCNDPM] failed!\n");
1882 return ret;
1883 }
1884 }
1885 }
1886
1887 return ret;
1888 }
1889
arcturus_fill_i2c_req(SwI2cRequest_t * req,bool write,uint8_t address,uint32_t numbytes,uint8_t * data)1890 static void arcturus_fill_i2c_req(SwI2cRequest_t *req, bool write,
1891 uint8_t address, uint32_t numbytes,
1892 uint8_t *data)
1893 {
1894 int i;
1895
1896 req->I2CcontrollerPort = 0;
1897 req->I2CSpeed = 2;
1898 req->SlaveAddress = address;
1899 req->NumCmds = numbytes;
1900
1901 for (i = 0; i < numbytes; i++) {
1902 SwI2cCmd_t *cmd = &req->SwI2cCmds[i];
1903
1904 /* First 2 bytes are always write for lower 2b EEPROM address */
1905 if (i < 2)
1906 cmd->Cmd = 1;
1907 else
1908 cmd->Cmd = write;
1909
1910
1911 /* Add RESTART for read after address filled */
1912 cmd->CmdConfig |= (i == 2 && !write) ? CMDCONFIG_RESTART_MASK : 0;
1913
1914 /* Add STOP in the end */
1915 cmd->CmdConfig |= (i == (numbytes - 1)) ? CMDCONFIG_STOP_MASK : 0;
1916
1917 /* Fill with data regardless if read or write to simplify code */
1918 cmd->RegisterAddr = data[i];
1919 }
1920 }
1921
arcturus_i2c_read_data(struct i2c_adapter * control,uint8_t address,uint8_t * data,uint32_t numbytes)1922 static int arcturus_i2c_read_data(struct i2c_adapter *control,
1923 uint8_t address,
1924 uint8_t *data,
1925 uint32_t numbytes)
1926 {
1927 uint32_t i, ret = 0;
1928 SwI2cRequest_t req;
1929 struct amdgpu_device *adev = to_amdgpu_device(control);
1930 struct smu_table_context *smu_table = &adev->smu.smu_table;
1931 struct smu_table *table = &smu_table->driver_table;
1932
1933 if (numbytes > MAX_SW_I2C_COMMANDS) {
1934 dev_err(adev->dev, "numbytes requested %d is over max allowed %d\n",
1935 numbytes, MAX_SW_I2C_COMMANDS);
1936 return -EINVAL;
1937 }
1938
1939 memset(&req, 0, sizeof(req));
1940 arcturus_fill_i2c_req(&req, false, address, numbytes, data);
1941
1942 mutex_lock(&adev->smu.mutex);
1943 /* Now read data starting with that address */
1944 ret = smu_cmn_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, &req,
1945 true);
1946 mutex_unlock(&adev->smu.mutex);
1947
1948 if (!ret) {
1949 SwI2cRequest_t *res = (SwI2cRequest_t *)table->cpu_addr;
1950
1951 /* Assume SMU fills res.SwI2cCmds[i].Data with read bytes */
1952 for (i = 0; i < numbytes; i++)
1953 data[i] = res->SwI2cCmds[i].Data;
1954
1955 dev_dbg(adev->dev, "arcturus_i2c_read_data, address = %x, bytes = %d, data :",
1956 (uint16_t)address, numbytes);
1957
1958 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_NONE,
1959 8, 1, data, numbytes, false);
1960 } else
1961 dev_err(adev->dev, "arcturus_i2c_read_data - error occurred :%x", ret);
1962
1963 return ret;
1964 }
1965
arcturus_i2c_write_data(struct i2c_adapter * control,uint8_t address,uint8_t * data,uint32_t numbytes)1966 static int arcturus_i2c_write_data(struct i2c_adapter *control,
1967 uint8_t address,
1968 uint8_t *data,
1969 uint32_t numbytes)
1970 {
1971 uint32_t ret;
1972 SwI2cRequest_t req;
1973 struct amdgpu_device *adev = to_amdgpu_device(control);
1974
1975 if (numbytes > MAX_SW_I2C_COMMANDS) {
1976 dev_err(adev->dev, "numbytes requested %d is over max allowed %d\n",
1977 numbytes, MAX_SW_I2C_COMMANDS);
1978 return -EINVAL;
1979 }
1980
1981 memset(&req, 0, sizeof(req));
1982 arcturus_fill_i2c_req(&req, true, address, numbytes, data);
1983
1984 mutex_lock(&adev->smu.mutex);
1985 ret = smu_cmn_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, &req, true);
1986 mutex_unlock(&adev->smu.mutex);
1987
1988 if (!ret) {
1989 dev_dbg(adev->dev, "arcturus_i2c_write(), address = %x, bytes = %d , data: ",
1990 (uint16_t)address, numbytes);
1991
1992 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_NONE,
1993 8, 1, data, numbytes, false);
1994 /*
1995 * According to EEPROM spec there is a MAX of 10 ms required for
1996 * EEPROM to flush internal RX buffer after STOP was issued at the
1997 * end of write transaction. During this time the EEPROM will not be
1998 * responsive to any more commands - so wait a bit more.
1999 */
2000 msleep(10);
2001
2002 } else
2003 dev_err(adev->dev, "arcturus_i2c_write- error occurred :%x", ret);
2004
2005 return ret;
2006 }
2007
arcturus_i2c_xfer(struct i2c_adapter * i2c_adap,struct i2c_msg * msgs,int num)2008 static int arcturus_i2c_xfer(struct i2c_adapter *i2c_adap,
2009 struct i2c_msg *msgs, int num)
2010 {
2011 uint32_t i, j, ret, data_size, data_chunk_size, next_eeprom_addr = 0;
2012 uint8_t *data_ptr, data_chunk[MAX_SW_I2C_COMMANDS] = { 0 };
2013
2014 for (i = 0; i < num; i++) {
2015 /*
2016 * SMU interface allows at most MAX_SW_I2C_COMMANDS bytes of data at
2017 * once and hence the data needs to be spliced into chunks and sent each
2018 * chunk separately
2019 */
2020 data_size = msgs[i].len - 2;
2021 data_chunk_size = MAX_SW_I2C_COMMANDS - 2;
2022 next_eeprom_addr = (msgs[i].buf[0] << 8 & 0xff00) | (msgs[i].buf[1] & 0xff);
2023 data_ptr = msgs[i].buf + 2;
2024
2025 for (j = 0; j < data_size / data_chunk_size; j++) {
2026 /* Insert the EEPROM dest addess, bits 0-15 */
2027 data_chunk[0] = ((next_eeprom_addr >> 8) & 0xff);
2028 data_chunk[1] = (next_eeprom_addr & 0xff);
2029
2030 if (msgs[i].flags & I2C_M_RD) {
2031 ret = arcturus_i2c_read_data(i2c_adap,
2032 (uint8_t)msgs[i].addr,
2033 data_chunk, MAX_SW_I2C_COMMANDS);
2034
2035 memcpy(data_ptr, data_chunk + 2, data_chunk_size);
2036 } else {
2037
2038 memcpy(data_chunk + 2, data_ptr, data_chunk_size);
2039
2040 ret = arcturus_i2c_write_data(i2c_adap,
2041 (uint8_t)msgs[i].addr,
2042 data_chunk, MAX_SW_I2C_COMMANDS);
2043 }
2044
2045 if (ret) {
2046 num = -EIO;
2047 goto fail;
2048 }
2049
2050 next_eeprom_addr += data_chunk_size;
2051 data_ptr += data_chunk_size;
2052 }
2053
2054 if (data_size % data_chunk_size) {
2055 data_chunk[0] = ((next_eeprom_addr >> 8) & 0xff);
2056 data_chunk[1] = (next_eeprom_addr & 0xff);
2057
2058 if (msgs[i].flags & I2C_M_RD) {
2059 ret = arcturus_i2c_read_data(i2c_adap,
2060 (uint8_t)msgs[i].addr,
2061 data_chunk, (data_size % data_chunk_size) + 2);
2062
2063 memcpy(data_ptr, data_chunk + 2, data_size % data_chunk_size);
2064 } else {
2065 memcpy(data_chunk + 2, data_ptr, data_size % data_chunk_size);
2066
2067 ret = arcturus_i2c_write_data(i2c_adap,
2068 (uint8_t)msgs[i].addr,
2069 data_chunk, (data_size % data_chunk_size) + 2);
2070 }
2071
2072 if (ret) {
2073 num = -EIO;
2074 goto fail;
2075 }
2076 }
2077 }
2078
2079 fail:
2080 return num;
2081 }
2082
arcturus_i2c_func(struct i2c_adapter * adap)2083 static u32 arcturus_i2c_func(struct i2c_adapter *adap)
2084 {
2085 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
2086 }
2087
2088
2089 static const struct i2c_algorithm arcturus_i2c_algo = {
2090 .master_xfer = arcturus_i2c_xfer,
2091 .functionality = arcturus_i2c_func,
2092 };
2093
arcturus_i2c_control_init(struct smu_context * smu,struct i2c_adapter * control)2094 static int arcturus_i2c_control_init(struct smu_context *smu, struct i2c_adapter *control)
2095 {
2096 struct amdgpu_device *adev = to_amdgpu_device(control);
2097 int res;
2098
2099 control->owner = THIS_MODULE;
2100 control->class = I2C_CLASS_SPD;
2101 control->dev.parent = &adev->pdev->dev;
2102 control->algo = &arcturus_i2c_algo;
2103 snprintf(control->name, sizeof(control->name), "AMDGPU SMU");
2104
2105 res = i2c_add_adapter(control);
2106 if (res)
2107 DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
2108
2109 return res;
2110 }
2111
arcturus_i2c_control_fini(struct smu_context * smu,struct i2c_adapter * control)2112 static void arcturus_i2c_control_fini(struct smu_context *smu, struct i2c_adapter *control)
2113 {
2114 i2c_del_adapter(control);
2115 }
2116
arcturus_get_unique_id(struct smu_context * smu)2117 static void arcturus_get_unique_id(struct smu_context *smu)
2118 {
2119 struct amdgpu_device *adev = smu->adev;
2120 uint32_t top32 = 0, bottom32 = 0, smu_version;
2121 uint64_t id;
2122
2123 if (smu_cmn_get_smc_version(smu, NULL, &smu_version)) {
2124 dev_warn(adev->dev, "Failed to get smu version, cannot get unique_id or serial_number\n");
2125 return;
2126 }
2127
2128 /* PPSMC_MSG_ReadSerial* is supported by 54.23.0 and onwards */
2129 if (smu_version < 0x361700) {
2130 dev_warn(adev->dev, "ReadSerial is only supported by PMFW 54.23.0 and onwards\n");
2131 return;
2132 }
2133
2134 /* Get the SN to turn into a Unique ID */
2135 smu_cmn_send_smc_msg(smu, SMU_MSG_ReadSerialNumTop32, &top32);
2136 smu_cmn_send_smc_msg(smu, SMU_MSG_ReadSerialNumBottom32, &bottom32);
2137
2138 id = ((uint64_t)bottom32 << 32) | top32;
2139 adev->unique_id = id;
2140 /* For Arcturus-and-later, unique_id == serial_number, so convert it to a
2141 * 16-digit HEX string for convenience and backwards-compatibility
2142 */
2143 sprintf(adev->serial, "%llx", id);
2144 }
2145
arcturus_is_baco_supported(struct smu_context * smu)2146 static bool arcturus_is_baco_supported(struct smu_context *smu)
2147 {
2148 struct amdgpu_device *adev = smu->adev;
2149
2150 if (!smu_v11_0_baco_is_support(smu) || amdgpu_sriov_vf(adev))
2151 return false;
2152
2153 return true;
2154 }
2155
arcturus_set_df_cstate(struct smu_context * smu,enum pp_df_cstate state)2156 static int arcturus_set_df_cstate(struct smu_context *smu,
2157 enum pp_df_cstate state)
2158 {
2159 uint32_t smu_version;
2160 int ret;
2161
2162 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
2163 if (ret) {
2164 dev_err(smu->adev->dev, "Failed to get smu version!\n");
2165 return ret;
2166 }
2167
2168 /* PPSMC_MSG_DFCstateControl is supported by 54.15.0 and onwards */
2169 if (smu_version < 0x360F00) {
2170 dev_err(smu->adev->dev, "DFCstateControl is only supported by PMFW 54.15.0 and onwards\n");
2171 return -EINVAL;
2172 }
2173
2174 return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DFCstateControl, state, NULL);
2175 }
2176
arcturus_allow_xgmi_power_down(struct smu_context * smu,bool en)2177 static int arcturus_allow_xgmi_power_down(struct smu_context *smu, bool en)
2178 {
2179 uint32_t smu_version;
2180 int ret;
2181
2182 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
2183 if (ret) {
2184 dev_err(smu->adev->dev, "Failed to get smu version!\n");
2185 return ret;
2186 }
2187
2188 /* PPSMC_MSG_GmiPwrDnControl is supported by 54.23.0 and onwards */
2189 if (smu_version < 0x00361700) {
2190 dev_err(smu->adev->dev, "XGMI power down control is only supported by PMFW 54.23.0 and onwards\n");
2191 return -EINVAL;
2192 }
2193
2194 if (en)
2195 return smu_cmn_send_smc_msg_with_param(smu,
2196 SMU_MSG_GmiPwrDnControl,
2197 1,
2198 NULL);
2199
2200 return smu_cmn_send_smc_msg_with_param(smu,
2201 SMU_MSG_GmiPwrDnControl,
2202 0,
2203 NULL);
2204 }
2205
2206 static const struct throttling_logging_label {
2207 uint32_t feature_mask;
2208 const char *label;
2209 } logging_label[] = {
2210 {(1U << THROTTLER_TEMP_HOTSPOT_BIT), "GPU"},
2211 {(1U << THROTTLER_TEMP_MEM_BIT), "HBM"},
2212 {(1U << THROTTLER_TEMP_VR_GFX_BIT), "VR of GFX rail"},
2213 {(1U << THROTTLER_TEMP_VR_MEM_BIT), "VR of HBM rail"},
2214 {(1U << THROTTLER_TEMP_VR_SOC_BIT), "VR of SOC rail"},
2215 {(1U << THROTTLER_VRHOT0_BIT), "VR0 HOT"},
2216 {(1U << THROTTLER_VRHOT1_BIT), "VR1 HOT"},
2217 };
arcturus_log_thermal_throttling_event(struct smu_context * smu)2218 static void arcturus_log_thermal_throttling_event(struct smu_context *smu)
2219 {
2220 int ret;
2221 int throttler_idx, throtting_events = 0, buf_idx = 0;
2222 struct amdgpu_device *adev = smu->adev;
2223 uint32_t throttler_status;
2224 char log_buf[256];
2225
2226 ret = arcturus_get_smu_metrics_data(smu,
2227 METRICS_THROTTLER_STATUS,
2228 &throttler_status);
2229 if (ret)
2230 return;
2231
2232 memset(log_buf, 0, sizeof(log_buf));
2233 for (throttler_idx = 0; throttler_idx < ARRAY_SIZE(logging_label);
2234 throttler_idx++) {
2235 if (throttler_status & logging_label[throttler_idx].feature_mask) {
2236 throtting_events++;
2237 buf_idx += snprintf(log_buf + buf_idx,
2238 sizeof(log_buf) - buf_idx,
2239 "%s%s",
2240 throtting_events > 1 ? " and " : "",
2241 logging_label[throttler_idx].label);
2242 if (buf_idx >= sizeof(log_buf)) {
2243 dev_err(adev->dev, "buffer overflow!\n");
2244 log_buf[sizeof(log_buf) - 1] = '\0';
2245 break;
2246 }
2247 }
2248 }
2249
2250 dev_warn(adev->dev, "WARN: GPU thermal throttling temperature reached, expect performance decrease. %s.\n",
2251 log_buf);
2252 kgd2kfd_smi_event_throttle(smu->adev->kfd.dev, throttler_status);
2253 }
2254
arcturus_get_current_pcie_link_speed(struct smu_context * smu)2255 static int arcturus_get_current_pcie_link_speed(struct smu_context *smu)
2256 {
2257 struct amdgpu_device *adev = smu->adev;
2258 uint32_t esm_ctrl;
2259
2260 /* TODO: confirm this on real target */
2261 esm_ctrl = RREG32_PCIE(smnPCIE_ESM_CTRL);
2262 if ((esm_ctrl >> 15) & 0x1FFFF)
2263 return (((esm_ctrl >> 8) & 0x3F) + 128);
2264
2265 return smu_v11_0_get_current_pcie_link_speed(smu);
2266 }
2267
arcturus_get_gpu_metrics(struct smu_context * smu,void ** table)2268 static ssize_t arcturus_get_gpu_metrics(struct smu_context *smu,
2269 void **table)
2270 {
2271 struct smu_table_context *smu_table = &smu->smu_table;
2272 struct gpu_metrics_v1_0 *gpu_metrics =
2273 (struct gpu_metrics_v1_0 *)smu_table->gpu_metrics_table;
2274 SmuMetrics_t metrics;
2275 int ret = 0;
2276
2277 ret = smu_cmn_get_metrics_table(smu,
2278 &metrics,
2279 true);
2280 if (ret)
2281 return ret;
2282
2283 smu_v11_0_init_gpu_metrics_v1_0(gpu_metrics);
2284
2285 gpu_metrics->temperature_edge = metrics.TemperatureEdge;
2286 gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot;
2287 gpu_metrics->temperature_mem = metrics.TemperatureHBM;
2288 gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx;
2289 gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc;
2290 gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem;
2291
2292 gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity;
2293 gpu_metrics->average_umc_activity = metrics.AverageUclkActivity;
2294 gpu_metrics->average_mm_activity = metrics.VcnActivityPercentage;
2295
2296 gpu_metrics->average_socket_power = metrics.AverageSocketPower;
2297 gpu_metrics->energy_accumulator = metrics.EnergyAccumulator;
2298
2299 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency;
2300 gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency;
2301 gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequency;
2302 gpu_metrics->average_vclk0_frequency = metrics.AverageVclkFrequency;
2303 gpu_metrics->average_dclk0_frequency = metrics.AverageDclkFrequency;
2304
2305 gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK];
2306 gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK];
2307 gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK];
2308 gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK];
2309 gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];
2310
2311 gpu_metrics->throttle_status = metrics.ThrottlerStatus;
2312
2313 gpu_metrics->current_fan_speed = metrics.CurrFanSpeed;
2314
2315 gpu_metrics->pcie_link_width =
2316 smu_v11_0_get_current_pcie_link_width(smu);
2317 gpu_metrics->pcie_link_speed =
2318 arcturus_get_current_pcie_link_speed(smu);
2319
2320 *table = (void *)gpu_metrics;
2321
2322 return sizeof(struct gpu_metrics_v1_0);
2323 }
2324
2325 static const struct pptable_funcs arcturus_ppt_funcs = {
2326 /* init dpm */
2327 .get_allowed_feature_mask = arcturus_get_allowed_feature_mask,
2328 /* btc */
2329 .run_btc = arcturus_run_btc,
2330 /* dpm/clk tables */
2331 .set_default_dpm_table = arcturus_set_default_dpm_table,
2332 .populate_umd_state_clk = arcturus_populate_umd_state_clk,
2333 .get_thermal_temperature_range = arcturus_get_thermal_temperature_range,
2334 .print_clk_levels = arcturus_print_clk_levels,
2335 .force_clk_levels = arcturus_force_clk_levels,
2336 .read_sensor = arcturus_read_sensor,
2337 .get_fan_speed_rpm = arcturus_get_fan_speed_rpm,
2338 .get_power_profile_mode = arcturus_get_power_profile_mode,
2339 .set_power_profile_mode = arcturus_set_power_profile_mode,
2340 .set_performance_level = arcturus_set_performance_level,
2341 /* debug (internal used) */
2342 .dump_pptable = arcturus_dump_pptable,
2343 .get_power_limit = arcturus_get_power_limit,
2344 .is_dpm_running = arcturus_is_dpm_running,
2345 .dpm_set_vcn_enable = arcturus_dpm_set_vcn_enable,
2346 .i2c_init = arcturus_i2c_control_init,
2347 .i2c_fini = arcturus_i2c_control_fini,
2348 .get_unique_id = arcturus_get_unique_id,
2349 .init_microcode = smu_v11_0_init_microcode,
2350 .load_microcode = smu_v11_0_load_microcode,
2351 .fini_microcode = smu_v11_0_fini_microcode,
2352 .init_smc_tables = arcturus_init_smc_tables,
2353 .fini_smc_tables = smu_v11_0_fini_smc_tables,
2354 .init_power = smu_v11_0_init_power,
2355 .fini_power = smu_v11_0_fini_power,
2356 .check_fw_status = smu_v11_0_check_fw_status,
2357 /* pptable related */
2358 .setup_pptable = arcturus_setup_pptable,
2359 .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
2360 .check_fw_version = smu_v11_0_check_fw_version,
2361 .write_pptable = smu_cmn_write_pptable,
2362 .set_driver_table_location = smu_v11_0_set_driver_table_location,
2363 .set_tool_table_location = smu_v11_0_set_tool_table_location,
2364 .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
2365 .system_features_control = smu_v11_0_system_features_control,
2366 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
2367 .send_smc_msg = smu_cmn_send_smc_msg,
2368 .init_display_count = NULL,
2369 .set_allowed_mask = smu_v11_0_set_allowed_mask,
2370 .get_enabled_mask = smu_cmn_get_enabled_mask,
2371 .feature_is_enabled = smu_cmn_feature_is_enabled,
2372 .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception,
2373 .notify_display_change = NULL,
2374 .set_power_limit = smu_v11_0_set_power_limit,
2375 .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
2376 .enable_thermal_alert = smu_v11_0_enable_thermal_alert,
2377 .disable_thermal_alert = smu_v11_0_disable_thermal_alert,
2378 .set_min_dcef_deep_sleep = NULL,
2379 .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
2380 .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
2381 .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
2382 .set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
2383 .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
2384 .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
2385 .gfx_off_control = smu_v11_0_gfx_off_control,
2386 .register_irq_handler = smu_v11_0_register_irq_handler,
2387 .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
2388 .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
2389 .baco_is_support= arcturus_is_baco_supported,
2390 .baco_get_state = smu_v11_0_baco_get_state,
2391 .baco_set_state = smu_v11_0_baco_set_state,
2392 .baco_enter = smu_v11_0_baco_enter,
2393 .baco_exit = smu_v11_0_baco_exit,
2394 .get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
2395 .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
2396 .set_df_cstate = arcturus_set_df_cstate,
2397 .allow_xgmi_power_down = arcturus_allow_xgmi_power_down,
2398 .log_thermal_throttling_event = arcturus_log_thermal_throttling_event,
2399 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
2400 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
2401 .get_gpu_metrics = arcturus_get_gpu_metrics,
2402 .gfx_ulv_control = smu_v11_0_gfx_ulv_control,
2403 .deep_sleep_control = smu_v11_0_deep_sleep_control,
2404 .get_fan_parameters = arcturus_get_fan_parameters,
2405 .interrupt_work = smu_v11_0_interrupt_work,
2406 };
2407
arcturus_set_ppt_funcs(struct smu_context * smu)2408 void arcturus_set_ppt_funcs(struct smu_context *smu)
2409 {
2410 smu->ppt_funcs = &arcturus_ppt_funcs;
2411 smu->message_map = arcturus_message_map;
2412 smu->clock_map = arcturus_clk_map;
2413 smu->feature_map = arcturus_feature_mask_map;
2414 smu->table_map = arcturus_table_map;
2415 smu->pwr_src_map = arcturus_pwr_src_map;
2416 smu->workload_map = arcturus_workload_map;
2417 }
2418