1 // SPDX-License-Identifier: ISC
2 /*
3 * Copyright (c) 2005-2011 Atheros Communications Inc.
4 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.
5 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
6 */
7
8 #include <linux/module.h>
9 #include <linux/firmware.h>
10 #include <linux/of.h>
11 #include <linux/property.h>
12 #include <linux/dmi.h>
13 #include <linux/ctype.h>
14 #include <linux/pm_qos.h>
15 #include <asm/byteorder.h>
16
17 #include "core.h"
18 #include "mac.h"
19 #include "htc.h"
20 #include "hif.h"
21 #include "wmi.h"
22 #include "bmi.h"
23 #include "debug.h"
24 #include "htt.h"
25 #include "testmode.h"
26 #include "wmi-ops.h"
27 #include "coredump.h"
28
29 unsigned int ath10k_debug_mask;
30 EXPORT_SYMBOL(ath10k_debug_mask);
31
32 static unsigned int ath10k_cryptmode_param;
33 static bool uart_print;
34 static bool skip_otp;
35 static bool rawmode;
36 static bool fw_diag_log;
37
38 unsigned long ath10k_coredump_mask = BIT(ATH10K_FW_CRASH_DUMP_REGISTERS) |
39 BIT(ATH10K_FW_CRASH_DUMP_CE_DATA);
40
41 /* FIXME: most of these should be readonly */
42 module_param_named(debug_mask, ath10k_debug_mask, uint, 0644);
43 module_param_named(cryptmode, ath10k_cryptmode_param, uint, 0644);
44 module_param(uart_print, bool, 0644);
45 module_param(skip_otp, bool, 0644);
46 module_param(rawmode, bool, 0644);
47 module_param(fw_diag_log, bool, 0644);
48 module_param_named(coredump_mask, ath10k_coredump_mask, ulong, 0444);
49
50 MODULE_PARM_DESC(debug_mask, "Debugging mask");
51 MODULE_PARM_DESC(uart_print, "Uart target debugging");
52 MODULE_PARM_DESC(skip_otp, "Skip otp failure for calibration in testmode");
53 MODULE_PARM_DESC(cryptmode, "Crypto mode: 0-hardware, 1-software");
54 MODULE_PARM_DESC(rawmode, "Use raw 802.11 frame datapath");
55 MODULE_PARM_DESC(coredump_mask, "Bitfield of what to include in firmware crash file");
56 MODULE_PARM_DESC(fw_diag_log, "Diag based fw log debugging");
57
58 static const struct ath10k_hw_params ath10k_hw_params_list[] = {
59 {
60 .id = QCA988X_HW_2_0_VERSION,
61 .dev_id = QCA988X_2_0_DEVICE_ID,
62 .bus = ATH10K_BUS_PCI,
63 .name = "qca988x hw2.0",
64 .patch_load_addr = QCA988X_HW_2_0_PATCH_LOAD_ADDR,
65 .uart_pin = 7,
66 .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_ALL,
67 .otp_exe_param = 0,
68 .channel_counters_freq_hz = 88000,
69 .max_probe_resp_desc_thres = 0,
70 .cal_data_len = 2116,
71 .fw = {
72 .dir = QCA988X_HW_2_0_FW_DIR,
73 .board = QCA988X_HW_2_0_BOARD_DATA_FILE,
74 .board_size = QCA988X_BOARD_DATA_SZ,
75 .board_ext_size = QCA988X_BOARD_EXT_DATA_SZ,
76 },
77 .hw_ops = &qca988x_ops,
78 .decap_align_bytes = 4,
79 .spectral_bin_discard = 0,
80 .spectral_bin_offset = 0,
81 .vht160_mcs_rx_highest = 0,
82 .vht160_mcs_tx_highest = 0,
83 .n_cipher_suites = 8,
84 .ast_skid_limit = 0x10,
85 .num_wds_entries = 0x20,
86 .target_64bit = false,
87 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
88 .shadow_reg_support = false,
89 .rri_on_ddr = false,
90 .hw_filter_reset_required = true,
91 .fw_diag_ce_download = false,
92 .credit_size_workaround = false,
93 .tx_stats_over_pktlog = true,
94 },
95 {
96 .id = QCA988X_HW_2_0_VERSION,
97 .dev_id = QCA988X_2_0_DEVICE_ID_UBNT,
98 .name = "qca988x hw2.0 ubiquiti",
99 .patch_load_addr = QCA988X_HW_2_0_PATCH_LOAD_ADDR,
100 .uart_pin = 7,
101 .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_ALL,
102 .otp_exe_param = 0,
103 .channel_counters_freq_hz = 88000,
104 .max_probe_resp_desc_thres = 0,
105 .cal_data_len = 2116,
106 .fw = {
107 .dir = QCA988X_HW_2_0_FW_DIR,
108 .board = QCA988X_HW_2_0_BOARD_DATA_FILE,
109 .board_size = QCA988X_BOARD_DATA_SZ,
110 .board_ext_size = QCA988X_BOARD_EXT_DATA_SZ,
111 },
112 .hw_ops = &qca988x_ops,
113 .decap_align_bytes = 4,
114 .spectral_bin_discard = 0,
115 .spectral_bin_offset = 0,
116 .vht160_mcs_rx_highest = 0,
117 .vht160_mcs_tx_highest = 0,
118 .n_cipher_suites = 8,
119 .ast_skid_limit = 0x10,
120 .num_wds_entries = 0x20,
121 .target_64bit = false,
122 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
123 .shadow_reg_support = false,
124 .rri_on_ddr = false,
125 .hw_filter_reset_required = true,
126 .fw_diag_ce_download = false,
127 .credit_size_workaround = false,
128 .tx_stats_over_pktlog = true,
129 },
130 {
131 .id = QCA9887_HW_1_0_VERSION,
132 .dev_id = QCA9887_1_0_DEVICE_ID,
133 .bus = ATH10K_BUS_PCI,
134 .name = "qca9887 hw1.0",
135 .patch_load_addr = QCA9887_HW_1_0_PATCH_LOAD_ADDR,
136 .uart_pin = 7,
137 .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_ALL,
138 .otp_exe_param = 0,
139 .channel_counters_freq_hz = 88000,
140 .max_probe_resp_desc_thres = 0,
141 .cal_data_len = 2116,
142 .fw = {
143 .dir = QCA9887_HW_1_0_FW_DIR,
144 .board = QCA9887_HW_1_0_BOARD_DATA_FILE,
145 .board_size = QCA9887_BOARD_DATA_SZ,
146 .board_ext_size = QCA9887_BOARD_EXT_DATA_SZ,
147 },
148 .hw_ops = &qca988x_ops,
149 .decap_align_bytes = 4,
150 .spectral_bin_discard = 0,
151 .spectral_bin_offset = 0,
152 .vht160_mcs_rx_highest = 0,
153 .vht160_mcs_tx_highest = 0,
154 .n_cipher_suites = 8,
155 .ast_skid_limit = 0x10,
156 .num_wds_entries = 0x20,
157 .target_64bit = false,
158 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
159 .shadow_reg_support = false,
160 .rri_on_ddr = false,
161 .hw_filter_reset_required = true,
162 .fw_diag_ce_download = false,
163 .credit_size_workaround = false,
164 .tx_stats_over_pktlog = false,
165 },
166 {
167 .id = QCA6174_HW_3_2_VERSION,
168 .dev_id = QCA6174_3_2_DEVICE_ID,
169 .bus = ATH10K_BUS_SDIO,
170 .name = "qca6174 hw3.2 sdio",
171 .patch_load_addr = QCA6174_HW_3_0_PATCH_LOAD_ADDR,
172 .uart_pin = 19,
173 .otp_exe_param = 0,
174 .channel_counters_freq_hz = 88000,
175 .max_probe_resp_desc_thres = 0,
176 .cal_data_len = 0,
177 .fw = {
178 .dir = QCA6174_HW_3_0_FW_DIR,
179 .board = QCA6174_HW_3_0_BOARD_DATA_FILE,
180 .board_size = QCA6174_BOARD_DATA_SZ,
181 .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ,
182 },
183 .hw_ops = &qca6174_sdio_ops,
184 .hw_clk = qca6174_clk,
185 .target_cpu_freq = 176000000,
186 .decap_align_bytes = 4,
187 .n_cipher_suites = 8,
188 .num_peers = 10,
189 .ast_skid_limit = 0x10,
190 .num_wds_entries = 0x20,
191 .uart_pin_workaround = true,
192 .tx_stats_over_pktlog = false,
193 .credit_size_workaround = false,
194 .bmi_large_size_download = true,
195 .supports_peer_stats_info = true,
196 },
197 {
198 .id = QCA6174_HW_2_1_VERSION,
199 .dev_id = QCA6164_2_1_DEVICE_ID,
200 .bus = ATH10K_BUS_PCI,
201 .name = "qca6164 hw2.1",
202 .patch_load_addr = QCA6174_HW_2_1_PATCH_LOAD_ADDR,
203 .uart_pin = 6,
204 .otp_exe_param = 0,
205 .channel_counters_freq_hz = 88000,
206 .max_probe_resp_desc_thres = 0,
207 .cal_data_len = 8124,
208 .fw = {
209 .dir = QCA6174_HW_2_1_FW_DIR,
210 .board = QCA6174_HW_2_1_BOARD_DATA_FILE,
211 .board_size = QCA6174_BOARD_DATA_SZ,
212 .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ,
213 },
214 .hw_ops = &qca988x_ops,
215 .decap_align_bytes = 4,
216 .spectral_bin_discard = 0,
217 .spectral_bin_offset = 0,
218 .vht160_mcs_rx_highest = 0,
219 .vht160_mcs_tx_highest = 0,
220 .n_cipher_suites = 8,
221 .ast_skid_limit = 0x10,
222 .num_wds_entries = 0x20,
223 .target_64bit = false,
224 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
225 .shadow_reg_support = false,
226 .rri_on_ddr = false,
227 .hw_filter_reset_required = true,
228 .fw_diag_ce_download = false,
229 .credit_size_workaround = false,
230 .tx_stats_over_pktlog = false,
231 },
232 {
233 .id = QCA6174_HW_2_1_VERSION,
234 .dev_id = QCA6174_2_1_DEVICE_ID,
235 .bus = ATH10K_BUS_PCI,
236 .name = "qca6174 hw2.1",
237 .patch_load_addr = QCA6174_HW_2_1_PATCH_LOAD_ADDR,
238 .uart_pin = 6,
239 .otp_exe_param = 0,
240 .channel_counters_freq_hz = 88000,
241 .max_probe_resp_desc_thres = 0,
242 .cal_data_len = 8124,
243 .fw = {
244 .dir = QCA6174_HW_2_1_FW_DIR,
245 .board = QCA6174_HW_2_1_BOARD_DATA_FILE,
246 .board_size = QCA6174_BOARD_DATA_SZ,
247 .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ,
248 },
249 .hw_ops = &qca988x_ops,
250 .decap_align_bytes = 4,
251 .spectral_bin_discard = 0,
252 .spectral_bin_offset = 0,
253 .vht160_mcs_rx_highest = 0,
254 .vht160_mcs_tx_highest = 0,
255 .n_cipher_suites = 8,
256 .ast_skid_limit = 0x10,
257 .num_wds_entries = 0x20,
258 .target_64bit = false,
259 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
260 .shadow_reg_support = false,
261 .rri_on_ddr = false,
262 .hw_filter_reset_required = true,
263 .fw_diag_ce_download = false,
264 .credit_size_workaround = false,
265 .tx_stats_over_pktlog = false,
266 },
267 {
268 .id = QCA6174_HW_3_0_VERSION,
269 .dev_id = QCA6174_2_1_DEVICE_ID,
270 .bus = ATH10K_BUS_PCI,
271 .name = "qca6174 hw3.0",
272 .patch_load_addr = QCA6174_HW_3_0_PATCH_LOAD_ADDR,
273 .uart_pin = 6,
274 .otp_exe_param = 0,
275 .channel_counters_freq_hz = 88000,
276 .max_probe_resp_desc_thres = 0,
277 .cal_data_len = 8124,
278 .fw = {
279 .dir = QCA6174_HW_3_0_FW_DIR,
280 .board = QCA6174_HW_3_0_BOARD_DATA_FILE,
281 .board_size = QCA6174_BOARD_DATA_SZ,
282 .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ,
283 },
284 .hw_ops = &qca988x_ops,
285 .decap_align_bytes = 4,
286 .spectral_bin_discard = 0,
287 .spectral_bin_offset = 0,
288 .vht160_mcs_rx_highest = 0,
289 .vht160_mcs_tx_highest = 0,
290 .n_cipher_suites = 8,
291 .ast_skid_limit = 0x10,
292 .num_wds_entries = 0x20,
293 .target_64bit = false,
294 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
295 .shadow_reg_support = false,
296 .rri_on_ddr = false,
297 .hw_filter_reset_required = true,
298 .fw_diag_ce_download = false,
299 .credit_size_workaround = false,
300 .tx_stats_over_pktlog = false,
301 },
302 {
303 .id = QCA6174_HW_3_2_VERSION,
304 .dev_id = QCA6174_2_1_DEVICE_ID,
305 .bus = ATH10K_BUS_PCI,
306 .name = "qca6174 hw3.2",
307 .patch_load_addr = QCA6174_HW_3_0_PATCH_LOAD_ADDR,
308 .uart_pin = 6,
309 .otp_exe_param = 0,
310 .channel_counters_freq_hz = 88000,
311 .max_probe_resp_desc_thres = 0,
312 .cal_data_len = 8124,
313 .fw = {
314 /* uses same binaries as hw3.0 */
315 .dir = QCA6174_HW_3_0_FW_DIR,
316 .board = QCA6174_HW_3_0_BOARD_DATA_FILE,
317 .board_size = QCA6174_BOARD_DATA_SZ,
318 .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ,
319 },
320 .hw_ops = &qca6174_ops,
321 .hw_clk = qca6174_clk,
322 .target_cpu_freq = 176000000,
323 .decap_align_bytes = 4,
324 .spectral_bin_discard = 0,
325 .spectral_bin_offset = 0,
326 .vht160_mcs_rx_highest = 0,
327 .vht160_mcs_tx_highest = 0,
328 .n_cipher_suites = 8,
329 .ast_skid_limit = 0x10,
330 .num_wds_entries = 0x20,
331 .target_64bit = false,
332 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
333 .shadow_reg_support = false,
334 .rri_on_ddr = false,
335 .hw_filter_reset_required = true,
336 .fw_diag_ce_download = true,
337 .credit_size_workaround = false,
338 .tx_stats_over_pktlog = false,
339 .supports_peer_stats_info = true,
340 },
341 {
342 .id = QCA99X0_HW_2_0_DEV_VERSION,
343 .dev_id = QCA99X0_2_0_DEVICE_ID,
344 .bus = ATH10K_BUS_PCI,
345 .name = "qca99x0 hw2.0",
346 .patch_load_addr = QCA99X0_HW_2_0_PATCH_LOAD_ADDR,
347 .uart_pin = 7,
348 .otp_exe_param = 0x00000700,
349 .continuous_frag_desc = true,
350 .cck_rate_map_rev2 = true,
351 .channel_counters_freq_hz = 150000,
352 .max_probe_resp_desc_thres = 24,
353 .tx_chain_mask = 0xf,
354 .rx_chain_mask = 0xf,
355 .max_spatial_stream = 4,
356 .cal_data_len = 12064,
357 .fw = {
358 .dir = QCA99X0_HW_2_0_FW_DIR,
359 .board = QCA99X0_HW_2_0_BOARD_DATA_FILE,
360 .board_size = QCA99X0_BOARD_DATA_SZ,
361 .board_ext_size = QCA99X0_BOARD_EXT_DATA_SZ,
362 },
363 .sw_decrypt_mcast_mgmt = true,
364 .hw_ops = &qca99x0_ops,
365 .decap_align_bytes = 1,
366 .spectral_bin_discard = 4,
367 .spectral_bin_offset = 0,
368 .vht160_mcs_rx_highest = 0,
369 .vht160_mcs_tx_highest = 0,
370 .n_cipher_suites = 11,
371 .ast_skid_limit = 0x10,
372 .num_wds_entries = 0x20,
373 .target_64bit = false,
374 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
375 .shadow_reg_support = false,
376 .rri_on_ddr = false,
377 .hw_filter_reset_required = true,
378 .fw_diag_ce_download = false,
379 .credit_size_workaround = false,
380 .tx_stats_over_pktlog = false,
381 },
382 {
383 .id = QCA9984_HW_1_0_DEV_VERSION,
384 .dev_id = QCA9984_1_0_DEVICE_ID,
385 .bus = ATH10K_BUS_PCI,
386 .name = "qca9984/qca9994 hw1.0",
387 .patch_load_addr = QCA9984_HW_1_0_PATCH_LOAD_ADDR,
388 .uart_pin = 7,
389 .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_EACH,
390 .otp_exe_param = 0x00000700,
391 .continuous_frag_desc = true,
392 .cck_rate_map_rev2 = true,
393 .channel_counters_freq_hz = 150000,
394 .max_probe_resp_desc_thres = 24,
395 .tx_chain_mask = 0xf,
396 .rx_chain_mask = 0xf,
397 .max_spatial_stream = 4,
398 .cal_data_len = 12064,
399 .fw = {
400 .dir = QCA9984_HW_1_0_FW_DIR,
401 .board = QCA9984_HW_1_0_BOARD_DATA_FILE,
402 .eboard = QCA9984_HW_1_0_EBOARD_DATA_FILE,
403 .board_size = QCA99X0_BOARD_DATA_SZ,
404 .board_ext_size = QCA99X0_BOARD_EXT_DATA_SZ,
405 .ext_board_size = QCA99X0_EXT_BOARD_DATA_SZ,
406 },
407 .sw_decrypt_mcast_mgmt = true,
408 .hw_ops = &qca99x0_ops,
409 .decap_align_bytes = 1,
410 .spectral_bin_discard = 12,
411 .spectral_bin_offset = 8,
412
413 /* Can do only 2x2 VHT160 or 80+80. 1560Mbps is 4x4 80Mhz
414 * or 2x2 160Mhz, long-guard-interval.
415 */
416 .vht160_mcs_rx_highest = 1560,
417 .vht160_mcs_tx_highest = 1560,
418 .n_cipher_suites = 11,
419 .ast_skid_limit = 0x10,
420 .num_wds_entries = 0x20,
421 .target_64bit = false,
422 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
423 .shadow_reg_support = false,
424 .rri_on_ddr = false,
425 .hw_filter_reset_required = true,
426 .fw_diag_ce_download = false,
427 .credit_size_workaround = false,
428 .tx_stats_over_pktlog = false,
429 },
430 {
431 .id = QCA9888_HW_2_0_DEV_VERSION,
432 .dev_id = QCA9888_2_0_DEVICE_ID,
433 .bus = ATH10K_BUS_PCI,
434 .name = "qca9888 hw2.0",
435 .patch_load_addr = QCA9888_HW_2_0_PATCH_LOAD_ADDR,
436 .uart_pin = 7,
437 .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_EACH,
438 .otp_exe_param = 0x00000700,
439 .continuous_frag_desc = true,
440 .channel_counters_freq_hz = 150000,
441 .max_probe_resp_desc_thres = 24,
442 .tx_chain_mask = 3,
443 .rx_chain_mask = 3,
444 .max_spatial_stream = 2,
445 .cal_data_len = 12064,
446 .fw = {
447 .dir = QCA9888_HW_2_0_FW_DIR,
448 .board = QCA9888_HW_2_0_BOARD_DATA_FILE,
449 .board_size = QCA99X0_BOARD_DATA_SZ,
450 .board_ext_size = QCA99X0_BOARD_EXT_DATA_SZ,
451 },
452 .sw_decrypt_mcast_mgmt = true,
453 .hw_ops = &qca99x0_ops,
454 .decap_align_bytes = 1,
455 .spectral_bin_discard = 12,
456 .spectral_bin_offset = 8,
457
458 /* Can do only 1x1 VHT160 or 80+80. 780Mbps is 2x2 80Mhz or
459 * 1x1 160Mhz, long-guard-interval.
460 */
461 .vht160_mcs_rx_highest = 780,
462 .vht160_mcs_tx_highest = 780,
463 .n_cipher_suites = 11,
464 .ast_skid_limit = 0x10,
465 .num_wds_entries = 0x20,
466 .target_64bit = false,
467 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
468 .shadow_reg_support = false,
469 .rri_on_ddr = false,
470 .hw_filter_reset_required = true,
471 .fw_diag_ce_download = false,
472 .credit_size_workaround = false,
473 .tx_stats_over_pktlog = false,
474 },
475 {
476 .id = QCA9377_HW_1_0_DEV_VERSION,
477 .dev_id = QCA9377_1_0_DEVICE_ID,
478 .bus = ATH10K_BUS_PCI,
479 .name = "qca9377 hw1.0",
480 .patch_load_addr = QCA9377_HW_1_0_PATCH_LOAD_ADDR,
481 .uart_pin = 6,
482 .otp_exe_param = 0,
483 .channel_counters_freq_hz = 88000,
484 .max_probe_resp_desc_thres = 0,
485 .cal_data_len = 8124,
486 .fw = {
487 .dir = QCA9377_HW_1_0_FW_DIR,
488 .board = QCA9377_HW_1_0_BOARD_DATA_FILE,
489 .board_size = QCA9377_BOARD_DATA_SZ,
490 .board_ext_size = QCA9377_BOARD_EXT_DATA_SZ,
491 },
492 .hw_ops = &qca988x_ops,
493 .decap_align_bytes = 4,
494 .spectral_bin_discard = 0,
495 .spectral_bin_offset = 0,
496 .vht160_mcs_rx_highest = 0,
497 .vht160_mcs_tx_highest = 0,
498 .n_cipher_suites = 8,
499 .ast_skid_limit = 0x10,
500 .num_wds_entries = 0x20,
501 .target_64bit = false,
502 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
503 .shadow_reg_support = false,
504 .rri_on_ddr = false,
505 .hw_filter_reset_required = true,
506 .fw_diag_ce_download = false,
507 .credit_size_workaround = false,
508 .tx_stats_over_pktlog = false,
509 },
510 {
511 .id = QCA9377_HW_1_1_DEV_VERSION,
512 .dev_id = QCA9377_1_0_DEVICE_ID,
513 .bus = ATH10K_BUS_PCI,
514 .name = "qca9377 hw1.1",
515 .patch_load_addr = QCA9377_HW_1_0_PATCH_LOAD_ADDR,
516 .uart_pin = 6,
517 .otp_exe_param = 0,
518 .channel_counters_freq_hz = 88000,
519 .max_probe_resp_desc_thres = 0,
520 .cal_data_len = 8124,
521 .fw = {
522 .dir = QCA9377_HW_1_0_FW_DIR,
523 .board = QCA9377_HW_1_0_BOARD_DATA_FILE,
524 .board_size = QCA9377_BOARD_DATA_SZ,
525 .board_ext_size = QCA9377_BOARD_EXT_DATA_SZ,
526 },
527 .hw_ops = &qca6174_ops,
528 .hw_clk = qca6174_clk,
529 .target_cpu_freq = 176000000,
530 .decap_align_bytes = 4,
531 .spectral_bin_discard = 0,
532 .spectral_bin_offset = 0,
533 .vht160_mcs_rx_highest = 0,
534 .vht160_mcs_tx_highest = 0,
535 .n_cipher_suites = 8,
536 .ast_skid_limit = 0x10,
537 .num_wds_entries = 0x20,
538 .target_64bit = false,
539 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
540 .shadow_reg_support = false,
541 .rri_on_ddr = false,
542 .hw_filter_reset_required = true,
543 .fw_diag_ce_download = true,
544 .credit_size_workaround = false,
545 .tx_stats_over_pktlog = false,
546 },
547 {
548 .id = QCA9377_HW_1_1_DEV_VERSION,
549 .dev_id = QCA9377_1_0_DEVICE_ID,
550 .bus = ATH10K_BUS_SDIO,
551 .name = "qca9377 hw1.1 sdio",
552 .patch_load_addr = QCA9377_HW_1_0_PATCH_LOAD_ADDR,
553 .uart_pin = 19,
554 .otp_exe_param = 0,
555 .channel_counters_freq_hz = 88000,
556 .max_probe_resp_desc_thres = 0,
557 .cal_data_len = 8124,
558 .fw = {
559 .dir = QCA9377_HW_1_0_FW_DIR,
560 .board = QCA9377_HW_1_0_BOARD_DATA_FILE,
561 .board_size = QCA9377_BOARD_DATA_SZ,
562 .board_ext_size = QCA9377_BOARD_EXT_DATA_SZ,
563 },
564 .hw_ops = &qca6174_ops,
565 .hw_clk = qca6174_clk,
566 .target_cpu_freq = 176000000,
567 .decap_align_bytes = 4,
568 .n_cipher_suites = 8,
569 .num_peers = TARGET_QCA9377_HL_NUM_PEERS,
570 .ast_skid_limit = 0x10,
571 .num_wds_entries = 0x20,
572 .uart_pin_workaround = true,
573 .credit_size_workaround = true,
574 },
575 {
576 .id = QCA4019_HW_1_0_DEV_VERSION,
577 .dev_id = 0,
578 .bus = ATH10K_BUS_AHB,
579 .name = "qca4019 hw1.0",
580 .patch_load_addr = QCA4019_HW_1_0_PATCH_LOAD_ADDR,
581 .uart_pin = 7,
582 .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_EACH,
583 .otp_exe_param = 0x0010000,
584 .continuous_frag_desc = true,
585 .cck_rate_map_rev2 = true,
586 .channel_counters_freq_hz = 125000,
587 .max_probe_resp_desc_thres = 24,
588 .tx_chain_mask = 0x3,
589 .rx_chain_mask = 0x3,
590 .max_spatial_stream = 2,
591 .cal_data_len = 12064,
592 .fw = {
593 .dir = QCA4019_HW_1_0_FW_DIR,
594 .board = QCA4019_HW_1_0_BOARD_DATA_FILE,
595 .board_size = QCA4019_BOARD_DATA_SZ,
596 .board_ext_size = QCA4019_BOARD_EXT_DATA_SZ,
597 },
598 .sw_decrypt_mcast_mgmt = true,
599 .hw_ops = &qca99x0_ops,
600 .decap_align_bytes = 1,
601 .spectral_bin_discard = 4,
602 .spectral_bin_offset = 0,
603 .vht160_mcs_rx_highest = 0,
604 .vht160_mcs_tx_highest = 0,
605 .n_cipher_suites = 11,
606 .ast_skid_limit = 0x10,
607 .num_wds_entries = 0x20,
608 .target_64bit = false,
609 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
610 .shadow_reg_support = false,
611 .rri_on_ddr = false,
612 .hw_filter_reset_required = true,
613 .fw_diag_ce_download = false,
614 .credit_size_workaround = false,
615 .tx_stats_over_pktlog = false,
616 },
617 {
618 .id = WCN3990_HW_1_0_DEV_VERSION,
619 .dev_id = 0,
620 .bus = ATH10K_BUS_SNOC,
621 .name = "wcn3990 hw1.0",
622 .continuous_frag_desc = true,
623 .tx_chain_mask = 0x7,
624 .rx_chain_mask = 0x7,
625 .max_spatial_stream = 4,
626 .fw = {
627 .dir = WCN3990_HW_1_0_FW_DIR,
628 },
629 .sw_decrypt_mcast_mgmt = true,
630 .hw_ops = &wcn3990_ops,
631 .decap_align_bytes = 1,
632 .num_peers = TARGET_HL_TLV_NUM_PEERS,
633 .n_cipher_suites = 11,
634 .ast_skid_limit = TARGET_HL_TLV_AST_SKID_LIMIT,
635 .num_wds_entries = TARGET_HL_TLV_NUM_WDS_ENTRIES,
636 .target_64bit = true,
637 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL_DUAL_MAC,
638 .shadow_reg_support = true,
639 .rri_on_ddr = true,
640 .hw_filter_reset_required = false,
641 .fw_diag_ce_download = false,
642 .credit_size_workaround = false,
643 .tx_stats_over_pktlog = false,
644 },
645 };
646
647 static const char *const ath10k_core_fw_feature_str[] = {
648 [ATH10K_FW_FEATURE_EXT_WMI_MGMT_RX] = "wmi-mgmt-rx",
649 [ATH10K_FW_FEATURE_WMI_10X] = "wmi-10.x",
650 [ATH10K_FW_FEATURE_HAS_WMI_MGMT_TX] = "has-wmi-mgmt-tx",
651 [ATH10K_FW_FEATURE_NO_P2P] = "no-p2p",
652 [ATH10K_FW_FEATURE_WMI_10_2] = "wmi-10.2",
653 [ATH10K_FW_FEATURE_MULTI_VIF_PS_SUPPORT] = "multi-vif-ps",
654 [ATH10K_FW_FEATURE_WOWLAN_SUPPORT] = "wowlan",
655 [ATH10K_FW_FEATURE_IGNORE_OTP_RESULT] = "ignore-otp",
656 [ATH10K_FW_FEATURE_NO_NWIFI_DECAP_4ADDR_PADDING] = "no-4addr-pad",
657 [ATH10K_FW_FEATURE_SUPPORTS_SKIP_CLOCK_INIT] = "skip-clock-init",
658 [ATH10K_FW_FEATURE_RAW_MODE_SUPPORT] = "raw-mode",
659 [ATH10K_FW_FEATURE_SUPPORTS_ADAPTIVE_CCA] = "adaptive-cca",
660 [ATH10K_FW_FEATURE_MFP_SUPPORT] = "mfp",
661 [ATH10K_FW_FEATURE_PEER_FLOW_CONTROL] = "peer-flow-ctrl",
662 [ATH10K_FW_FEATURE_BTCOEX_PARAM] = "btcoex-param",
663 [ATH10K_FW_FEATURE_SKIP_NULL_FUNC_WAR] = "skip-null-func-war",
664 [ATH10K_FW_FEATURE_ALLOWS_MESH_BCAST] = "allows-mesh-bcast",
665 [ATH10K_FW_FEATURE_NO_PS] = "no-ps",
666 [ATH10K_FW_FEATURE_MGMT_TX_BY_REF] = "mgmt-tx-by-reference",
667 [ATH10K_FW_FEATURE_NON_BMI] = "non-bmi",
668 [ATH10K_FW_FEATURE_SINGLE_CHAN_INFO_PER_CHANNEL] = "single-chan-info-per-channel",
669 [ATH10K_FW_FEATURE_PEER_FIXED_RATE] = "peer-fixed-rate",
670 };
671
ath10k_core_get_fw_feature_str(char * buf,size_t buf_len,enum ath10k_fw_features feat)672 static unsigned int ath10k_core_get_fw_feature_str(char *buf,
673 size_t buf_len,
674 enum ath10k_fw_features feat)
675 {
676 /* make sure that ath10k_core_fw_feature_str[] gets updated */
677 BUILD_BUG_ON(ARRAY_SIZE(ath10k_core_fw_feature_str) !=
678 ATH10K_FW_FEATURE_COUNT);
679
680 if (feat >= ARRAY_SIZE(ath10k_core_fw_feature_str) ||
681 WARN_ON(!ath10k_core_fw_feature_str[feat])) {
682 return scnprintf(buf, buf_len, "bit%d", feat);
683 }
684
685 return scnprintf(buf, buf_len, "%s", ath10k_core_fw_feature_str[feat]);
686 }
687
ath10k_core_get_fw_features_str(struct ath10k * ar,char * buf,size_t buf_len)688 void ath10k_core_get_fw_features_str(struct ath10k *ar,
689 char *buf,
690 size_t buf_len)
691 {
692 size_t len = 0;
693 int i;
694
695 for (i = 0; i < ATH10K_FW_FEATURE_COUNT; i++) {
696 if (test_bit(i, ar->normal_mode_fw.fw_file.fw_features)) {
697 if (len > 0)
698 len += scnprintf(buf + len, buf_len - len, ",");
699
700 len += ath10k_core_get_fw_feature_str(buf + len,
701 buf_len - len,
702 i);
703 }
704 }
705 }
706
ath10k_send_suspend_complete(struct ath10k * ar)707 static void ath10k_send_suspend_complete(struct ath10k *ar)
708 {
709 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot suspend complete\n");
710
711 complete(&ar->target_suspend);
712 }
713
ath10k_init_sdio(struct ath10k * ar,enum ath10k_firmware_mode mode)714 static int ath10k_init_sdio(struct ath10k *ar, enum ath10k_firmware_mode mode)
715 {
716 bool mtu_workaround = ar->hw_params.credit_size_workaround;
717 int ret;
718 u32 param = 0;
719
720 ret = ath10k_bmi_write32(ar, hi_mbox_io_block_sz, 256);
721 if (ret)
722 return ret;
723
724 ret = ath10k_bmi_write32(ar, hi_mbox_isr_yield_limit, 99);
725 if (ret)
726 return ret;
727
728 ret = ath10k_bmi_read32(ar, hi_acs_flags, ¶m);
729 if (ret)
730 return ret;
731
732 param |= HI_ACS_FLAGS_SDIO_REDUCE_TX_COMPL_SET;
733
734 if (mode == ATH10K_FIRMWARE_MODE_NORMAL && !mtu_workaround)
735 param |= HI_ACS_FLAGS_ALT_DATA_CREDIT_SIZE;
736 else
737 param &= ~HI_ACS_FLAGS_ALT_DATA_CREDIT_SIZE;
738
739 if (mode == ATH10K_FIRMWARE_MODE_UTF)
740 param &= ~HI_ACS_FLAGS_SDIO_SWAP_MAILBOX_SET;
741 else
742 param |= HI_ACS_FLAGS_SDIO_SWAP_MAILBOX_SET;
743
744 ret = ath10k_bmi_write32(ar, hi_acs_flags, param);
745 if (ret)
746 return ret;
747
748 ret = ath10k_bmi_read32(ar, hi_option_flag2, ¶m);
749 if (ret)
750 return ret;
751
752 param |= HI_OPTION_SDIO_CRASH_DUMP_ENHANCEMENT_HOST;
753
754 ret = ath10k_bmi_write32(ar, hi_option_flag2, param);
755 if (ret)
756 return ret;
757
758 return 0;
759 }
760
ath10k_init_configure_target(struct ath10k * ar)761 static int ath10k_init_configure_target(struct ath10k *ar)
762 {
763 u32 param_host;
764 int ret;
765
766 /* tell target which HTC version it is used*/
767 ret = ath10k_bmi_write32(ar, hi_app_host_interest,
768 HTC_PROTOCOL_VERSION);
769 if (ret) {
770 ath10k_err(ar, "settings HTC version failed\n");
771 return ret;
772 }
773
774 /* set the firmware mode to STA/IBSS/AP */
775 ret = ath10k_bmi_read32(ar, hi_option_flag, ¶m_host);
776 if (ret) {
777 ath10k_err(ar, "setting firmware mode (1/2) failed\n");
778 return ret;
779 }
780
781 /* TODO following parameters need to be re-visited. */
782 /* num_device */
783 param_host |= (1 << HI_OPTION_NUM_DEV_SHIFT);
784 /* Firmware mode */
785 /* FIXME: Why FW_MODE_AP ??.*/
786 param_host |= (HI_OPTION_FW_MODE_AP << HI_OPTION_FW_MODE_SHIFT);
787 /* mac_addr_method */
788 param_host |= (1 << HI_OPTION_MAC_ADDR_METHOD_SHIFT);
789 /* firmware_bridge */
790 param_host |= (0 << HI_OPTION_FW_BRIDGE_SHIFT);
791 /* fwsubmode */
792 param_host |= (0 << HI_OPTION_FW_SUBMODE_SHIFT);
793
794 ret = ath10k_bmi_write32(ar, hi_option_flag, param_host);
795 if (ret) {
796 ath10k_err(ar, "setting firmware mode (2/2) failed\n");
797 return ret;
798 }
799
800 /* We do all byte-swapping on the host */
801 ret = ath10k_bmi_write32(ar, hi_be, 0);
802 if (ret) {
803 ath10k_err(ar, "setting host CPU BE mode failed\n");
804 return ret;
805 }
806
807 /* FW descriptor/Data swap flags */
808 ret = ath10k_bmi_write32(ar, hi_fw_swap, 0);
809
810 if (ret) {
811 ath10k_err(ar, "setting FW data/desc swap flags failed\n");
812 return ret;
813 }
814
815 /* Some devices have a special sanity check that verifies the PCI
816 * Device ID is written to this host interest var. It is known to be
817 * required to boot QCA6164.
818 */
819 ret = ath10k_bmi_write32(ar, hi_hci_uart_pwr_mgmt_params_ext,
820 ar->dev_id);
821 if (ret) {
822 ath10k_err(ar, "failed to set pwr_mgmt_params: %d\n", ret);
823 return ret;
824 }
825
826 return 0;
827 }
828
ath10k_fetch_fw_file(struct ath10k * ar,const char * dir,const char * file)829 static const struct firmware *ath10k_fetch_fw_file(struct ath10k *ar,
830 const char *dir,
831 const char *file)
832 {
833 char filename[100];
834 const struct firmware *fw;
835 int ret;
836
837 if (file == NULL)
838 return ERR_PTR(-ENOENT);
839
840 if (dir == NULL)
841 dir = ".";
842
843 snprintf(filename, sizeof(filename), "%s/%s", dir, file);
844 ret = firmware_request_nowarn(&fw, filename, ar->dev);
845 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot fw request '%s': %d\n",
846 filename, ret);
847
848 if (ret)
849 return ERR_PTR(ret);
850
851 return fw;
852 }
853
ath10k_push_board_ext_data(struct ath10k * ar,const void * data,size_t data_len)854 static int ath10k_push_board_ext_data(struct ath10k *ar, const void *data,
855 size_t data_len)
856 {
857 u32 board_data_size = ar->hw_params.fw.board_size;
858 u32 board_ext_data_size = ar->hw_params.fw.board_ext_size;
859 u32 board_ext_data_addr;
860 int ret;
861
862 ret = ath10k_bmi_read32(ar, hi_board_ext_data, &board_ext_data_addr);
863 if (ret) {
864 ath10k_err(ar, "could not read board ext data addr (%d)\n",
865 ret);
866 return ret;
867 }
868
869 ath10k_dbg(ar, ATH10K_DBG_BOOT,
870 "boot push board extended data addr 0x%x\n",
871 board_ext_data_addr);
872
873 if (board_ext_data_addr == 0)
874 return 0;
875
876 if (data_len != (board_data_size + board_ext_data_size)) {
877 ath10k_err(ar, "invalid board (ext) data sizes %zu != %d+%d\n",
878 data_len, board_data_size, board_ext_data_size);
879 return -EINVAL;
880 }
881
882 ret = ath10k_bmi_write_memory(ar, board_ext_data_addr,
883 data + board_data_size,
884 board_ext_data_size);
885 if (ret) {
886 ath10k_err(ar, "could not write board ext data (%d)\n", ret);
887 return ret;
888 }
889
890 ret = ath10k_bmi_write32(ar, hi_board_ext_data_config,
891 (board_ext_data_size << 16) | 1);
892 if (ret) {
893 ath10k_err(ar, "could not write board ext data bit (%d)\n",
894 ret);
895 return ret;
896 }
897
898 return 0;
899 }
900
ath10k_core_get_board_id_from_otp(struct ath10k * ar)901 static int ath10k_core_get_board_id_from_otp(struct ath10k *ar)
902 {
903 u32 result, address;
904 u8 board_id, chip_id;
905 bool ext_bid_support;
906 int ret, bmi_board_id_param;
907
908 address = ar->hw_params.patch_load_addr;
909
910 if (!ar->normal_mode_fw.fw_file.otp_data ||
911 !ar->normal_mode_fw.fw_file.otp_len) {
912 ath10k_warn(ar,
913 "failed to retrieve board id because of invalid otp\n");
914 return -ENODATA;
915 }
916
917 if (ar->id.bmi_ids_valid) {
918 ath10k_dbg(ar, ATH10K_DBG_BOOT,
919 "boot already acquired valid otp board id,skip download, board_id %d chip_id %d\n",
920 ar->id.bmi_board_id, ar->id.bmi_chip_id);
921 goto skip_otp_download;
922 }
923
924 ath10k_dbg(ar, ATH10K_DBG_BOOT,
925 "boot upload otp to 0x%x len %zd for board id\n",
926 address, ar->normal_mode_fw.fw_file.otp_len);
927
928 ret = ath10k_bmi_fast_download(ar, address,
929 ar->normal_mode_fw.fw_file.otp_data,
930 ar->normal_mode_fw.fw_file.otp_len);
931 if (ret) {
932 ath10k_err(ar, "could not write otp for board id check: %d\n",
933 ret);
934 return ret;
935 }
936
937 if (ar->cal_mode == ATH10K_PRE_CAL_MODE_DT ||
938 ar->cal_mode == ATH10K_PRE_CAL_MODE_FILE)
939 bmi_board_id_param = BMI_PARAM_GET_FLASH_BOARD_ID;
940 else
941 bmi_board_id_param = BMI_PARAM_GET_EEPROM_BOARD_ID;
942
943 ret = ath10k_bmi_execute(ar, address, bmi_board_id_param, &result);
944 if (ret) {
945 ath10k_err(ar, "could not execute otp for board id check: %d\n",
946 ret);
947 return ret;
948 }
949
950 board_id = MS(result, ATH10K_BMI_BOARD_ID_FROM_OTP);
951 chip_id = MS(result, ATH10K_BMI_CHIP_ID_FROM_OTP);
952 ext_bid_support = (result & ATH10K_BMI_EXT_BOARD_ID_SUPPORT);
953
954 ath10k_dbg(ar, ATH10K_DBG_BOOT,
955 "boot get otp board id result 0x%08x board_id %d chip_id %d ext_bid_support %d\n",
956 result, board_id, chip_id, ext_bid_support);
957
958 ar->id.ext_bid_supported = ext_bid_support;
959
960 if ((result & ATH10K_BMI_BOARD_ID_STATUS_MASK) != 0 ||
961 (board_id == 0)) {
962 ath10k_dbg(ar, ATH10K_DBG_BOOT,
963 "board id does not exist in otp, ignore it\n");
964 return -EOPNOTSUPP;
965 }
966
967 ar->id.bmi_ids_valid = true;
968 ar->id.bmi_board_id = board_id;
969 ar->id.bmi_chip_id = chip_id;
970
971 skip_otp_download:
972
973 return 0;
974 }
975
ath10k_core_check_bdfext(const struct dmi_header * hdr,void * data)976 static void ath10k_core_check_bdfext(const struct dmi_header *hdr, void *data)
977 {
978 struct ath10k *ar = data;
979 const char *bdf_ext;
980 const char *magic = ATH10K_SMBIOS_BDF_EXT_MAGIC;
981 u8 bdf_enabled;
982 int i;
983
984 if (hdr->type != ATH10K_SMBIOS_BDF_EXT_TYPE)
985 return;
986
987 if (hdr->length != ATH10K_SMBIOS_BDF_EXT_LENGTH) {
988 ath10k_dbg(ar, ATH10K_DBG_BOOT,
989 "wrong smbios bdf ext type length (%d).\n",
990 hdr->length);
991 return;
992 }
993
994 bdf_enabled = *((u8 *)hdr + ATH10K_SMBIOS_BDF_EXT_OFFSET);
995 if (!bdf_enabled) {
996 ath10k_dbg(ar, ATH10K_DBG_BOOT, "bdf variant name not found.\n");
997 return;
998 }
999
1000 /* Only one string exists (per spec) */
1001 bdf_ext = (char *)hdr + hdr->length;
1002
1003 if (memcmp(bdf_ext, magic, strlen(magic)) != 0) {
1004 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1005 "bdf variant magic does not match.\n");
1006 return;
1007 }
1008
1009 for (i = 0; i < strlen(bdf_ext); i++) {
1010 if (!isascii(bdf_ext[i]) || !isprint(bdf_ext[i])) {
1011 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1012 "bdf variant name contains non ascii chars.\n");
1013 return;
1014 }
1015 }
1016
1017 /* Copy extension name without magic suffix */
1018 if (strscpy(ar->id.bdf_ext, bdf_ext + strlen(magic),
1019 sizeof(ar->id.bdf_ext)) < 0) {
1020 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1021 "bdf variant string is longer than the buffer can accommodate (variant: %s)\n",
1022 bdf_ext);
1023 return;
1024 }
1025
1026 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1027 "found and validated bdf variant smbios_type 0x%x bdf %s\n",
1028 ATH10K_SMBIOS_BDF_EXT_TYPE, bdf_ext);
1029 }
1030
ath10k_core_check_smbios(struct ath10k * ar)1031 static int ath10k_core_check_smbios(struct ath10k *ar)
1032 {
1033 ar->id.bdf_ext[0] = '\0';
1034 dmi_walk(ath10k_core_check_bdfext, ar);
1035
1036 if (ar->id.bdf_ext[0] == '\0')
1037 return -ENODATA;
1038
1039 return 0;
1040 }
1041
ath10k_core_check_dt(struct ath10k * ar)1042 int ath10k_core_check_dt(struct ath10k *ar)
1043 {
1044 struct device_node *node;
1045 const char *variant = NULL;
1046
1047 node = ar->dev->of_node;
1048 if (!node)
1049 return -ENOENT;
1050
1051 of_property_read_string(node, "qcom,ath10k-calibration-variant",
1052 &variant);
1053 if (!variant)
1054 return -ENODATA;
1055
1056 if (strscpy(ar->id.bdf_ext, variant, sizeof(ar->id.bdf_ext)) < 0)
1057 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1058 "bdf variant string is longer than the buffer can accommodate (variant: %s)\n",
1059 variant);
1060
1061 return 0;
1062 }
1063 EXPORT_SYMBOL(ath10k_core_check_dt);
1064
ath10k_download_fw(struct ath10k * ar)1065 static int ath10k_download_fw(struct ath10k *ar)
1066 {
1067 u32 address, data_len;
1068 const void *data;
1069 int ret;
1070 struct pm_qos_request latency_qos;
1071
1072 address = ar->hw_params.patch_load_addr;
1073
1074 data = ar->running_fw->fw_file.firmware_data;
1075 data_len = ar->running_fw->fw_file.firmware_len;
1076
1077 ret = ath10k_swap_code_seg_configure(ar, &ar->running_fw->fw_file);
1078 if (ret) {
1079 ath10k_err(ar, "failed to configure fw code swap: %d\n",
1080 ret);
1081 return ret;
1082 }
1083
1084 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1085 "boot uploading firmware image %pK len %d\n",
1086 data, data_len);
1087
1088 /* Check if device supports to download firmware via
1089 * diag copy engine. Downloading firmware via diag CE
1090 * greatly reduces the time to download firmware.
1091 */
1092 if (ar->hw_params.fw_diag_ce_download) {
1093 ret = ath10k_hw_diag_fast_download(ar, address,
1094 data, data_len);
1095 if (ret == 0)
1096 /* firmware upload via diag ce was successful */
1097 return 0;
1098
1099 ath10k_warn(ar,
1100 "failed to upload firmware via diag ce, trying BMI: %d",
1101 ret);
1102 }
1103
1104 memset(&latency_qos, 0, sizeof(latency_qos));
1105 cpu_latency_qos_add_request(&latency_qos, 0);
1106
1107 ret = ath10k_bmi_fast_download(ar, address, data, data_len);
1108
1109 cpu_latency_qos_remove_request(&latency_qos);
1110
1111 return ret;
1112 }
1113
ath10k_core_free_board_files(struct ath10k * ar)1114 void ath10k_core_free_board_files(struct ath10k *ar)
1115 {
1116 if (!IS_ERR(ar->normal_mode_fw.board))
1117 release_firmware(ar->normal_mode_fw.board);
1118
1119 if (!IS_ERR(ar->normal_mode_fw.ext_board))
1120 release_firmware(ar->normal_mode_fw.ext_board);
1121
1122 ar->normal_mode_fw.board = NULL;
1123 ar->normal_mode_fw.board_data = NULL;
1124 ar->normal_mode_fw.board_len = 0;
1125 ar->normal_mode_fw.ext_board = NULL;
1126 ar->normal_mode_fw.ext_board_data = NULL;
1127 ar->normal_mode_fw.ext_board_len = 0;
1128 }
1129 EXPORT_SYMBOL(ath10k_core_free_board_files);
1130
ath10k_core_free_firmware_files(struct ath10k * ar)1131 static void ath10k_core_free_firmware_files(struct ath10k *ar)
1132 {
1133 if (!IS_ERR(ar->normal_mode_fw.fw_file.firmware))
1134 release_firmware(ar->normal_mode_fw.fw_file.firmware);
1135
1136 if (!IS_ERR(ar->cal_file))
1137 release_firmware(ar->cal_file);
1138
1139 if (!IS_ERR(ar->pre_cal_file))
1140 release_firmware(ar->pre_cal_file);
1141
1142 ath10k_swap_code_seg_release(ar, &ar->normal_mode_fw.fw_file);
1143
1144 ar->normal_mode_fw.fw_file.otp_data = NULL;
1145 ar->normal_mode_fw.fw_file.otp_len = 0;
1146
1147 ar->normal_mode_fw.fw_file.firmware = NULL;
1148 ar->normal_mode_fw.fw_file.firmware_data = NULL;
1149 ar->normal_mode_fw.fw_file.firmware_len = 0;
1150
1151 ar->cal_file = NULL;
1152 ar->pre_cal_file = NULL;
1153 }
1154
ath10k_fetch_cal_file(struct ath10k * ar)1155 static int ath10k_fetch_cal_file(struct ath10k *ar)
1156 {
1157 char filename[100];
1158
1159 /* pre-cal-<bus>-<id>.bin */
1160 scnprintf(filename, sizeof(filename), "pre-cal-%s-%s.bin",
1161 ath10k_bus_str(ar->hif.bus), dev_name(ar->dev));
1162
1163 ar->pre_cal_file = ath10k_fetch_fw_file(ar, ATH10K_FW_DIR, filename);
1164 if (!IS_ERR(ar->pre_cal_file))
1165 goto success;
1166
1167 /* cal-<bus>-<id>.bin */
1168 scnprintf(filename, sizeof(filename), "cal-%s-%s.bin",
1169 ath10k_bus_str(ar->hif.bus), dev_name(ar->dev));
1170
1171 ar->cal_file = ath10k_fetch_fw_file(ar, ATH10K_FW_DIR, filename);
1172 if (IS_ERR(ar->cal_file))
1173 /* calibration file is optional, don't print any warnings */
1174 return PTR_ERR(ar->cal_file);
1175 success:
1176 ath10k_dbg(ar, ATH10K_DBG_BOOT, "found calibration file %s/%s\n",
1177 ATH10K_FW_DIR, filename);
1178
1179 return 0;
1180 }
1181
ath10k_core_fetch_board_data_api_1(struct ath10k * ar,int bd_ie_type)1182 static int ath10k_core_fetch_board_data_api_1(struct ath10k *ar, int bd_ie_type)
1183 {
1184 const struct firmware *fw;
1185
1186 if (bd_ie_type == ATH10K_BD_IE_BOARD) {
1187 if (!ar->hw_params.fw.board) {
1188 ath10k_err(ar, "failed to find board file fw entry\n");
1189 return -EINVAL;
1190 }
1191
1192 ar->normal_mode_fw.board = ath10k_fetch_fw_file(ar,
1193 ar->hw_params.fw.dir,
1194 ar->hw_params.fw.board);
1195 if (IS_ERR(ar->normal_mode_fw.board))
1196 return PTR_ERR(ar->normal_mode_fw.board);
1197
1198 ar->normal_mode_fw.board_data = ar->normal_mode_fw.board->data;
1199 ar->normal_mode_fw.board_len = ar->normal_mode_fw.board->size;
1200 } else if (bd_ie_type == ATH10K_BD_IE_BOARD_EXT) {
1201 if (!ar->hw_params.fw.eboard) {
1202 ath10k_err(ar, "failed to find eboard file fw entry\n");
1203 return -EINVAL;
1204 }
1205
1206 fw = ath10k_fetch_fw_file(ar, ar->hw_params.fw.dir,
1207 ar->hw_params.fw.eboard);
1208 ar->normal_mode_fw.ext_board = fw;
1209 if (IS_ERR(ar->normal_mode_fw.ext_board))
1210 return PTR_ERR(ar->normal_mode_fw.ext_board);
1211
1212 ar->normal_mode_fw.ext_board_data = ar->normal_mode_fw.ext_board->data;
1213 ar->normal_mode_fw.ext_board_len = ar->normal_mode_fw.ext_board->size;
1214 }
1215
1216 return 0;
1217 }
1218
ath10k_core_parse_bd_ie_board(struct ath10k * ar,const void * buf,size_t buf_len,const char * boardname,int bd_ie_type)1219 static int ath10k_core_parse_bd_ie_board(struct ath10k *ar,
1220 const void *buf, size_t buf_len,
1221 const char *boardname,
1222 int bd_ie_type)
1223 {
1224 const struct ath10k_fw_ie *hdr;
1225 bool name_match_found;
1226 int ret, board_ie_id;
1227 size_t board_ie_len;
1228 const void *board_ie_data;
1229
1230 name_match_found = false;
1231
1232 /* go through ATH10K_BD_IE_BOARD_ elements */
1233 while (buf_len > sizeof(struct ath10k_fw_ie)) {
1234 hdr = buf;
1235 board_ie_id = le32_to_cpu(hdr->id);
1236 board_ie_len = le32_to_cpu(hdr->len);
1237 board_ie_data = hdr->data;
1238
1239 buf_len -= sizeof(*hdr);
1240 buf += sizeof(*hdr);
1241
1242 if (buf_len < ALIGN(board_ie_len, 4)) {
1243 ath10k_err(ar, "invalid ATH10K_BD_IE_BOARD length: %zu < %zu\n",
1244 buf_len, ALIGN(board_ie_len, 4));
1245 ret = -EINVAL;
1246 goto out;
1247 }
1248
1249 switch (board_ie_id) {
1250 case ATH10K_BD_IE_BOARD_NAME:
1251 ath10k_dbg_dump(ar, ATH10K_DBG_BOOT, "board name", "",
1252 board_ie_data, board_ie_len);
1253
1254 if (board_ie_len != strlen(boardname))
1255 break;
1256
1257 ret = memcmp(board_ie_data, boardname, strlen(boardname));
1258 if (ret)
1259 break;
1260
1261 name_match_found = true;
1262 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1263 "boot found match for name '%s'",
1264 boardname);
1265 break;
1266 case ATH10K_BD_IE_BOARD_DATA:
1267 if (!name_match_found)
1268 /* no match found */
1269 break;
1270
1271 if (bd_ie_type == ATH10K_BD_IE_BOARD) {
1272 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1273 "boot found board data for '%s'",
1274 boardname);
1275
1276 ar->normal_mode_fw.board_data = board_ie_data;
1277 ar->normal_mode_fw.board_len = board_ie_len;
1278 } else if (bd_ie_type == ATH10K_BD_IE_BOARD_EXT) {
1279 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1280 "boot found eboard data for '%s'",
1281 boardname);
1282
1283 ar->normal_mode_fw.ext_board_data = board_ie_data;
1284 ar->normal_mode_fw.ext_board_len = board_ie_len;
1285 }
1286
1287 ret = 0;
1288 goto out;
1289 default:
1290 ath10k_warn(ar, "unknown ATH10K_BD_IE_BOARD found: %d\n",
1291 board_ie_id);
1292 break;
1293 }
1294
1295 /* jump over the padding */
1296 board_ie_len = ALIGN(board_ie_len, 4);
1297
1298 buf_len -= board_ie_len;
1299 buf += board_ie_len;
1300 }
1301
1302 /* no match found */
1303 ret = -ENOENT;
1304
1305 out:
1306 return ret;
1307 }
1308
ath10k_core_search_bd(struct ath10k * ar,const char * boardname,const u8 * data,size_t len)1309 static int ath10k_core_search_bd(struct ath10k *ar,
1310 const char *boardname,
1311 const u8 *data,
1312 size_t len)
1313 {
1314 size_t ie_len;
1315 struct ath10k_fw_ie *hdr;
1316 int ret = -ENOENT, ie_id;
1317
1318 while (len > sizeof(struct ath10k_fw_ie)) {
1319 hdr = (struct ath10k_fw_ie *)data;
1320 ie_id = le32_to_cpu(hdr->id);
1321 ie_len = le32_to_cpu(hdr->len);
1322
1323 len -= sizeof(*hdr);
1324 data = hdr->data;
1325
1326 if (len < ALIGN(ie_len, 4)) {
1327 ath10k_err(ar, "invalid length for board ie_id %d ie_len %zu len %zu\n",
1328 ie_id, ie_len, len);
1329 return -EINVAL;
1330 }
1331
1332 switch (ie_id) {
1333 case ATH10K_BD_IE_BOARD:
1334 ret = ath10k_core_parse_bd_ie_board(ar, data, ie_len,
1335 boardname,
1336 ATH10K_BD_IE_BOARD);
1337 if (ret == -ENOENT)
1338 /* no match found, continue */
1339 break;
1340
1341 /* either found or error, so stop searching */
1342 goto out;
1343 case ATH10K_BD_IE_BOARD_EXT:
1344 ret = ath10k_core_parse_bd_ie_board(ar, data, ie_len,
1345 boardname,
1346 ATH10K_BD_IE_BOARD_EXT);
1347 if (ret == -ENOENT)
1348 /* no match found, continue */
1349 break;
1350
1351 /* either found or error, so stop searching */
1352 goto out;
1353 }
1354
1355 /* jump over the padding */
1356 ie_len = ALIGN(ie_len, 4);
1357
1358 len -= ie_len;
1359 data += ie_len;
1360 }
1361
1362 out:
1363 /* return result of parse_bd_ie_board() or -ENOENT */
1364 return ret;
1365 }
1366
ath10k_core_fetch_board_data_api_n(struct ath10k * ar,const char * boardname,const char * fallback_boardname,const char * filename)1367 static int ath10k_core_fetch_board_data_api_n(struct ath10k *ar,
1368 const char *boardname,
1369 const char *fallback_boardname,
1370 const char *filename)
1371 {
1372 size_t len, magic_len;
1373 const u8 *data;
1374 int ret;
1375
1376 /* Skip if already fetched during board data download */
1377 if (!ar->normal_mode_fw.board)
1378 ar->normal_mode_fw.board = ath10k_fetch_fw_file(ar,
1379 ar->hw_params.fw.dir,
1380 filename);
1381 if (IS_ERR(ar->normal_mode_fw.board))
1382 return PTR_ERR(ar->normal_mode_fw.board);
1383
1384 data = ar->normal_mode_fw.board->data;
1385 len = ar->normal_mode_fw.board->size;
1386
1387 /* magic has extra null byte padded */
1388 magic_len = strlen(ATH10K_BOARD_MAGIC) + 1;
1389 if (len < magic_len) {
1390 ath10k_err(ar, "failed to find magic value in %s/%s, file too short: %zu\n",
1391 ar->hw_params.fw.dir, filename, len);
1392 ret = -EINVAL;
1393 goto err;
1394 }
1395
1396 if (memcmp(data, ATH10K_BOARD_MAGIC, magic_len)) {
1397 ath10k_err(ar, "found invalid board magic\n");
1398 ret = -EINVAL;
1399 goto err;
1400 }
1401
1402 /* magic is padded to 4 bytes */
1403 magic_len = ALIGN(magic_len, 4);
1404 if (len < magic_len) {
1405 ath10k_err(ar, "failed: %s/%s too small to contain board data, len: %zu\n",
1406 ar->hw_params.fw.dir, filename, len);
1407 ret = -EINVAL;
1408 goto err;
1409 }
1410
1411 data += magic_len;
1412 len -= magic_len;
1413
1414 /* attempt to find boardname in the IE list */
1415 ret = ath10k_core_search_bd(ar, boardname, data, len);
1416
1417 /* if we didn't find it and have a fallback name, try that */
1418 if (ret == -ENOENT && fallback_boardname)
1419 ret = ath10k_core_search_bd(ar, fallback_boardname, data, len);
1420
1421 if (ret == -ENOENT) {
1422 ath10k_err(ar,
1423 "failed to fetch board data for %s from %s/%s\n",
1424 boardname, ar->hw_params.fw.dir, filename);
1425 ret = -ENODATA;
1426 }
1427
1428 if (ret)
1429 goto err;
1430
1431 return 0;
1432
1433 err:
1434 ath10k_core_free_board_files(ar);
1435 return ret;
1436 }
1437
ath10k_core_create_board_name(struct ath10k * ar,char * name,size_t name_len,bool with_variant)1438 static int ath10k_core_create_board_name(struct ath10k *ar, char *name,
1439 size_t name_len, bool with_variant)
1440 {
1441 /* strlen(',variant=') + strlen(ar->id.bdf_ext) */
1442 char variant[9 + ATH10K_SMBIOS_BDF_EXT_STR_LENGTH] = { 0 };
1443
1444 if (with_variant && ar->id.bdf_ext[0] != '\0')
1445 scnprintf(variant, sizeof(variant), ",variant=%s",
1446 ar->id.bdf_ext);
1447
1448 if (ar->id.bmi_ids_valid) {
1449 scnprintf(name, name_len,
1450 "bus=%s,bmi-chip-id=%d,bmi-board-id=%d%s",
1451 ath10k_bus_str(ar->hif.bus),
1452 ar->id.bmi_chip_id,
1453 ar->id.bmi_board_id, variant);
1454 goto out;
1455 }
1456
1457 if (ar->id.qmi_ids_valid) {
1458 if (with_variant && ar->id.bdf_ext[0] != '\0')
1459 scnprintf(name, name_len,
1460 "bus=%s,qmi-board-id=%x,qmi-chip-id=%x%s",
1461 ath10k_bus_str(ar->hif.bus),
1462 ar->id.qmi_board_id, ar->id.qmi_chip_id,
1463 variant);
1464 else
1465 scnprintf(name, name_len,
1466 "bus=%s,qmi-board-id=%x",
1467 ath10k_bus_str(ar->hif.bus),
1468 ar->id.qmi_board_id);
1469 goto out;
1470 }
1471
1472 scnprintf(name, name_len,
1473 "bus=%s,vendor=%04x,device=%04x,subsystem-vendor=%04x,subsystem-device=%04x%s",
1474 ath10k_bus_str(ar->hif.bus),
1475 ar->id.vendor, ar->id.device,
1476 ar->id.subsystem_vendor, ar->id.subsystem_device, variant);
1477 out:
1478 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot using board name '%s'\n", name);
1479
1480 return 0;
1481 }
1482
ath10k_core_create_eboard_name(struct ath10k * ar,char * name,size_t name_len)1483 static int ath10k_core_create_eboard_name(struct ath10k *ar, char *name,
1484 size_t name_len)
1485 {
1486 if (ar->id.bmi_ids_valid) {
1487 scnprintf(name, name_len,
1488 "bus=%s,bmi-chip-id=%d,bmi-eboard-id=%d",
1489 ath10k_bus_str(ar->hif.bus),
1490 ar->id.bmi_chip_id,
1491 ar->id.bmi_eboard_id);
1492
1493 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot using eboard name '%s'\n", name);
1494 return 0;
1495 }
1496 /* Fallback if returned board id is zero */
1497 return -1;
1498 }
1499
ath10k_core_fetch_board_file(struct ath10k * ar,int bd_ie_type)1500 int ath10k_core_fetch_board_file(struct ath10k *ar, int bd_ie_type)
1501 {
1502 char boardname[100], fallback_boardname[100];
1503 int ret;
1504
1505 if (bd_ie_type == ATH10K_BD_IE_BOARD) {
1506 ret = ath10k_core_create_board_name(ar, boardname,
1507 sizeof(boardname), true);
1508 if (ret) {
1509 ath10k_err(ar, "failed to create board name: %d", ret);
1510 return ret;
1511 }
1512
1513 ret = ath10k_core_create_board_name(ar, fallback_boardname,
1514 sizeof(boardname), false);
1515 if (ret) {
1516 ath10k_err(ar, "failed to create fallback board name: %d", ret);
1517 return ret;
1518 }
1519 } else if (bd_ie_type == ATH10K_BD_IE_BOARD_EXT) {
1520 ret = ath10k_core_create_eboard_name(ar, boardname,
1521 sizeof(boardname));
1522 if (ret) {
1523 ath10k_err(ar, "fallback to eboard.bin since board id 0");
1524 goto fallback;
1525 }
1526 }
1527
1528 ar->bd_api = 2;
1529 ret = ath10k_core_fetch_board_data_api_n(ar, boardname,
1530 fallback_boardname,
1531 ATH10K_BOARD_API2_FILE);
1532 if (!ret)
1533 goto success;
1534
1535 fallback:
1536 ar->bd_api = 1;
1537 ret = ath10k_core_fetch_board_data_api_1(ar, bd_ie_type);
1538 if (ret) {
1539 ath10k_err(ar, "failed to fetch board-2.bin or board.bin from %s\n",
1540 ar->hw_params.fw.dir);
1541 return ret;
1542 }
1543
1544 success:
1545 ath10k_dbg(ar, ATH10K_DBG_BOOT, "using board api %d\n", ar->bd_api);
1546 return 0;
1547 }
1548 EXPORT_SYMBOL(ath10k_core_fetch_board_file);
1549
ath10k_core_get_ext_board_id_from_otp(struct ath10k * ar)1550 static int ath10k_core_get_ext_board_id_from_otp(struct ath10k *ar)
1551 {
1552 u32 result, address;
1553 u8 ext_board_id;
1554 int ret;
1555
1556 address = ar->hw_params.patch_load_addr;
1557
1558 if (!ar->normal_mode_fw.fw_file.otp_data ||
1559 !ar->normal_mode_fw.fw_file.otp_len) {
1560 ath10k_warn(ar,
1561 "failed to retrieve extended board id due to otp binary missing\n");
1562 return -ENODATA;
1563 }
1564
1565 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1566 "boot upload otp to 0x%x len %zd for ext board id\n",
1567 address, ar->normal_mode_fw.fw_file.otp_len);
1568
1569 ret = ath10k_bmi_fast_download(ar, address,
1570 ar->normal_mode_fw.fw_file.otp_data,
1571 ar->normal_mode_fw.fw_file.otp_len);
1572 if (ret) {
1573 ath10k_err(ar, "could not write otp for ext board id check: %d\n",
1574 ret);
1575 return ret;
1576 }
1577
1578 ret = ath10k_bmi_execute(ar, address, BMI_PARAM_GET_EXT_BOARD_ID, &result);
1579 if (ret) {
1580 ath10k_err(ar, "could not execute otp for ext board id check: %d\n",
1581 ret);
1582 return ret;
1583 }
1584
1585 if (!result) {
1586 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1587 "ext board id does not exist in otp, ignore it\n");
1588 return -EOPNOTSUPP;
1589 }
1590
1591 ext_board_id = result & ATH10K_BMI_EBOARD_ID_STATUS_MASK;
1592
1593 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1594 "boot get otp ext board id result 0x%08x ext_board_id %d\n",
1595 result, ext_board_id);
1596
1597 ar->id.bmi_eboard_id = ext_board_id;
1598
1599 return 0;
1600 }
1601
ath10k_download_board_data(struct ath10k * ar,const void * data,size_t data_len)1602 static int ath10k_download_board_data(struct ath10k *ar, const void *data,
1603 size_t data_len)
1604 {
1605 u32 board_data_size = ar->hw_params.fw.board_size;
1606 u32 eboard_data_size = ar->hw_params.fw.ext_board_size;
1607 u32 board_address;
1608 u32 ext_board_address;
1609 int ret;
1610
1611 ret = ath10k_push_board_ext_data(ar, data, data_len);
1612 if (ret) {
1613 ath10k_err(ar, "could not push board ext data (%d)\n", ret);
1614 goto exit;
1615 }
1616
1617 ret = ath10k_bmi_read32(ar, hi_board_data, &board_address);
1618 if (ret) {
1619 ath10k_err(ar, "could not read board data addr (%d)\n", ret);
1620 goto exit;
1621 }
1622
1623 ret = ath10k_bmi_write_memory(ar, board_address, data,
1624 min_t(u32, board_data_size,
1625 data_len));
1626 if (ret) {
1627 ath10k_err(ar, "could not write board data (%d)\n", ret);
1628 goto exit;
1629 }
1630
1631 ret = ath10k_bmi_write32(ar, hi_board_data_initialized, 1);
1632 if (ret) {
1633 ath10k_err(ar, "could not write board data bit (%d)\n", ret);
1634 goto exit;
1635 }
1636
1637 if (!ar->id.ext_bid_supported)
1638 goto exit;
1639
1640 /* Extended board data download */
1641 ret = ath10k_core_get_ext_board_id_from_otp(ar);
1642 if (ret == -EOPNOTSUPP) {
1643 /* Not fetching ext_board_data if ext board id is 0 */
1644 ath10k_dbg(ar, ATH10K_DBG_BOOT, "otp returned ext board id 0\n");
1645 return 0;
1646 } else if (ret) {
1647 ath10k_err(ar, "failed to get extended board id: %d\n", ret);
1648 goto exit;
1649 }
1650
1651 ret = ath10k_core_fetch_board_file(ar, ATH10K_BD_IE_BOARD_EXT);
1652 if (ret)
1653 goto exit;
1654
1655 if (ar->normal_mode_fw.ext_board_data) {
1656 ext_board_address = board_address + EXT_BOARD_ADDRESS_OFFSET;
1657 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1658 "boot writing ext board data to addr 0x%x",
1659 ext_board_address);
1660 ret = ath10k_bmi_write_memory(ar, ext_board_address,
1661 ar->normal_mode_fw.ext_board_data,
1662 min_t(u32, eboard_data_size, data_len));
1663 if (ret)
1664 ath10k_err(ar, "failed to write ext board data: %d\n", ret);
1665 }
1666
1667 exit:
1668 return ret;
1669 }
1670
ath10k_download_and_run_otp(struct ath10k * ar)1671 static int ath10k_download_and_run_otp(struct ath10k *ar)
1672 {
1673 u32 result, address = ar->hw_params.patch_load_addr;
1674 u32 bmi_otp_exe_param = ar->hw_params.otp_exe_param;
1675 int ret;
1676
1677 ret = ath10k_download_board_data(ar,
1678 ar->running_fw->board_data,
1679 ar->running_fw->board_len);
1680 if (ret) {
1681 ath10k_err(ar, "failed to download board data: %d\n", ret);
1682 return ret;
1683 }
1684
1685 /* OTP is optional */
1686
1687 if (!ar->running_fw->fw_file.otp_data ||
1688 !ar->running_fw->fw_file.otp_len) {
1689 ath10k_warn(ar, "Not running otp, calibration will be incorrect (otp-data %pK otp_len %zd)!\n",
1690 ar->running_fw->fw_file.otp_data,
1691 ar->running_fw->fw_file.otp_len);
1692 return 0;
1693 }
1694
1695 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot upload otp to 0x%x len %zd\n",
1696 address, ar->running_fw->fw_file.otp_len);
1697
1698 ret = ath10k_bmi_fast_download(ar, address,
1699 ar->running_fw->fw_file.otp_data,
1700 ar->running_fw->fw_file.otp_len);
1701 if (ret) {
1702 ath10k_err(ar, "could not write otp (%d)\n", ret);
1703 return ret;
1704 }
1705
1706 /* As of now pre-cal is valid for 10_4 variants */
1707 if (ar->cal_mode == ATH10K_PRE_CAL_MODE_DT ||
1708 ar->cal_mode == ATH10K_PRE_CAL_MODE_FILE)
1709 bmi_otp_exe_param = BMI_PARAM_FLASH_SECTION_ALL;
1710
1711 ret = ath10k_bmi_execute(ar, address, bmi_otp_exe_param, &result);
1712 if (ret) {
1713 ath10k_err(ar, "could not execute otp (%d)\n", ret);
1714 return ret;
1715 }
1716
1717 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot otp execute result %d\n", result);
1718
1719 if (!(skip_otp || test_bit(ATH10K_FW_FEATURE_IGNORE_OTP_RESULT,
1720 ar->running_fw->fw_file.fw_features)) &&
1721 result != 0) {
1722 ath10k_err(ar, "otp calibration failed: %d", result);
1723 return -EINVAL;
1724 }
1725
1726 return 0;
1727 }
1728
ath10k_download_cal_file(struct ath10k * ar,const struct firmware * file)1729 static int ath10k_download_cal_file(struct ath10k *ar,
1730 const struct firmware *file)
1731 {
1732 int ret;
1733
1734 if (!file)
1735 return -ENOENT;
1736
1737 if (IS_ERR(file))
1738 return PTR_ERR(file);
1739
1740 ret = ath10k_download_board_data(ar, file->data, file->size);
1741 if (ret) {
1742 ath10k_err(ar, "failed to download cal_file data: %d\n", ret);
1743 return ret;
1744 }
1745
1746 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot cal file downloaded\n");
1747
1748 return 0;
1749 }
1750
ath10k_download_cal_dt(struct ath10k * ar,const char * dt_name)1751 static int ath10k_download_cal_dt(struct ath10k *ar, const char *dt_name)
1752 {
1753 struct device_node *node;
1754 int data_len;
1755 void *data;
1756 int ret;
1757
1758 node = ar->dev->of_node;
1759 if (!node)
1760 /* Device Tree is optional, don't print any warnings if
1761 * there's no node for ath10k.
1762 */
1763 return -ENOENT;
1764
1765 if (!of_get_property(node, dt_name, &data_len)) {
1766 /* The calibration data node is optional */
1767 return -ENOENT;
1768 }
1769
1770 if (data_len != ar->hw_params.cal_data_len) {
1771 ath10k_warn(ar, "invalid calibration data length in DT: %d\n",
1772 data_len);
1773 ret = -EMSGSIZE;
1774 goto out;
1775 }
1776
1777 data = kmalloc(data_len, GFP_KERNEL);
1778 if (!data) {
1779 ret = -ENOMEM;
1780 goto out;
1781 }
1782
1783 ret = of_property_read_u8_array(node, dt_name, data, data_len);
1784 if (ret) {
1785 ath10k_warn(ar, "failed to read calibration data from DT: %d\n",
1786 ret);
1787 goto out_free;
1788 }
1789
1790 ret = ath10k_download_board_data(ar, data, data_len);
1791 if (ret) {
1792 ath10k_warn(ar, "failed to download calibration data from Device Tree: %d\n",
1793 ret);
1794 goto out_free;
1795 }
1796
1797 ret = 0;
1798
1799 out_free:
1800 kfree(data);
1801
1802 out:
1803 return ret;
1804 }
1805
ath10k_download_cal_eeprom(struct ath10k * ar)1806 static int ath10k_download_cal_eeprom(struct ath10k *ar)
1807 {
1808 size_t data_len;
1809 void *data = NULL;
1810 int ret;
1811
1812 ret = ath10k_hif_fetch_cal_eeprom(ar, &data, &data_len);
1813 if (ret) {
1814 if (ret != -EOPNOTSUPP)
1815 ath10k_warn(ar, "failed to read calibration data from EEPROM: %d\n",
1816 ret);
1817 goto out_free;
1818 }
1819
1820 ret = ath10k_download_board_data(ar, data, data_len);
1821 if (ret) {
1822 ath10k_warn(ar, "failed to download calibration data from EEPROM: %d\n",
1823 ret);
1824 goto out_free;
1825 }
1826
1827 ret = 0;
1828
1829 out_free:
1830 kfree(data);
1831
1832 return ret;
1833 }
1834
ath10k_core_fetch_firmware_api_n(struct ath10k * ar,const char * name,struct ath10k_fw_file * fw_file)1835 int ath10k_core_fetch_firmware_api_n(struct ath10k *ar, const char *name,
1836 struct ath10k_fw_file *fw_file)
1837 {
1838 size_t magic_len, len, ie_len;
1839 int ie_id, i, index, bit, ret;
1840 struct ath10k_fw_ie *hdr;
1841 const u8 *data;
1842 __le32 *timestamp, *version;
1843
1844 /* first fetch the firmware file (firmware-*.bin) */
1845 fw_file->firmware = ath10k_fetch_fw_file(ar, ar->hw_params.fw.dir,
1846 name);
1847 if (IS_ERR(fw_file->firmware))
1848 return PTR_ERR(fw_file->firmware);
1849
1850 data = fw_file->firmware->data;
1851 len = fw_file->firmware->size;
1852
1853 /* magic also includes the null byte, check that as well */
1854 magic_len = strlen(ATH10K_FIRMWARE_MAGIC) + 1;
1855
1856 if (len < magic_len) {
1857 ath10k_err(ar, "firmware file '%s/%s' too small to contain magic: %zu\n",
1858 ar->hw_params.fw.dir, name, len);
1859 ret = -EINVAL;
1860 goto err;
1861 }
1862
1863 if (memcmp(data, ATH10K_FIRMWARE_MAGIC, magic_len) != 0) {
1864 ath10k_err(ar, "invalid firmware magic\n");
1865 ret = -EINVAL;
1866 goto err;
1867 }
1868
1869 /* jump over the padding */
1870 magic_len = ALIGN(magic_len, 4);
1871
1872 len -= magic_len;
1873 data += magic_len;
1874
1875 /* loop elements */
1876 while (len > sizeof(struct ath10k_fw_ie)) {
1877 hdr = (struct ath10k_fw_ie *)data;
1878
1879 ie_id = le32_to_cpu(hdr->id);
1880 ie_len = le32_to_cpu(hdr->len);
1881
1882 len -= sizeof(*hdr);
1883 data += sizeof(*hdr);
1884
1885 if (len < ie_len) {
1886 ath10k_err(ar, "invalid length for FW IE %d (%zu < %zu)\n",
1887 ie_id, len, ie_len);
1888 ret = -EINVAL;
1889 goto err;
1890 }
1891
1892 switch (ie_id) {
1893 case ATH10K_FW_IE_FW_VERSION:
1894 if (ie_len > sizeof(fw_file->fw_version) - 1)
1895 break;
1896
1897 memcpy(fw_file->fw_version, data, ie_len);
1898 fw_file->fw_version[ie_len] = '\0';
1899
1900 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1901 "found fw version %s\n",
1902 fw_file->fw_version);
1903 break;
1904 case ATH10K_FW_IE_TIMESTAMP:
1905 if (ie_len != sizeof(u32))
1906 break;
1907
1908 timestamp = (__le32 *)data;
1909
1910 ath10k_dbg(ar, ATH10K_DBG_BOOT, "found fw timestamp %d\n",
1911 le32_to_cpup(timestamp));
1912 break;
1913 case ATH10K_FW_IE_FEATURES:
1914 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1915 "found firmware features ie (%zd B)\n",
1916 ie_len);
1917
1918 for (i = 0; i < ATH10K_FW_FEATURE_COUNT; i++) {
1919 index = i / 8;
1920 bit = i % 8;
1921
1922 if (index == ie_len)
1923 break;
1924
1925 if (data[index] & (1 << bit)) {
1926 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1927 "Enabling feature bit: %i\n",
1928 i);
1929 __set_bit(i, fw_file->fw_features);
1930 }
1931 }
1932
1933 ath10k_dbg_dump(ar, ATH10K_DBG_BOOT, "features", "",
1934 fw_file->fw_features,
1935 sizeof(fw_file->fw_features));
1936 break;
1937 case ATH10K_FW_IE_FW_IMAGE:
1938 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1939 "found fw image ie (%zd B)\n",
1940 ie_len);
1941
1942 fw_file->firmware_data = data;
1943 fw_file->firmware_len = ie_len;
1944
1945 break;
1946 case ATH10K_FW_IE_OTP_IMAGE:
1947 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1948 "found otp image ie (%zd B)\n",
1949 ie_len);
1950
1951 fw_file->otp_data = data;
1952 fw_file->otp_len = ie_len;
1953
1954 break;
1955 case ATH10K_FW_IE_WMI_OP_VERSION:
1956 if (ie_len != sizeof(u32))
1957 break;
1958
1959 version = (__le32 *)data;
1960
1961 fw_file->wmi_op_version = le32_to_cpup(version);
1962
1963 ath10k_dbg(ar, ATH10K_DBG_BOOT, "found fw ie wmi op version %d\n",
1964 fw_file->wmi_op_version);
1965 break;
1966 case ATH10K_FW_IE_HTT_OP_VERSION:
1967 if (ie_len != sizeof(u32))
1968 break;
1969
1970 version = (__le32 *)data;
1971
1972 fw_file->htt_op_version = le32_to_cpup(version);
1973
1974 ath10k_dbg(ar, ATH10K_DBG_BOOT, "found fw ie htt op version %d\n",
1975 fw_file->htt_op_version);
1976 break;
1977 case ATH10K_FW_IE_FW_CODE_SWAP_IMAGE:
1978 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1979 "found fw code swap image ie (%zd B)\n",
1980 ie_len);
1981 fw_file->codeswap_data = data;
1982 fw_file->codeswap_len = ie_len;
1983 break;
1984 default:
1985 ath10k_warn(ar, "Unknown FW IE: %u\n",
1986 le32_to_cpu(hdr->id));
1987 break;
1988 }
1989
1990 /* jump over the padding */
1991 ie_len = ALIGN(ie_len, 4);
1992
1993 len -= ie_len;
1994 data += ie_len;
1995 }
1996
1997 if (!test_bit(ATH10K_FW_FEATURE_NON_BMI, fw_file->fw_features) &&
1998 (!fw_file->firmware_data || !fw_file->firmware_len)) {
1999 ath10k_warn(ar, "No ATH10K_FW_IE_FW_IMAGE found from '%s/%s', skipping\n",
2000 ar->hw_params.fw.dir, name);
2001 ret = -ENOMEDIUM;
2002 goto err;
2003 }
2004
2005 return 0;
2006
2007 err:
2008 ath10k_core_free_firmware_files(ar);
2009 return ret;
2010 }
2011
ath10k_core_get_fw_name(struct ath10k * ar,char * fw_name,size_t fw_name_len,int fw_api)2012 static void ath10k_core_get_fw_name(struct ath10k *ar, char *fw_name,
2013 size_t fw_name_len, int fw_api)
2014 {
2015 switch (ar->hif.bus) {
2016 case ATH10K_BUS_SDIO:
2017 case ATH10K_BUS_USB:
2018 scnprintf(fw_name, fw_name_len, "%s-%s-%d.bin",
2019 ATH10K_FW_FILE_BASE, ath10k_bus_str(ar->hif.bus),
2020 fw_api);
2021 break;
2022 case ATH10K_BUS_PCI:
2023 case ATH10K_BUS_AHB:
2024 case ATH10K_BUS_SNOC:
2025 scnprintf(fw_name, fw_name_len, "%s-%d.bin",
2026 ATH10K_FW_FILE_BASE, fw_api);
2027 break;
2028 }
2029 }
2030
ath10k_core_fetch_firmware_files(struct ath10k * ar)2031 static int ath10k_core_fetch_firmware_files(struct ath10k *ar)
2032 {
2033 int ret, i;
2034 char fw_name[100];
2035
2036 /* calibration file is optional, don't check for any errors */
2037 ath10k_fetch_cal_file(ar);
2038
2039 for (i = ATH10K_FW_API_MAX; i >= ATH10K_FW_API_MIN; i--) {
2040 ar->fw_api = i;
2041 ath10k_dbg(ar, ATH10K_DBG_BOOT, "trying fw api %d\n",
2042 ar->fw_api);
2043
2044 ath10k_core_get_fw_name(ar, fw_name, sizeof(fw_name), ar->fw_api);
2045 ret = ath10k_core_fetch_firmware_api_n(ar, fw_name,
2046 &ar->normal_mode_fw.fw_file);
2047 if (!ret)
2048 goto success;
2049 }
2050
2051 /* we end up here if we couldn't fetch any firmware */
2052
2053 ath10k_err(ar, "Failed to find firmware-N.bin (N between %d and %d) from %s: %d",
2054 ATH10K_FW_API_MIN, ATH10K_FW_API_MAX, ar->hw_params.fw.dir,
2055 ret);
2056
2057 return ret;
2058
2059 success:
2060 ath10k_dbg(ar, ATH10K_DBG_BOOT, "using fw api %d\n", ar->fw_api);
2061
2062 return 0;
2063 }
2064
ath10k_core_pre_cal_download(struct ath10k * ar)2065 static int ath10k_core_pre_cal_download(struct ath10k *ar)
2066 {
2067 int ret;
2068
2069 ret = ath10k_download_cal_file(ar, ar->pre_cal_file);
2070 if (ret == 0) {
2071 ar->cal_mode = ATH10K_PRE_CAL_MODE_FILE;
2072 goto success;
2073 }
2074
2075 ath10k_dbg(ar, ATH10K_DBG_BOOT,
2076 "boot did not find a pre calibration file, try DT next: %d\n",
2077 ret);
2078
2079 ret = ath10k_download_cal_dt(ar, "qcom,ath10k-pre-calibration-data");
2080 if (ret) {
2081 ath10k_dbg(ar, ATH10K_DBG_BOOT,
2082 "unable to load pre cal data from DT: %d\n", ret);
2083 return ret;
2084 }
2085 ar->cal_mode = ATH10K_PRE_CAL_MODE_DT;
2086
2087 success:
2088 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot using calibration mode %s\n",
2089 ath10k_cal_mode_str(ar->cal_mode));
2090
2091 return 0;
2092 }
2093
ath10k_core_pre_cal_config(struct ath10k * ar)2094 static int ath10k_core_pre_cal_config(struct ath10k *ar)
2095 {
2096 int ret;
2097
2098 ret = ath10k_core_pre_cal_download(ar);
2099 if (ret) {
2100 ath10k_dbg(ar, ATH10K_DBG_BOOT,
2101 "failed to load pre cal data: %d\n", ret);
2102 return ret;
2103 }
2104
2105 ret = ath10k_core_get_board_id_from_otp(ar);
2106 if (ret) {
2107 ath10k_err(ar, "failed to get board id: %d\n", ret);
2108 return ret;
2109 }
2110
2111 ret = ath10k_download_and_run_otp(ar);
2112 if (ret) {
2113 ath10k_err(ar, "failed to run otp: %d\n", ret);
2114 return ret;
2115 }
2116
2117 ath10k_dbg(ar, ATH10K_DBG_BOOT,
2118 "pre cal configuration done successfully\n");
2119
2120 return 0;
2121 }
2122
ath10k_download_cal_data(struct ath10k * ar)2123 static int ath10k_download_cal_data(struct ath10k *ar)
2124 {
2125 int ret;
2126
2127 ret = ath10k_core_pre_cal_config(ar);
2128 if (ret == 0)
2129 return 0;
2130
2131 ath10k_dbg(ar, ATH10K_DBG_BOOT,
2132 "pre cal download procedure failed, try cal file: %d\n",
2133 ret);
2134
2135 ret = ath10k_download_cal_file(ar, ar->cal_file);
2136 if (ret == 0) {
2137 ar->cal_mode = ATH10K_CAL_MODE_FILE;
2138 goto done;
2139 }
2140
2141 ath10k_dbg(ar, ATH10K_DBG_BOOT,
2142 "boot did not find a calibration file, try DT next: %d\n",
2143 ret);
2144
2145 ret = ath10k_download_cal_dt(ar, "qcom,ath10k-calibration-data");
2146 if (ret == 0) {
2147 ar->cal_mode = ATH10K_CAL_MODE_DT;
2148 goto done;
2149 }
2150
2151 ath10k_dbg(ar, ATH10K_DBG_BOOT,
2152 "boot did not find DT entry, try target EEPROM next: %d\n",
2153 ret);
2154
2155 ret = ath10k_download_cal_eeprom(ar);
2156 if (ret == 0) {
2157 ar->cal_mode = ATH10K_CAL_MODE_EEPROM;
2158 goto done;
2159 }
2160
2161 ath10k_dbg(ar, ATH10K_DBG_BOOT,
2162 "boot did not find target EEPROM entry, try OTP next: %d\n",
2163 ret);
2164
2165 ret = ath10k_download_and_run_otp(ar);
2166 if (ret) {
2167 ath10k_err(ar, "failed to run otp: %d\n", ret);
2168 return ret;
2169 }
2170
2171 ar->cal_mode = ATH10K_CAL_MODE_OTP;
2172
2173 done:
2174 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot using calibration mode %s\n",
2175 ath10k_cal_mode_str(ar->cal_mode));
2176 return 0;
2177 }
2178
ath10k_core_fetch_btcoex_dt(struct ath10k * ar)2179 static void ath10k_core_fetch_btcoex_dt(struct ath10k *ar)
2180 {
2181 struct device_node *node;
2182 u8 coex_support = 0;
2183 int ret;
2184
2185 node = ar->dev->of_node;
2186 if (!node)
2187 goto out;
2188
2189 ret = of_property_read_u8(node, "qcom,coexist-support", &coex_support);
2190 if (ret) {
2191 ar->coex_support = true;
2192 goto out;
2193 }
2194
2195 if (coex_support) {
2196 ar->coex_support = true;
2197 } else {
2198 ar->coex_support = false;
2199 ar->coex_gpio_pin = -1;
2200 goto out;
2201 }
2202
2203 ret = of_property_read_u32(node, "qcom,coexist-gpio-pin",
2204 &ar->coex_gpio_pin);
2205 if (ret)
2206 ar->coex_gpio_pin = -1;
2207
2208 out:
2209 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot coex_support %d coex_gpio_pin %d\n",
2210 ar->coex_support, ar->coex_gpio_pin);
2211 }
2212
ath10k_init_uart(struct ath10k * ar)2213 static int ath10k_init_uart(struct ath10k *ar)
2214 {
2215 int ret;
2216
2217 /*
2218 * Explicitly setting UART prints to zero as target turns it on
2219 * based on scratch registers.
2220 */
2221 ret = ath10k_bmi_write32(ar, hi_serial_enable, 0);
2222 if (ret) {
2223 ath10k_warn(ar, "could not disable UART prints (%d)\n", ret);
2224 return ret;
2225 }
2226
2227 if (!uart_print) {
2228 if (ar->hw_params.uart_pin_workaround) {
2229 ret = ath10k_bmi_write32(ar, hi_dbg_uart_txpin,
2230 ar->hw_params.uart_pin);
2231 if (ret) {
2232 ath10k_warn(ar, "failed to set UART TX pin: %d",
2233 ret);
2234 return ret;
2235 }
2236 }
2237
2238 return 0;
2239 }
2240
2241 ret = ath10k_bmi_write32(ar, hi_dbg_uart_txpin, ar->hw_params.uart_pin);
2242 if (ret) {
2243 ath10k_warn(ar, "could not enable UART prints (%d)\n", ret);
2244 return ret;
2245 }
2246
2247 ret = ath10k_bmi_write32(ar, hi_serial_enable, 1);
2248 if (ret) {
2249 ath10k_warn(ar, "could not enable UART prints (%d)\n", ret);
2250 return ret;
2251 }
2252
2253 /* Set the UART baud rate to 19200. */
2254 ret = ath10k_bmi_write32(ar, hi_desired_baud_rate, 19200);
2255 if (ret) {
2256 ath10k_warn(ar, "could not set the baud rate (%d)\n", ret);
2257 return ret;
2258 }
2259
2260 ath10k_info(ar, "UART prints enabled\n");
2261 return 0;
2262 }
2263
ath10k_init_hw_params(struct ath10k * ar)2264 static int ath10k_init_hw_params(struct ath10k *ar)
2265 {
2266 const struct ath10k_hw_params *hw_params;
2267 int i;
2268
2269 for (i = 0; i < ARRAY_SIZE(ath10k_hw_params_list); i++) {
2270 hw_params = &ath10k_hw_params_list[i];
2271
2272 if (hw_params->bus == ar->hif.bus &&
2273 hw_params->id == ar->target_version &&
2274 hw_params->dev_id == ar->dev_id)
2275 break;
2276 }
2277
2278 if (i == ARRAY_SIZE(ath10k_hw_params_list)) {
2279 ath10k_err(ar, "Unsupported hardware version: 0x%x\n",
2280 ar->target_version);
2281 return -EINVAL;
2282 }
2283
2284 ar->hw_params = *hw_params;
2285
2286 ath10k_dbg(ar, ATH10K_DBG_BOOT, "Hardware name %s version 0x%x\n",
2287 ar->hw_params.name, ar->target_version);
2288
2289 return 0;
2290 }
2291
ath10k_core_restart(struct work_struct * work)2292 static void ath10k_core_restart(struct work_struct *work)
2293 {
2294 struct ath10k *ar = container_of(work, struct ath10k, restart_work);
2295 int ret;
2296
2297 set_bit(ATH10K_FLAG_CRASH_FLUSH, &ar->dev_flags);
2298
2299 /* Place a barrier to make sure the compiler doesn't reorder
2300 * CRASH_FLUSH and calling other functions.
2301 */
2302 barrier();
2303
2304 ieee80211_stop_queues(ar->hw);
2305 ath10k_drain_tx(ar);
2306 complete(&ar->scan.started);
2307 complete(&ar->scan.completed);
2308 complete(&ar->scan.on_channel);
2309 complete(&ar->offchan_tx_completed);
2310 complete(&ar->install_key_done);
2311 complete(&ar->vdev_setup_done);
2312 complete(&ar->vdev_delete_done);
2313 complete(&ar->thermal.wmi_sync);
2314 complete(&ar->bss_survey_done);
2315 wake_up(&ar->htt.empty_tx_wq);
2316 wake_up(&ar->wmi.tx_credits_wq);
2317 wake_up(&ar->peer_mapping_wq);
2318
2319 /* TODO: We can have one instance of cancelling coverage_class_work by
2320 * moving it to ath10k_halt(), so that both stop() and restart() would
2321 * call that but it takes conf_mutex() and if we call cancel_work_sync()
2322 * with conf_mutex it will deadlock.
2323 */
2324 cancel_work_sync(&ar->set_coverage_class_work);
2325
2326 mutex_lock(&ar->conf_mutex);
2327
2328 switch (ar->state) {
2329 case ATH10K_STATE_ON:
2330 ar->state = ATH10K_STATE_RESTARTING;
2331 ath10k_halt(ar);
2332 ath10k_scan_finish(ar);
2333 ieee80211_restart_hw(ar->hw);
2334 break;
2335 case ATH10K_STATE_OFF:
2336 /* this can happen if driver is being unloaded
2337 * or if the crash happens during FW probing
2338 */
2339 ath10k_warn(ar, "cannot restart a device that hasn't been started\n");
2340 break;
2341 case ATH10K_STATE_RESTARTING:
2342 /* hw restart might be requested from multiple places */
2343 break;
2344 case ATH10K_STATE_RESTARTED:
2345 ar->state = ATH10K_STATE_WEDGED;
2346 fallthrough;
2347 case ATH10K_STATE_WEDGED:
2348 ath10k_warn(ar, "device is wedged, will not restart\n");
2349 break;
2350 case ATH10K_STATE_UTF:
2351 ath10k_warn(ar, "firmware restart in UTF mode not supported\n");
2352 break;
2353 }
2354
2355 mutex_unlock(&ar->conf_mutex);
2356
2357 ret = ath10k_coredump_submit(ar);
2358 if (ret)
2359 ath10k_warn(ar, "failed to send firmware crash dump via devcoredump: %d",
2360 ret);
2361
2362 complete(&ar->driver_recovery);
2363 }
2364
ath10k_core_set_coverage_class_work(struct work_struct * work)2365 static void ath10k_core_set_coverage_class_work(struct work_struct *work)
2366 {
2367 struct ath10k *ar = container_of(work, struct ath10k,
2368 set_coverage_class_work);
2369
2370 if (ar->hw_params.hw_ops->set_coverage_class)
2371 ar->hw_params.hw_ops->set_coverage_class(ar, -1);
2372 }
2373
ath10k_core_init_firmware_features(struct ath10k * ar)2374 static int ath10k_core_init_firmware_features(struct ath10k *ar)
2375 {
2376 struct ath10k_fw_file *fw_file = &ar->normal_mode_fw.fw_file;
2377 int max_num_peers;
2378
2379 if (test_bit(ATH10K_FW_FEATURE_WMI_10_2, fw_file->fw_features) &&
2380 !test_bit(ATH10K_FW_FEATURE_WMI_10X, fw_file->fw_features)) {
2381 ath10k_err(ar, "feature bits corrupted: 10.2 feature requires 10.x feature to be set as well");
2382 return -EINVAL;
2383 }
2384
2385 if (fw_file->wmi_op_version >= ATH10K_FW_WMI_OP_VERSION_MAX) {
2386 ath10k_err(ar, "unsupported WMI OP version (max %d): %d\n",
2387 ATH10K_FW_WMI_OP_VERSION_MAX, fw_file->wmi_op_version);
2388 return -EINVAL;
2389 }
2390
2391 ar->wmi.rx_decap_mode = ATH10K_HW_TXRX_NATIVE_WIFI;
2392 switch (ath10k_cryptmode_param) {
2393 case ATH10K_CRYPT_MODE_HW:
2394 clear_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags);
2395 clear_bit(ATH10K_FLAG_HW_CRYPTO_DISABLED, &ar->dev_flags);
2396 break;
2397 case ATH10K_CRYPT_MODE_SW:
2398 if (!test_bit(ATH10K_FW_FEATURE_RAW_MODE_SUPPORT,
2399 fw_file->fw_features)) {
2400 ath10k_err(ar, "cryptmode > 0 requires raw mode support from firmware");
2401 return -EINVAL;
2402 }
2403
2404 set_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags);
2405 set_bit(ATH10K_FLAG_HW_CRYPTO_DISABLED, &ar->dev_flags);
2406 break;
2407 default:
2408 ath10k_info(ar, "invalid cryptmode: %d\n",
2409 ath10k_cryptmode_param);
2410 return -EINVAL;
2411 }
2412
2413 ar->htt.max_num_amsdu = ATH10K_HTT_MAX_NUM_AMSDU_DEFAULT;
2414 ar->htt.max_num_ampdu = ATH10K_HTT_MAX_NUM_AMPDU_DEFAULT;
2415
2416 if (rawmode) {
2417 if (!test_bit(ATH10K_FW_FEATURE_RAW_MODE_SUPPORT,
2418 fw_file->fw_features)) {
2419 ath10k_err(ar, "rawmode = 1 requires support from firmware");
2420 return -EINVAL;
2421 }
2422 set_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags);
2423 }
2424
2425 if (test_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags)) {
2426 ar->wmi.rx_decap_mode = ATH10K_HW_TXRX_RAW;
2427
2428 /* Workaround:
2429 *
2430 * Firmware A-MSDU aggregation breaks with RAW Tx encap mode
2431 * and causes enormous performance issues (malformed frames,
2432 * etc).
2433 *
2434 * Disabling A-MSDU makes RAW mode stable with heavy traffic
2435 * albeit a bit slower compared to regular operation.
2436 */
2437 ar->htt.max_num_amsdu = 1;
2438 }
2439
2440 /* Backwards compatibility for firmwares without
2441 * ATH10K_FW_IE_WMI_OP_VERSION.
2442 */
2443 if (fw_file->wmi_op_version == ATH10K_FW_WMI_OP_VERSION_UNSET) {
2444 if (test_bit(ATH10K_FW_FEATURE_WMI_10X, fw_file->fw_features)) {
2445 if (test_bit(ATH10K_FW_FEATURE_WMI_10_2,
2446 fw_file->fw_features))
2447 fw_file->wmi_op_version = ATH10K_FW_WMI_OP_VERSION_10_2;
2448 else
2449 fw_file->wmi_op_version = ATH10K_FW_WMI_OP_VERSION_10_1;
2450 } else {
2451 fw_file->wmi_op_version = ATH10K_FW_WMI_OP_VERSION_MAIN;
2452 }
2453 }
2454
2455 switch (fw_file->wmi_op_version) {
2456 case ATH10K_FW_WMI_OP_VERSION_MAIN:
2457 max_num_peers = TARGET_NUM_PEERS;
2458 ar->max_num_stations = TARGET_NUM_STATIONS;
2459 ar->max_num_vdevs = TARGET_NUM_VDEVS;
2460 ar->htt.max_num_pending_tx = TARGET_NUM_MSDU_DESC;
2461 ar->fw_stats_req_mask = WMI_STAT_PDEV | WMI_STAT_VDEV |
2462 WMI_STAT_PEER;
2463 ar->max_spatial_stream = WMI_MAX_SPATIAL_STREAM;
2464 break;
2465 case ATH10K_FW_WMI_OP_VERSION_10_1:
2466 case ATH10K_FW_WMI_OP_VERSION_10_2:
2467 case ATH10K_FW_WMI_OP_VERSION_10_2_4:
2468 if (ath10k_peer_stats_enabled(ar)) {
2469 max_num_peers = TARGET_10X_TX_STATS_NUM_PEERS;
2470 ar->max_num_stations = TARGET_10X_TX_STATS_NUM_STATIONS;
2471 } else {
2472 max_num_peers = TARGET_10X_NUM_PEERS;
2473 ar->max_num_stations = TARGET_10X_NUM_STATIONS;
2474 }
2475 ar->max_num_vdevs = TARGET_10X_NUM_VDEVS;
2476 ar->htt.max_num_pending_tx = TARGET_10X_NUM_MSDU_DESC;
2477 ar->fw_stats_req_mask = WMI_STAT_PEER;
2478 ar->max_spatial_stream = WMI_MAX_SPATIAL_STREAM;
2479 break;
2480 case ATH10K_FW_WMI_OP_VERSION_TLV:
2481 max_num_peers = TARGET_TLV_NUM_PEERS;
2482 ar->max_num_stations = TARGET_TLV_NUM_STATIONS;
2483 ar->max_num_vdevs = TARGET_TLV_NUM_VDEVS;
2484 ar->max_num_tdls_vdevs = TARGET_TLV_NUM_TDLS_VDEVS;
2485 if (ar->hif.bus == ATH10K_BUS_SDIO)
2486 ar->htt.max_num_pending_tx =
2487 TARGET_TLV_NUM_MSDU_DESC_HL;
2488 else
2489 ar->htt.max_num_pending_tx = TARGET_TLV_NUM_MSDU_DESC;
2490 ar->wow.max_num_patterns = TARGET_TLV_NUM_WOW_PATTERNS;
2491 ar->fw_stats_req_mask = WMI_TLV_STAT_PDEV | WMI_TLV_STAT_VDEV |
2492 WMI_TLV_STAT_PEER | WMI_TLV_STAT_PEER_EXTD;
2493 ar->max_spatial_stream = WMI_MAX_SPATIAL_STREAM;
2494 ar->wmi.mgmt_max_num_pending_tx = TARGET_TLV_MGMT_NUM_MSDU_DESC;
2495 break;
2496 case ATH10K_FW_WMI_OP_VERSION_10_4:
2497 max_num_peers = TARGET_10_4_NUM_PEERS;
2498 ar->max_num_stations = TARGET_10_4_NUM_STATIONS;
2499 ar->num_active_peers = TARGET_10_4_ACTIVE_PEERS;
2500 ar->max_num_vdevs = TARGET_10_4_NUM_VDEVS;
2501 ar->num_tids = TARGET_10_4_TGT_NUM_TIDS;
2502 ar->fw_stats_req_mask = WMI_10_4_STAT_PEER |
2503 WMI_10_4_STAT_PEER_EXTD |
2504 WMI_10_4_STAT_VDEV_EXTD;
2505 ar->max_spatial_stream = ar->hw_params.max_spatial_stream;
2506 ar->max_num_tdls_vdevs = TARGET_10_4_NUM_TDLS_VDEVS;
2507
2508 if (test_bit(ATH10K_FW_FEATURE_PEER_FLOW_CONTROL,
2509 fw_file->fw_features))
2510 ar->htt.max_num_pending_tx = TARGET_10_4_NUM_MSDU_DESC_PFC;
2511 else
2512 ar->htt.max_num_pending_tx = TARGET_10_4_NUM_MSDU_DESC;
2513 break;
2514 case ATH10K_FW_WMI_OP_VERSION_UNSET:
2515 case ATH10K_FW_WMI_OP_VERSION_MAX:
2516 default:
2517 WARN_ON(1);
2518 return -EINVAL;
2519 }
2520
2521 if (ar->hw_params.num_peers)
2522 ar->max_num_peers = ar->hw_params.num_peers;
2523 else
2524 ar->max_num_peers = max_num_peers;
2525
2526 /* Backwards compatibility for firmwares without
2527 * ATH10K_FW_IE_HTT_OP_VERSION.
2528 */
2529 if (fw_file->htt_op_version == ATH10K_FW_HTT_OP_VERSION_UNSET) {
2530 switch (fw_file->wmi_op_version) {
2531 case ATH10K_FW_WMI_OP_VERSION_MAIN:
2532 fw_file->htt_op_version = ATH10K_FW_HTT_OP_VERSION_MAIN;
2533 break;
2534 case ATH10K_FW_WMI_OP_VERSION_10_1:
2535 case ATH10K_FW_WMI_OP_VERSION_10_2:
2536 case ATH10K_FW_WMI_OP_VERSION_10_2_4:
2537 fw_file->htt_op_version = ATH10K_FW_HTT_OP_VERSION_10_1;
2538 break;
2539 case ATH10K_FW_WMI_OP_VERSION_TLV:
2540 fw_file->htt_op_version = ATH10K_FW_HTT_OP_VERSION_TLV;
2541 break;
2542 case ATH10K_FW_WMI_OP_VERSION_10_4:
2543 case ATH10K_FW_WMI_OP_VERSION_UNSET:
2544 case ATH10K_FW_WMI_OP_VERSION_MAX:
2545 ath10k_err(ar, "htt op version not found from fw meta data");
2546 return -EINVAL;
2547 }
2548 }
2549
2550 return 0;
2551 }
2552
ath10k_core_reset_rx_filter(struct ath10k * ar)2553 static int ath10k_core_reset_rx_filter(struct ath10k *ar)
2554 {
2555 int ret;
2556 int vdev_id;
2557 int vdev_type;
2558 int vdev_subtype;
2559 const u8 *vdev_addr;
2560
2561 vdev_id = 0;
2562 vdev_type = WMI_VDEV_TYPE_STA;
2563 vdev_subtype = ath10k_wmi_get_vdev_subtype(ar, WMI_VDEV_SUBTYPE_NONE);
2564 vdev_addr = ar->mac_addr;
2565
2566 ret = ath10k_wmi_vdev_create(ar, vdev_id, vdev_type, vdev_subtype,
2567 vdev_addr);
2568 if (ret) {
2569 ath10k_err(ar, "failed to create dummy vdev: %d\n", ret);
2570 return ret;
2571 }
2572
2573 ret = ath10k_wmi_vdev_delete(ar, vdev_id);
2574 if (ret) {
2575 ath10k_err(ar, "failed to delete dummy vdev: %d\n", ret);
2576 return ret;
2577 }
2578
2579 /* WMI and HTT may use separate HIF pipes and are not guaranteed to be
2580 * serialized properly implicitly.
2581 *
2582 * Moreover (most) WMI commands have no explicit acknowledges. It is
2583 * possible to infer it implicitly by poking firmware with echo
2584 * command - getting a reply means all preceding comments have been
2585 * (mostly) processed.
2586 *
2587 * In case of vdev create/delete this is sufficient.
2588 *
2589 * Without this it's possible to end up with a race when HTT Rx ring is
2590 * started before vdev create/delete hack is complete allowing a short
2591 * window of opportunity to receive (and Tx ACK) a bunch of frames.
2592 */
2593 ret = ath10k_wmi_barrier(ar);
2594 if (ret) {
2595 ath10k_err(ar, "failed to ping firmware: %d\n", ret);
2596 return ret;
2597 }
2598
2599 return 0;
2600 }
2601
ath10k_core_compat_services(struct ath10k * ar)2602 static int ath10k_core_compat_services(struct ath10k *ar)
2603 {
2604 struct ath10k_fw_file *fw_file = &ar->normal_mode_fw.fw_file;
2605
2606 /* all 10.x firmware versions support thermal throttling but don't
2607 * advertise the support via service flags so we have to hardcode
2608 * it here
2609 */
2610 switch (fw_file->wmi_op_version) {
2611 case ATH10K_FW_WMI_OP_VERSION_10_1:
2612 case ATH10K_FW_WMI_OP_VERSION_10_2:
2613 case ATH10K_FW_WMI_OP_VERSION_10_2_4:
2614 case ATH10K_FW_WMI_OP_VERSION_10_4:
2615 set_bit(WMI_SERVICE_THERM_THROT, ar->wmi.svc_map);
2616 break;
2617 default:
2618 break;
2619 }
2620
2621 return 0;
2622 }
2623
ath10k_core_start(struct ath10k * ar,enum ath10k_firmware_mode mode,const struct ath10k_fw_components * fw)2624 int ath10k_core_start(struct ath10k *ar, enum ath10k_firmware_mode mode,
2625 const struct ath10k_fw_components *fw)
2626 {
2627 int status;
2628 u32 val;
2629
2630 lockdep_assert_held(&ar->conf_mutex);
2631
2632 clear_bit(ATH10K_FLAG_CRASH_FLUSH, &ar->dev_flags);
2633
2634 ar->running_fw = fw;
2635
2636 if (!test_bit(ATH10K_FW_FEATURE_NON_BMI,
2637 ar->running_fw->fw_file.fw_features)) {
2638 ath10k_bmi_start(ar);
2639
2640 /* Enable hardware clock to speed up firmware download */
2641 if (ar->hw_params.hw_ops->enable_pll_clk) {
2642 status = ar->hw_params.hw_ops->enable_pll_clk(ar);
2643 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot enable pll ret %d\n",
2644 status);
2645 }
2646
2647 if (ath10k_init_configure_target(ar)) {
2648 status = -EINVAL;
2649 goto err;
2650 }
2651
2652 status = ath10k_download_cal_data(ar);
2653 if (status)
2654 goto err;
2655
2656 /* Some of of qca988x solutions are having global reset issue
2657 * during target initialization. Bypassing PLL setting before
2658 * downloading firmware and letting the SoC run on REF_CLK is
2659 * fixing the problem. Corresponding firmware change is also
2660 * needed to set the clock source once the target is
2661 * initialized.
2662 */
2663 if (test_bit(ATH10K_FW_FEATURE_SUPPORTS_SKIP_CLOCK_INIT,
2664 ar->running_fw->fw_file.fw_features)) {
2665 status = ath10k_bmi_write32(ar, hi_skip_clock_init, 1);
2666 if (status) {
2667 ath10k_err(ar, "could not write to skip_clock_init: %d\n",
2668 status);
2669 goto err;
2670 }
2671 }
2672
2673 status = ath10k_download_fw(ar);
2674 if (status)
2675 goto err;
2676
2677 status = ath10k_init_uart(ar);
2678 if (status)
2679 goto err;
2680
2681 if (ar->hif.bus == ATH10K_BUS_SDIO) {
2682 status = ath10k_init_sdio(ar, mode);
2683 if (status) {
2684 ath10k_err(ar, "failed to init SDIO: %d\n", status);
2685 goto err;
2686 }
2687 }
2688 }
2689
2690 ar->htc.htc_ops.target_send_suspend_complete =
2691 ath10k_send_suspend_complete;
2692
2693 status = ath10k_htc_init(ar);
2694 if (status) {
2695 ath10k_err(ar, "could not init HTC (%d)\n", status);
2696 goto err;
2697 }
2698
2699 if (!test_bit(ATH10K_FW_FEATURE_NON_BMI,
2700 ar->running_fw->fw_file.fw_features)) {
2701 status = ath10k_bmi_done(ar);
2702 if (status)
2703 goto err;
2704 }
2705
2706 status = ath10k_wmi_attach(ar);
2707 if (status) {
2708 ath10k_err(ar, "WMI attach failed: %d\n", status);
2709 goto err;
2710 }
2711
2712 status = ath10k_htt_init(ar);
2713 if (status) {
2714 ath10k_err(ar, "failed to init htt: %d\n", status);
2715 goto err_wmi_detach;
2716 }
2717
2718 status = ath10k_htt_tx_start(&ar->htt);
2719 if (status) {
2720 ath10k_err(ar, "failed to alloc htt tx: %d\n", status);
2721 goto err_wmi_detach;
2722 }
2723
2724 /* If firmware indicates Full Rx Reorder support it must be used in a
2725 * slightly different manner. Let HTT code know.
2726 */
2727 ar->htt.rx_ring.in_ord_rx = !!(test_bit(WMI_SERVICE_RX_FULL_REORDER,
2728 ar->wmi.svc_map));
2729
2730 status = ath10k_htt_rx_alloc(&ar->htt);
2731 if (status) {
2732 ath10k_err(ar, "failed to alloc htt rx: %d\n", status);
2733 goto err_htt_tx_detach;
2734 }
2735
2736 status = ath10k_hif_start(ar);
2737 if (status) {
2738 ath10k_err(ar, "could not start HIF: %d\n", status);
2739 goto err_htt_rx_detach;
2740 }
2741
2742 status = ath10k_htc_wait_target(&ar->htc);
2743 if (status) {
2744 ath10k_err(ar, "failed to connect to HTC: %d\n", status);
2745 goto err_hif_stop;
2746 }
2747
2748 status = ath10k_hif_start_post(ar);
2749 if (status) {
2750 ath10k_err(ar, "failed to swap mailbox: %d\n", status);
2751 goto err_hif_stop;
2752 }
2753
2754 if (mode == ATH10K_FIRMWARE_MODE_NORMAL) {
2755 status = ath10k_htt_connect(&ar->htt);
2756 if (status) {
2757 ath10k_err(ar, "failed to connect htt (%d)\n", status);
2758 goto err_hif_stop;
2759 }
2760 }
2761
2762 status = ath10k_wmi_connect(ar);
2763 if (status) {
2764 ath10k_err(ar, "could not connect wmi: %d\n", status);
2765 goto err_hif_stop;
2766 }
2767
2768 status = ath10k_htc_start(&ar->htc);
2769 if (status) {
2770 ath10k_err(ar, "failed to start htc: %d\n", status);
2771 goto err_hif_stop;
2772 }
2773
2774 if (mode == ATH10K_FIRMWARE_MODE_NORMAL) {
2775 status = ath10k_wmi_wait_for_service_ready(ar);
2776 if (status) {
2777 ath10k_warn(ar, "wmi service ready event not received");
2778 goto err_hif_stop;
2779 }
2780 }
2781
2782 ath10k_dbg(ar, ATH10K_DBG_BOOT, "firmware %s booted\n",
2783 ar->hw->wiphy->fw_version);
2784
2785 if (test_bit(WMI_SERVICE_EXT_RES_CFG_SUPPORT, ar->wmi.svc_map) &&
2786 mode == ATH10K_FIRMWARE_MODE_NORMAL) {
2787 val = 0;
2788 if (ath10k_peer_stats_enabled(ar))
2789 val = WMI_10_4_PEER_STATS;
2790
2791 /* Enable vdev stats by default */
2792 val |= WMI_10_4_VDEV_STATS;
2793
2794 if (test_bit(WMI_SERVICE_BSS_CHANNEL_INFO_64, ar->wmi.svc_map))
2795 val |= WMI_10_4_BSS_CHANNEL_INFO_64;
2796
2797 ath10k_core_fetch_btcoex_dt(ar);
2798
2799 /* 10.4 firmware supports BT-Coex without reloading firmware
2800 * via pdev param. To support Bluetooth coexistence pdev param,
2801 * WMI_COEX_GPIO_SUPPORT of extended resource config should be
2802 * enabled always.
2803 *
2804 * We can still enable BTCOEX if firmware has the support
2805 * eventhough btceox_support value is
2806 * ATH10K_DT_BTCOEX_NOT_FOUND
2807 */
2808
2809 if (test_bit(WMI_SERVICE_COEX_GPIO, ar->wmi.svc_map) &&
2810 test_bit(ATH10K_FW_FEATURE_BTCOEX_PARAM,
2811 ar->running_fw->fw_file.fw_features) &&
2812 ar->coex_support)
2813 val |= WMI_10_4_COEX_GPIO_SUPPORT;
2814
2815 if (test_bit(WMI_SERVICE_TDLS_EXPLICIT_MODE_ONLY,
2816 ar->wmi.svc_map))
2817 val |= WMI_10_4_TDLS_EXPLICIT_MODE_ONLY;
2818
2819 if (test_bit(WMI_SERVICE_TDLS_UAPSD_BUFFER_STA,
2820 ar->wmi.svc_map))
2821 val |= WMI_10_4_TDLS_UAPSD_BUFFER_STA;
2822
2823 if (test_bit(WMI_SERVICE_TX_DATA_ACK_RSSI,
2824 ar->wmi.svc_map))
2825 val |= WMI_10_4_TX_DATA_ACK_RSSI;
2826
2827 if (test_bit(WMI_SERVICE_REPORT_AIRTIME, ar->wmi.svc_map))
2828 val |= WMI_10_4_REPORT_AIRTIME;
2829
2830 if (test_bit(WMI_SERVICE_EXT_PEER_TID_CONFIGS_SUPPORT,
2831 ar->wmi.svc_map))
2832 val |= WMI_10_4_EXT_PEER_TID_CONFIGS_SUPPORT;
2833
2834 status = ath10k_mac_ext_resource_config(ar, val);
2835 if (status) {
2836 ath10k_err(ar,
2837 "failed to send ext resource cfg command : %d\n",
2838 status);
2839 goto err_hif_stop;
2840 }
2841 }
2842
2843 status = ath10k_wmi_cmd_init(ar);
2844 if (status) {
2845 ath10k_err(ar, "could not send WMI init command (%d)\n",
2846 status);
2847 goto err_hif_stop;
2848 }
2849
2850 status = ath10k_wmi_wait_for_unified_ready(ar);
2851 if (status) {
2852 ath10k_err(ar, "wmi unified ready event not received\n");
2853 goto err_hif_stop;
2854 }
2855
2856 status = ath10k_core_compat_services(ar);
2857 if (status) {
2858 ath10k_err(ar, "compat services failed: %d\n", status);
2859 goto err_hif_stop;
2860 }
2861
2862 status = ath10k_wmi_pdev_set_base_macaddr(ar, ar->mac_addr);
2863 if (status && status != -EOPNOTSUPP) {
2864 ath10k_err(ar,
2865 "failed to set base mac address: %d\n", status);
2866 goto err_hif_stop;
2867 }
2868
2869 /* Some firmware revisions do not properly set up hardware rx filter
2870 * registers.
2871 *
2872 * A known example from QCA9880 and 10.2.4 is that MAC_PCU_ADDR1_MASK
2873 * is filled with 0s instead of 1s allowing HW to respond with ACKs to
2874 * any frames that matches MAC_PCU_RX_FILTER which is also
2875 * misconfigured to accept anything.
2876 *
2877 * The ADDR1 is programmed using internal firmware structure field and
2878 * can't be (easily/sanely) reached from the driver explicitly. It is
2879 * possible to implicitly make it correct by creating a dummy vdev and
2880 * then deleting it.
2881 */
2882 if (ar->hw_params.hw_filter_reset_required &&
2883 mode == ATH10K_FIRMWARE_MODE_NORMAL) {
2884 status = ath10k_core_reset_rx_filter(ar);
2885 if (status) {
2886 ath10k_err(ar,
2887 "failed to reset rx filter: %d\n", status);
2888 goto err_hif_stop;
2889 }
2890 }
2891
2892 status = ath10k_htt_rx_ring_refill(ar);
2893 if (status) {
2894 ath10k_err(ar, "failed to refill htt rx ring: %d\n", status);
2895 goto err_hif_stop;
2896 }
2897
2898 if (ar->max_num_vdevs >= 64)
2899 ar->free_vdev_map = 0xFFFFFFFFFFFFFFFFLL;
2900 else
2901 ar->free_vdev_map = (1LL << ar->max_num_vdevs) - 1;
2902
2903 INIT_LIST_HEAD(&ar->arvifs);
2904
2905 /* we don't care about HTT in UTF mode */
2906 if (mode == ATH10K_FIRMWARE_MODE_NORMAL) {
2907 status = ath10k_htt_setup(&ar->htt);
2908 if (status) {
2909 ath10k_err(ar, "failed to setup htt: %d\n", status);
2910 goto err_hif_stop;
2911 }
2912 }
2913
2914 status = ath10k_debug_start(ar);
2915 if (status)
2916 goto err_hif_stop;
2917
2918 status = ath10k_hif_set_target_log_mode(ar, fw_diag_log);
2919 if (status && status != -EOPNOTSUPP) {
2920 ath10k_warn(ar, "set target log mode failed: %d\n", status);
2921 goto err_hif_stop;
2922 }
2923
2924 return 0;
2925
2926 err_hif_stop:
2927 ath10k_hif_stop(ar);
2928 err_htt_rx_detach:
2929 ath10k_htt_rx_free(&ar->htt);
2930 err_htt_tx_detach:
2931 ath10k_htt_tx_free(&ar->htt);
2932 err_wmi_detach:
2933 ath10k_wmi_detach(ar);
2934 err:
2935 return status;
2936 }
2937 EXPORT_SYMBOL(ath10k_core_start);
2938
ath10k_wait_for_suspend(struct ath10k * ar,u32 suspend_opt)2939 int ath10k_wait_for_suspend(struct ath10k *ar, u32 suspend_opt)
2940 {
2941 int ret;
2942 unsigned long time_left;
2943
2944 reinit_completion(&ar->target_suspend);
2945
2946 ret = ath10k_wmi_pdev_suspend_target(ar, suspend_opt);
2947 if (ret) {
2948 ath10k_warn(ar, "could not suspend target (%d)\n", ret);
2949 return ret;
2950 }
2951
2952 time_left = wait_for_completion_timeout(&ar->target_suspend, 1 * HZ);
2953
2954 if (!time_left) {
2955 ath10k_warn(ar, "suspend timed out - target pause event never came\n");
2956 return -ETIMEDOUT;
2957 }
2958
2959 return 0;
2960 }
2961
ath10k_core_stop(struct ath10k * ar)2962 void ath10k_core_stop(struct ath10k *ar)
2963 {
2964 lockdep_assert_held(&ar->conf_mutex);
2965 ath10k_debug_stop(ar);
2966
2967 /* try to suspend target */
2968 if (ar->state != ATH10K_STATE_RESTARTING &&
2969 ar->state != ATH10K_STATE_UTF)
2970 ath10k_wait_for_suspend(ar, WMI_PDEV_SUSPEND_AND_DISABLE_INTR);
2971
2972 ath10k_hif_stop(ar);
2973 ath10k_htt_tx_stop(&ar->htt);
2974 ath10k_htt_rx_free(&ar->htt);
2975 ath10k_wmi_detach(ar);
2976
2977 ar->id.bmi_ids_valid = false;
2978 }
2979 EXPORT_SYMBOL(ath10k_core_stop);
2980
2981 /* mac80211 manages fw/hw initialization through start/stop hooks. However in
2982 * order to know what hw capabilities should be advertised to mac80211 it is
2983 * necessary to load the firmware (and tear it down immediately since start
2984 * hook will try to init it again) before registering
2985 */
ath10k_core_probe_fw(struct ath10k * ar)2986 static int ath10k_core_probe_fw(struct ath10k *ar)
2987 {
2988 struct bmi_target_info target_info;
2989 int ret = 0;
2990
2991 ret = ath10k_hif_power_up(ar, ATH10K_FIRMWARE_MODE_NORMAL);
2992 if (ret) {
2993 ath10k_err(ar, "could not power on hif bus (%d)\n", ret);
2994 return ret;
2995 }
2996
2997 switch (ar->hif.bus) {
2998 case ATH10K_BUS_SDIO:
2999 memset(&target_info, 0, sizeof(target_info));
3000 ret = ath10k_bmi_get_target_info_sdio(ar, &target_info);
3001 if (ret) {
3002 ath10k_err(ar, "could not get target info (%d)\n", ret);
3003 goto err_power_down;
3004 }
3005 ar->target_version = target_info.version;
3006 ar->hw->wiphy->hw_version = target_info.version;
3007 break;
3008 case ATH10K_BUS_PCI:
3009 case ATH10K_BUS_AHB:
3010 case ATH10K_BUS_USB:
3011 memset(&target_info, 0, sizeof(target_info));
3012 ret = ath10k_bmi_get_target_info(ar, &target_info);
3013 if (ret) {
3014 ath10k_err(ar, "could not get target info (%d)\n", ret);
3015 goto err_power_down;
3016 }
3017 ar->target_version = target_info.version;
3018 ar->hw->wiphy->hw_version = target_info.version;
3019 break;
3020 case ATH10K_BUS_SNOC:
3021 memset(&target_info, 0, sizeof(target_info));
3022 ret = ath10k_hif_get_target_info(ar, &target_info);
3023 if (ret) {
3024 ath10k_err(ar, "could not get target info (%d)\n", ret);
3025 goto err_power_down;
3026 }
3027 ar->target_version = target_info.version;
3028 ar->hw->wiphy->hw_version = target_info.version;
3029 break;
3030 default:
3031 ath10k_err(ar, "incorrect hif bus type: %d\n", ar->hif.bus);
3032 }
3033
3034 ret = ath10k_init_hw_params(ar);
3035 if (ret) {
3036 ath10k_err(ar, "could not get hw params (%d)\n", ret);
3037 goto err_power_down;
3038 }
3039
3040 ret = ath10k_core_fetch_firmware_files(ar);
3041 if (ret) {
3042 ath10k_err(ar, "could not fetch firmware files (%d)\n", ret);
3043 goto err_power_down;
3044 }
3045
3046 BUILD_BUG_ON(sizeof(ar->hw->wiphy->fw_version) !=
3047 sizeof(ar->normal_mode_fw.fw_file.fw_version));
3048 memcpy(ar->hw->wiphy->fw_version, ar->normal_mode_fw.fw_file.fw_version,
3049 sizeof(ar->hw->wiphy->fw_version));
3050
3051 ath10k_debug_print_hwfw_info(ar);
3052
3053 if (!test_bit(ATH10K_FW_FEATURE_NON_BMI,
3054 ar->normal_mode_fw.fw_file.fw_features)) {
3055 ret = ath10k_core_pre_cal_download(ar);
3056 if (ret) {
3057 /* pre calibration data download is not necessary
3058 * for all the chipsets. Ignore failures and continue.
3059 */
3060 ath10k_dbg(ar, ATH10K_DBG_BOOT,
3061 "could not load pre cal data: %d\n", ret);
3062 }
3063
3064 ret = ath10k_core_get_board_id_from_otp(ar);
3065 if (ret && ret != -EOPNOTSUPP) {
3066 ath10k_err(ar, "failed to get board id from otp: %d\n",
3067 ret);
3068 goto err_free_firmware_files;
3069 }
3070
3071 ret = ath10k_core_check_smbios(ar);
3072 if (ret)
3073 ath10k_dbg(ar, ATH10K_DBG_BOOT, "SMBIOS bdf variant name not set.\n");
3074
3075 ret = ath10k_core_check_dt(ar);
3076 if (ret)
3077 ath10k_dbg(ar, ATH10K_DBG_BOOT, "DT bdf variant name not set.\n");
3078
3079 ret = ath10k_core_fetch_board_file(ar, ATH10K_BD_IE_BOARD);
3080 if (ret) {
3081 ath10k_err(ar, "failed to fetch board file: %d\n", ret);
3082 goto err_free_firmware_files;
3083 }
3084
3085 ath10k_debug_print_board_info(ar);
3086 }
3087
3088 device_get_mac_address(ar->dev, ar->mac_addr, sizeof(ar->mac_addr));
3089
3090 ret = ath10k_core_init_firmware_features(ar);
3091 if (ret) {
3092 ath10k_err(ar, "fatal problem with firmware features: %d\n",
3093 ret);
3094 goto err_free_firmware_files;
3095 }
3096
3097 if (!test_bit(ATH10K_FW_FEATURE_NON_BMI,
3098 ar->normal_mode_fw.fw_file.fw_features)) {
3099 ret = ath10k_swap_code_seg_init(ar,
3100 &ar->normal_mode_fw.fw_file);
3101 if (ret) {
3102 ath10k_err(ar, "failed to initialize code swap segment: %d\n",
3103 ret);
3104 goto err_free_firmware_files;
3105 }
3106 }
3107
3108 mutex_lock(&ar->conf_mutex);
3109
3110 ret = ath10k_core_start(ar, ATH10K_FIRMWARE_MODE_NORMAL,
3111 &ar->normal_mode_fw);
3112 if (ret) {
3113 ath10k_err(ar, "could not init core (%d)\n", ret);
3114 goto err_unlock;
3115 }
3116
3117 ath10k_debug_print_boot_info(ar);
3118 ath10k_core_stop(ar);
3119
3120 mutex_unlock(&ar->conf_mutex);
3121
3122 ath10k_hif_power_down(ar);
3123 return 0;
3124
3125 err_unlock:
3126 mutex_unlock(&ar->conf_mutex);
3127
3128 err_free_firmware_files:
3129 ath10k_core_free_firmware_files(ar);
3130
3131 err_power_down:
3132 ath10k_hif_power_down(ar);
3133
3134 return ret;
3135 }
3136
ath10k_core_register_work(struct work_struct * work)3137 static void ath10k_core_register_work(struct work_struct *work)
3138 {
3139 struct ath10k *ar = container_of(work, struct ath10k, register_work);
3140 int status;
3141
3142 /* peer stats are enabled by default */
3143 set_bit(ATH10K_FLAG_PEER_STATS, &ar->dev_flags);
3144
3145 status = ath10k_core_probe_fw(ar);
3146 if (status) {
3147 ath10k_err(ar, "could not probe fw (%d)\n", status);
3148 goto err;
3149 }
3150
3151 status = ath10k_mac_register(ar);
3152 if (status) {
3153 ath10k_err(ar, "could not register to mac80211 (%d)\n", status);
3154 goto err_release_fw;
3155 }
3156
3157 status = ath10k_coredump_register(ar);
3158 if (status) {
3159 ath10k_err(ar, "unable to register coredump\n");
3160 goto err_unregister_mac;
3161 }
3162
3163 status = ath10k_debug_register(ar);
3164 if (status) {
3165 ath10k_err(ar, "unable to initialize debugfs\n");
3166 goto err_unregister_coredump;
3167 }
3168
3169 status = ath10k_spectral_create(ar);
3170 if (status) {
3171 ath10k_err(ar, "failed to initialize spectral\n");
3172 goto err_debug_destroy;
3173 }
3174
3175 status = ath10k_thermal_register(ar);
3176 if (status) {
3177 ath10k_err(ar, "could not register thermal device: %d\n",
3178 status);
3179 goto err_spectral_destroy;
3180 }
3181
3182 set_bit(ATH10K_FLAG_CORE_REGISTERED, &ar->dev_flags);
3183 return;
3184
3185 err_spectral_destroy:
3186 ath10k_spectral_destroy(ar);
3187 err_debug_destroy:
3188 ath10k_debug_destroy(ar);
3189 err_unregister_coredump:
3190 ath10k_coredump_unregister(ar);
3191 err_unregister_mac:
3192 ath10k_mac_unregister(ar);
3193 err_release_fw:
3194 ath10k_core_free_firmware_files(ar);
3195 err:
3196 /* TODO: It's probably a good idea to release device from the driver
3197 * but calling device_release_driver() here will cause a deadlock.
3198 */
3199 return;
3200 }
3201
ath10k_core_register(struct ath10k * ar,const struct ath10k_bus_params * bus_params)3202 int ath10k_core_register(struct ath10k *ar,
3203 const struct ath10k_bus_params *bus_params)
3204 {
3205 ar->bus_param = *bus_params;
3206
3207 queue_work(ar->workqueue, &ar->register_work);
3208
3209 return 0;
3210 }
3211 EXPORT_SYMBOL(ath10k_core_register);
3212
ath10k_core_unregister(struct ath10k * ar)3213 void ath10k_core_unregister(struct ath10k *ar)
3214 {
3215 cancel_work_sync(&ar->register_work);
3216
3217 if (!test_bit(ATH10K_FLAG_CORE_REGISTERED, &ar->dev_flags))
3218 return;
3219
3220 ath10k_thermal_unregister(ar);
3221 /* Stop spectral before unregistering from mac80211 to remove the
3222 * relayfs debugfs file cleanly. Otherwise the parent debugfs tree
3223 * would be already be free'd recursively, leading to a double free.
3224 */
3225 ath10k_spectral_destroy(ar);
3226
3227 /* We must unregister from mac80211 before we stop HTC and HIF.
3228 * Otherwise we will fail to submit commands to FW and mac80211 will be
3229 * unhappy about callback failures.
3230 */
3231 ath10k_mac_unregister(ar);
3232
3233 ath10k_testmode_destroy(ar);
3234
3235 ath10k_core_free_firmware_files(ar);
3236 ath10k_core_free_board_files(ar);
3237
3238 ath10k_debug_unregister(ar);
3239 }
3240 EXPORT_SYMBOL(ath10k_core_unregister);
3241
ath10k_core_create(size_t priv_size,struct device * dev,enum ath10k_bus bus,enum ath10k_hw_rev hw_rev,const struct ath10k_hif_ops * hif_ops)3242 struct ath10k *ath10k_core_create(size_t priv_size, struct device *dev,
3243 enum ath10k_bus bus,
3244 enum ath10k_hw_rev hw_rev,
3245 const struct ath10k_hif_ops *hif_ops)
3246 {
3247 struct ath10k *ar;
3248 int ret;
3249
3250 ar = ath10k_mac_create(priv_size);
3251 if (!ar)
3252 return NULL;
3253
3254 ar->ath_common.priv = ar;
3255 ar->ath_common.hw = ar->hw;
3256 ar->dev = dev;
3257 ar->hw_rev = hw_rev;
3258 ar->hif.ops = hif_ops;
3259 ar->hif.bus = bus;
3260
3261 switch (hw_rev) {
3262 case ATH10K_HW_QCA988X:
3263 case ATH10K_HW_QCA9887:
3264 ar->regs = &qca988x_regs;
3265 ar->hw_ce_regs = &qcax_ce_regs;
3266 ar->hw_values = &qca988x_values;
3267 break;
3268 case ATH10K_HW_QCA6174:
3269 case ATH10K_HW_QCA9377:
3270 ar->regs = &qca6174_regs;
3271 ar->hw_ce_regs = &qcax_ce_regs;
3272 ar->hw_values = &qca6174_values;
3273 break;
3274 case ATH10K_HW_QCA99X0:
3275 case ATH10K_HW_QCA9984:
3276 ar->regs = &qca99x0_regs;
3277 ar->hw_ce_regs = &qcax_ce_regs;
3278 ar->hw_values = &qca99x0_values;
3279 break;
3280 case ATH10K_HW_QCA9888:
3281 ar->regs = &qca99x0_regs;
3282 ar->hw_ce_regs = &qcax_ce_regs;
3283 ar->hw_values = &qca9888_values;
3284 break;
3285 case ATH10K_HW_QCA4019:
3286 ar->regs = &qca4019_regs;
3287 ar->hw_ce_regs = &qcax_ce_regs;
3288 ar->hw_values = &qca4019_values;
3289 break;
3290 case ATH10K_HW_WCN3990:
3291 ar->regs = &wcn3990_regs;
3292 ar->hw_ce_regs = &wcn3990_ce_regs;
3293 ar->hw_values = &wcn3990_values;
3294 break;
3295 default:
3296 ath10k_err(ar, "unsupported core hardware revision %d\n",
3297 hw_rev);
3298 ret = -ENOTSUPP;
3299 goto err_free_mac;
3300 }
3301
3302 init_completion(&ar->scan.started);
3303 init_completion(&ar->scan.completed);
3304 init_completion(&ar->scan.on_channel);
3305 init_completion(&ar->target_suspend);
3306 init_completion(&ar->driver_recovery);
3307 init_completion(&ar->wow.wakeup_completed);
3308
3309 init_completion(&ar->install_key_done);
3310 init_completion(&ar->vdev_setup_done);
3311 init_completion(&ar->vdev_delete_done);
3312 init_completion(&ar->thermal.wmi_sync);
3313 init_completion(&ar->bss_survey_done);
3314 init_completion(&ar->peer_delete_done);
3315 init_completion(&ar->peer_stats_info_complete);
3316
3317 INIT_DELAYED_WORK(&ar->scan.timeout, ath10k_scan_timeout_work);
3318
3319 ar->workqueue = create_singlethread_workqueue("ath10k_wq");
3320 if (!ar->workqueue)
3321 goto err_free_mac;
3322
3323 ar->workqueue_aux = create_singlethread_workqueue("ath10k_aux_wq");
3324 if (!ar->workqueue_aux)
3325 goto err_free_wq;
3326
3327 ar->workqueue_tx_complete =
3328 create_singlethread_workqueue("ath10k_tx_complete_wq");
3329 if (!ar->workqueue_tx_complete)
3330 goto err_free_aux_wq;
3331
3332 mutex_init(&ar->conf_mutex);
3333 mutex_init(&ar->dump_mutex);
3334 spin_lock_init(&ar->data_lock);
3335
3336 INIT_LIST_HEAD(&ar->peers);
3337 init_waitqueue_head(&ar->peer_mapping_wq);
3338 init_waitqueue_head(&ar->htt.empty_tx_wq);
3339 init_waitqueue_head(&ar->wmi.tx_credits_wq);
3340
3341 skb_queue_head_init(&ar->htt.rx_indication_head);
3342
3343 init_completion(&ar->offchan_tx_completed);
3344 INIT_WORK(&ar->offchan_tx_work, ath10k_offchan_tx_work);
3345 skb_queue_head_init(&ar->offchan_tx_queue);
3346
3347 INIT_WORK(&ar->wmi_mgmt_tx_work, ath10k_mgmt_over_wmi_tx_work);
3348 skb_queue_head_init(&ar->wmi_mgmt_tx_queue);
3349
3350 INIT_WORK(&ar->register_work, ath10k_core_register_work);
3351 INIT_WORK(&ar->restart_work, ath10k_core_restart);
3352 INIT_WORK(&ar->set_coverage_class_work,
3353 ath10k_core_set_coverage_class_work);
3354
3355 init_dummy_netdev(&ar->napi_dev);
3356
3357 ret = ath10k_coredump_create(ar);
3358 if (ret)
3359 goto err_free_tx_complete;
3360
3361 ret = ath10k_debug_create(ar);
3362 if (ret)
3363 goto err_free_coredump;
3364
3365 return ar;
3366
3367 err_free_coredump:
3368 ath10k_coredump_destroy(ar);
3369 err_free_tx_complete:
3370 destroy_workqueue(ar->workqueue_tx_complete);
3371 err_free_aux_wq:
3372 destroy_workqueue(ar->workqueue_aux);
3373 err_free_wq:
3374 destroy_workqueue(ar->workqueue);
3375 err_free_mac:
3376 ath10k_mac_destroy(ar);
3377
3378 return NULL;
3379 }
3380 EXPORT_SYMBOL(ath10k_core_create);
3381
ath10k_core_destroy(struct ath10k * ar)3382 void ath10k_core_destroy(struct ath10k *ar)
3383 {
3384 flush_workqueue(ar->workqueue);
3385 destroy_workqueue(ar->workqueue);
3386
3387 flush_workqueue(ar->workqueue_aux);
3388 destroy_workqueue(ar->workqueue_aux);
3389
3390 flush_workqueue(ar->workqueue_tx_complete);
3391 destroy_workqueue(ar->workqueue_tx_complete);
3392
3393 ath10k_debug_destroy(ar);
3394 ath10k_coredump_destroy(ar);
3395 ath10k_htt_tx_destroy(&ar->htt);
3396 ath10k_wmi_free_host_mem(ar);
3397 ath10k_mac_destroy(ar);
3398 }
3399 EXPORT_SYMBOL(ath10k_core_destroy);
3400
3401 MODULE_AUTHOR("Qualcomm Atheros");
3402 MODULE_DESCRIPTION("Core module for Qualcomm Atheros 802.11ac wireless LAN cards.");
3403 MODULE_LICENSE("Dual BSD/GPL");
3404