| /drivers/gpu/drm/amd/pm/swsmu/smu12/ |
| D | renoir_ppt.c | 177 static int renoir_get_dpm_clk_limited(struct smu_context *smu, enum smu_clk_type clk_type, in renoir_get_dpm_clk_limited()
245 enum smu_clk_type clk_type, in renoir_get_dpm_ultimate_freq()
348 enum smu_clk_type clk_type, char *buf) in renoir_print_clk_levels()
497 enum smu_clk_type clk_type, in renoir_get_current_clk_freq_by_table()
522 enum smu_clk_type clk_type; in renoir_force_dpm_limit_value() local
549 enum smu_clk_type clk_type; in renoir_unforce_dpm_levels() local
552 enum smu_clk_type clk_type; in renoir_unforce_dpm_levels() member
695 enum smu_clk_type clk_type, uint32_t mask) in renoir_force_clk_levels()
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| D | smu_v12_0.c | 207 int smu_v12_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type, in smu_v12_0_set_soft_freq_limited_range()
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| /drivers/clk/imx/ |
| D | clk-scu.h | 18 u8 clk_type) in imx_clk_scu()
24 int num_parents, u32 rsrc_id, u8 clk_type) in imx_clk_scu2()
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| D | clk-scu.c | 29 u8 clk_type; member
348 int num_parents, u32 rsrc_id, u8 clk_type) in __imx_clk_scu()
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| /drivers/gpu/drm/amd/pm/swsmu/smu11/ |
| D | smu_v11_0.c | 1015 enum amd_pp_clock_type clk_type = clock_req->clock_type; in smu_v11_0_display_clock_voltage_request() local
1581 int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type, in smu_v11_0_get_dpm_ultimate_freq()
1641 enum smu_clk_type clk_type, in smu_v11_0_set_soft_freq_limited_range()
1685 enum smu_clk_type clk_type, in smu_v11_0_set_hard_freq_limited_range()
1842 enum smu_clk_type clk_type, in smu_v11_0_get_dpm_freq_by_index()
1880 enum smu_clk_type clk_type, in smu_v11_0_get_dpm_level_count()
1890 enum smu_clk_type clk_type, in smu_v11_0_set_single_dpm_table()
1928 enum smu_clk_type clk_type, in smu_v11_0_get_dpm_level_range()
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| D | sienna_cichlid_ppt.c | 869 enum smu_clk_type clk_type, in sienna_cichlid_get_current_clk_freq_by_table()
919 …ool sienna_cichlid_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type) in sienna_cichlid_is_support_fine_grained_dpm()
935 enum smu_clk_type clk_type, char *buf) in sienna_cichlid_print_clk_levels()
1034 enum smu_clk_type clk_type, uint32_t mask) in sienna_cichlid_force_clk_levels()
1747 enum smu_clk_type clk_type, in sienna_cichlid_get_dpm_ultimate_freq()
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| D | navi10_ppt.c | 863 enum smu_clk_type clk_type, in navi10_get_current_clk_freq_by_table()
903 static bool navi10_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type) in navi10_is_support_fine_grained_dpm()
934 enum smu_clk_type clk_type, char *buf) in navi10_print_clk_levels()
1113 enum smu_clk_type clk_type, uint32_t mask) in navi10_force_clk_levels()
1250 enum smu_clk_type clk_type, in navi10_get_clock_by_type_with_latency()
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| D | arcturus_ppt.c | 662 enum smu_clk_type clk_type, in arcturus_get_current_clk_freq_by_table()
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| /drivers/gpu/drm/amd/display/amdgpu_dm/ |
| D | amdgpu_dm_pp_smu.c | 120 enum dm_pp_clock_type clk_type, in get_default_clock_levels()
333 enum dm_pp_clock_type clk_type, in dm_pp_get_clock_levels_by_type()
419 enum dm_pp_clock_type clk_type, in dm_pp_get_clock_levels_by_type_with_latency()
449 enum dm_pp_clock_type clk_type, in dm_pp_get_clock_levels_by_type_with_voltage()
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| /drivers/gpu/drm/amd/pm/swsmu/ |
| D | amdgpu_smu.c | 94 enum smu_clk_type clk_type, in smu_set_soft_freq_range()
114 enum smu_clk_type clk_type, in smu_get_dpm_freq_range()
1701 enum smu_clk_type clk_type, in smu_force_clk_levels()
2020 int smu_print_clk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf) in smu_print_clk_levels()
2344 enum smu_clk_type clk_type, in smu_get_clock_by_type_with_latency()
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| D | smu_cmn.c | 293 enum smu_clk_type clk_type) in smu_cmn_clk_dpm_is_enabled()
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| /drivers/nfc/s3fwrn5/ |
| D | nci.h | 64 __u8 clk_type; member
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| /drivers/phy/ |
| D | phy-xgene.c | 534 enum clk_type_t clk_type; /* Input clock selection */ member
705 enum clk_type_t clk_type) in xgene_phy_cfg_cmu_clk_type()
759 enum clk_type_t clk_type) in xgene_phy_sata_cfg_cmu_core()
1135 enum clk_type_t clk_type) in xgene_phy_cal_rdy_chk()
1235 enum clk_type_t clk_type) in xgene_phy_pdwn_force_vco()
1252 enum clk_type_t clk_type, int ssc_enable) in xgene_phy_hw_init_sata()
1316 enum clk_type_t clk_type, in xgene_phy_hw_initialize()
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| /drivers/gpu/drm/amd/display/dc/ |
| D | dm_services_types.h | 82 #define DC_DECODE_PP_CLOCK_TYPE(clk_type) \ argument
254 enum dm_pp_clock_type clk_type; member
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| /drivers/input/ |
| D | evdev.c | 49 enum input_clock_type clk_type; member
177 enum input_clock_type clk_type; in evdev_set_clk_type() local
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| /drivers/gpu/drm/amd/amdgpu/ |
| D | atombios_crtc.c | 527 u32 freq, u8 clk_type, u8 clk_src) in amdgpu_atombios_crtc_set_dce_clock()
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| /drivers/clk/zynqmp/ |
| D | clkc.c | 42 enum clk_type { enum
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| /drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| D | smu10_hwmgr.c | 55 enum amd_pp_clock_type clk_type = clock_req->clock_type; in smu10_display_clock_voltage_request() local
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| D | vega12_hwmgr.c | 1548 enum amd_pp_clock_type clk_type = clock_req->clock_type; in vega12_display_clock_voltage_request() local
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| D | vega20_hwmgr.c | 2292 enum amd_pp_clock_type clk_type = clock_req->clock_type; in vega20_display_clock_voltage_request() local
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| D | vega10_hwmgr.c | 3977 enum amd_pp_clock_type clk_type = clock_req->clock_type; in vega10_display_clock_voltage_request() local
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| /drivers/media/dvb-frontends/ |
| D | mxl5xx.c | 1391 u32 clk_type = 0; in config_ts() local
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| /drivers/clk/ |
| D | clk-u300.c | 878 u32 clk_type; in of_u300_syscon_clk_init() local
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| /drivers/video/fbdev/aty/ |
| D | atyfb_base.c | 2363 u8 dac_type, dac_subtype, clk_type; in aty_init() local
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