1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2018, Intel Corporation. */
3
4 #ifndef _ICE_TYPE_H_
5 #define _ICE_TYPE_H_
6
7 #define ICE_BYTES_PER_WORD 2
8 #define ICE_BYTES_PER_DWORD 4
9
10 #include "ice_status.h"
11 #include "ice_hw_autogen.h"
12 #include "ice_osdep.h"
13 #include "ice_controlq.h"
14 #include "ice_lan_tx_rx.h"
15 #include "ice_flex_type.h"
16 #include "ice_protocol_type.h"
17
ice_is_tc_ena(unsigned long bitmap,u8 tc)18 static inline bool ice_is_tc_ena(unsigned long bitmap, u8 tc)
19 {
20 return test_bit(tc, &bitmap);
21 }
22
round_up_64bit(u64 a,u32 b)23 static inline u64 round_up_64bit(u64 a, u32 b)
24 {
25 return div64_long(((a) + (b) / 2), (b));
26 }
27
ice_round_to_num(u32 N,u32 R)28 static inline u32 ice_round_to_num(u32 N, u32 R)
29 {
30 return ((((N) % (R)) < ((R) / 2)) ? (((N) / (R)) * (R)) :
31 ((((N) + (R) - 1) / (R)) * (R)));
32 }
33
34 /* Driver always calls main vsi_handle first */
35 #define ICE_MAIN_VSI_HANDLE 0
36
37 /* debug masks - set these bits in hw->debug_mask to control output */
38 #define ICE_DBG_INIT BIT_ULL(1)
39 #define ICE_DBG_FW_LOG BIT_ULL(3)
40 #define ICE_DBG_LINK BIT_ULL(4)
41 #define ICE_DBG_PHY BIT_ULL(5)
42 #define ICE_DBG_QCTX BIT_ULL(6)
43 #define ICE_DBG_NVM BIT_ULL(7)
44 #define ICE_DBG_LAN BIT_ULL(8)
45 #define ICE_DBG_FLOW BIT_ULL(9)
46 #define ICE_DBG_SW BIT_ULL(13)
47 #define ICE_DBG_SCHED BIT_ULL(14)
48 #define ICE_DBG_PKG BIT_ULL(16)
49 #define ICE_DBG_RES BIT_ULL(17)
50 #define ICE_DBG_AQ_MSG BIT_ULL(24)
51 #define ICE_DBG_AQ_DESC BIT_ULL(25)
52 #define ICE_DBG_AQ_DESC_BUF BIT_ULL(26)
53 #define ICE_DBG_AQ_CMD BIT_ULL(27)
54 #define ICE_DBG_USER BIT_ULL(31)
55
56 enum ice_aq_res_ids {
57 ICE_NVM_RES_ID = 1,
58 ICE_SPD_RES_ID,
59 ICE_CHANGE_LOCK_RES_ID,
60 ICE_GLOBAL_CFG_LOCK_RES_ID
61 };
62
63 /* FW update timeout definitions are in milliseconds */
64 #define ICE_NVM_TIMEOUT 180000
65 #define ICE_CHANGE_LOCK_TIMEOUT 1000
66 #define ICE_GLOBAL_CFG_LOCK_TIMEOUT 5000
67
68 enum ice_aq_res_access_type {
69 ICE_RES_READ = 1,
70 ICE_RES_WRITE
71 };
72
73 struct ice_driver_ver {
74 u8 major_ver;
75 u8 minor_ver;
76 u8 build_ver;
77 u8 subbuild_ver;
78 u8 driver_string[32];
79 };
80
81 enum ice_fc_mode {
82 ICE_FC_NONE = 0,
83 ICE_FC_RX_PAUSE,
84 ICE_FC_TX_PAUSE,
85 ICE_FC_FULL,
86 ICE_FC_PFC,
87 ICE_FC_DFLT
88 };
89
90 enum ice_phy_cache_mode {
91 ICE_FC_MODE = 0,
92 ICE_SPEED_MODE,
93 ICE_FEC_MODE
94 };
95
96 enum ice_fec_mode {
97 ICE_FEC_NONE = 0,
98 ICE_FEC_RS,
99 ICE_FEC_BASER,
100 ICE_FEC_AUTO
101 };
102
103 struct ice_phy_cache_mode_data {
104 union {
105 enum ice_fec_mode curr_user_fec_req;
106 enum ice_fc_mode curr_user_fc_req;
107 u16 curr_user_speed_req;
108 } data;
109 };
110
111 enum ice_set_fc_aq_failures {
112 ICE_SET_FC_AQ_FAIL_NONE = 0,
113 ICE_SET_FC_AQ_FAIL_GET,
114 ICE_SET_FC_AQ_FAIL_SET,
115 ICE_SET_FC_AQ_FAIL_UPDATE
116 };
117
118 /* Various MAC types */
119 enum ice_mac_type {
120 ICE_MAC_UNKNOWN = 0,
121 ICE_MAC_E810,
122 ICE_MAC_GENERIC,
123 };
124
125 /* Media Types */
126 enum ice_media_type {
127 ICE_MEDIA_UNKNOWN = 0,
128 ICE_MEDIA_FIBER,
129 ICE_MEDIA_BASET,
130 ICE_MEDIA_BACKPLANE,
131 ICE_MEDIA_DA,
132 };
133
134 enum ice_vsi_type {
135 ICE_VSI_PF = 0,
136 ICE_VSI_VF = 1,
137 ICE_VSI_CTRL = 3, /* equates to ICE_VSI_PF with 1 queue pair */
138 ICE_VSI_LB = 6,
139 };
140
141 struct ice_link_status {
142 /* Refer to ice_aq_phy_type for bits definition */
143 u64 phy_type_low;
144 u64 phy_type_high;
145 u8 topo_media_conflict;
146 u16 max_frame_size;
147 u16 link_speed;
148 u16 req_speeds;
149 u8 lse_ena; /* Link Status Event notification */
150 u8 link_info;
151 u8 an_info;
152 u8 ext_info;
153 u8 fec_info;
154 u8 pacing;
155 /* Refer to #define from module_type[ICE_MODULE_TYPE_TOTAL_BYTE] of
156 * ice_aqc_get_phy_caps structure
157 */
158 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE];
159 };
160
161 /* Different reset sources for which a disable queue AQ call has to be made in
162 * order to clean the Tx scheduler as a part of the reset
163 */
164 enum ice_disq_rst_src {
165 ICE_NO_RESET = 0,
166 ICE_VM_RESET,
167 ICE_VF_RESET,
168 };
169
170 /* PHY info such as phy_type, etc... */
171 struct ice_phy_info {
172 struct ice_link_status link_info;
173 struct ice_link_status link_info_old;
174 u64 phy_type_low;
175 u64 phy_type_high;
176 enum ice_media_type media_type;
177 u8 get_link_info;
178 /* Please refer to struct ice_aqc_get_link_status_data to get
179 * detail of enable bit in curr_user_speed_req
180 */
181 u16 curr_user_speed_req;
182 enum ice_fec_mode curr_user_fec_req;
183 enum ice_fc_mode curr_user_fc_req;
184 struct ice_aqc_set_phy_cfg_data curr_user_phy_cfg;
185 };
186
187 /* protocol enumeration for filters */
188 enum ice_fltr_ptype {
189 /* NONE - used for undef/error */
190 ICE_FLTR_PTYPE_NONF_NONE = 0,
191 ICE_FLTR_PTYPE_NONF_IPV4_UDP,
192 ICE_FLTR_PTYPE_NONF_IPV4_TCP,
193 ICE_FLTR_PTYPE_NONF_IPV4_SCTP,
194 ICE_FLTR_PTYPE_NONF_IPV4_OTHER,
195 ICE_FLTR_PTYPE_FRAG_IPV4,
196 ICE_FLTR_PTYPE_NONF_IPV6_UDP,
197 ICE_FLTR_PTYPE_NONF_IPV6_TCP,
198 ICE_FLTR_PTYPE_NONF_IPV6_SCTP,
199 ICE_FLTR_PTYPE_NONF_IPV6_OTHER,
200 ICE_FLTR_PTYPE_MAX,
201 };
202
203 enum ice_fd_hw_seg {
204 ICE_FD_HW_SEG_NON_TUN = 0,
205 ICE_FD_HW_SEG_TUN,
206 ICE_FD_HW_SEG_MAX,
207 };
208
209 /* 2 VSI = 1 ICE_VSI_PF + 1 ICE_VSI_CTRL */
210 #define ICE_MAX_FDIR_VSI_PER_FILTER 2
211
212 struct ice_fd_hw_prof {
213 struct ice_flow_seg_info *fdir_seg[ICE_FD_HW_SEG_MAX];
214 int cnt;
215 u64 entry_h[ICE_MAX_FDIR_VSI_PER_FILTER][ICE_FD_HW_SEG_MAX];
216 u16 vsi_h[ICE_MAX_FDIR_VSI_PER_FILTER];
217 };
218
219 /* Common HW capabilities for SW use */
220 struct ice_hw_common_caps {
221 u32 valid_functions;
222 /* DCB capabilities */
223 u32 active_tc_bitmap;
224 u32 maxtc;
225
226 /* Tx/Rx queues */
227 u16 num_rxq; /* Number/Total Rx queues */
228 u16 rxq_first_id; /* First queue ID for Rx queues */
229 u16 num_txq; /* Number/Total Tx queues */
230 u16 txq_first_id; /* First queue ID for Tx queues */
231
232 /* MSI-X vectors */
233 u16 num_msix_vectors;
234 u16 msix_vector_first_id;
235
236 /* Max MTU for function or device */
237 u16 max_mtu;
238
239 /* Virtualization support */
240 u8 sr_iov_1_1; /* SR-IOV enabled */
241
242 /* RSS related capabilities */
243 u16 rss_table_size; /* 512 for PFs and 64 for VFs */
244 u8 rss_table_entry_width; /* RSS Entry width in bits */
245
246 u8 dcb;
247
248 bool nvm_update_pending_nvm;
249 bool nvm_update_pending_orom;
250 bool nvm_update_pending_netlist;
251 #define ICE_NVM_PENDING_NVM_IMAGE BIT(0)
252 #define ICE_NVM_PENDING_OROM BIT(1)
253 #define ICE_NVM_PENDING_NETLIST BIT(2)
254 bool nvm_unified_update;
255 #define ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT BIT(3)
256 };
257
258 /* Function specific capabilities */
259 struct ice_hw_func_caps {
260 struct ice_hw_common_caps common_cap;
261 u32 num_allocd_vfs; /* Number of allocated VFs */
262 u32 vf_base_id; /* Logical ID of the first VF */
263 u32 guar_num_vsi;
264 u32 fd_fltr_guar; /* Number of filters guaranteed */
265 u32 fd_fltr_best_effort; /* Number of best effort filters */
266 };
267
268 /* Device wide capabilities */
269 struct ice_hw_dev_caps {
270 struct ice_hw_common_caps common_cap;
271 u32 num_vfs_exposed; /* Total number of VFs exposed */
272 u32 num_vsi_allocd_to_host; /* Excluding EMP VSI */
273 u32 num_flow_director_fltr; /* Number of FD filters available */
274 u32 num_funcs;
275 };
276
277 /* MAC info */
278 struct ice_mac_info {
279 u8 lan_addr[ETH_ALEN];
280 u8 perm_addr[ETH_ALEN];
281 };
282
283 /* Reset types used to determine which kind of reset was requested. These
284 * defines match what the RESET_TYPE field of the GLGEN_RSTAT register.
285 * ICE_RESET_PFR does not match any RESET_TYPE field in the GLGEN_RSTAT register
286 * because its reset source is different than the other types listed.
287 */
288 enum ice_reset_req {
289 ICE_RESET_POR = 0,
290 ICE_RESET_INVAL = 0,
291 ICE_RESET_CORER = 1,
292 ICE_RESET_GLOBR = 2,
293 ICE_RESET_EMPR = 3,
294 ICE_RESET_PFR = 4,
295 };
296
297 /* Bus parameters */
298 struct ice_bus_info {
299 u16 device;
300 u8 func;
301 };
302
303 /* Flow control (FC) parameters */
304 struct ice_fc_info {
305 enum ice_fc_mode current_mode; /* FC mode in effect */
306 enum ice_fc_mode req_mode; /* FC mode requested by caller */
307 };
308
309 /* Option ROM version information */
310 struct ice_orom_info {
311 u8 major; /* Major version of OROM */
312 u8 patch; /* Patch version of OROM */
313 u16 build; /* Build version of OROM */
314 };
315
316 /* NVM Information */
317 struct ice_nvm_info {
318 struct ice_orom_info orom; /* Option ROM version info */
319 u32 eetrack; /* NVM data version */
320 u16 sr_words; /* Shadow RAM size in words */
321 u32 flash_size; /* Size of available flash in bytes */
322 u8 major_ver; /* major version of NVM package */
323 u8 minor_ver; /* minor version of dev starter */
324 u8 blank_nvm_mode; /* is NVM empty (no FW present) */
325 };
326
327 struct ice_link_default_override_tlv {
328 u8 options;
329 #define ICE_LINK_OVERRIDE_OPT_M 0x3F
330 #define ICE_LINK_OVERRIDE_STRICT_MODE BIT(0)
331 #define ICE_LINK_OVERRIDE_EPCT_DIS BIT(1)
332 #define ICE_LINK_OVERRIDE_PORT_DIS BIT(2)
333 #define ICE_LINK_OVERRIDE_EN BIT(3)
334 #define ICE_LINK_OVERRIDE_AUTO_LINK_DIS BIT(4)
335 #define ICE_LINK_OVERRIDE_EEE_EN BIT(5)
336 u8 phy_config;
337 #define ICE_LINK_OVERRIDE_PHY_CFG_S 8
338 #define ICE_LINK_OVERRIDE_PHY_CFG_M (0xC3 << ICE_LINK_OVERRIDE_PHY_CFG_S)
339 #define ICE_LINK_OVERRIDE_PAUSE_M 0x3
340 #define ICE_LINK_OVERRIDE_LESM_EN BIT(6)
341 #define ICE_LINK_OVERRIDE_AUTO_FEC_EN BIT(7)
342 u8 fec_options;
343 #define ICE_LINK_OVERRIDE_FEC_OPT_M 0xFF
344 u8 rsvd1;
345 u64 phy_type_low;
346 u64 phy_type_high;
347 };
348
349 #define ICE_NVM_VER_LEN 32
350
351 /* netlist version information */
352 struct ice_netlist_ver_info {
353 u32 major; /* major high/low */
354 u32 minor; /* minor high/low */
355 u32 type; /* type high/low */
356 u32 rev; /* revision high/low */
357 u32 hash; /* SHA-1 hash word */
358 u16 cust_ver; /* customer version */
359 };
360
361 /* Max number of port to queue branches w.r.t topology */
362 #define ICE_MAX_TRAFFIC_CLASS 8
363 #define ICE_TXSCHED_MAX_BRANCHES ICE_MAX_TRAFFIC_CLASS
364
365 #define ice_for_each_traffic_class(_i) \
366 for ((_i) = 0; (_i) < ICE_MAX_TRAFFIC_CLASS; (_i)++)
367
368 #define ICE_INVAL_TEID 0xFFFFFFFF
369
370 struct ice_sched_node {
371 struct ice_sched_node *parent;
372 struct ice_sched_node *sibling; /* next sibling in the same layer */
373 struct ice_sched_node **children;
374 struct ice_aqc_txsched_elem_data info;
375 u32 agg_id; /* aggregator group ID */
376 u16 vsi_handle;
377 u8 in_use; /* suspended or in use */
378 u8 tx_sched_layer; /* Logical Layer (1-9) */
379 u8 num_children;
380 u8 tc_num;
381 u8 owner;
382 #define ICE_SCHED_NODE_OWNER_LAN 0
383 };
384
385 /* Access Macros for Tx Sched Elements data */
386 #define ICE_TXSCHED_GET_NODE_TEID(x) le32_to_cpu((x)->info.node_teid)
387
388 /* The aggregator type determines if identifier is for a VSI group,
389 * aggregator group, aggregator of queues, or queue group.
390 */
391 enum ice_agg_type {
392 ICE_AGG_TYPE_UNKNOWN = 0,
393 ICE_AGG_TYPE_VSI,
394 ICE_AGG_TYPE_AGG, /* aggregator */
395 ICE_AGG_TYPE_Q,
396 ICE_AGG_TYPE_QG
397 };
398
399 /* Rate limit types */
400 enum ice_rl_type {
401 ICE_UNKNOWN_BW = 0,
402 ICE_MIN_BW, /* for CIR profile */
403 ICE_MAX_BW, /* for EIR profile */
404 ICE_SHARED_BW /* for shared profile */
405 };
406
407 #define ICE_SCHED_MIN_BW 500 /* in Kbps */
408 #define ICE_SCHED_MAX_BW 100000000 /* in Kbps */
409 #define ICE_SCHED_DFLT_BW 0xFFFFFFFF /* unlimited */
410 #define ICE_SCHED_DFLT_RL_PROF_ID 0
411 #define ICE_SCHED_NO_SHARED_RL_PROF_ID 0xFFFF
412 #define ICE_SCHED_DFLT_BW_WT 4
413 #define ICE_SCHED_INVAL_PROF_ID 0xFFFF
414 #define ICE_SCHED_DFLT_BURST_SIZE (15 * 1024) /* in bytes (15k) */
415
416 /* Data structure for saving BW information */
417 enum ice_bw_type {
418 ICE_BW_TYPE_PRIO,
419 ICE_BW_TYPE_CIR,
420 ICE_BW_TYPE_CIR_WT,
421 ICE_BW_TYPE_EIR,
422 ICE_BW_TYPE_EIR_WT,
423 ICE_BW_TYPE_SHARED,
424 ICE_BW_TYPE_CNT /* This must be last */
425 };
426
427 struct ice_bw {
428 u32 bw;
429 u16 bw_alloc;
430 };
431
432 struct ice_bw_type_info {
433 DECLARE_BITMAP(bw_t_bitmap, ICE_BW_TYPE_CNT);
434 u8 generic;
435 struct ice_bw cir_bw;
436 struct ice_bw eir_bw;
437 u32 shared_bw;
438 };
439
440 /* VSI queue context structure for given TC */
441 struct ice_q_ctx {
442 u16 q_handle;
443 u32 q_teid;
444 /* bw_t_info saves queue BW information */
445 struct ice_bw_type_info bw_t_info;
446 };
447
448 /* VSI type list entry to locate corresponding VSI/aggregator nodes */
449 struct ice_sched_vsi_info {
450 struct ice_sched_node *vsi_node[ICE_MAX_TRAFFIC_CLASS];
451 struct ice_sched_node *ag_node[ICE_MAX_TRAFFIC_CLASS];
452 struct list_head list_entry;
453 u16 max_lanq[ICE_MAX_TRAFFIC_CLASS];
454 };
455
456 /* driver defines the policy */
457 struct ice_sched_tx_policy {
458 u16 max_num_vsis;
459 u8 max_num_lan_qs_per_tc[ICE_MAX_TRAFFIC_CLASS];
460 u8 rdma_ena;
461 };
462
463 /* CEE or IEEE 802.1Qaz ETS Configuration data */
464 struct ice_dcb_ets_cfg {
465 u8 willing;
466 u8 cbs;
467 u8 maxtcs;
468 u8 prio_table[ICE_MAX_TRAFFIC_CLASS];
469 u8 tcbwtable[ICE_MAX_TRAFFIC_CLASS];
470 u8 tsatable[ICE_MAX_TRAFFIC_CLASS];
471 };
472
473 /* CEE or IEEE 802.1Qaz PFC Configuration data */
474 struct ice_dcb_pfc_cfg {
475 u8 willing;
476 u8 mbc;
477 u8 pfccap;
478 u8 pfcena;
479 };
480
481 /* CEE or IEEE 802.1Qaz Application Priority data */
482 struct ice_dcb_app_priority_table {
483 u16 prot_id;
484 u8 priority;
485 u8 selector;
486 };
487
488 #define ICE_MAX_USER_PRIORITY 8
489 #define ICE_DCBX_MAX_APPS 32
490 #define ICE_LLDPDU_SIZE 1500
491 #define ICE_TLV_STATUS_OPER 0x1
492 #define ICE_TLV_STATUS_SYNC 0x2
493 #define ICE_TLV_STATUS_ERR 0x4
494 #define ICE_APP_PROT_ID_FCOE 0x8906
495 #define ICE_APP_PROT_ID_ISCSI 0x0cbc
496 #define ICE_APP_PROT_ID_ISCSI_860 0x035c
497 #define ICE_APP_PROT_ID_FIP 0x8914
498 #define ICE_APP_SEL_ETHTYPE 0x1
499 #define ICE_APP_SEL_TCPIP 0x2
500 #define ICE_CEE_APP_SEL_ETHTYPE 0x0
501 #define ICE_SR_LINK_DEFAULT_OVERRIDE_PTR 0x134
502 #define ICE_CEE_APP_SEL_TCPIP 0x1
503
504 struct ice_dcbx_cfg {
505 u32 numapps;
506 u32 tlv_status; /* CEE mode TLV status */
507 struct ice_dcb_ets_cfg etscfg;
508 struct ice_dcb_ets_cfg etsrec;
509 struct ice_dcb_pfc_cfg pfc;
510 struct ice_dcb_app_priority_table app[ICE_DCBX_MAX_APPS];
511 u8 dcbx_mode;
512 #define ICE_DCBX_MODE_CEE 0x1
513 #define ICE_DCBX_MODE_IEEE 0x2
514 u8 app_mode;
515 #define ICE_DCBX_APPS_NON_WILLING 0x1
516 };
517
518 struct ice_qos_cfg {
519 struct ice_dcbx_cfg local_dcbx_cfg; /* Oper/Local Cfg */
520 struct ice_dcbx_cfg desired_dcbx_cfg; /* CEE Desired Cfg */
521 struct ice_dcbx_cfg remote_dcbx_cfg; /* Peer Cfg */
522 u8 dcbx_status : 3; /* see ICE_DCBX_STATUS_DIS */
523 u8 is_sw_lldp : 1;
524 };
525
526 struct ice_port_info {
527 struct ice_sched_node *root; /* Root Node per Port */
528 struct ice_hw *hw; /* back pointer to HW instance */
529 u32 last_node_teid; /* scheduler last node info */
530 u16 sw_id; /* Initial switch ID belongs to port */
531 u16 pf_vf_num;
532 u8 port_state;
533 #define ICE_SCHED_PORT_STATE_INIT 0x0
534 #define ICE_SCHED_PORT_STATE_READY 0x1
535 u8 lport;
536 #define ICE_LPORT_MASK 0xff
537 u16 dflt_tx_vsi_rule_id;
538 u16 dflt_tx_vsi_num;
539 u16 dflt_rx_vsi_rule_id;
540 u16 dflt_rx_vsi_num;
541 struct ice_fc_info fc;
542 struct ice_mac_info mac;
543 struct ice_phy_info phy;
544 struct mutex sched_lock; /* protect access to TXSched tree */
545 struct ice_sched_node *
546 sib_head[ICE_MAX_TRAFFIC_CLASS][ICE_AQC_TOPO_MAX_LEVEL_NUM];
547 /* List contain profile ID(s) and other params per layer */
548 struct list_head rl_prof_list[ICE_AQC_TOPO_MAX_LEVEL_NUM];
549 struct ice_qos_cfg qos_cfg;
550 u8 is_vf:1;
551 };
552
553 struct ice_switch_info {
554 struct list_head vsi_list_map_head;
555 struct ice_sw_recipe *recp_list;
556 };
557
558 /* FW logging configuration */
559 struct ice_fw_log_evnt {
560 u8 cfg : 4; /* New event enables to configure */
561 u8 cur : 4; /* Current/active event enables */
562 };
563
564 struct ice_fw_log_cfg {
565 u8 cq_en : 1; /* FW logging is enabled via the control queue */
566 u8 uart_en : 1; /* FW logging is enabled via UART for all PFs */
567 u8 actv_evnts; /* Cumulation of currently enabled log events */
568
569 #define ICE_FW_LOG_EVNT_INFO (ICE_AQC_FW_LOG_INFO_EN >> ICE_AQC_FW_LOG_EN_S)
570 #define ICE_FW_LOG_EVNT_INIT (ICE_AQC_FW_LOG_INIT_EN >> ICE_AQC_FW_LOG_EN_S)
571 #define ICE_FW_LOG_EVNT_FLOW (ICE_AQC_FW_LOG_FLOW_EN >> ICE_AQC_FW_LOG_EN_S)
572 #define ICE_FW_LOG_EVNT_ERR (ICE_AQC_FW_LOG_ERR_EN >> ICE_AQC_FW_LOG_EN_S)
573 struct ice_fw_log_evnt evnts[ICE_AQC_FW_LOG_ID_MAX];
574 };
575
576 /* Port hardware description */
577 struct ice_hw {
578 u8 __iomem *hw_addr;
579 void *back;
580 struct ice_aqc_layer_props *layer_info;
581 struct ice_port_info *port_info;
582 u64 debug_mask; /* bitmap for debug mask */
583 enum ice_mac_type mac_type;
584
585 u16 fd_ctr_base; /* FD counter base index */
586
587 /* pci info */
588 u16 device_id;
589 u16 vendor_id;
590 u16 subsystem_device_id;
591 u16 subsystem_vendor_id;
592 u8 revision_id;
593
594 u8 pf_id; /* device profile info */
595
596 u16 max_burst_size; /* driver sets this value */
597
598 /* Tx Scheduler values */
599 u8 num_tx_sched_layers;
600 u8 num_tx_sched_phys_layers;
601 u8 flattened_layers;
602 u8 max_cgds;
603 u8 sw_entry_point_layer;
604 u16 max_children[ICE_AQC_TOPO_MAX_LEVEL_NUM];
605 struct list_head agg_list; /* lists all aggregator */
606
607 struct ice_vsi_ctx *vsi_ctx[ICE_MAX_VSI];
608 u8 evb_veb; /* true for VEB, false for VEPA */
609 u8 reset_ongoing; /* true if HW is in reset, false otherwise */
610 struct ice_bus_info bus;
611 struct ice_nvm_info nvm;
612 struct ice_hw_dev_caps dev_caps; /* device capabilities */
613 struct ice_hw_func_caps func_caps; /* function capabilities */
614 struct ice_netlist_ver_info netlist_ver; /* netlist version info */
615
616 struct ice_switch_info *switch_info; /* switch filter lists */
617
618 /* Control Queue info */
619 struct ice_ctl_q_info adminq;
620 struct ice_ctl_q_info mailboxq;
621
622 u8 api_branch; /* API branch version */
623 u8 api_maj_ver; /* API major version */
624 u8 api_min_ver; /* API minor version */
625 u8 api_patch; /* API patch version */
626 u8 fw_branch; /* firmware branch version */
627 u8 fw_maj_ver; /* firmware major version */
628 u8 fw_min_ver; /* firmware minor version */
629 u8 fw_patch; /* firmware patch version */
630 u32 fw_build; /* firmware build number */
631
632 struct ice_fw_log_cfg fw_log;
633
634 /* Device max aggregate bandwidths corresponding to the GL_PWR_MODE_CTL
635 * register. Used for determining the ITR/INTRL granularity during
636 * initialization.
637 */
638 #define ICE_MAX_AGG_BW_200G 0x0
639 #define ICE_MAX_AGG_BW_100G 0X1
640 #define ICE_MAX_AGG_BW_50G 0x2
641 #define ICE_MAX_AGG_BW_25G 0x3
642 /* ITR granularity for different speeds */
643 #define ICE_ITR_GRAN_ABOVE_25 2
644 #define ICE_ITR_GRAN_MAX_25 4
645 /* ITR granularity in 1 us */
646 u8 itr_gran;
647 /* INTRL granularity for different speeds */
648 #define ICE_INTRL_GRAN_ABOVE_25 4
649 #define ICE_INTRL_GRAN_MAX_25 8
650 /* INTRL granularity in 1 us */
651 u8 intrl_gran;
652
653 u8 ucast_shared; /* true if VSIs can share unicast addr */
654
655 /* Active package version (currently active) */
656 struct ice_pkg_ver active_pkg_ver;
657 u32 active_track_id;
658 u8 active_pkg_name[ICE_PKG_NAME_SIZE];
659 u8 active_pkg_in_nvm;
660
661 enum ice_aq_err pkg_dwnld_status;
662
663 /* Driver's package ver - (from the Metadata seg) */
664 struct ice_pkg_ver pkg_ver;
665 u8 pkg_name[ICE_PKG_NAME_SIZE];
666
667 /* Driver's Ice package version (from the Ice seg) */
668 struct ice_pkg_ver ice_pkg_ver;
669 u8 ice_pkg_name[ICE_PKG_NAME_SIZE];
670
671 /* Pointer to the ice segment */
672 struct ice_seg *seg;
673
674 /* Pointer to allocated copy of pkg memory */
675 u8 *pkg_copy;
676 u32 pkg_size;
677
678 /* tunneling info */
679 struct mutex tnl_lock;
680 struct ice_tunnel_table tnl;
681
682 struct udp_tunnel_nic_shared udp_tunnel_shared;
683 struct udp_tunnel_nic_info udp_tunnel_nic;
684
685 /* HW block tables */
686 struct ice_blk_info blk[ICE_BLK_COUNT];
687 struct mutex fl_profs_locks[ICE_BLK_COUNT]; /* lock fltr profiles */
688 struct list_head fl_profs[ICE_BLK_COUNT];
689
690 /* Flow Director filter info */
691 int fdir_active_fltr;
692
693 struct mutex fdir_fltr_lock; /* protect Flow Director */
694 struct list_head fdir_list_head;
695
696 /* Book-keeping of side-band filter count per flow-type.
697 * This is used to detect and handle input set changes for
698 * respective flow-type.
699 */
700 u16 fdir_fltr_cnt[ICE_FLTR_PTYPE_MAX];
701
702 struct ice_fd_hw_prof **fdir_prof;
703 DECLARE_BITMAP(fdir_perfect_fltr, ICE_FLTR_PTYPE_MAX);
704 struct mutex rss_locks; /* protect RSS configuration */
705 struct list_head rss_list_head;
706 };
707
708 /* Statistics collected by each port, VSI, VEB, and S-channel */
709 struct ice_eth_stats {
710 u64 rx_bytes; /* gorc */
711 u64 rx_unicast; /* uprc */
712 u64 rx_multicast; /* mprc */
713 u64 rx_broadcast; /* bprc */
714 u64 rx_discards; /* rdpc */
715 u64 rx_unknown_protocol; /* rupp */
716 u64 tx_bytes; /* gotc */
717 u64 tx_unicast; /* uptc */
718 u64 tx_multicast; /* mptc */
719 u64 tx_broadcast; /* bptc */
720 u64 tx_discards; /* tdpc */
721 u64 tx_errors; /* tepc */
722 };
723
724 #define ICE_MAX_UP 8
725
726 /* Statistics collected by the MAC */
727 struct ice_hw_port_stats {
728 /* eth stats collected by the port */
729 struct ice_eth_stats eth;
730 /* additional port specific stats */
731 u64 tx_dropped_link_down; /* tdold */
732 u64 crc_errors; /* crcerrs */
733 u64 illegal_bytes; /* illerrc */
734 u64 error_bytes; /* errbc */
735 u64 mac_local_faults; /* mlfc */
736 u64 mac_remote_faults; /* mrfc */
737 u64 rx_len_errors; /* rlec */
738 u64 link_xon_rx; /* lxonrxc */
739 u64 link_xoff_rx; /* lxoffrxc */
740 u64 link_xon_tx; /* lxontxc */
741 u64 link_xoff_tx; /* lxofftxc */
742 u64 priority_xon_rx[8]; /* pxonrxc[8] */
743 u64 priority_xoff_rx[8]; /* pxoffrxc[8] */
744 u64 priority_xon_tx[8]; /* pxontxc[8] */
745 u64 priority_xoff_tx[8]; /* pxofftxc[8] */
746 u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */
747 u64 rx_size_64; /* prc64 */
748 u64 rx_size_127; /* prc127 */
749 u64 rx_size_255; /* prc255 */
750 u64 rx_size_511; /* prc511 */
751 u64 rx_size_1023; /* prc1023 */
752 u64 rx_size_1522; /* prc1522 */
753 u64 rx_size_big; /* prc9522 */
754 u64 rx_undersize; /* ruc */
755 u64 rx_fragments; /* rfc */
756 u64 rx_oversize; /* roc */
757 u64 rx_jabber; /* rjc */
758 u64 tx_size_64; /* ptc64 */
759 u64 tx_size_127; /* ptc127 */
760 u64 tx_size_255; /* ptc255 */
761 u64 tx_size_511; /* ptc511 */
762 u64 tx_size_1023; /* ptc1023 */
763 u64 tx_size_1522; /* ptc1522 */
764 u64 tx_size_big; /* ptc9522 */
765 /* flow director stats */
766 u32 fd_sb_status;
767 u64 fd_sb_match;
768 };
769
770 /* Checksum and Shadow RAM pointers */
771 #define ICE_SR_BOOT_CFG_PTR 0x132
772 #define ICE_SR_NVM_WOL_CFG 0x19
773 #define ICE_NVM_OROM_VER_OFF 0x02
774 #define ICE_SR_PBA_BLOCK_PTR 0x16
775 #define ICE_SR_NVM_DEV_STARTER_VER 0x18
776 #define ICE_SR_NVM_EETRACK_LO 0x2D
777 #define ICE_SR_NVM_EETRACK_HI 0x2E
778 #define ICE_NVM_VER_LO_SHIFT 0
779 #define ICE_NVM_VER_LO_MASK (0xff << ICE_NVM_VER_LO_SHIFT)
780 #define ICE_NVM_VER_HI_SHIFT 12
781 #define ICE_NVM_VER_HI_MASK (0xf << ICE_NVM_VER_HI_SHIFT)
782 #define ICE_OROM_VER_PATCH_SHIFT 0
783 #define ICE_OROM_VER_PATCH_MASK (0xff << ICE_OROM_VER_PATCH_SHIFT)
784 #define ICE_OROM_VER_BUILD_SHIFT 8
785 #define ICE_OROM_VER_BUILD_MASK (0xffff << ICE_OROM_VER_BUILD_SHIFT)
786 #define ICE_OROM_VER_SHIFT 24
787 #define ICE_OROM_VER_MASK (0xff << ICE_OROM_VER_SHIFT)
788 #define ICE_SR_PFA_PTR 0x40
789 #define ICE_SR_1ST_NVM_BANK_PTR 0x42
790 #define ICE_SR_1ST_OROM_BANK_PTR 0x44
791 #define ICE_SR_NETLIST_BANK_PTR 0x46
792 #define ICE_SR_SECTOR_SIZE_IN_WORDS 0x800
793
794 /* Link override related */
795 #define ICE_SR_PFA_LINK_OVERRIDE_WORDS 10
796 #define ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS 4
797 #define ICE_SR_PFA_LINK_OVERRIDE_OFFSET 2
798 #define ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET 1
799 #define ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET 2
800 #define ICE_FW_API_LINK_OVERRIDE_MAJ 1
801 #define ICE_FW_API_LINK_OVERRIDE_MIN 5
802 #define ICE_FW_API_LINK_OVERRIDE_PATCH 2
803
804 #define ICE_SR_WORDS_IN_1KB 512
805
806 /* Hash redirection LUT for VSI - maximum array size */
807 #define ICE_VSIQF_HLUT_ARRAY_SIZE ((VSIQF_HLUT_MAX_INDEX + 1) * 4)
808
809 #endif /* _ICE_TYPE_H_ */
810