1 /*
2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
23 * IN THE SOFTWARE.
24 */
25
26 #ifndef __INTEL_DISPLAY_TYPES_H__
27 #define __INTEL_DISPLAY_TYPES_H__
28
29 #include <linux/async.h>
30 #include <linux/i2c.h>
31 #include <linux/pwm.h>
32 #include <linux/sched/clock.h>
33
34 #include <drm/drm_atomic.h>
35 #include <drm/drm_crtc.h>
36 #include <drm/drm_dp_dual_mode_helper.h>
37 #include <drm/drm_dp_mst_helper.h>
38 #include <drm/drm_encoder.h>
39 #include <drm/drm_fb_helper.h>
40 #include <drm/drm_probe_helper.h>
41 #include <drm/drm_rect.h>
42 #include <drm/drm_vblank.h>
43 #include <drm/i915_mei_hdcp_interface.h>
44 #include <media/cec-notifier.h>
45
46 #include "i915_drv.h"
47 #include "intel_de.h"
48
49 struct drm_printer;
50 struct __intel_global_objs_state;
51
52 /*
53 * Display related stuff
54 */
55
56 /* these are outputs from the chip - integrated only
57 external chips are via DVO or SDVO output */
58 enum intel_output_type {
59 INTEL_OUTPUT_UNUSED = 0,
60 INTEL_OUTPUT_ANALOG = 1,
61 INTEL_OUTPUT_DVO = 2,
62 INTEL_OUTPUT_SDVO = 3,
63 INTEL_OUTPUT_LVDS = 4,
64 INTEL_OUTPUT_TVOUT = 5,
65 INTEL_OUTPUT_HDMI = 6,
66 INTEL_OUTPUT_DP = 7,
67 INTEL_OUTPUT_EDP = 8,
68 INTEL_OUTPUT_DSI = 9,
69 INTEL_OUTPUT_DDI = 10,
70 INTEL_OUTPUT_DP_MST = 11,
71 };
72
73 enum hdmi_force_audio {
74 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
75 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
76 HDMI_AUDIO_AUTO, /* trust EDID */
77 HDMI_AUDIO_ON, /* force turn on HDMI audio */
78 };
79
80 /* "Broadcast RGB" property */
81 enum intel_broadcast_rgb {
82 INTEL_BROADCAST_RGB_AUTO,
83 INTEL_BROADCAST_RGB_FULL,
84 INTEL_BROADCAST_RGB_LIMITED,
85 };
86
87 struct intel_framebuffer {
88 struct drm_framebuffer base;
89 struct intel_frontbuffer *frontbuffer;
90 struct intel_rotation_info rot_info;
91
92 /* for each plane in the normal GTT view */
93 struct {
94 unsigned int x, y;
95 } normal[4];
96 /* for each plane in the rotated GTT view for no-CCS formats */
97 struct {
98 unsigned int x, y;
99 unsigned int pitch; /* pixels */
100 } rotated[2];
101 };
102
103 struct intel_fbdev {
104 struct drm_fb_helper helper;
105 struct intel_framebuffer *fb;
106 struct i915_vma *vma;
107 unsigned long vma_flags;
108 async_cookie_t cookie;
109 int preferred_bpp;
110
111 /* Whether or not fbdev hpd processing is temporarily suspended */
112 bool hpd_suspended : 1;
113 /* Set when a hotplug was received while HPD processing was
114 * suspended
115 */
116 bool hpd_waiting : 1;
117
118 /* Protects hpd_suspended */
119 struct mutex hpd_lock;
120 };
121
122 enum intel_hotplug_state {
123 INTEL_HOTPLUG_UNCHANGED,
124 INTEL_HOTPLUG_CHANGED,
125 INTEL_HOTPLUG_RETRY,
126 };
127
128 struct intel_encoder {
129 struct drm_encoder base;
130
131 enum intel_output_type type;
132 enum port port;
133 u16 cloneable;
134 u8 pipe_mask;
135 enum intel_hotplug_state (*hotplug)(struct intel_encoder *encoder,
136 struct intel_connector *connector);
137 enum intel_output_type (*compute_output_type)(struct intel_encoder *,
138 struct intel_crtc_state *,
139 struct drm_connector_state *);
140 int (*compute_config)(struct intel_encoder *,
141 struct intel_crtc_state *,
142 struct drm_connector_state *);
143 int (*compute_config_late)(struct intel_encoder *,
144 struct intel_crtc_state *,
145 struct drm_connector_state *);
146 void (*update_prepare)(struct intel_atomic_state *,
147 struct intel_encoder *,
148 struct intel_crtc *);
149 void (*pre_pll_enable)(struct intel_atomic_state *,
150 struct intel_encoder *,
151 const struct intel_crtc_state *,
152 const struct drm_connector_state *);
153 void (*pre_enable)(struct intel_atomic_state *,
154 struct intel_encoder *,
155 const struct intel_crtc_state *,
156 const struct drm_connector_state *);
157 void (*enable)(struct intel_atomic_state *,
158 struct intel_encoder *,
159 const struct intel_crtc_state *,
160 const struct drm_connector_state *);
161 void (*update_complete)(struct intel_atomic_state *,
162 struct intel_encoder *,
163 struct intel_crtc *);
164 void (*disable)(struct intel_atomic_state *,
165 struct intel_encoder *,
166 const struct intel_crtc_state *,
167 const struct drm_connector_state *);
168 void (*post_disable)(struct intel_atomic_state *,
169 struct intel_encoder *,
170 const struct intel_crtc_state *,
171 const struct drm_connector_state *);
172 void (*post_pll_disable)(struct intel_atomic_state *,
173 struct intel_encoder *,
174 const struct intel_crtc_state *,
175 const struct drm_connector_state *);
176 void (*update_pipe)(struct intel_atomic_state *,
177 struct intel_encoder *,
178 const struct intel_crtc_state *,
179 const struct drm_connector_state *);
180 /* Read out the current hw state of this connector, returning true if
181 * the encoder is active. If the encoder is enabled it also set the pipe
182 * it is connected to in the pipe parameter. */
183 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
184 /* Reconstructs the equivalent mode flags for the current hardware
185 * state. This must be called _after_ display->get_pipe_config has
186 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
187 * be set correctly before calling this function. */
188 void (*get_config)(struct intel_encoder *,
189 struct intel_crtc_state *pipe_config);
190 /*
191 * Acquires the power domains needed for an active encoder during
192 * hardware state readout.
193 */
194 void (*get_power_domains)(struct intel_encoder *encoder,
195 struct intel_crtc_state *crtc_state);
196 /*
197 * Called during system suspend after all pending requests for the
198 * encoder are flushed (for example for DP AUX transactions) and
199 * device interrupts are disabled.
200 */
201 void (*suspend)(struct intel_encoder *);
202 enum hpd_pin hpd_pin;
203 enum intel_display_power_domain power_domain;
204 /* for communication with audio component; protected by av_mutex */
205 const struct drm_connector *audio_connector;
206 };
207
208 struct intel_panel {
209 struct drm_display_mode *fixed_mode;
210 struct drm_display_mode *downclock_mode;
211
212 /* backlight */
213 struct {
214 bool present;
215 u32 level;
216 u32 min;
217 u32 max;
218 bool enabled;
219 bool combination_mode; /* gen 2/4 only */
220 bool active_low_pwm;
221 bool alternate_pwm_increment; /* lpt+ */
222
223 /* PWM chip */
224 bool util_pin_active_low; /* bxt+ */
225 u8 controller; /* bxt+ only */
226 struct pwm_device *pwm;
227 struct pwm_state pwm_state;
228
229 /* DPCD backlight */
230 u8 pwmgen_bit_count;
231
232 struct backlight_device *device;
233
234 /* Connector and platform specific backlight functions */
235 int (*setup)(struct intel_connector *connector, enum pipe pipe);
236 u32 (*get)(struct intel_connector *connector);
237 void (*set)(const struct drm_connector_state *conn_state, u32 level);
238 void (*disable)(const struct drm_connector_state *conn_state);
239 void (*enable)(const struct intel_crtc_state *crtc_state,
240 const struct drm_connector_state *conn_state);
241 u32 (*hz_to_pwm)(struct intel_connector *connector, u32 hz);
242 void (*power)(struct intel_connector *, bool enable);
243 } backlight;
244 };
245
246 struct intel_digital_port;
247
248 enum check_link_response {
249 HDCP_LINK_PROTECTED = 0,
250 HDCP_TOPOLOGY_CHANGE,
251 HDCP_LINK_INTEGRITY_FAILURE,
252 HDCP_REAUTH_REQUEST
253 };
254
255 /*
256 * This structure serves as a translation layer between the generic HDCP code
257 * and the bus-specific code. What that means is that HDCP over HDMI differs
258 * from HDCP over DP, so to account for these differences, we need to
259 * communicate with the receiver through this shim.
260 *
261 * For completeness, the 2 buses differ in the following ways:
262 * - DP AUX vs. DDC
263 * HDCP registers on the receiver are set via DP AUX for DP, and
264 * they are set via DDC for HDMI.
265 * - Receiver register offsets
266 * The offsets of the registers are different for DP vs. HDMI
267 * - Receiver register masks/offsets
268 * For instance, the ready bit for the KSV fifo is in a different
269 * place on DP vs HDMI
270 * - Receiver register names
271 * Seriously. In the DP spec, the 16-bit register containing
272 * downstream information is called BINFO, on HDMI it's called
273 * BSTATUS. To confuse matters further, DP has a BSTATUS register
274 * with a completely different definition.
275 * - KSV FIFO
276 * On HDMI, the ksv fifo is read all at once, whereas on DP it must
277 * be read 3 keys at a time
278 * - Aksv output
279 * Since Aksv is hidden in hardware, there's different procedures
280 * to send it over DP AUX vs DDC
281 */
282 struct intel_hdcp_shim {
283 /* Outputs the transmitter's An and Aksv values to the receiver. */
284 int (*write_an_aksv)(struct intel_digital_port *dig_port, u8 *an);
285
286 /* Reads the receiver's key selection vector */
287 int (*read_bksv)(struct intel_digital_port *dig_port, u8 *bksv);
288
289 /*
290 * Reads BINFO from DP receivers and BSTATUS from HDMI receivers. The
291 * definitions are the same in the respective specs, but the names are
292 * different. Call it BSTATUS since that's the name the HDMI spec
293 * uses and it was there first.
294 */
295 int (*read_bstatus)(struct intel_digital_port *dig_port,
296 u8 *bstatus);
297
298 /* Determines whether a repeater is present downstream */
299 int (*repeater_present)(struct intel_digital_port *dig_port,
300 bool *repeater_present);
301
302 /* Reads the receiver's Ri' value */
303 int (*read_ri_prime)(struct intel_digital_port *dig_port, u8 *ri);
304
305 /* Determines if the receiver's KSV FIFO is ready for consumption */
306 int (*read_ksv_ready)(struct intel_digital_port *dig_port,
307 bool *ksv_ready);
308
309 /* Reads the ksv fifo for num_downstream devices */
310 int (*read_ksv_fifo)(struct intel_digital_port *dig_port,
311 int num_downstream, u8 *ksv_fifo);
312
313 /* Reads a 32-bit part of V' from the receiver */
314 int (*read_v_prime_part)(struct intel_digital_port *dig_port,
315 int i, u32 *part);
316
317 /* Enables HDCP signalling on the port */
318 int (*toggle_signalling)(struct intel_digital_port *dig_port,
319 enum transcoder cpu_transcoder,
320 bool enable);
321
322 /* Ensures the link is still protected */
323 bool (*check_link)(struct intel_digital_port *dig_port,
324 struct intel_connector *connector);
325
326 /* Detects panel's hdcp capability. This is optional for HDMI. */
327 int (*hdcp_capable)(struct intel_digital_port *dig_port,
328 bool *hdcp_capable);
329
330 /* HDCP adaptation(DP/HDMI) required on the port */
331 enum hdcp_wired_protocol protocol;
332
333 /* Detects whether sink is HDCP2.2 capable */
334 int (*hdcp_2_2_capable)(struct intel_digital_port *dig_port,
335 bool *capable);
336
337 /* Write HDCP2.2 messages */
338 int (*write_2_2_msg)(struct intel_digital_port *dig_port,
339 void *buf, size_t size);
340
341 /* Read HDCP2.2 messages */
342 int (*read_2_2_msg)(struct intel_digital_port *dig_port,
343 u8 msg_id, void *buf, size_t size);
344
345 /*
346 * Implementation of DP HDCP2.2 Errata for the communication of stream
347 * type to Receivers. In DP HDCP2.2 Stream type is one of the input to
348 * the HDCP2.2 Cipher for En/De-Cryption. Not applicable for HDMI.
349 */
350 int (*config_stream_type)(struct intel_digital_port *dig_port,
351 bool is_repeater, u8 type);
352
353 /* HDCP2.2 Link Integrity Check */
354 int (*check_2_2_link)(struct intel_digital_port *dig_port);
355 };
356
357 struct intel_hdcp {
358 const struct intel_hdcp_shim *shim;
359 /* Mutex for hdcp state of the connector */
360 struct mutex mutex;
361 u64 value;
362 struct delayed_work check_work;
363 struct work_struct prop_work;
364
365 /* HDCP1.4 Encryption status */
366 bool hdcp_encrypted;
367
368 /* HDCP2.2 related definitions */
369 /* Flag indicates whether this connector supports HDCP2.2 or not. */
370 bool hdcp2_supported;
371
372 /* HDCP2.2 Encryption status */
373 bool hdcp2_encrypted;
374
375 /*
376 * Content Stream Type defined by content owner. TYPE0(0x0) content can
377 * flow in the link protected by HDCP2.2 or HDCP1.4, where as TYPE1(0x1)
378 * content can flow only through a link protected by HDCP2.2.
379 */
380 u8 content_type;
381 struct hdcp_port_data port_data;
382
383 bool is_paired;
384 bool is_repeater;
385
386 /*
387 * Count of ReceiverID_List received. Initialized to 0 at AKE_INIT.
388 * Incremented after processing the RepeaterAuth_Send_ReceiverID_List.
389 * When it rolls over re-auth has to be triggered.
390 */
391 u32 seq_num_v;
392
393 /*
394 * Count of RepeaterAuth_Stream_Manage msg propagated.
395 * Initialized to 0 on AKE_INIT. Incremented after every successful
396 * transmission of RepeaterAuth_Stream_Manage message. When it rolls
397 * over re-Auth has to be triggered.
398 */
399 u32 seq_num_m;
400
401 /*
402 * Work queue to signal the CP_IRQ. Used for the waiters to read the
403 * available information from HDCP DP sink.
404 */
405 wait_queue_head_t cp_irq_queue;
406 atomic_t cp_irq_count;
407 int cp_irq_count_cached;
408
409 /*
410 * HDCP register access for gen12+ need the transcoder associated.
411 * Transcoder attached to the connector could be changed at modeset.
412 * Hence caching the transcoder here.
413 */
414 enum transcoder cpu_transcoder;
415 };
416
417 struct intel_connector {
418 struct drm_connector base;
419 /*
420 * The fixed encoder this connector is connected to.
421 */
422 struct intel_encoder *encoder;
423
424 /* ACPI device id for ACPI and driver cooperation */
425 u32 acpi_device_id;
426
427 /* Reads out the current hw, returning true if the connector is enabled
428 * and active (i.e. dpms ON state). */
429 bool (*get_hw_state)(struct intel_connector *);
430
431 /* Panel info for eDP and LVDS */
432 struct intel_panel panel;
433
434 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
435 struct edid *edid;
436 struct edid *detect_edid;
437
438 /* Number of times hotplug detection was tried after an HPD interrupt */
439 int hotplug_retries;
440
441 /* since POLL and HPD connectors may use the same HPD line keep the native
442 state of connector->polled in case hotplug storm detection changes it */
443 u8 polled;
444
445 struct drm_dp_mst_port *port;
446
447 struct intel_dp *mst_port;
448
449 /* Work struct to schedule a uevent on link train failure */
450 struct work_struct modeset_retry_work;
451
452 struct intel_hdcp hdcp;
453 };
454
455 struct intel_digital_connector_state {
456 struct drm_connector_state base;
457
458 enum hdmi_force_audio force_audio;
459 int broadcast_rgb;
460 };
461
462 #define to_intel_digital_connector_state(x) container_of(x, struct intel_digital_connector_state, base)
463
464 struct dpll {
465 /* given values */
466 int n;
467 int m1, m2;
468 int p1, p2;
469 /* derived values */
470 int dot;
471 int vco;
472 int m;
473 int p;
474 };
475
476 struct intel_atomic_state {
477 struct drm_atomic_state base;
478
479 intel_wakeref_t wakeref;
480
481 struct __intel_global_objs_state *global_objs;
482 int num_global_objs;
483
484 bool dpll_set, modeset;
485
486 struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];
487
488 /*
489 * Current watermarks can't be trusted during hardware readout, so
490 * don't bother calculating intermediate watermarks.
491 */
492 bool skip_intermediate_wm;
493
494 bool rps_interactive;
495
496 struct i915_sw_fence commit_ready;
497
498 struct llist_node freed;
499 };
500
501 struct intel_plane_state {
502 struct drm_plane_state uapi;
503
504 /*
505 * actual hardware state, the state we program to the hardware.
506 * The following members are used to verify the hardware state:
507 * During initial hw readout, they need to be copied from uapi.
508 */
509 struct {
510 struct drm_crtc *crtc;
511 struct drm_framebuffer *fb;
512
513 u16 alpha;
514 uint16_t pixel_blend_mode;
515 unsigned int rotation;
516 enum drm_color_encoding color_encoding;
517 enum drm_color_range color_range;
518 } hw;
519
520 struct i915_ggtt_view view;
521 struct i915_vma *vma;
522 unsigned long flags;
523 #define PLANE_HAS_FENCE BIT(0)
524
525 struct {
526 u32 offset;
527 /*
528 * Plane stride in:
529 * bytes for 0/180 degree rotation
530 * pixels for 90/270 degree rotation
531 */
532 u32 stride;
533 int x, y;
534 } color_plane[4];
535
536 /* plane control register */
537 u32 ctl;
538
539 /* plane color control register */
540 u32 color_ctl;
541
542 /* chroma upsampler control register */
543 u32 cus_ctl;
544
545 /*
546 * scaler_id
547 * = -1 : not using a scaler
548 * >= 0 : using a scalers
549 *
550 * plane requiring a scaler:
551 * - During check_plane, its bit is set in
552 * crtc_state->scaler_state.scaler_users by calling helper function
553 * update_scaler_plane.
554 * - scaler_id indicates the scaler it got assigned.
555 *
556 * plane doesn't require a scaler:
557 * - this can happen when scaling is no more required or plane simply
558 * got disabled.
559 * - During check_plane, corresponding bit is reset in
560 * crtc_state->scaler_state.scaler_users by calling helper function
561 * update_scaler_plane.
562 */
563 int scaler_id;
564
565 /*
566 * planar_linked_plane:
567 *
568 * ICL planar formats require 2 planes that are updated as pairs.
569 * This member is used to make sure the other plane is also updated
570 * when required, and for update_slave() to find the correct
571 * plane_state to pass as argument.
572 */
573 struct intel_plane *planar_linked_plane;
574
575 /*
576 * planar_slave:
577 * If set don't update use the linked plane's state for updating
578 * this plane during atomic commit with the update_slave() callback.
579 *
580 * It's also used by the watermark code to ignore wm calculations on
581 * this plane. They're calculated by the linked plane's wm code.
582 */
583 u32 planar_slave;
584
585 struct drm_intel_sprite_colorkey ckey;
586 };
587
588 struct intel_initial_plane_config {
589 struct intel_framebuffer *fb;
590 struct i915_vma *vma;
591 unsigned int tiling;
592 int size;
593 u32 base;
594 u8 rotation;
595 };
596
597 struct intel_scaler {
598 int in_use;
599 u32 mode;
600 };
601
602 struct intel_crtc_scaler_state {
603 #define SKL_NUM_SCALERS 2
604 struct intel_scaler scalers[SKL_NUM_SCALERS];
605
606 /*
607 * scaler_users: keeps track of users requesting scalers on this crtc.
608 *
609 * If a bit is set, a user is using a scaler.
610 * Here user can be a plane or crtc as defined below:
611 * bits 0-30 - plane (bit position is index from drm_plane_index)
612 * bit 31 - crtc
613 *
614 * Instead of creating a new index to cover planes and crtc, using
615 * existing drm_plane_index for planes which is well less than 31
616 * planes and bit 31 for crtc. This should be fine to cover all
617 * our platforms.
618 *
619 * intel_atomic_setup_scalers will setup available scalers to users
620 * requesting scalers. It will gracefully fail if request exceeds
621 * avilability.
622 */
623 #define SKL_CRTC_INDEX 31
624 unsigned scaler_users;
625
626 /* scaler used by crtc for panel fitting purpose */
627 int scaler_id;
628 };
629
630 /* {crtc,crtc_state}->mode_flags */
631 /* Flag to get scanline using frame time stamps */
632 #define I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP (1<<1)
633 /* Flag to use the scanline counter instead of the pixel counter */
634 #define I915_MODE_FLAG_USE_SCANLINE_COUNTER (1<<2)
635 /*
636 * TE0 or TE1 flag is set if the crtc has a DSI encoder which
637 * is operating in command mode.
638 * Flag to use TE from DSI0 instead of VBI in command mode
639 */
640 #define I915_MODE_FLAG_DSI_USE_TE0 (1<<3)
641 /* Flag to use TE from DSI1 instead of VBI in command mode */
642 #define I915_MODE_FLAG_DSI_USE_TE1 (1<<4)
643 /* Flag to indicate mipi dsi periodic command mode where we do not get TE */
644 #define I915_MODE_FLAG_DSI_PERIODIC_CMD_MODE (1<<5)
645
646 struct intel_wm_level {
647 bool enable;
648 u32 pri_val;
649 u32 spr_val;
650 u32 cur_val;
651 u32 fbc_val;
652 };
653
654 struct intel_pipe_wm {
655 struct intel_wm_level wm[5];
656 bool fbc_wm_enabled;
657 bool pipe_enabled;
658 bool sprites_enabled;
659 bool sprites_scaled;
660 };
661
662 struct skl_wm_level {
663 u16 min_ddb_alloc;
664 u16 plane_res_b;
665 u8 plane_res_l;
666 bool plane_en;
667 bool ignore_lines;
668 };
669
670 struct skl_plane_wm {
671 struct skl_wm_level wm[8];
672 struct skl_wm_level uv_wm[8];
673 struct skl_wm_level trans_wm;
674 struct skl_wm_level sagv_wm0;
675 bool is_planar;
676 };
677
678 struct skl_pipe_wm {
679 struct skl_plane_wm planes[I915_MAX_PLANES];
680 bool use_sagv_wm;
681 };
682
683 enum vlv_wm_level {
684 VLV_WM_LEVEL_PM2,
685 VLV_WM_LEVEL_PM5,
686 VLV_WM_LEVEL_DDR_DVFS,
687 NUM_VLV_WM_LEVELS,
688 };
689
690 struct vlv_wm_state {
691 struct g4x_pipe_wm wm[NUM_VLV_WM_LEVELS];
692 struct g4x_sr_wm sr[NUM_VLV_WM_LEVELS];
693 u8 num_levels;
694 bool cxsr;
695 };
696
697 struct vlv_fifo_state {
698 u16 plane[I915_MAX_PLANES];
699 };
700
701 enum g4x_wm_level {
702 G4X_WM_LEVEL_NORMAL,
703 G4X_WM_LEVEL_SR,
704 G4X_WM_LEVEL_HPLL,
705 NUM_G4X_WM_LEVELS,
706 };
707
708 struct g4x_wm_state {
709 struct g4x_pipe_wm wm;
710 struct g4x_sr_wm sr;
711 struct g4x_sr_wm hpll;
712 bool cxsr;
713 bool hpll_en;
714 bool fbc_en;
715 };
716
717 struct intel_crtc_wm_state {
718 union {
719 struct {
720 /*
721 * Intermediate watermarks; these can be
722 * programmed immediately since they satisfy
723 * both the current configuration we're
724 * switching away from and the new
725 * configuration we're switching to.
726 */
727 struct intel_pipe_wm intermediate;
728
729 /*
730 * Optimal watermarks, programmed post-vblank
731 * when this state is committed.
732 */
733 struct intel_pipe_wm optimal;
734 } ilk;
735
736 struct {
737 /* gen9+ only needs 1-step wm programming */
738 struct skl_pipe_wm optimal;
739 struct skl_ddb_entry ddb;
740 struct skl_ddb_entry plane_ddb_y[I915_MAX_PLANES];
741 struct skl_ddb_entry plane_ddb_uv[I915_MAX_PLANES];
742 } skl;
743
744 struct {
745 /* "raw" watermarks (not inverted) */
746 struct g4x_pipe_wm raw[NUM_VLV_WM_LEVELS];
747 /* intermediate watermarks (inverted) */
748 struct vlv_wm_state intermediate;
749 /* optimal watermarks (inverted) */
750 struct vlv_wm_state optimal;
751 /* display FIFO split */
752 struct vlv_fifo_state fifo_state;
753 } vlv;
754
755 struct {
756 /* "raw" watermarks */
757 struct g4x_pipe_wm raw[NUM_G4X_WM_LEVELS];
758 /* intermediate watermarks */
759 struct g4x_wm_state intermediate;
760 /* optimal watermarks */
761 struct g4x_wm_state optimal;
762 } g4x;
763 };
764
765 /*
766 * Platforms with two-step watermark programming will need to
767 * update watermark programming post-vblank to switch from the
768 * safe intermediate watermarks to the optimal final
769 * watermarks.
770 */
771 bool need_postvbl_update;
772 };
773
774 enum intel_output_format {
775 INTEL_OUTPUT_FORMAT_INVALID,
776 INTEL_OUTPUT_FORMAT_RGB,
777 INTEL_OUTPUT_FORMAT_YCBCR420,
778 INTEL_OUTPUT_FORMAT_YCBCR444,
779 };
780
781 struct intel_crtc_state {
782 /*
783 * uapi (drm) state. This is the software state shown to userspace.
784 * In particular, the following members are used for bookkeeping:
785 * - crtc
786 * - state
787 * - *_changed
788 * - event
789 * - commit
790 * - mode_blob
791 */
792 struct drm_crtc_state uapi;
793
794 /*
795 * actual hardware state, the state we program to the hardware.
796 * The following members are used to verify the hardware state:
797 * - enable
798 * - active
799 * - mode / adjusted_mode
800 * - color property blobs.
801 *
802 * During initial hw readout, they need to be copied to uapi.
803 */
804 struct {
805 bool active, enable;
806 struct drm_property_blob *degamma_lut, *gamma_lut, *ctm;
807 struct drm_display_mode mode, adjusted_mode;
808 } hw;
809
810 /**
811 * quirks - bitfield with hw state readout quirks
812 *
813 * For various reasons the hw state readout code might not be able to
814 * completely faithfully read out the current state. These cases are
815 * tracked with quirk flags so that fastboot and state checker can act
816 * accordingly.
817 */
818 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
819 unsigned long quirks;
820
821 unsigned fb_bits; /* framebuffers to flip */
822 bool update_pipe; /* can a fast modeset be performed? */
823 bool disable_cxsr;
824 bool update_wm_pre, update_wm_post; /* watermarks are updated */
825 bool fifo_changed; /* FIFO split is changed */
826 bool preload_luts;
827 bool inherited; /* state inherited from BIOS? */
828
829 /* Pipe source size (ie. panel fitter input size)
830 * All planes will be positioned inside this space,
831 * and get clipped at the edges. */
832 int pipe_src_w, pipe_src_h;
833
834 /*
835 * Pipe pixel rate, adjusted for
836 * panel fitter/pipe scaler downscaling.
837 */
838 unsigned int pixel_rate;
839
840 /* Whether to set up the PCH/FDI. Note that we never allow sharing
841 * between pch encoders and cpu encoders. */
842 bool has_pch_encoder;
843
844 /* Are we sending infoframes on the attached port */
845 bool has_infoframe;
846
847 /* CPU Transcoder for the pipe. Currently this can only differ from the
848 * pipe on Haswell and later (where we have a special eDP transcoder)
849 * and Broxton (where we have special DSI transcoders). */
850 enum transcoder cpu_transcoder;
851
852 /*
853 * Use reduced/limited/broadcast rbg range, compressing from the full
854 * range fed into the crtcs.
855 */
856 bool limited_color_range;
857
858 /* Bitmask of encoder types (enum intel_output_type)
859 * driven by the pipe.
860 */
861 unsigned int output_types;
862
863 /* Whether we should send NULL infoframes. Required for audio. */
864 bool has_hdmi_sink;
865
866 /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
867 * has_dp_encoder is set. */
868 bool has_audio;
869
870 /*
871 * Enable dithering, used when the selected pipe bpp doesn't match the
872 * plane bpp.
873 */
874 bool dither;
875
876 /*
877 * Dither gets enabled for 18bpp which causes CRC mismatch errors for
878 * compliance video pattern tests.
879 * Disable dither only if it is a compliance test request for
880 * 18bpp.
881 */
882 bool dither_force_disable;
883
884 /* Controls for the clock computation, to override various stages. */
885 bool clock_set;
886
887 /* SDVO TV has a bunch of special case. To make multifunction encoders
888 * work correctly, we need to track this at runtime.*/
889 bool sdvo_tv_clock;
890
891 /*
892 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
893 * required. This is set in the 2nd loop of calling encoder's
894 * ->compute_config if the first pick doesn't work out.
895 */
896 bool bw_constrained;
897
898 /* Settings for the intel dpll used on pretty much everything but
899 * haswell. */
900 struct dpll dpll;
901
902 /* Selected dpll when shared or NULL. */
903 struct intel_shared_dpll *shared_dpll;
904
905 /* Actual register state of the dpll, for shared dpll cross-checking. */
906 struct intel_dpll_hw_state dpll_hw_state;
907
908 /*
909 * ICL reserved DPLLs for the CRTC/port. The active PLL is selected by
910 * setting shared_dpll and dpll_hw_state to one of these reserved ones.
911 */
912 struct icl_port_dpll {
913 struct intel_shared_dpll *pll;
914 struct intel_dpll_hw_state hw_state;
915 } icl_port_dplls[ICL_PORT_DPLL_COUNT];
916
917 /* DSI PLL registers */
918 struct {
919 u32 ctrl, div;
920 } dsi_pll;
921
922 int pipe_bpp;
923 struct intel_link_m_n dp_m_n;
924
925 /* m2_n2 for eDP downclock */
926 struct intel_link_m_n dp_m2_n2;
927 bool has_drrs;
928
929 bool has_psr;
930 bool has_psr2;
931 bool enable_psr2_sel_fetch;
932 u32 dc3co_exitline;
933
934 /*
935 * Frequence the dpll for the port should run at. Differs from the
936 * adjusted dotclock e.g. for DP or 10/12bpc hdmi mode. This is also
937 * already multiplied by pixel_multiplier.
938 */
939 int port_clock;
940
941 /* Used by SDVO (and if we ever fix it, HDMI). */
942 unsigned pixel_multiplier;
943
944 /* I915_MODE_FLAG_* */
945 u8 mode_flags;
946
947 u8 lane_count;
948
949 /*
950 * Used by platforms having DP/HDMI PHY with programmable lane
951 * latency optimization.
952 */
953 u8 lane_lat_optim_mask;
954
955 /* minimum acceptable voltage level */
956 u8 min_voltage_level;
957
958 /* Panel fitter controls for gen2-gen4 + VLV */
959 struct {
960 u32 control;
961 u32 pgm_ratios;
962 u32 lvds_border_bits;
963 } gmch_pfit;
964
965 /* Panel fitter placement and size for Ironlake+ */
966 struct {
967 struct drm_rect dst;
968 bool enabled;
969 bool force_thru;
970 } pch_pfit;
971
972 /* FDI configuration, only valid if has_pch_encoder is set. */
973 int fdi_lanes;
974 struct intel_link_m_n fdi_m_n;
975
976 bool ips_enabled;
977
978 bool crc_enabled;
979
980 bool enable_fbc;
981
982 bool double_wide;
983
984 int pbn;
985
986 struct intel_crtc_scaler_state scaler_state;
987
988 /* w/a for waiting 2 vblanks during crtc enable */
989 enum pipe hsw_workaround_pipe;
990
991 /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
992 bool disable_lp_wm;
993
994 struct intel_crtc_wm_state wm;
995
996 int min_cdclk[I915_MAX_PLANES];
997
998 u32 data_rate[I915_MAX_PLANES];
999
1000 /* Gamma mode programmed on the pipe */
1001 u32 gamma_mode;
1002
1003 union {
1004 /* CSC mode programmed on the pipe */
1005 u32 csc_mode;
1006
1007 /* CHV CGM mode */
1008 u32 cgm_mode;
1009 };
1010
1011 /* bitmask of visible planes (enum plane_id) */
1012 u8 active_planes;
1013 u8 nv12_planes;
1014 u8 c8_planes;
1015
1016 /* bitmask of planes that will be updated during the commit */
1017 u8 update_planes;
1018
1019 struct {
1020 u32 enable;
1021 u32 gcp;
1022 union hdmi_infoframe avi;
1023 union hdmi_infoframe spd;
1024 union hdmi_infoframe hdmi;
1025 union hdmi_infoframe drm;
1026 struct drm_dp_vsc_sdp vsc;
1027 } infoframes;
1028
1029 /* HDMI scrambling status */
1030 bool hdmi_scrambling;
1031
1032 /* HDMI High TMDS char rate ratio */
1033 bool hdmi_high_tmds_clock_ratio;
1034
1035 /* Output format RGB/YCBCR etc */
1036 enum intel_output_format output_format;
1037
1038 /* Output down scaling is done in LSPCON device */
1039 bool lspcon_downsampling;
1040
1041 /* enable pipe gamma? */
1042 bool gamma_enable;
1043
1044 /* enable pipe csc? */
1045 bool csc_enable;
1046
1047 /* Display Stream compression state */
1048 struct {
1049 bool compression_enable;
1050 bool dsc_split;
1051 u16 compressed_bpp;
1052 u8 slice_count;
1053 struct drm_dsc_config config;
1054 } dsc;
1055
1056 /* HSW+ linetime watermarks */
1057 u16 linetime;
1058 u16 ips_linetime;
1059
1060 /* Forward Error correction State */
1061 bool fec_enable;
1062
1063 /* Pointer to master transcoder in case of tiled displays */
1064 enum transcoder master_transcoder;
1065
1066 /* Bitmask to indicate slaves attached */
1067 u8 sync_mode_slaves_mask;
1068
1069 /* Only valid on TGL+ */
1070 enum transcoder mst_master_transcoder;
1071
1072 /* For DSB related info */
1073 struct intel_dsb *dsb;
1074
1075 u32 psr2_man_track_ctl;
1076 };
1077
1078 enum intel_pipe_crc_source {
1079 INTEL_PIPE_CRC_SOURCE_NONE,
1080 INTEL_PIPE_CRC_SOURCE_PLANE1,
1081 INTEL_PIPE_CRC_SOURCE_PLANE2,
1082 INTEL_PIPE_CRC_SOURCE_PLANE3,
1083 INTEL_PIPE_CRC_SOURCE_PLANE4,
1084 INTEL_PIPE_CRC_SOURCE_PLANE5,
1085 INTEL_PIPE_CRC_SOURCE_PLANE6,
1086 INTEL_PIPE_CRC_SOURCE_PLANE7,
1087 INTEL_PIPE_CRC_SOURCE_PIPE,
1088 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1089 INTEL_PIPE_CRC_SOURCE_TV,
1090 INTEL_PIPE_CRC_SOURCE_DP_B,
1091 INTEL_PIPE_CRC_SOURCE_DP_C,
1092 INTEL_PIPE_CRC_SOURCE_DP_D,
1093 INTEL_PIPE_CRC_SOURCE_AUTO,
1094 INTEL_PIPE_CRC_SOURCE_MAX,
1095 };
1096
1097 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1098 struct intel_pipe_crc {
1099 spinlock_t lock;
1100 int skipped;
1101 enum intel_pipe_crc_source source;
1102 };
1103
1104 struct intel_crtc {
1105 struct drm_crtc base;
1106 enum pipe pipe;
1107 /*
1108 * Whether the crtc and the connected output pipeline is active. Implies
1109 * that crtc->enabled is set, i.e. the current mode configuration has
1110 * some outputs connected to this crtc.
1111 */
1112 bool active;
1113 u8 plane_ids_mask;
1114
1115 /* I915_MODE_FLAG_* */
1116 u8 mode_flags;
1117
1118 unsigned long long enabled_power_domains;
1119 struct intel_overlay *overlay;
1120
1121 struct intel_crtc_state *config;
1122
1123 /* Access to these should be protected by dev_priv->irq_lock. */
1124 bool cpu_fifo_underrun_disabled;
1125 bool pch_fifo_underrun_disabled;
1126
1127 /* per-pipe watermark state */
1128 struct {
1129 /* watermarks currently being used */
1130 union {
1131 struct intel_pipe_wm ilk;
1132 struct vlv_wm_state vlv;
1133 struct g4x_wm_state g4x;
1134 } active;
1135 } wm;
1136
1137 int scanline_offset;
1138
1139 struct {
1140 unsigned start_vbl_count;
1141 ktime_t start_vbl_time;
1142 int min_vbl, max_vbl;
1143 int scanline_start;
1144 } debug;
1145
1146 /* scalers available on this crtc */
1147 int num_scalers;
1148
1149 #ifdef CONFIG_DEBUG_FS
1150 struct intel_pipe_crc pipe_crc;
1151 #endif
1152 };
1153
1154 struct intel_plane {
1155 struct drm_plane base;
1156 enum i9xx_plane_id i9xx_plane;
1157 enum plane_id id;
1158 enum pipe pipe;
1159 bool has_fbc;
1160 bool has_ccs;
1161 u32 frontbuffer_bit;
1162
1163 struct {
1164 u32 base, cntl, size;
1165 } cursor;
1166
1167 /*
1168 * NOTE: Do not place new plane state fields here (e.g., when adding
1169 * new plane properties). New runtime state should now be placed in
1170 * the intel_plane_state structure and accessed via plane_state.
1171 */
1172
1173 unsigned int (*max_stride)(struct intel_plane *plane,
1174 u32 pixel_format, u64 modifier,
1175 unsigned int rotation);
1176 void (*update_plane)(struct intel_plane *plane,
1177 const struct intel_crtc_state *crtc_state,
1178 const struct intel_plane_state *plane_state);
1179 void (*disable_plane)(struct intel_plane *plane,
1180 const struct intel_crtc_state *crtc_state);
1181 bool (*get_hw_state)(struct intel_plane *plane, enum pipe *pipe);
1182 int (*check_plane)(struct intel_crtc_state *crtc_state,
1183 struct intel_plane_state *plane_state);
1184 int (*min_cdclk)(const struct intel_crtc_state *crtc_state,
1185 const struct intel_plane_state *plane_state);
1186 };
1187
1188 struct intel_watermark_params {
1189 u16 fifo_size;
1190 u16 max_wm;
1191 u8 default_wm;
1192 u8 guard_size;
1193 u8 cacheline_size;
1194 };
1195
1196 struct cxsr_latency {
1197 bool is_desktop : 1;
1198 bool is_ddr3 : 1;
1199 u16 fsb_freq;
1200 u16 mem_freq;
1201 u16 display_sr;
1202 u16 display_hpll_disable;
1203 u16 cursor_sr;
1204 u16 cursor_hpll_disable;
1205 };
1206
1207 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
1208 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
1209 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, uapi)
1210 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
1211 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
1212 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
1213 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
1214 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, uapi)
1215 #define intel_fb_obj(x) ((x) ? to_intel_bo((x)->obj[0]) : NULL)
1216
1217 struct intel_hdmi {
1218 i915_reg_t hdmi_reg;
1219 int ddc_bus;
1220 struct {
1221 enum drm_dp_dual_mode_type type;
1222 int max_tmds_clock;
1223 } dp_dual_mode;
1224 bool has_hdmi_sink;
1225 bool has_audio;
1226 struct intel_connector *attached_connector;
1227 struct cec_notifier *cec_notifier;
1228 };
1229
1230 struct intel_dp_mst_encoder;
1231 /*
1232 * enum link_m_n_set:
1233 * When platform provides two set of M_N registers for dp, we can
1234 * program them and switch between them incase of DRRS.
1235 * But When only one such register is provided, we have to program the
1236 * required divider value on that registers itself based on the DRRS state.
1237 *
1238 * M1_N1 : Program dp_m_n on M1_N1 registers
1239 * dp_m2_n2 on M2_N2 registers (If supported)
1240 *
1241 * M2_N2 : Program dp_m2_n2 on M1_N1 registers
1242 * M2_N2 registers are not supported
1243 */
1244
1245 enum link_m_n_set {
1246 /* Sets the m1_n1 and m2_n2 */
1247 M1_N1 = 0,
1248 M2_N2
1249 };
1250
1251 struct intel_dp_compliance_data {
1252 unsigned long edid;
1253 u8 video_pattern;
1254 u16 hdisplay, vdisplay;
1255 u8 bpc;
1256 struct drm_dp_phy_test_params phytest;
1257 };
1258
1259 struct intel_dp_compliance {
1260 unsigned long test_type;
1261 struct intel_dp_compliance_data test_data;
1262 bool test_active;
1263 int test_link_rate;
1264 u8 test_lane_count;
1265 };
1266
1267 struct intel_dp {
1268 i915_reg_t output_reg;
1269 u32 DP;
1270 int link_rate;
1271 u8 lane_count;
1272 u8 sink_count;
1273 bool link_mst;
1274 bool link_trained;
1275 bool has_hdmi_sink;
1276 bool has_audio;
1277 bool reset_link_params;
1278 u8 dpcd[DP_RECEIVER_CAP_SIZE];
1279 u8 psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
1280 u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
1281 u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
1282 u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE];
1283 u8 fec_capable;
1284 /* source rates */
1285 int num_source_rates;
1286 const int *source_rates;
1287 /* sink rates as reported by DP_MAX_LINK_RATE/DP_SUPPORTED_LINK_RATES */
1288 int num_sink_rates;
1289 int sink_rates[DP_MAX_SUPPORTED_RATES];
1290 bool use_rate_select;
1291 /* intersection of source and sink rates */
1292 int num_common_rates;
1293 int common_rates[DP_MAX_SUPPORTED_RATES];
1294 /* Max lane count for the current link */
1295 int max_link_lane_count;
1296 /* Max rate for the current link */
1297 int max_link_rate;
1298 /* sink or branch descriptor */
1299 struct drm_dp_desc desc;
1300 u32 edid_quirks;
1301 struct drm_dp_aux aux;
1302 u32 aux_busy_last_status;
1303 u8 train_set[4];
1304 int panel_power_up_delay;
1305 int panel_power_down_delay;
1306 int panel_power_cycle_delay;
1307 int backlight_on_delay;
1308 int backlight_off_delay;
1309 struct delayed_work panel_vdd_work;
1310 bool want_panel_vdd;
1311 unsigned long last_power_on;
1312 unsigned long last_backlight_off;
1313 ktime_t panel_power_off_time;
1314
1315 struct notifier_block edp_notifier;
1316
1317 /*
1318 * Pipe whose power sequencer is currently locked into
1319 * this port. Only relevant on VLV/CHV.
1320 */
1321 enum pipe pps_pipe;
1322 /*
1323 * Pipe currently driving the port. Used for preventing
1324 * the use of the PPS for any pipe currentrly driving
1325 * external DP as that will mess things up on VLV.
1326 */
1327 enum pipe active_pipe;
1328 /*
1329 * Set if the sequencer may be reset due to a power transition,
1330 * requiring a reinitialization. Only relevant on BXT.
1331 */
1332 bool pps_reset;
1333 struct edp_power_seq pps_delays;
1334
1335 bool can_mst; /* this port supports mst */
1336 bool is_mst;
1337 int active_mst_links;
1338
1339 /*
1340 * DP_TP_* registers may be either on port or transcoder register space.
1341 */
1342 struct {
1343 i915_reg_t dp_tp_ctl;
1344 i915_reg_t dp_tp_status;
1345 } regs;
1346
1347 /* connector directly attached - won't be use for modeset in mst world */
1348 struct intel_connector *attached_connector;
1349
1350 /* mst connector list */
1351 struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
1352 struct drm_dp_mst_topology_mgr mst_mgr;
1353
1354 u32 (*get_aux_clock_divider)(struct intel_dp *dp, int index);
1355 /*
1356 * This function returns the value we have to program the AUX_CTL
1357 * register with to kick off an AUX transaction.
1358 */
1359 u32 (*get_aux_send_ctl)(struct intel_dp *dp, int send_bytes,
1360 u32 aux_clock_divider);
1361
1362 i915_reg_t (*aux_ch_ctl_reg)(struct intel_dp *dp);
1363 i915_reg_t (*aux_ch_data_reg)(struct intel_dp *dp, int index);
1364
1365 /* This is called before a link training is starterd */
1366 void (*prepare_link_retrain)(struct intel_dp *intel_dp);
1367 void (*set_link_train)(struct intel_dp *intel_dp, u8 dp_train_pat);
1368 void (*set_idle_link_train)(struct intel_dp *intel_dp);
1369 void (*set_signal_levels)(struct intel_dp *intel_dp);
1370
1371 u8 (*preemph_max)(struct intel_dp *intel_dp);
1372 u8 (*voltage_max)(struct intel_dp *intel_dp);
1373
1374 /* Displayport compliance testing */
1375 struct intel_dp_compliance compliance;
1376
1377 /* Downstream facing port caps */
1378 struct {
1379 int min_tmds_clock, max_tmds_clock;
1380 int max_dotclock;
1381 u8 max_bpc;
1382 bool ycbcr_444_to_420;
1383 } dfp;
1384
1385 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1386 struct pm_qos_request pm_qos;
1387
1388 /* Display stream compression testing */
1389 bool force_dsc_en;
1390
1391 bool hobl_failed;
1392 bool hobl_active;
1393 };
1394
1395 enum lspcon_vendor {
1396 LSPCON_VENDOR_MCA,
1397 LSPCON_VENDOR_PARADE
1398 };
1399
1400 struct intel_lspcon {
1401 bool active;
1402 enum drm_lspcon_mode mode;
1403 enum lspcon_vendor vendor;
1404 };
1405
1406 struct intel_digital_port {
1407 struct intel_encoder base;
1408 u32 saved_port_bits;
1409 struct intel_dp dp;
1410 struct intel_hdmi hdmi;
1411 struct intel_lspcon lspcon;
1412 enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
1413 bool release_cl2_override;
1414 u8 max_lanes;
1415 /* Used for DP and ICL+ TypeC/DP and TypeC/HDMI ports. */
1416 enum aux_ch aux_ch;
1417 enum intel_display_power_domain ddi_io_power_domain;
1418 struct mutex tc_lock; /* protects the TypeC port mode */
1419 intel_wakeref_t tc_lock_wakeref;
1420 int tc_link_refcount;
1421 bool tc_legacy_port:1;
1422 char tc_port_name[8];
1423 enum tc_port_mode tc_mode;
1424 enum phy_fia tc_phy_fia;
1425 u8 tc_phy_fia_idx;
1426
1427 /* protects num_hdcp_streams reference count */
1428 struct mutex hdcp_mutex;
1429 /* the number of pipes using HDCP signalling out of this port */
1430 unsigned int num_hdcp_streams;
1431
1432 void (*write_infoframe)(struct intel_encoder *encoder,
1433 const struct intel_crtc_state *crtc_state,
1434 unsigned int type,
1435 const void *frame, ssize_t len);
1436 void (*read_infoframe)(struct intel_encoder *encoder,
1437 const struct intel_crtc_state *crtc_state,
1438 unsigned int type,
1439 void *frame, ssize_t len);
1440 void (*set_infoframes)(struct intel_encoder *encoder,
1441 bool enable,
1442 const struct intel_crtc_state *crtc_state,
1443 const struct drm_connector_state *conn_state);
1444 u32 (*infoframes_enabled)(struct intel_encoder *encoder,
1445 const struct intel_crtc_state *pipe_config);
1446 bool (*connected)(struct intel_encoder *encoder);
1447 };
1448
1449 struct intel_dp_mst_encoder {
1450 struct intel_encoder base;
1451 enum pipe pipe;
1452 struct intel_digital_port *primary;
1453 struct intel_connector *connector;
1454 };
1455
1456 static inline enum dpio_channel
vlv_dig_port_to_channel(struct intel_digital_port * dig_port)1457 vlv_dig_port_to_channel(struct intel_digital_port *dig_port)
1458 {
1459 switch (dig_port->base.port) {
1460 case PORT_B:
1461 case PORT_D:
1462 return DPIO_CH0;
1463 case PORT_C:
1464 return DPIO_CH1;
1465 default:
1466 BUG();
1467 }
1468 }
1469
1470 static inline enum dpio_phy
vlv_dig_port_to_phy(struct intel_digital_port * dig_port)1471 vlv_dig_port_to_phy(struct intel_digital_port *dig_port)
1472 {
1473 switch (dig_port->base.port) {
1474 case PORT_B:
1475 case PORT_C:
1476 return DPIO_PHY0;
1477 case PORT_D:
1478 return DPIO_PHY1;
1479 default:
1480 BUG();
1481 }
1482 }
1483
1484 static inline enum dpio_channel
vlv_pipe_to_channel(enum pipe pipe)1485 vlv_pipe_to_channel(enum pipe pipe)
1486 {
1487 switch (pipe) {
1488 case PIPE_A:
1489 case PIPE_C:
1490 return DPIO_CH0;
1491 case PIPE_B:
1492 return DPIO_CH1;
1493 default:
1494 BUG();
1495 }
1496 }
1497
1498 static inline struct intel_crtc *
intel_get_first_crtc(struct drm_i915_private * dev_priv)1499 intel_get_first_crtc(struct drm_i915_private *dev_priv)
1500 {
1501 return to_intel_crtc(drm_crtc_from_index(&dev_priv->drm, 0));
1502 }
1503
1504 static inline struct intel_crtc *
intel_get_crtc_for_pipe(struct drm_i915_private * dev_priv,enum pipe pipe)1505 intel_get_crtc_for_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
1506 {
1507 /* pipe_to_crtc_mapping may have hole on any of 3 display pipe system */
1508 drm_WARN_ON(&dev_priv->drm,
1509 !(INTEL_INFO(dev_priv)->pipe_mask & BIT(pipe)));
1510 return dev_priv->pipe_to_crtc_mapping[pipe];
1511 }
1512
1513 static inline struct intel_crtc *
intel_get_crtc_for_plane(struct drm_i915_private * dev_priv,enum i9xx_plane_id plane)1514 intel_get_crtc_for_plane(struct drm_i915_private *dev_priv, enum i9xx_plane_id plane)
1515 {
1516 return dev_priv->plane_to_crtc_mapping[plane];
1517 }
1518
1519 struct intel_load_detect_pipe {
1520 struct drm_atomic_state *restore_state;
1521 };
1522
1523 static inline struct intel_encoder *
intel_attached_encoder(struct intel_connector * connector)1524 intel_attached_encoder(struct intel_connector *connector)
1525 {
1526 return connector->encoder;
1527 }
1528
intel_encoder_is_dig_port(struct intel_encoder * encoder)1529 static inline bool intel_encoder_is_dig_port(struct intel_encoder *encoder)
1530 {
1531 switch (encoder->type) {
1532 case INTEL_OUTPUT_DDI:
1533 case INTEL_OUTPUT_DP:
1534 case INTEL_OUTPUT_EDP:
1535 case INTEL_OUTPUT_HDMI:
1536 return true;
1537 default:
1538 return false;
1539 }
1540 }
1541
intel_encoder_is_mst(struct intel_encoder * encoder)1542 static inline bool intel_encoder_is_mst(struct intel_encoder *encoder)
1543 {
1544 return encoder->type == INTEL_OUTPUT_DP_MST;
1545 }
1546
1547 static inline struct intel_dp_mst_encoder *
enc_to_mst(struct intel_encoder * encoder)1548 enc_to_mst(struct intel_encoder *encoder)
1549 {
1550 return container_of(&encoder->base, struct intel_dp_mst_encoder,
1551 base.base);
1552 }
1553
1554 static inline struct intel_digital_port *
enc_to_dig_port(struct intel_encoder * encoder)1555 enc_to_dig_port(struct intel_encoder *encoder)
1556 {
1557 struct intel_encoder *intel_encoder = encoder;
1558
1559 if (intel_encoder_is_dig_port(intel_encoder))
1560 return container_of(&encoder->base, struct intel_digital_port,
1561 base.base);
1562 else if (intel_encoder_is_mst(intel_encoder))
1563 return enc_to_mst(encoder)->primary;
1564 else
1565 return NULL;
1566 }
1567
1568 static inline struct intel_digital_port *
intel_attached_dig_port(struct intel_connector * connector)1569 intel_attached_dig_port(struct intel_connector *connector)
1570 {
1571 return enc_to_dig_port(intel_attached_encoder(connector));
1572 }
1573
enc_to_intel_dp(struct intel_encoder * encoder)1574 static inline struct intel_dp *enc_to_intel_dp(struct intel_encoder *encoder)
1575 {
1576 return &enc_to_dig_port(encoder)->dp;
1577 }
1578
intel_attached_dp(struct intel_connector * connector)1579 static inline struct intel_dp *intel_attached_dp(struct intel_connector *connector)
1580 {
1581 return enc_to_intel_dp(intel_attached_encoder(connector));
1582 }
1583
intel_encoder_is_dp(struct intel_encoder * encoder)1584 static inline bool intel_encoder_is_dp(struct intel_encoder *encoder)
1585 {
1586 switch (encoder->type) {
1587 case INTEL_OUTPUT_DP:
1588 case INTEL_OUTPUT_EDP:
1589 return true;
1590 case INTEL_OUTPUT_DDI:
1591 /* Skip pure HDMI/DVI DDI encoders */
1592 return i915_mmio_reg_valid(enc_to_intel_dp(encoder)->output_reg);
1593 default:
1594 return false;
1595 }
1596 }
1597
1598 static inline struct intel_lspcon *
enc_to_intel_lspcon(struct intel_encoder * encoder)1599 enc_to_intel_lspcon(struct intel_encoder *encoder)
1600 {
1601 return &enc_to_dig_port(encoder)->lspcon;
1602 }
1603
1604 static inline struct intel_digital_port *
dp_to_dig_port(struct intel_dp * intel_dp)1605 dp_to_dig_port(struct intel_dp *intel_dp)
1606 {
1607 return container_of(intel_dp, struct intel_digital_port, dp);
1608 }
1609
1610 static inline struct intel_lspcon *
dp_to_lspcon(struct intel_dp * intel_dp)1611 dp_to_lspcon(struct intel_dp *intel_dp)
1612 {
1613 return &dp_to_dig_port(intel_dp)->lspcon;
1614 }
1615
1616 static inline struct drm_i915_private *
dp_to_i915(struct intel_dp * intel_dp)1617 dp_to_i915(struct intel_dp *intel_dp)
1618 {
1619 return to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
1620 }
1621
1622 static inline struct intel_digital_port *
hdmi_to_dig_port(struct intel_hdmi * intel_hdmi)1623 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
1624 {
1625 return container_of(intel_hdmi, struct intel_digital_port, hdmi);
1626 }
1627
1628 static inline struct intel_plane_state *
intel_atomic_get_plane_state(struct intel_atomic_state * state,struct intel_plane * plane)1629 intel_atomic_get_plane_state(struct intel_atomic_state *state,
1630 struct intel_plane *plane)
1631 {
1632 struct drm_plane_state *ret =
1633 drm_atomic_get_plane_state(&state->base, &plane->base);
1634
1635 if (IS_ERR(ret))
1636 return ERR_CAST(ret);
1637
1638 return to_intel_plane_state(ret);
1639 }
1640
1641 static inline struct intel_plane_state *
intel_atomic_get_old_plane_state(struct intel_atomic_state * state,struct intel_plane * plane)1642 intel_atomic_get_old_plane_state(struct intel_atomic_state *state,
1643 struct intel_plane *plane)
1644 {
1645 return to_intel_plane_state(drm_atomic_get_old_plane_state(&state->base,
1646 &plane->base));
1647 }
1648
1649 static inline struct intel_plane_state *
intel_atomic_get_new_plane_state(struct intel_atomic_state * state,struct intel_plane * plane)1650 intel_atomic_get_new_plane_state(struct intel_atomic_state *state,
1651 struct intel_plane *plane)
1652 {
1653 return to_intel_plane_state(drm_atomic_get_new_plane_state(&state->base,
1654 &plane->base));
1655 }
1656
1657 static inline struct intel_crtc_state *
intel_atomic_get_old_crtc_state(struct intel_atomic_state * state,struct intel_crtc * crtc)1658 intel_atomic_get_old_crtc_state(struct intel_atomic_state *state,
1659 struct intel_crtc *crtc)
1660 {
1661 return to_intel_crtc_state(drm_atomic_get_old_crtc_state(&state->base,
1662 &crtc->base));
1663 }
1664
1665 static inline struct intel_crtc_state *
intel_atomic_get_new_crtc_state(struct intel_atomic_state * state,struct intel_crtc * crtc)1666 intel_atomic_get_new_crtc_state(struct intel_atomic_state *state,
1667 struct intel_crtc *crtc)
1668 {
1669 return to_intel_crtc_state(drm_atomic_get_new_crtc_state(&state->base,
1670 &crtc->base));
1671 }
1672
1673 static inline struct intel_digital_connector_state *
intel_atomic_get_new_connector_state(struct intel_atomic_state * state,struct intel_connector * connector)1674 intel_atomic_get_new_connector_state(struct intel_atomic_state *state,
1675 struct intel_connector *connector)
1676 {
1677 return to_intel_digital_connector_state(
1678 drm_atomic_get_new_connector_state(&state->base,
1679 &connector->base));
1680 }
1681
1682 static inline struct intel_digital_connector_state *
intel_atomic_get_old_connector_state(struct intel_atomic_state * state,struct intel_connector * connector)1683 intel_atomic_get_old_connector_state(struct intel_atomic_state *state,
1684 struct intel_connector *connector)
1685 {
1686 return to_intel_digital_connector_state(
1687 drm_atomic_get_old_connector_state(&state->base,
1688 &connector->base));
1689 }
1690
1691 /* intel_display.c */
1692 static inline bool
intel_crtc_has_type(const struct intel_crtc_state * crtc_state,enum intel_output_type type)1693 intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
1694 enum intel_output_type type)
1695 {
1696 return crtc_state->output_types & (1 << type);
1697 }
1698 static inline bool
intel_crtc_has_dp_encoder(const struct intel_crtc_state * crtc_state)1699 intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state)
1700 {
1701 return crtc_state->output_types &
1702 ((1 << INTEL_OUTPUT_DP) |
1703 (1 << INTEL_OUTPUT_DP_MST) |
1704 (1 << INTEL_OUTPUT_EDP));
1705 }
1706
1707 static inline void
intel_wait_for_vblank(struct drm_i915_private * dev_priv,enum pipe pipe)1708 intel_wait_for_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
1709 {
1710 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1711
1712 drm_crtc_wait_one_vblank(&crtc->base);
1713 }
1714
1715 static inline void
intel_wait_for_vblank_if_active(struct drm_i915_private * dev_priv,enum pipe pipe)1716 intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, enum pipe pipe)
1717 {
1718 const struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1719
1720 if (crtc->active)
1721 intel_wait_for_vblank(dev_priv, pipe);
1722 }
1723
intel_plane_ggtt_offset(const struct intel_plane_state * state)1724 static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state)
1725 {
1726 return i915_ggtt_offset(state->vma);
1727 }
1728
1729 #endif /* __INTEL_DISPLAY_TYPES_H__ */
1730