1 /*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include <linux/slab.h>
27
28 #include "dm_services.h"
29
30
31 #include "dc_types.h"
32 #include "core_types.h"
33
34 #include "include/grph_object_id.h"
35 #include "include/logger_interface.h"
36
37 #include "dce_clock_source.h"
38 #include "clk_mgr.h"
39
40 #include "reg_helper.h"
41
42 #define REG(reg)\
43 (clk_src->regs->reg)
44
45 #define CTX \
46 clk_src->base.ctx
47
48 #define DC_LOGGER_INIT()
49
50 #undef FN
51 #define FN(reg_name, field_name) \
52 clk_src->cs_shift->field_name, clk_src->cs_mask->field_name
53
54 #define FRACT_FB_DIVIDER_DEC_POINTS_MAX_NUM 6
55 #define CALC_PLL_CLK_SRC_ERR_TOLERANCE 1
56 #define MAX_PLL_CALC_ERROR 0xFFFFFFFF
57
58 #define NUM_ELEMENTS(a) (sizeof(a) / sizeof((a)[0]))
59
get_ss_data_entry(struct dce110_clk_src * clk_src,enum signal_type signal,uint32_t pix_clk_khz)60 static const struct spread_spectrum_data *get_ss_data_entry(
61 struct dce110_clk_src *clk_src,
62 enum signal_type signal,
63 uint32_t pix_clk_khz)
64 {
65
66 uint32_t entrys_num;
67 uint32_t i;
68 struct spread_spectrum_data *ss_parm = NULL;
69 struct spread_spectrum_data *ret = NULL;
70
71 switch (signal) {
72 case SIGNAL_TYPE_DVI_SINGLE_LINK:
73 case SIGNAL_TYPE_DVI_DUAL_LINK:
74 ss_parm = clk_src->dvi_ss_params;
75 entrys_num = clk_src->dvi_ss_params_cnt;
76 break;
77
78 case SIGNAL_TYPE_HDMI_TYPE_A:
79 ss_parm = clk_src->hdmi_ss_params;
80 entrys_num = clk_src->hdmi_ss_params_cnt;
81 break;
82
83 case SIGNAL_TYPE_LVDS:
84 ss_parm = clk_src->lvds_ss_params;
85 entrys_num = clk_src->lvds_ss_params_cnt;
86 break;
87
88 case SIGNAL_TYPE_DISPLAY_PORT:
89 case SIGNAL_TYPE_DISPLAY_PORT_MST:
90 case SIGNAL_TYPE_EDP:
91 case SIGNAL_TYPE_VIRTUAL:
92 ss_parm = clk_src->dp_ss_params;
93 entrys_num = clk_src->dp_ss_params_cnt;
94 break;
95
96 default:
97 ss_parm = NULL;
98 entrys_num = 0;
99 break;
100 }
101
102 if (ss_parm == NULL)
103 return ret;
104
105 for (i = 0; i < entrys_num; ++i, ++ss_parm) {
106 if (ss_parm->freq_range_khz >= pix_clk_khz) {
107 ret = ss_parm;
108 break;
109 }
110 }
111
112 return ret;
113 }
114
115 /**
116 * Function: calculate_fb_and_fractional_fb_divider
117 *
118 * * DESCRIPTION: Calculates feedback and fractional feedback dividers values
119 *
120 *PARAMETERS:
121 * targetPixelClock Desired frequency in 100 Hz
122 * ref_divider Reference divider (already known)
123 * postDivider Post Divider (already known)
124 * feedback_divider_param Pointer where to store
125 * calculated feedback divider value
126 * fract_feedback_divider_param Pointer where to store
127 * calculated fract feedback divider value
128 *
129 *RETURNS:
130 * It fills the locations pointed by feedback_divider_param
131 * and fract_feedback_divider_param
132 * It returns - true if feedback divider not 0
133 * - false should never happen)
134 */
calculate_fb_and_fractional_fb_divider(struct calc_pll_clock_source * calc_pll_cs,uint32_t target_pix_clk_100hz,uint32_t ref_divider,uint32_t post_divider,uint32_t * feedback_divider_param,uint32_t * fract_feedback_divider_param)135 static bool calculate_fb_and_fractional_fb_divider(
136 struct calc_pll_clock_source *calc_pll_cs,
137 uint32_t target_pix_clk_100hz,
138 uint32_t ref_divider,
139 uint32_t post_divider,
140 uint32_t *feedback_divider_param,
141 uint32_t *fract_feedback_divider_param)
142 {
143 uint64_t feedback_divider;
144
145 feedback_divider =
146 (uint64_t)target_pix_clk_100hz * ref_divider * post_divider;
147 feedback_divider *= 10;
148 /* additional factor, since we divide by 10 afterwards */
149 feedback_divider *= (uint64_t)(calc_pll_cs->fract_fb_divider_factor);
150 feedback_divider = div_u64(feedback_divider, calc_pll_cs->ref_freq_khz * 10ull);
151
152 /*Round to the number of precision
153 * The following code replace the old code (ullfeedbackDivider + 5)/10
154 * for example if the difference between the number
155 * of fractional feedback decimal point and the fractional FB Divider precision
156 * is 2 then the equation becomes (ullfeedbackDivider + 5*100) / (10*100))*/
157
158 feedback_divider += 5ULL *
159 calc_pll_cs->fract_fb_divider_precision_factor;
160 feedback_divider =
161 div_u64(feedback_divider,
162 calc_pll_cs->fract_fb_divider_precision_factor * 10);
163 feedback_divider *= (uint64_t)
164 (calc_pll_cs->fract_fb_divider_precision_factor);
165
166 *feedback_divider_param =
167 div_u64_rem(
168 feedback_divider,
169 calc_pll_cs->fract_fb_divider_factor,
170 fract_feedback_divider_param);
171
172 if (*feedback_divider_param != 0)
173 return true;
174 return false;
175 }
176
177 /**
178 *calc_fb_divider_checking_tolerance
179 *
180 *DESCRIPTION: Calculates Feedback and Fractional Feedback divider values
181 * for passed Reference and Post divider, checking for tolerance.
182 *PARAMETERS:
183 * pll_settings Pointer to structure
184 * ref_divider Reference divider (already known)
185 * postDivider Post Divider (already known)
186 * tolerance Tolerance for Calculated Pixel Clock to be within
187 *
188 *RETURNS:
189 * It fills the PLLSettings structure with PLL Dividers values
190 * if calculated values are within required tolerance
191 * It returns - true if error is within tolerance
192 * - false if error is not within tolerance
193 */
calc_fb_divider_checking_tolerance(struct calc_pll_clock_source * calc_pll_cs,struct pll_settings * pll_settings,uint32_t ref_divider,uint32_t post_divider,uint32_t tolerance)194 static bool calc_fb_divider_checking_tolerance(
195 struct calc_pll_clock_source *calc_pll_cs,
196 struct pll_settings *pll_settings,
197 uint32_t ref_divider,
198 uint32_t post_divider,
199 uint32_t tolerance)
200 {
201 uint32_t feedback_divider;
202 uint32_t fract_feedback_divider;
203 uint32_t actual_calculated_clock_100hz;
204 uint32_t abs_err;
205 uint64_t actual_calc_clk_100hz;
206
207 calculate_fb_and_fractional_fb_divider(
208 calc_pll_cs,
209 pll_settings->adjusted_pix_clk_100hz,
210 ref_divider,
211 post_divider,
212 &feedback_divider,
213 &fract_feedback_divider);
214
215 /*Actual calculated value*/
216 actual_calc_clk_100hz = (uint64_t)feedback_divider *
217 calc_pll_cs->fract_fb_divider_factor +
218 fract_feedback_divider;
219 actual_calc_clk_100hz *= calc_pll_cs->ref_freq_khz * 10;
220 actual_calc_clk_100hz =
221 div_u64(actual_calc_clk_100hz,
222 ref_divider * post_divider *
223 calc_pll_cs->fract_fb_divider_factor);
224
225 actual_calculated_clock_100hz = (uint32_t)(actual_calc_clk_100hz);
226
227 abs_err = (actual_calculated_clock_100hz >
228 pll_settings->adjusted_pix_clk_100hz)
229 ? actual_calculated_clock_100hz -
230 pll_settings->adjusted_pix_clk_100hz
231 : pll_settings->adjusted_pix_clk_100hz -
232 actual_calculated_clock_100hz;
233
234 if (abs_err <= tolerance) {
235 /*found good values*/
236 pll_settings->reference_freq = calc_pll_cs->ref_freq_khz;
237 pll_settings->reference_divider = ref_divider;
238 pll_settings->feedback_divider = feedback_divider;
239 pll_settings->fract_feedback_divider = fract_feedback_divider;
240 pll_settings->pix_clk_post_divider = post_divider;
241 pll_settings->calculated_pix_clk_100hz =
242 actual_calculated_clock_100hz;
243 pll_settings->vco_freq =
244 actual_calculated_clock_100hz * post_divider / 10;
245 return true;
246 }
247 return false;
248 }
249
calc_pll_dividers_in_range(struct calc_pll_clock_source * calc_pll_cs,struct pll_settings * pll_settings,uint32_t min_ref_divider,uint32_t max_ref_divider,uint32_t min_post_divider,uint32_t max_post_divider,uint32_t err_tolerance)250 static bool calc_pll_dividers_in_range(
251 struct calc_pll_clock_source *calc_pll_cs,
252 struct pll_settings *pll_settings,
253 uint32_t min_ref_divider,
254 uint32_t max_ref_divider,
255 uint32_t min_post_divider,
256 uint32_t max_post_divider,
257 uint32_t err_tolerance)
258 {
259 uint32_t ref_divider;
260 uint32_t post_divider;
261 uint32_t tolerance;
262
263 /* This is err_tolerance / 10000 = 0.0025 - acceptable error of 0.25%
264 * This is errorTolerance / 10000 = 0.0001 - acceptable error of 0.01%*/
265 tolerance = (pll_settings->adjusted_pix_clk_100hz * err_tolerance) /
266 100000;
267 if (tolerance < CALC_PLL_CLK_SRC_ERR_TOLERANCE)
268 tolerance = CALC_PLL_CLK_SRC_ERR_TOLERANCE;
269
270 for (
271 post_divider = max_post_divider;
272 post_divider >= min_post_divider;
273 --post_divider) {
274 for (
275 ref_divider = min_ref_divider;
276 ref_divider <= max_ref_divider;
277 ++ref_divider) {
278 if (calc_fb_divider_checking_tolerance(
279 calc_pll_cs,
280 pll_settings,
281 ref_divider,
282 post_divider,
283 tolerance)) {
284 return true;
285 }
286 }
287 }
288
289 return false;
290 }
291
calculate_pixel_clock_pll_dividers(struct calc_pll_clock_source * calc_pll_cs,struct pll_settings * pll_settings)292 static uint32_t calculate_pixel_clock_pll_dividers(
293 struct calc_pll_clock_source *calc_pll_cs,
294 struct pll_settings *pll_settings)
295 {
296 uint32_t err_tolerance;
297 uint32_t min_post_divider;
298 uint32_t max_post_divider;
299 uint32_t min_ref_divider;
300 uint32_t max_ref_divider;
301
302 if (pll_settings->adjusted_pix_clk_100hz == 0) {
303 DC_LOG_ERROR(
304 "%s Bad requested pixel clock", __func__);
305 return MAX_PLL_CALC_ERROR;
306 }
307
308 /* 1) Find Post divider ranges */
309 if (pll_settings->pix_clk_post_divider) {
310 min_post_divider = pll_settings->pix_clk_post_divider;
311 max_post_divider = pll_settings->pix_clk_post_divider;
312 } else {
313 min_post_divider = calc_pll_cs->min_pix_clock_pll_post_divider;
314 if (min_post_divider * pll_settings->adjusted_pix_clk_100hz <
315 calc_pll_cs->min_vco_khz * 10) {
316 min_post_divider = calc_pll_cs->min_vco_khz * 10 /
317 pll_settings->adjusted_pix_clk_100hz;
318 if ((min_post_divider *
319 pll_settings->adjusted_pix_clk_100hz) <
320 calc_pll_cs->min_vco_khz * 10)
321 min_post_divider++;
322 }
323
324 max_post_divider = calc_pll_cs->max_pix_clock_pll_post_divider;
325 if (max_post_divider * pll_settings->adjusted_pix_clk_100hz
326 > calc_pll_cs->max_vco_khz * 10)
327 max_post_divider = calc_pll_cs->max_vco_khz * 10 /
328 pll_settings->adjusted_pix_clk_100hz;
329 }
330
331 /* 2) Find Reference divider ranges
332 * When SS is enabled, or for Display Port even without SS,
333 * pll_settings->referenceDivider is not zero.
334 * So calculate PPLL FB and fractional FB divider
335 * using the passed reference divider*/
336
337 if (pll_settings->reference_divider) {
338 min_ref_divider = pll_settings->reference_divider;
339 max_ref_divider = pll_settings->reference_divider;
340 } else {
341 min_ref_divider = ((calc_pll_cs->ref_freq_khz
342 / calc_pll_cs->max_pll_input_freq_khz)
343 > calc_pll_cs->min_pll_ref_divider)
344 ? calc_pll_cs->ref_freq_khz
345 / calc_pll_cs->max_pll_input_freq_khz
346 : calc_pll_cs->min_pll_ref_divider;
347
348 max_ref_divider = ((calc_pll_cs->ref_freq_khz
349 / calc_pll_cs->min_pll_input_freq_khz)
350 < calc_pll_cs->max_pll_ref_divider)
351 ? calc_pll_cs->ref_freq_khz /
352 calc_pll_cs->min_pll_input_freq_khz
353 : calc_pll_cs->max_pll_ref_divider;
354 }
355
356 /* If some parameters are invalid we could have scenario when "min">"max"
357 * which produced endless loop later.
358 * We should investigate why we get the wrong parameters.
359 * But to follow the similar logic when "adjustedPixelClock" is set to be 0
360 * it is better to return here than cause system hang/watchdog timeout later.
361 * ## SVS Wed 15 Jul 2009 */
362
363 if (min_post_divider > max_post_divider) {
364 DC_LOG_ERROR(
365 "%s Post divider range is invalid", __func__);
366 return MAX_PLL_CALC_ERROR;
367 }
368
369 if (min_ref_divider > max_ref_divider) {
370 DC_LOG_ERROR(
371 "%s Reference divider range is invalid", __func__);
372 return MAX_PLL_CALC_ERROR;
373 }
374
375 /* 3) Try to find PLL dividers given ranges
376 * starting with minimal error tolerance.
377 * Increase error tolerance until PLL dividers found*/
378 err_tolerance = MAX_PLL_CALC_ERROR;
379
380 while (!calc_pll_dividers_in_range(
381 calc_pll_cs,
382 pll_settings,
383 min_ref_divider,
384 max_ref_divider,
385 min_post_divider,
386 max_post_divider,
387 err_tolerance))
388 err_tolerance += (err_tolerance > 10)
389 ? (err_tolerance / 10)
390 : 1;
391
392 return err_tolerance;
393 }
394
pll_adjust_pix_clk(struct dce110_clk_src * clk_src,struct pixel_clk_params * pix_clk_params,struct pll_settings * pll_settings)395 static bool pll_adjust_pix_clk(
396 struct dce110_clk_src *clk_src,
397 struct pixel_clk_params *pix_clk_params,
398 struct pll_settings *pll_settings)
399 {
400 uint32_t actual_pix_clk_100hz = 0;
401 uint32_t requested_clk_100hz = 0;
402 struct bp_adjust_pixel_clock_parameters bp_adjust_pixel_clock_params = {
403 0 };
404 enum bp_result bp_result;
405 switch (pix_clk_params->signal_type) {
406 case SIGNAL_TYPE_HDMI_TYPE_A: {
407 requested_clk_100hz = pix_clk_params->requested_pix_clk_100hz;
408 if (pix_clk_params->pixel_encoding != PIXEL_ENCODING_YCBCR422) {
409 switch (pix_clk_params->color_depth) {
410 case COLOR_DEPTH_101010:
411 requested_clk_100hz = (requested_clk_100hz * 5) >> 2;
412 break; /* x1.25*/
413 case COLOR_DEPTH_121212:
414 requested_clk_100hz = (requested_clk_100hz * 6) >> 2;
415 break; /* x1.5*/
416 case COLOR_DEPTH_161616:
417 requested_clk_100hz = requested_clk_100hz * 2;
418 break; /* x2.0*/
419 default:
420 break;
421 }
422 }
423 actual_pix_clk_100hz = requested_clk_100hz;
424 }
425 break;
426
427 case SIGNAL_TYPE_DISPLAY_PORT:
428 case SIGNAL_TYPE_DISPLAY_PORT_MST:
429 case SIGNAL_TYPE_EDP:
430 requested_clk_100hz = pix_clk_params->requested_sym_clk * 10;
431 actual_pix_clk_100hz = pix_clk_params->requested_pix_clk_100hz;
432 break;
433
434 default:
435 requested_clk_100hz = pix_clk_params->requested_pix_clk_100hz;
436 actual_pix_clk_100hz = pix_clk_params->requested_pix_clk_100hz;
437 break;
438 }
439
440 bp_adjust_pixel_clock_params.pixel_clock = requested_clk_100hz / 10;
441 bp_adjust_pixel_clock_params.
442 encoder_object_id = pix_clk_params->encoder_object_id;
443 bp_adjust_pixel_clock_params.signal_type = pix_clk_params->signal_type;
444 bp_adjust_pixel_clock_params.
445 ss_enable = pix_clk_params->flags.ENABLE_SS;
446 bp_result = clk_src->bios->funcs->adjust_pixel_clock(
447 clk_src->bios, &bp_adjust_pixel_clock_params);
448 if (bp_result == BP_RESULT_OK) {
449 pll_settings->actual_pix_clk_100hz = actual_pix_clk_100hz;
450 pll_settings->adjusted_pix_clk_100hz =
451 bp_adjust_pixel_clock_params.adjusted_pixel_clock * 10;
452 pll_settings->reference_divider =
453 bp_adjust_pixel_clock_params.reference_divider;
454 pll_settings->pix_clk_post_divider =
455 bp_adjust_pixel_clock_params.pixel_clock_post_divider;
456
457 return true;
458 }
459
460 return false;
461 }
462
463 /**
464 * Calculate PLL Dividers for given Clock Value.
465 * First will call VBIOS Adjust Exec table to check if requested Pixel clock
466 * will be Adjusted based on usage.
467 * Then it will calculate PLL Dividers for this Adjusted clock using preferred
468 * method (Maximum VCO frequency).
469 *
470 * \return
471 * Calculation error in units of 0.01%
472 */
473
dce110_get_pix_clk_dividers_helper(struct dce110_clk_src * clk_src,struct pll_settings * pll_settings,struct pixel_clk_params * pix_clk_params)474 static uint32_t dce110_get_pix_clk_dividers_helper (
475 struct dce110_clk_src *clk_src,
476 struct pll_settings *pll_settings,
477 struct pixel_clk_params *pix_clk_params)
478 {
479 uint32_t field = 0;
480 uint32_t pll_calc_error = MAX_PLL_CALC_ERROR;
481 DC_LOGGER_INIT();
482 /* Check if reference clock is external (not pcie/xtalin)
483 * HW Dce80 spec:
484 * 00 - PCIE_REFCLK, 01 - XTALIN, 02 - GENERICA, 03 - GENERICB
485 * 04 - HSYNCA, 05 - GENLK_CLK, 06 - PCIE_REFCLK, 07 - DVOCLK0 */
486 REG_GET(PLL_CNTL, PLL_REF_DIV_SRC, &field);
487 pll_settings->use_external_clk = (field > 1);
488
489 /* VBIOS by default enables DP SS (spread on IDCLK) for DCE 8.0 always
490 * (we do not care any more from SI for some older DP Sink which
491 * does not report SS support, no known issues) */
492 if ((pix_clk_params->flags.ENABLE_SS) ||
493 (dc_is_dp_signal(pix_clk_params->signal_type))) {
494
495 const struct spread_spectrum_data *ss_data = get_ss_data_entry(
496 clk_src,
497 pix_clk_params->signal_type,
498 pll_settings->adjusted_pix_clk_100hz / 10);
499
500 if (NULL != ss_data)
501 pll_settings->ss_percentage = ss_data->percentage;
502 }
503
504 /* Check VBIOS AdjustPixelClock Exec table */
505 if (!pll_adjust_pix_clk(clk_src, pix_clk_params, pll_settings)) {
506 /* Should never happen, ASSERT and fill up values to be able
507 * to continue. */
508 DC_LOG_ERROR(
509 "%s: Failed to adjust pixel clock!!", __func__);
510 pll_settings->actual_pix_clk_100hz =
511 pix_clk_params->requested_pix_clk_100hz;
512 pll_settings->adjusted_pix_clk_100hz =
513 pix_clk_params->requested_pix_clk_100hz;
514
515 if (dc_is_dp_signal(pix_clk_params->signal_type))
516 pll_settings->adjusted_pix_clk_100hz = 1000000;
517 }
518
519 /* Calculate Dividers */
520 if (pix_clk_params->signal_type == SIGNAL_TYPE_HDMI_TYPE_A)
521 /*Calculate Dividers by HDMI object, no SS case or SS case */
522 pll_calc_error =
523 calculate_pixel_clock_pll_dividers(
524 &clk_src->calc_pll_hdmi,
525 pll_settings);
526 else
527 /*Calculate Dividers by default object, no SS case or SS case */
528 pll_calc_error =
529 calculate_pixel_clock_pll_dividers(
530 &clk_src->calc_pll,
531 pll_settings);
532
533 return pll_calc_error;
534 }
535
dce112_get_pix_clk_dividers_helper(struct dce110_clk_src * clk_src,struct pll_settings * pll_settings,struct pixel_clk_params * pix_clk_params)536 static void dce112_get_pix_clk_dividers_helper (
537 struct dce110_clk_src *clk_src,
538 struct pll_settings *pll_settings,
539 struct pixel_clk_params *pix_clk_params)
540 {
541 uint32_t actual_pixel_clock_100hz;
542
543 actual_pixel_clock_100hz = pix_clk_params->requested_pix_clk_100hz;
544 /* Calculate Dividers */
545 if (pix_clk_params->signal_type == SIGNAL_TYPE_HDMI_TYPE_A) {
546 switch (pix_clk_params->color_depth) {
547 case COLOR_DEPTH_101010:
548 actual_pixel_clock_100hz = (actual_pixel_clock_100hz * 5) >> 2;
549 actual_pixel_clock_100hz -= actual_pixel_clock_100hz % 10;
550 break;
551 case COLOR_DEPTH_121212:
552 actual_pixel_clock_100hz = (actual_pixel_clock_100hz * 6) >> 2;
553 actual_pixel_clock_100hz -= actual_pixel_clock_100hz % 10;
554 break;
555 case COLOR_DEPTH_161616:
556 actual_pixel_clock_100hz = actual_pixel_clock_100hz * 2;
557 break;
558 default:
559 break;
560 }
561 }
562 pll_settings->actual_pix_clk_100hz = actual_pixel_clock_100hz;
563 pll_settings->adjusted_pix_clk_100hz = actual_pixel_clock_100hz;
564 pll_settings->calculated_pix_clk_100hz = pix_clk_params->requested_pix_clk_100hz;
565 }
566
dce110_get_pix_clk_dividers(struct clock_source * cs,struct pixel_clk_params * pix_clk_params,struct pll_settings * pll_settings)567 static uint32_t dce110_get_pix_clk_dividers(
568 struct clock_source *cs,
569 struct pixel_clk_params *pix_clk_params,
570 struct pll_settings *pll_settings)
571 {
572 struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(cs);
573 uint32_t pll_calc_error = MAX_PLL_CALC_ERROR;
574 DC_LOGGER_INIT();
575
576 if (pix_clk_params == NULL || pll_settings == NULL
577 || pix_clk_params->requested_pix_clk_100hz == 0) {
578 DC_LOG_ERROR(
579 "%s: Invalid parameters!!\n", __func__);
580 return pll_calc_error;
581 }
582
583 memset(pll_settings, 0, sizeof(*pll_settings));
584
585 if (cs->id == CLOCK_SOURCE_ID_DP_DTO ||
586 cs->id == CLOCK_SOURCE_ID_EXTERNAL) {
587 pll_settings->adjusted_pix_clk_100hz = clk_src->ext_clk_khz * 10;
588 pll_settings->calculated_pix_clk_100hz = clk_src->ext_clk_khz * 10;
589 pll_settings->actual_pix_clk_100hz =
590 pix_clk_params->requested_pix_clk_100hz;
591 return 0;
592 }
593
594 pll_calc_error = dce110_get_pix_clk_dividers_helper(clk_src,
595 pll_settings, pix_clk_params);
596
597 return pll_calc_error;
598 }
599
dce112_get_pix_clk_dividers(struct clock_source * cs,struct pixel_clk_params * pix_clk_params,struct pll_settings * pll_settings)600 static uint32_t dce112_get_pix_clk_dividers(
601 struct clock_source *cs,
602 struct pixel_clk_params *pix_clk_params,
603 struct pll_settings *pll_settings)
604 {
605 struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(cs);
606 DC_LOGGER_INIT();
607
608 if (pix_clk_params == NULL || pll_settings == NULL
609 || pix_clk_params->requested_pix_clk_100hz == 0) {
610 DC_LOG_ERROR(
611 "%s: Invalid parameters!!\n", __func__);
612 return -1;
613 }
614
615 memset(pll_settings, 0, sizeof(*pll_settings));
616
617 if (cs->id == CLOCK_SOURCE_ID_DP_DTO ||
618 cs->id == CLOCK_SOURCE_ID_EXTERNAL) {
619 pll_settings->adjusted_pix_clk_100hz = clk_src->ext_clk_khz * 10;
620 pll_settings->calculated_pix_clk_100hz = clk_src->ext_clk_khz * 10;
621 pll_settings->actual_pix_clk_100hz =
622 pix_clk_params->requested_pix_clk_100hz;
623 return -1;
624 }
625
626 dce112_get_pix_clk_dividers_helper(clk_src,
627 pll_settings, pix_clk_params);
628
629 return 0;
630 }
631
disable_spread_spectrum(struct dce110_clk_src * clk_src)632 static bool disable_spread_spectrum(struct dce110_clk_src *clk_src)
633 {
634 enum bp_result result;
635 struct bp_spread_spectrum_parameters bp_ss_params = {0};
636
637 bp_ss_params.pll_id = clk_src->base.id;
638
639 /*Call ASICControl to process ATOMBIOS Exec table*/
640 result = clk_src->bios->funcs->enable_spread_spectrum_on_ppll(
641 clk_src->bios,
642 &bp_ss_params,
643 false);
644
645 return result == BP_RESULT_OK;
646 }
647
calculate_ss(const struct pll_settings * pll_settings,const struct spread_spectrum_data * ss_data,struct delta_sigma_data * ds_data)648 static bool calculate_ss(
649 const struct pll_settings *pll_settings,
650 const struct spread_spectrum_data *ss_data,
651 struct delta_sigma_data *ds_data)
652 {
653 struct fixed31_32 fb_div;
654 struct fixed31_32 ss_amount;
655 struct fixed31_32 ss_nslip_amount;
656 struct fixed31_32 ss_ds_frac_amount;
657 struct fixed31_32 ss_step_size;
658 struct fixed31_32 modulation_time;
659
660 if (ds_data == NULL)
661 return false;
662 if (ss_data == NULL)
663 return false;
664 if (ss_data->percentage == 0)
665 return false;
666 if (pll_settings == NULL)
667 return false;
668
669 memset(ds_data, 0, sizeof(struct delta_sigma_data));
670
671 /* compute SS_AMOUNT_FBDIV & SS_AMOUNT_NFRAC_SLIP & SS_AMOUNT_DSFRAC*/
672 /* 6 decimal point support in fractional feedback divider */
673 fb_div = dc_fixpt_from_fraction(
674 pll_settings->fract_feedback_divider, 1000000);
675 fb_div = dc_fixpt_add_int(fb_div, pll_settings->feedback_divider);
676
677 ds_data->ds_frac_amount = 0;
678 /*spreadSpectrumPercentage is in the unit of .01%,
679 * so have to divided by 100 * 100*/
680 ss_amount = dc_fixpt_mul(
681 fb_div, dc_fixpt_from_fraction(ss_data->percentage,
682 100 * ss_data->percentage_divider));
683 ds_data->feedback_amount = dc_fixpt_floor(ss_amount);
684
685 ss_nslip_amount = dc_fixpt_sub(ss_amount,
686 dc_fixpt_from_int(ds_data->feedback_amount));
687 ss_nslip_amount = dc_fixpt_mul_int(ss_nslip_amount, 10);
688 ds_data->nfrac_amount = dc_fixpt_floor(ss_nslip_amount);
689
690 ss_ds_frac_amount = dc_fixpt_sub(ss_nslip_amount,
691 dc_fixpt_from_int(ds_data->nfrac_amount));
692 ss_ds_frac_amount = dc_fixpt_mul_int(ss_ds_frac_amount, 65536);
693 ds_data->ds_frac_amount = dc_fixpt_floor(ss_ds_frac_amount);
694
695 /* compute SS_STEP_SIZE_DSFRAC */
696 modulation_time = dc_fixpt_from_fraction(
697 pll_settings->reference_freq * 1000,
698 pll_settings->reference_divider * ss_data->modulation_freq_hz);
699
700 if (ss_data->flags.CENTER_SPREAD)
701 modulation_time = dc_fixpt_div_int(modulation_time, 4);
702 else
703 modulation_time = dc_fixpt_div_int(modulation_time, 2);
704
705 ss_step_size = dc_fixpt_div(ss_amount, modulation_time);
706 /* SS_STEP_SIZE_DSFRAC_DEC = Int(SS_STEP_SIZE * 2 ^ 16 * 10)*/
707 ss_step_size = dc_fixpt_mul_int(ss_step_size, 65536 * 10);
708 ds_data->ds_frac_size = dc_fixpt_floor(ss_step_size);
709
710 return true;
711 }
712
enable_spread_spectrum(struct dce110_clk_src * clk_src,enum signal_type signal,struct pll_settings * pll_settings)713 static bool enable_spread_spectrum(
714 struct dce110_clk_src *clk_src,
715 enum signal_type signal, struct pll_settings *pll_settings)
716 {
717 struct bp_spread_spectrum_parameters bp_params = {0};
718 struct delta_sigma_data d_s_data;
719 const struct spread_spectrum_data *ss_data = NULL;
720
721 ss_data = get_ss_data_entry(
722 clk_src,
723 signal,
724 pll_settings->calculated_pix_clk_100hz / 10);
725
726 /* Pixel clock PLL has been programmed to generate desired pixel clock,
727 * now enable SS on pixel clock */
728 /* TODO is it OK to return true not doing anything ??*/
729 if (ss_data != NULL && pll_settings->ss_percentage != 0) {
730 if (calculate_ss(pll_settings, ss_data, &d_s_data)) {
731 bp_params.ds.feedback_amount =
732 d_s_data.feedback_amount;
733 bp_params.ds.nfrac_amount =
734 d_s_data.nfrac_amount;
735 bp_params.ds.ds_frac_size = d_s_data.ds_frac_size;
736 bp_params.ds_frac_amount =
737 d_s_data.ds_frac_amount;
738 bp_params.flags.DS_TYPE = 1;
739 bp_params.pll_id = clk_src->base.id;
740 bp_params.percentage = ss_data->percentage;
741 if (ss_data->flags.CENTER_SPREAD)
742 bp_params.flags.CENTER_SPREAD = 1;
743 if (ss_data->flags.EXTERNAL_SS)
744 bp_params.flags.EXTERNAL_SS = 1;
745
746 if (BP_RESULT_OK !=
747 clk_src->bios->funcs->
748 enable_spread_spectrum_on_ppll(
749 clk_src->bios,
750 &bp_params,
751 true))
752 return false;
753 } else
754 return false;
755 }
756 return true;
757 }
758
dce110_program_pixel_clk_resync(struct dce110_clk_src * clk_src,enum signal_type signal_type,enum dc_color_depth colordepth)759 static void dce110_program_pixel_clk_resync(
760 struct dce110_clk_src *clk_src,
761 enum signal_type signal_type,
762 enum dc_color_depth colordepth)
763 {
764 REG_UPDATE(RESYNC_CNTL,
765 DCCG_DEEP_COLOR_CNTL1, 0);
766 /*
767 24 bit mode: TMDS clock = 1.0 x pixel clock (1:1)
768 30 bit mode: TMDS clock = 1.25 x pixel clock (5:4)
769 36 bit mode: TMDS clock = 1.5 x pixel clock (3:2)
770 48 bit mode: TMDS clock = 2 x pixel clock (2:1)
771 */
772 if (signal_type != SIGNAL_TYPE_HDMI_TYPE_A)
773 return;
774
775 switch (colordepth) {
776 case COLOR_DEPTH_888:
777 REG_UPDATE(RESYNC_CNTL,
778 DCCG_DEEP_COLOR_CNTL1, 0);
779 break;
780 case COLOR_DEPTH_101010:
781 REG_UPDATE(RESYNC_CNTL,
782 DCCG_DEEP_COLOR_CNTL1, 1);
783 break;
784 case COLOR_DEPTH_121212:
785 REG_UPDATE(RESYNC_CNTL,
786 DCCG_DEEP_COLOR_CNTL1, 2);
787 break;
788 case COLOR_DEPTH_161616:
789 REG_UPDATE(RESYNC_CNTL,
790 DCCG_DEEP_COLOR_CNTL1, 3);
791 break;
792 default:
793 break;
794 }
795 }
796
dce112_program_pixel_clk_resync(struct dce110_clk_src * clk_src,enum signal_type signal_type,enum dc_color_depth colordepth,bool enable_ycbcr420)797 static void dce112_program_pixel_clk_resync(
798 struct dce110_clk_src *clk_src,
799 enum signal_type signal_type,
800 enum dc_color_depth colordepth,
801 bool enable_ycbcr420)
802 {
803 uint32_t deep_color_cntl = 0;
804 uint32_t double_rate_enable = 0;
805
806 /*
807 24 bit mode: TMDS clock = 1.0 x pixel clock (1:1)
808 30 bit mode: TMDS clock = 1.25 x pixel clock (5:4)
809 36 bit mode: TMDS clock = 1.5 x pixel clock (3:2)
810 48 bit mode: TMDS clock = 2 x pixel clock (2:1)
811 */
812 if (signal_type == SIGNAL_TYPE_HDMI_TYPE_A) {
813 double_rate_enable = enable_ycbcr420 ? 1 : 0;
814
815 switch (colordepth) {
816 case COLOR_DEPTH_888:
817 deep_color_cntl = 0;
818 break;
819 case COLOR_DEPTH_101010:
820 deep_color_cntl = 1;
821 break;
822 case COLOR_DEPTH_121212:
823 deep_color_cntl = 2;
824 break;
825 case COLOR_DEPTH_161616:
826 deep_color_cntl = 3;
827 break;
828 default:
829 break;
830 }
831 }
832
833 if (clk_src->cs_mask->PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE)
834 REG_UPDATE_2(PIXCLK_RESYNC_CNTL,
835 PHYPLLA_DCCG_DEEP_COLOR_CNTL, deep_color_cntl,
836 PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE, double_rate_enable);
837 else
838 REG_UPDATE(PIXCLK_RESYNC_CNTL,
839 PHYPLLA_DCCG_DEEP_COLOR_CNTL, deep_color_cntl);
840
841 }
842
dce110_program_pix_clk(struct clock_source * clock_source,struct pixel_clk_params * pix_clk_params,struct pll_settings * pll_settings)843 static bool dce110_program_pix_clk(
844 struct clock_source *clock_source,
845 struct pixel_clk_params *pix_clk_params,
846 struct pll_settings *pll_settings)
847 {
848 struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source);
849 struct bp_pixel_clock_parameters bp_pc_params = {0};
850
851 /* First disable SS
852 * ATOMBIOS will enable by default SS on PLL for DP,
853 * do not disable it here
854 */
855 if (clock_source->id != CLOCK_SOURCE_ID_EXTERNAL &&
856 !dc_is_dp_signal(pix_clk_params->signal_type) &&
857 clock_source->ctx->dce_version <= DCE_VERSION_11_0)
858 disable_spread_spectrum(clk_src);
859
860 /*ATOMBIOS expects pixel rate adjusted by deep color ratio)*/
861 bp_pc_params.controller_id = pix_clk_params->controller_id;
862 bp_pc_params.pll_id = clock_source->id;
863 bp_pc_params.target_pixel_clock_100hz = pll_settings->actual_pix_clk_100hz;
864 bp_pc_params.encoder_object_id = pix_clk_params->encoder_object_id;
865 bp_pc_params.signal_type = pix_clk_params->signal_type;
866
867 bp_pc_params.reference_divider = pll_settings->reference_divider;
868 bp_pc_params.feedback_divider = pll_settings->feedback_divider;
869 bp_pc_params.fractional_feedback_divider =
870 pll_settings->fract_feedback_divider;
871 bp_pc_params.pixel_clock_post_divider =
872 pll_settings->pix_clk_post_divider;
873 bp_pc_params.flags.SET_EXTERNAL_REF_DIV_SRC =
874 pll_settings->use_external_clk;
875
876 switch (pix_clk_params->color_depth) {
877 case COLOR_DEPTH_101010:
878 bp_pc_params.color_depth = TRANSMITTER_COLOR_DEPTH_30;
879 break;
880 case COLOR_DEPTH_121212:
881 bp_pc_params.color_depth = TRANSMITTER_COLOR_DEPTH_36;
882 break;
883 case COLOR_DEPTH_161616:
884 bp_pc_params.color_depth = TRANSMITTER_COLOR_DEPTH_48;
885 break;
886 default:
887 break;
888 }
889
890 if (clk_src->bios->funcs->set_pixel_clock(
891 clk_src->bios, &bp_pc_params) != BP_RESULT_OK)
892 return false;
893 /* Enable SS
894 * ATOMBIOS will enable by default SS for DP on PLL ( DP ID clock),
895 * based on HW display PLL team, SS control settings should be programmed
896 * during PLL Reset, but they do not have effect
897 * until SS_EN is asserted.*/
898 if (clock_source->id != CLOCK_SOURCE_ID_EXTERNAL
899 && !dc_is_dp_signal(pix_clk_params->signal_type)) {
900
901 if (pix_clk_params->flags.ENABLE_SS)
902 if (!enable_spread_spectrum(clk_src,
903 pix_clk_params->signal_type,
904 pll_settings))
905 return false;
906
907 /* Resync deep color DTO */
908 dce110_program_pixel_clk_resync(clk_src,
909 pix_clk_params->signal_type,
910 pix_clk_params->color_depth);
911 }
912
913 return true;
914 }
915
dce112_program_pix_clk(struct clock_source * clock_source,struct pixel_clk_params * pix_clk_params,struct pll_settings * pll_settings)916 static bool dce112_program_pix_clk(
917 struct clock_source *clock_source,
918 struct pixel_clk_params *pix_clk_params,
919 struct pll_settings *pll_settings)
920 {
921 struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source);
922 struct bp_pixel_clock_parameters bp_pc_params = {0};
923
924 #if defined(CONFIG_DRM_AMD_DC_DCN)
925 if (IS_FPGA_MAXIMUS_DC(clock_source->ctx->dce_environment)) {
926 unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0;
927 unsigned dp_dto_ref_100hz = 7000000;
928 unsigned clock_100hz = pll_settings->actual_pix_clk_100hz;
929
930 /* Set DTO values: phase = target clock, modulo = reference clock */
931 REG_WRITE(PHASE[inst], clock_100hz);
932 REG_WRITE(MODULO[inst], dp_dto_ref_100hz);
933
934 /* Enable DTO */
935 REG_UPDATE(PIXEL_RATE_CNTL[inst], DP_DTO0_ENABLE, 1);
936 return true;
937 }
938 #endif
939 /* First disable SS
940 * ATOMBIOS will enable by default SS on PLL for DP,
941 * do not disable it here
942 */
943 if (clock_source->id != CLOCK_SOURCE_ID_EXTERNAL &&
944 !dc_is_dp_signal(pix_clk_params->signal_type) &&
945 clock_source->ctx->dce_version <= DCE_VERSION_11_0)
946 disable_spread_spectrum(clk_src);
947
948 /*ATOMBIOS expects pixel rate adjusted by deep color ratio)*/
949 bp_pc_params.controller_id = pix_clk_params->controller_id;
950 bp_pc_params.pll_id = clock_source->id;
951 bp_pc_params.target_pixel_clock_100hz = pll_settings->actual_pix_clk_100hz;
952 bp_pc_params.encoder_object_id = pix_clk_params->encoder_object_id;
953 bp_pc_params.signal_type = pix_clk_params->signal_type;
954
955 if (clock_source->id != CLOCK_SOURCE_ID_DP_DTO) {
956 bp_pc_params.flags.SET_GENLOCK_REF_DIV_SRC =
957 pll_settings->use_external_clk;
958 bp_pc_params.flags.SET_XTALIN_REF_SRC =
959 !pll_settings->use_external_clk;
960 if (pix_clk_params->flags.SUPPORT_YCBCR420) {
961 bp_pc_params.flags.SUPPORT_YUV_420 = 1;
962 }
963 }
964 if (clk_src->bios->funcs->set_pixel_clock(
965 clk_src->bios, &bp_pc_params) != BP_RESULT_OK)
966 return false;
967 /* Resync deep color DTO */
968 if (clock_source->id != CLOCK_SOURCE_ID_DP_DTO)
969 dce112_program_pixel_clk_resync(clk_src,
970 pix_clk_params->signal_type,
971 pix_clk_params->color_depth,
972 pix_clk_params->flags.SUPPORT_YCBCR420);
973
974 return true;
975 }
976
977
dce110_clock_source_power_down(struct clock_source * clk_src)978 static bool dce110_clock_source_power_down(
979 struct clock_source *clk_src)
980 {
981 struct dce110_clk_src *dce110_clk_src = TO_DCE110_CLK_SRC(clk_src);
982 enum bp_result bp_result;
983 struct bp_pixel_clock_parameters bp_pixel_clock_params = {0};
984
985 if (clk_src->dp_clk_src)
986 return true;
987
988 /* If Pixel Clock is 0 it means Power Down Pll*/
989 bp_pixel_clock_params.controller_id = CONTROLLER_ID_UNDEFINED;
990 bp_pixel_clock_params.pll_id = clk_src->id;
991 bp_pixel_clock_params.flags.FORCE_PROGRAMMING_OF_PLL = 1;
992
993 /*Call ASICControl to process ATOMBIOS Exec table*/
994 bp_result = dce110_clk_src->bios->funcs->set_pixel_clock(
995 dce110_clk_src->bios,
996 &bp_pixel_clock_params);
997
998 return bp_result == BP_RESULT_OK;
999 }
1000
get_pixel_clk_frequency_100hz(const struct clock_source * clock_source,unsigned int inst,unsigned int * pixel_clk_khz)1001 static bool get_pixel_clk_frequency_100hz(
1002 const struct clock_source *clock_source,
1003 unsigned int inst,
1004 unsigned int *pixel_clk_khz)
1005 {
1006 struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source);
1007 unsigned int clock_hz = 0;
1008
1009 if (clock_source->id == CLOCK_SOURCE_ID_DP_DTO) {
1010 clock_hz = REG_READ(PHASE[inst]);
1011
1012 /* NOTE: There is agreement with VBIOS here that MODULO is
1013 * programmed equal to DPREFCLK, in which case PHASE will be
1014 * equivalent to pixel clock.
1015 */
1016 *pixel_clk_khz = clock_hz / 100;
1017 return true;
1018 }
1019
1020 return false;
1021 }
1022
1023 #if defined(CONFIG_DRM_AMD_DC_DCN3_0)
1024 /* this table is use to find *1.001 and /1.001 pixel rates from non-precise pixel rate */
1025 const struct pixel_rate_range_table_entry video_optimized_pixel_rates[] = {
1026 // /1.001 rates
1027 {25170, 25180, 25200, 1000, 1001}, //25.2MHz -> 25.17
1028 {59340, 59350, 59400, 1000, 1001}, //59.4Mhz -> 59.340
1029 {74170, 74180, 74250, 1000, 1001}, //74.25Mhz -> 74.1758
1030 {125870, 125880, 126000, 1000, 1001}, //126Mhz -> 125.87
1031 {148350, 148360, 148500, 1000, 1001}, //148.5Mhz -> 148.3516
1032 {167830, 167840, 168000, 1000, 1001}, //168Mhz -> 167.83
1033 {222520, 222530, 222750, 1000, 1001}, //222.75Mhz -> 222.527
1034 {257140, 257150, 257400, 1000, 1001}, //257.4Mhz -> 257.1429
1035 {296700, 296710, 297000, 1000, 1001}, //297Mhz -> 296.7033
1036 {342850, 342860, 343200, 1000, 1001}, //343.2Mhz -> 342.857
1037 {395600, 395610, 396000, 1000, 1001}, //396Mhz -> 395.6
1038 {409090, 409100, 409500, 1000, 1001}, //409.5Mhz -> 409.091
1039 {445050, 445060, 445500, 1000, 1001}, //445.5Mhz -> 445.055
1040 {467530, 467540, 468000, 1000, 1001}, //468Mhz -> 467.5325
1041 {519230, 519240, 519750, 1000, 1001}, //519.75Mhz -> 519.231
1042 {525970, 525980, 526500, 1000, 1001}, //526.5Mhz -> 525.974
1043 {545450, 545460, 546000, 1000, 1001}, //546Mhz -> 545.455
1044 {593400, 593410, 594000, 1000, 1001}, //594Mhz -> 593.4066
1045 {623370, 623380, 624000, 1000, 1001}, //624Mhz -> 623.377
1046 {692300, 692310, 693000, 1000, 1001}, //693Mhz -> 692.308
1047 {701290, 701300, 702000, 1000, 1001}, //702Mhz -> 701.2987
1048 {791200, 791210, 792000, 1000, 1001}, //792Mhz -> 791.209
1049 {890100, 890110, 891000, 1000, 1001}, //891Mhz -> 890.1099
1050 {1186810, 1186820, 1188000, 1000, 1001},//1188Mhz -> 1186.8131
1051
1052 // *1.001 rates
1053 {27020, 27030, 27000, 1001, 1000}, //27Mhz
1054 {54050, 54060, 54000, 1001, 1000}, //54Mhz
1055 {108100, 108110, 108000, 1001, 1000},//108Mhz
1056 };
1057
look_up_in_video_optimized_rate_tlb(unsigned int pixel_rate_khz)1058 const struct pixel_rate_range_table_entry *look_up_in_video_optimized_rate_tlb(
1059 unsigned int pixel_rate_khz)
1060 {
1061 int i;
1062
1063 for (i = 0; i < NUM_ELEMENTS(video_optimized_pixel_rates); i++) {
1064 const struct pixel_rate_range_table_entry *e = &video_optimized_pixel_rates[i];
1065
1066 if (e->range_min_khz <= pixel_rate_khz && pixel_rate_khz <= e->range_max_khz) {
1067 return e;
1068 }
1069 }
1070
1071 return NULL;
1072 }
1073 #endif
1074
dcn20_program_pix_clk(struct clock_source * clock_source,struct pixel_clk_params * pix_clk_params,struct pll_settings * pll_settings)1075 static bool dcn20_program_pix_clk(
1076 struct clock_source *clock_source,
1077 struct pixel_clk_params *pix_clk_params,
1078 struct pll_settings *pll_settings)
1079 {
1080 dce112_program_pix_clk(clock_source, pix_clk_params, pll_settings);
1081
1082 return true;
1083 }
1084
1085 static const struct clock_source_funcs dcn20_clk_src_funcs = {
1086 .cs_power_down = dce110_clock_source_power_down,
1087 .program_pix_clk = dcn20_program_pix_clk,
1088 .get_pix_clk_dividers = dce112_get_pix_clk_dividers,
1089 .get_pixel_clk_frequency_100hz = get_pixel_clk_frequency_100hz
1090 };
1091
1092 #if defined(CONFIG_DRM_AMD_DC_DCN3_0)
dcn3_program_pix_clk(struct clock_source * clock_source,struct pixel_clk_params * pix_clk_params,struct pll_settings * pll_settings)1093 static bool dcn3_program_pix_clk(
1094 struct clock_source *clock_source,
1095 struct pixel_clk_params *pix_clk_params,
1096 struct pll_settings *pll_settings)
1097 {
1098 struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source);
1099 unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0;
1100 unsigned int dp_dto_ref_khz = clock_source->ctx->dc->clk_mgr->dprefclk_khz;
1101 const struct pixel_rate_range_table_entry *e =
1102 look_up_in_video_optimized_rate_tlb(pix_clk_params->requested_pix_clk_100hz / 10);
1103
1104 // For these signal types Driver to program DP_DTO without calling VBIOS Command table
1105 if (dc_is_dp_signal(pix_clk_params->signal_type)) {
1106 if (e) {
1107 /* Set DTO values: phase = target clock, modulo = reference clock*/
1108 REG_WRITE(PHASE[inst], e->target_pixel_rate_khz * e->mult_factor);
1109 REG_WRITE(MODULO[inst], dp_dto_ref_khz * e->div_factor);
1110 } else {
1111 /* Set DTO values: phase = target clock, modulo = reference clock*/
1112 REG_WRITE(PHASE[inst], pll_settings->actual_pix_clk_100hz * 100);
1113 REG_WRITE(MODULO[inst], dp_dto_ref_khz * 1000);
1114 }
1115 REG_UPDATE(PIXEL_RATE_CNTL[inst], DP_DTO0_ENABLE, 1);
1116 } else
1117 // For other signal types(HDMI_TYPE_A, DVI) Driver still to call VBIOS Command table
1118 dce112_program_pix_clk(clock_source, pix_clk_params, pll_settings);
1119
1120 return true;
1121 }
1122
dcn3_get_pix_clk_dividers(struct clock_source * cs,struct pixel_clk_params * pix_clk_params,struct pll_settings * pll_settings)1123 static uint32_t dcn3_get_pix_clk_dividers(
1124 struct clock_source *cs,
1125 struct pixel_clk_params *pix_clk_params,
1126 struct pll_settings *pll_settings)
1127 {
1128 unsigned long long actual_pix_clk_100Hz = pix_clk_params->requested_pix_clk_100hz;
1129 struct dce110_clk_src *clk_src;
1130
1131 clk_src = TO_DCE110_CLK_SRC(cs);
1132 DC_LOGGER_INIT();
1133
1134 if (pix_clk_params == NULL || pll_settings == NULL
1135 || pix_clk_params->requested_pix_clk_100hz == 0) {
1136 DC_LOG_ERROR(
1137 "%s: Invalid parameters!!\n", __func__);
1138 return -1;
1139 }
1140
1141 memset(pll_settings, 0, sizeof(*pll_settings));
1142 /* Adjust for HDMI Type A deep color */
1143 if (pix_clk_params->signal_type == SIGNAL_TYPE_HDMI_TYPE_A) {
1144 switch (pix_clk_params->color_depth) {
1145 case COLOR_DEPTH_101010:
1146 actual_pix_clk_100Hz = (actual_pix_clk_100Hz * 5) >> 2;
1147 break;
1148 case COLOR_DEPTH_121212:
1149 actual_pix_clk_100Hz = (actual_pix_clk_100Hz * 6) >> 2;
1150 break;
1151 case COLOR_DEPTH_161616:
1152 actual_pix_clk_100Hz = actual_pix_clk_100Hz * 2;
1153 break;
1154 default:
1155 break;
1156 }
1157 }
1158 pll_settings->actual_pix_clk_100hz = (unsigned int) actual_pix_clk_100Hz;
1159 pll_settings->adjusted_pix_clk_100hz = (unsigned int) actual_pix_clk_100Hz;
1160 pll_settings->calculated_pix_clk_100hz = (unsigned int) actual_pix_clk_100Hz;
1161
1162 return 0;
1163 }
1164
1165 static const struct clock_source_funcs dcn3_clk_src_funcs = {
1166 .cs_power_down = dce110_clock_source_power_down,
1167 .program_pix_clk = dcn3_program_pix_clk,
1168 .get_pix_clk_dividers = dcn3_get_pix_clk_dividers,
1169 .get_pixel_clk_frequency_100hz = get_pixel_clk_frequency_100hz
1170 };
1171 #endif
1172 /*****************************************/
1173 /* Constructor */
1174 /*****************************************/
1175
1176 static const struct clock_source_funcs dce112_clk_src_funcs = {
1177 .cs_power_down = dce110_clock_source_power_down,
1178 .program_pix_clk = dce112_program_pix_clk,
1179 .get_pix_clk_dividers = dce112_get_pix_clk_dividers,
1180 .get_pixel_clk_frequency_100hz = get_pixel_clk_frequency_100hz
1181 };
1182 static const struct clock_source_funcs dce110_clk_src_funcs = {
1183 .cs_power_down = dce110_clock_source_power_down,
1184 .program_pix_clk = dce110_program_pix_clk,
1185 .get_pix_clk_dividers = dce110_get_pix_clk_dividers,
1186 .get_pixel_clk_frequency_100hz = get_pixel_clk_frequency_100hz
1187 };
1188
1189
get_ss_info_from_atombios(struct dce110_clk_src * clk_src,enum as_signal_type as_signal,struct spread_spectrum_data * spread_spectrum_data[],uint32_t * ss_entries_num)1190 static void get_ss_info_from_atombios(
1191 struct dce110_clk_src *clk_src,
1192 enum as_signal_type as_signal,
1193 struct spread_spectrum_data *spread_spectrum_data[],
1194 uint32_t *ss_entries_num)
1195 {
1196 enum bp_result bp_result = BP_RESULT_FAILURE;
1197 struct spread_spectrum_info *ss_info;
1198 struct spread_spectrum_data *ss_data;
1199 struct spread_spectrum_info *ss_info_cur;
1200 struct spread_spectrum_data *ss_data_cur;
1201 uint32_t i;
1202 DC_LOGGER_INIT();
1203 if (ss_entries_num == NULL) {
1204 DC_LOG_SYNC(
1205 "Invalid entry !!!\n");
1206 return;
1207 }
1208 if (spread_spectrum_data == NULL) {
1209 DC_LOG_SYNC(
1210 "Invalid array pointer!!!\n");
1211 return;
1212 }
1213
1214 spread_spectrum_data[0] = NULL;
1215 *ss_entries_num = 0;
1216
1217 *ss_entries_num = clk_src->bios->funcs->get_ss_entry_number(
1218 clk_src->bios,
1219 as_signal);
1220
1221 if (*ss_entries_num == 0)
1222 return;
1223
1224 ss_info = kcalloc(*ss_entries_num,
1225 sizeof(struct spread_spectrum_info),
1226 GFP_KERNEL);
1227 ss_info_cur = ss_info;
1228 if (ss_info == NULL)
1229 return;
1230
1231 ss_data = kcalloc(*ss_entries_num,
1232 sizeof(struct spread_spectrum_data),
1233 GFP_KERNEL);
1234 if (ss_data == NULL)
1235 goto out_free_info;
1236
1237 for (i = 0, ss_info_cur = ss_info;
1238 i < (*ss_entries_num);
1239 ++i, ++ss_info_cur) {
1240
1241 bp_result = clk_src->bios->funcs->get_spread_spectrum_info(
1242 clk_src->bios,
1243 as_signal,
1244 i,
1245 ss_info_cur);
1246
1247 if (bp_result != BP_RESULT_OK)
1248 goto out_free_data;
1249 }
1250
1251 for (i = 0, ss_info_cur = ss_info, ss_data_cur = ss_data;
1252 i < (*ss_entries_num);
1253 ++i, ++ss_info_cur, ++ss_data_cur) {
1254
1255 if (ss_info_cur->type.STEP_AND_DELAY_INFO != false) {
1256 DC_LOG_SYNC(
1257 "Invalid ATOMBIOS SS Table!!!\n");
1258 goto out_free_data;
1259 }
1260
1261 /* for HDMI check SS percentage,
1262 * if it is > 6 (0.06%), the ATOMBIOS table info is invalid*/
1263 if (as_signal == AS_SIGNAL_TYPE_HDMI
1264 && ss_info_cur->spread_spectrum_percentage > 6){
1265 /* invalid input, do nothing */
1266 DC_LOG_SYNC(
1267 "Invalid SS percentage ");
1268 DC_LOG_SYNC(
1269 "for HDMI in ATOMBIOS info Table!!!\n");
1270 continue;
1271 }
1272 if (ss_info_cur->spread_percentage_divider == 1000) {
1273 /* Keep previous precision from ATOMBIOS for these
1274 * in case new precision set by ATOMBIOS for these
1275 * (otherwise all code in DCE specific classes
1276 * for all previous ASICs would need
1277 * to be updated for SS calculations,
1278 * Audio SS compensation and DP DTO SS compensation
1279 * which assumes fixed SS percentage Divider = 100)*/
1280 ss_info_cur->spread_spectrum_percentage /= 10;
1281 ss_info_cur->spread_percentage_divider = 100;
1282 }
1283
1284 ss_data_cur->freq_range_khz = ss_info_cur->target_clock_range;
1285 ss_data_cur->percentage =
1286 ss_info_cur->spread_spectrum_percentage;
1287 ss_data_cur->percentage_divider =
1288 ss_info_cur->spread_percentage_divider;
1289 ss_data_cur->modulation_freq_hz =
1290 ss_info_cur->spread_spectrum_range;
1291
1292 if (ss_info_cur->type.CENTER_MODE)
1293 ss_data_cur->flags.CENTER_SPREAD = 1;
1294
1295 if (ss_info_cur->type.EXTERNAL)
1296 ss_data_cur->flags.EXTERNAL_SS = 1;
1297
1298 }
1299
1300 *spread_spectrum_data = ss_data;
1301 kfree(ss_info);
1302 return;
1303
1304 out_free_data:
1305 kfree(ss_data);
1306 *ss_entries_num = 0;
1307 out_free_info:
1308 kfree(ss_info);
1309 }
1310
ss_info_from_atombios_create(struct dce110_clk_src * clk_src)1311 static void ss_info_from_atombios_create(
1312 struct dce110_clk_src *clk_src)
1313 {
1314 get_ss_info_from_atombios(
1315 clk_src,
1316 AS_SIGNAL_TYPE_DISPLAY_PORT,
1317 &clk_src->dp_ss_params,
1318 &clk_src->dp_ss_params_cnt);
1319 get_ss_info_from_atombios(
1320 clk_src,
1321 AS_SIGNAL_TYPE_HDMI,
1322 &clk_src->hdmi_ss_params,
1323 &clk_src->hdmi_ss_params_cnt);
1324 get_ss_info_from_atombios(
1325 clk_src,
1326 AS_SIGNAL_TYPE_DVI,
1327 &clk_src->dvi_ss_params,
1328 &clk_src->dvi_ss_params_cnt);
1329 get_ss_info_from_atombios(
1330 clk_src,
1331 AS_SIGNAL_TYPE_LVDS,
1332 &clk_src->lvds_ss_params,
1333 &clk_src->lvds_ss_params_cnt);
1334 }
1335
calc_pll_max_vco_construct(struct calc_pll_clock_source * calc_pll_cs,struct calc_pll_clock_source_init_data * init_data)1336 static bool calc_pll_max_vco_construct(
1337 struct calc_pll_clock_source *calc_pll_cs,
1338 struct calc_pll_clock_source_init_data *init_data)
1339 {
1340 uint32_t i;
1341 struct dc_firmware_info *fw_info;
1342 if (calc_pll_cs == NULL ||
1343 init_data == NULL ||
1344 init_data->bp == NULL)
1345 return false;
1346
1347 if (!init_data->bp->fw_info_valid)
1348 return false;
1349
1350 fw_info = &init_data->bp->fw_info;
1351 calc_pll_cs->ctx = init_data->ctx;
1352 calc_pll_cs->ref_freq_khz = fw_info->pll_info.crystal_frequency;
1353 calc_pll_cs->min_vco_khz =
1354 fw_info->pll_info.min_output_pxl_clk_pll_frequency;
1355 calc_pll_cs->max_vco_khz =
1356 fw_info->pll_info.max_output_pxl_clk_pll_frequency;
1357
1358 if (init_data->max_override_input_pxl_clk_pll_freq_khz != 0)
1359 calc_pll_cs->max_pll_input_freq_khz =
1360 init_data->max_override_input_pxl_clk_pll_freq_khz;
1361 else
1362 calc_pll_cs->max_pll_input_freq_khz =
1363 fw_info->pll_info.max_input_pxl_clk_pll_frequency;
1364
1365 if (init_data->min_override_input_pxl_clk_pll_freq_khz != 0)
1366 calc_pll_cs->min_pll_input_freq_khz =
1367 init_data->min_override_input_pxl_clk_pll_freq_khz;
1368 else
1369 calc_pll_cs->min_pll_input_freq_khz =
1370 fw_info->pll_info.min_input_pxl_clk_pll_frequency;
1371
1372 calc_pll_cs->min_pix_clock_pll_post_divider =
1373 init_data->min_pix_clk_pll_post_divider;
1374 calc_pll_cs->max_pix_clock_pll_post_divider =
1375 init_data->max_pix_clk_pll_post_divider;
1376 calc_pll_cs->min_pll_ref_divider =
1377 init_data->min_pll_ref_divider;
1378 calc_pll_cs->max_pll_ref_divider =
1379 init_data->max_pll_ref_divider;
1380
1381 if (init_data->num_fract_fb_divider_decimal_point == 0 ||
1382 init_data->num_fract_fb_divider_decimal_point_precision >
1383 init_data->num_fract_fb_divider_decimal_point) {
1384 DC_LOG_ERROR(
1385 "The dec point num or precision is incorrect!");
1386 return false;
1387 }
1388 if (init_data->num_fract_fb_divider_decimal_point_precision == 0) {
1389 DC_LOG_ERROR(
1390 "Incorrect fract feedback divider precision num!");
1391 return false;
1392 }
1393
1394 calc_pll_cs->fract_fb_divider_decimal_points_num =
1395 init_data->num_fract_fb_divider_decimal_point;
1396 calc_pll_cs->fract_fb_divider_precision =
1397 init_data->num_fract_fb_divider_decimal_point_precision;
1398 calc_pll_cs->fract_fb_divider_factor = 1;
1399 for (i = 0; i < calc_pll_cs->fract_fb_divider_decimal_points_num; ++i)
1400 calc_pll_cs->fract_fb_divider_factor *= 10;
1401
1402 calc_pll_cs->fract_fb_divider_precision_factor = 1;
1403 for (
1404 i = 0;
1405 i < (calc_pll_cs->fract_fb_divider_decimal_points_num -
1406 calc_pll_cs->fract_fb_divider_precision);
1407 ++i)
1408 calc_pll_cs->fract_fb_divider_precision_factor *= 10;
1409
1410 return true;
1411 }
1412
dce110_clk_src_construct(struct dce110_clk_src * clk_src,struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,const struct dce110_clk_src_shift * cs_shift,const struct dce110_clk_src_mask * cs_mask)1413 bool dce110_clk_src_construct(
1414 struct dce110_clk_src *clk_src,
1415 struct dc_context *ctx,
1416 struct dc_bios *bios,
1417 enum clock_source_id id,
1418 const struct dce110_clk_src_regs *regs,
1419 const struct dce110_clk_src_shift *cs_shift,
1420 const struct dce110_clk_src_mask *cs_mask)
1421 {
1422 struct calc_pll_clock_source_init_data calc_pll_cs_init_data_hdmi;
1423 struct calc_pll_clock_source_init_data calc_pll_cs_init_data;
1424
1425 clk_src->base.ctx = ctx;
1426 clk_src->bios = bios;
1427 clk_src->base.id = id;
1428 clk_src->base.funcs = &dce110_clk_src_funcs;
1429
1430 clk_src->regs = regs;
1431 clk_src->cs_shift = cs_shift;
1432 clk_src->cs_mask = cs_mask;
1433
1434 if (!clk_src->bios->fw_info_valid) {
1435 ASSERT_CRITICAL(false);
1436 goto unexpected_failure;
1437 }
1438
1439 clk_src->ext_clk_khz = clk_src->bios->fw_info.external_clock_source_frequency_for_dp;
1440
1441 /* structure normally used with PLL ranges from ATOMBIOS; DS on by default */
1442 calc_pll_cs_init_data.bp = bios;
1443 calc_pll_cs_init_data.min_pix_clk_pll_post_divider = 1;
1444 calc_pll_cs_init_data.max_pix_clk_pll_post_divider =
1445 clk_src->cs_mask->PLL_POST_DIV_PIXCLK;
1446 calc_pll_cs_init_data.min_pll_ref_divider = 1;
1447 calc_pll_cs_init_data.max_pll_ref_divider = clk_src->cs_mask->PLL_REF_DIV;
1448 /* when 0 use minInputPxlClkPLLFrequencyInKHz from firmwareInfo*/
1449 calc_pll_cs_init_data.min_override_input_pxl_clk_pll_freq_khz = 0;
1450 /* when 0 use maxInputPxlClkPLLFrequencyInKHz from firmwareInfo*/
1451 calc_pll_cs_init_data.max_override_input_pxl_clk_pll_freq_khz = 0;
1452 /*numberOfFractFBDividerDecimalPoints*/
1453 calc_pll_cs_init_data.num_fract_fb_divider_decimal_point =
1454 FRACT_FB_DIVIDER_DEC_POINTS_MAX_NUM;
1455 /*number of decimal point to round off for fractional feedback divider value*/
1456 calc_pll_cs_init_data.num_fract_fb_divider_decimal_point_precision =
1457 FRACT_FB_DIVIDER_DEC_POINTS_MAX_NUM;
1458 calc_pll_cs_init_data.ctx = ctx;
1459
1460 /*structure for HDMI, no SS or SS% <= 0.06% for 27 MHz Ref clock */
1461 calc_pll_cs_init_data_hdmi.bp = bios;
1462 calc_pll_cs_init_data_hdmi.min_pix_clk_pll_post_divider = 1;
1463 calc_pll_cs_init_data_hdmi.max_pix_clk_pll_post_divider =
1464 clk_src->cs_mask->PLL_POST_DIV_PIXCLK;
1465 calc_pll_cs_init_data_hdmi.min_pll_ref_divider = 1;
1466 calc_pll_cs_init_data_hdmi.max_pll_ref_divider = clk_src->cs_mask->PLL_REF_DIV;
1467 /* when 0 use minInputPxlClkPLLFrequencyInKHz from firmwareInfo*/
1468 calc_pll_cs_init_data_hdmi.min_override_input_pxl_clk_pll_freq_khz = 13500;
1469 /* when 0 use maxInputPxlClkPLLFrequencyInKHz from firmwareInfo*/
1470 calc_pll_cs_init_data_hdmi.max_override_input_pxl_clk_pll_freq_khz = 27000;
1471 /*numberOfFractFBDividerDecimalPoints*/
1472 calc_pll_cs_init_data_hdmi.num_fract_fb_divider_decimal_point =
1473 FRACT_FB_DIVIDER_DEC_POINTS_MAX_NUM;
1474 /*number of decimal point to round off for fractional feedback divider value*/
1475 calc_pll_cs_init_data_hdmi.num_fract_fb_divider_decimal_point_precision =
1476 FRACT_FB_DIVIDER_DEC_POINTS_MAX_NUM;
1477 calc_pll_cs_init_data_hdmi.ctx = ctx;
1478
1479 clk_src->ref_freq_khz = clk_src->bios->fw_info.pll_info.crystal_frequency;
1480
1481 if (clk_src->base.id == CLOCK_SOURCE_ID_EXTERNAL)
1482 return true;
1483
1484 /* PLL only from here on */
1485 ss_info_from_atombios_create(clk_src);
1486
1487 if (!calc_pll_max_vco_construct(
1488 &clk_src->calc_pll,
1489 &calc_pll_cs_init_data)) {
1490 ASSERT_CRITICAL(false);
1491 goto unexpected_failure;
1492 }
1493
1494
1495 calc_pll_cs_init_data_hdmi.
1496 min_override_input_pxl_clk_pll_freq_khz = clk_src->ref_freq_khz/2;
1497 calc_pll_cs_init_data_hdmi.
1498 max_override_input_pxl_clk_pll_freq_khz = clk_src->ref_freq_khz;
1499
1500
1501 if (!calc_pll_max_vco_construct(
1502 &clk_src->calc_pll_hdmi, &calc_pll_cs_init_data_hdmi)) {
1503 ASSERT_CRITICAL(false);
1504 goto unexpected_failure;
1505 }
1506
1507 return true;
1508
1509 unexpected_failure:
1510 return false;
1511 }
1512
dce112_clk_src_construct(struct dce110_clk_src * clk_src,struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,const struct dce110_clk_src_shift * cs_shift,const struct dce110_clk_src_mask * cs_mask)1513 bool dce112_clk_src_construct(
1514 struct dce110_clk_src *clk_src,
1515 struct dc_context *ctx,
1516 struct dc_bios *bios,
1517 enum clock_source_id id,
1518 const struct dce110_clk_src_regs *regs,
1519 const struct dce110_clk_src_shift *cs_shift,
1520 const struct dce110_clk_src_mask *cs_mask)
1521 {
1522 clk_src->base.ctx = ctx;
1523 clk_src->bios = bios;
1524 clk_src->base.id = id;
1525 clk_src->base.funcs = &dce112_clk_src_funcs;
1526
1527 clk_src->regs = regs;
1528 clk_src->cs_shift = cs_shift;
1529 clk_src->cs_mask = cs_mask;
1530
1531 if (!clk_src->bios->fw_info_valid) {
1532 ASSERT_CRITICAL(false);
1533 return false;
1534 }
1535
1536 clk_src->ext_clk_khz = clk_src->bios->fw_info.external_clock_source_frequency_for_dp;
1537
1538 return true;
1539 }
1540
dcn20_clk_src_construct(struct dce110_clk_src * clk_src,struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,const struct dce110_clk_src_shift * cs_shift,const struct dce110_clk_src_mask * cs_mask)1541 bool dcn20_clk_src_construct(
1542 struct dce110_clk_src *clk_src,
1543 struct dc_context *ctx,
1544 struct dc_bios *bios,
1545 enum clock_source_id id,
1546 const struct dce110_clk_src_regs *regs,
1547 const struct dce110_clk_src_shift *cs_shift,
1548 const struct dce110_clk_src_mask *cs_mask)
1549 {
1550 bool ret = dce112_clk_src_construct(clk_src, ctx, bios, id, regs, cs_shift, cs_mask);
1551
1552 clk_src->base.funcs = &dcn20_clk_src_funcs;
1553
1554 return ret;
1555 }
1556
1557 #if defined(CONFIG_DRM_AMD_DC_DCN3_0)
dcn3_clk_src_construct(struct dce110_clk_src * clk_src,struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,const struct dce110_clk_src_shift * cs_shift,const struct dce110_clk_src_mask * cs_mask)1558 bool dcn3_clk_src_construct(
1559 struct dce110_clk_src *clk_src,
1560 struct dc_context *ctx,
1561 struct dc_bios *bios,
1562 enum clock_source_id id,
1563 const struct dce110_clk_src_regs *regs,
1564 const struct dce110_clk_src_shift *cs_shift,
1565 const struct dce110_clk_src_mask *cs_mask)
1566 {
1567 bool ret = dce112_clk_src_construct(clk_src, ctx, bios, id, regs, cs_shift, cs_mask);
1568
1569 clk_src->base.funcs = &dcn3_clk_src_funcs;
1570
1571 return ret;
1572 }
1573 #endif
1574