1 /*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26
27 #include "dcn20_hubbub.h"
28 #include "reg_helper.h"
29 #include "clk_mgr.h"
30
31 #define REG(reg)\
32 hubbub1->regs->reg
33
34 #define CTX \
35 hubbub1->base.ctx
36
37 #undef FN
38 #define FN(reg_name, field_name) \
39 hubbub1->shifts->field_name, hubbub1->masks->field_name
40
41 #define REG(reg)\
42 hubbub1->regs->reg
43
44 #define CTX \
45 hubbub1->base.ctx
46
47 #undef FN
48 #define FN(reg_name, field_name) \
49 hubbub1->shifts->field_name, hubbub1->masks->field_name
50
51 #ifdef NUM_VMID
52 #undef NUM_VMID
53 #endif
54 #define NUM_VMID 16
55
hubbub2_dcc_support_swizzle(enum swizzle_mode_values swizzle,unsigned int bytes_per_element,enum segment_order * segment_order_horz,enum segment_order * segment_order_vert)56 bool hubbub2_dcc_support_swizzle(
57 enum swizzle_mode_values swizzle,
58 unsigned int bytes_per_element,
59 enum segment_order *segment_order_horz,
60 enum segment_order *segment_order_vert)
61 {
62 bool standard_swizzle = false;
63 bool display_swizzle = false;
64 bool render_swizzle = false;
65
66 switch (swizzle) {
67 case DC_SW_4KB_S:
68 case DC_SW_64KB_S:
69 case DC_SW_VAR_S:
70 case DC_SW_4KB_S_X:
71 case DC_SW_64KB_S_X:
72 case DC_SW_VAR_S_X:
73 standard_swizzle = true;
74 break;
75 case DC_SW_64KB_R_X:
76 render_swizzle = true;
77 break;
78 case DC_SW_4KB_D:
79 case DC_SW_64KB_D:
80 case DC_SW_VAR_D:
81 case DC_SW_4KB_D_X:
82 case DC_SW_64KB_D_X:
83 case DC_SW_VAR_D_X:
84 display_swizzle = true;
85 break;
86 default:
87 break;
88 }
89
90 if (standard_swizzle) {
91 if (bytes_per_element == 1) {
92 *segment_order_horz = segment_order__contiguous;
93 *segment_order_vert = segment_order__na;
94 return true;
95 }
96 if (bytes_per_element == 2) {
97 *segment_order_horz = segment_order__non_contiguous;
98 *segment_order_vert = segment_order__contiguous;
99 return true;
100 }
101 if (bytes_per_element == 4) {
102 *segment_order_horz = segment_order__non_contiguous;
103 *segment_order_vert = segment_order__contiguous;
104 return true;
105 }
106 if (bytes_per_element == 8) {
107 *segment_order_horz = segment_order__na;
108 *segment_order_vert = segment_order__contiguous;
109 return true;
110 }
111 }
112 if (render_swizzle) {
113 if (bytes_per_element == 2) {
114 *segment_order_horz = segment_order__contiguous;
115 *segment_order_vert = segment_order__contiguous;
116 return true;
117 }
118 if (bytes_per_element == 4) {
119 *segment_order_horz = segment_order__non_contiguous;
120 *segment_order_vert = segment_order__contiguous;
121 return true;
122 }
123 if (bytes_per_element == 8) {
124 *segment_order_horz = segment_order__contiguous;
125 *segment_order_vert = segment_order__non_contiguous;
126 return true;
127 }
128 }
129 if (display_swizzle && bytes_per_element == 8) {
130 *segment_order_horz = segment_order__contiguous;
131 *segment_order_vert = segment_order__non_contiguous;
132 return true;
133 }
134
135 return false;
136 }
137
hubbub2_dcc_support_pixel_format(enum surface_pixel_format format,unsigned int * bytes_per_element)138 bool hubbub2_dcc_support_pixel_format(
139 enum surface_pixel_format format,
140 unsigned int *bytes_per_element)
141 {
142 /* DML: get_bytes_per_element */
143 switch (format) {
144 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
145 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
146 *bytes_per_element = 2;
147 return true;
148 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
149 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
150 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
151 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
152 case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX:
153 case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX:
154 case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT:
155 case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT:
156 #if defined(CONFIG_DRM_AMD_DC_DCN3_0)
157 case SURFACE_PIXEL_FORMAT_GRPH_RGBE:
158 case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA:
159 #endif
160 *bytes_per_element = 4;
161 return true;
162 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
163 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
164 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
165 *bytes_per_element = 8;
166 return true;
167 default:
168 return false;
169 }
170 }
171
hubbub2_get_blk256_size(unsigned int * blk256_width,unsigned int * blk256_height,unsigned int bytes_per_element)172 static void hubbub2_get_blk256_size(unsigned int *blk256_width, unsigned int *blk256_height,
173 unsigned int bytes_per_element)
174 {
175 /* copied from DML. might want to refactor DML to leverage from DML */
176 /* DML : get_blk256_size */
177 if (bytes_per_element == 1) {
178 *blk256_width = 16;
179 *blk256_height = 16;
180 } else if (bytes_per_element == 2) {
181 *blk256_width = 16;
182 *blk256_height = 8;
183 } else if (bytes_per_element == 4) {
184 *blk256_width = 8;
185 *blk256_height = 8;
186 } else if (bytes_per_element == 8) {
187 *blk256_width = 8;
188 *blk256_height = 4;
189 }
190 }
191
hubbub2_det_request_size(unsigned int detile_buf_size,unsigned int height,unsigned int width,unsigned int bpe,bool * req128_horz_wc,bool * req128_vert_wc)192 static void hubbub2_det_request_size(
193 unsigned int detile_buf_size,
194 unsigned int height,
195 unsigned int width,
196 unsigned int bpe,
197 bool *req128_horz_wc,
198 bool *req128_vert_wc)
199 {
200 unsigned int blk256_height = 0;
201 unsigned int blk256_width = 0;
202 unsigned int swath_bytes_horz_wc, swath_bytes_vert_wc;
203
204 hubbub2_get_blk256_size(&blk256_width, &blk256_height, bpe);
205
206 swath_bytes_horz_wc = width * blk256_height * bpe;
207 swath_bytes_vert_wc = height * blk256_width * bpe;
208
209 *req128_horz_wc = (2 * swath_bytes_horz_wc <= detile_buf_size) ?
210 false : /* full 256B request */
211 true; /* half 128b request */
212
213 *req128_vert_wc = (2 * swath_bytes_vert_wc <= detile_buf_size) ?
214 false : /* full 256B request */
215 true; /* half 128b request */
216 }
217
hubbub2_get_dcc_compression_cap(struct hubbub * hubbub,const struct dc_dcc_surface_param * input,struct dc_surface_dcc_cap * output)218 bool hubbub2_get_dcc_compression_cap(struct hubbub *hubbub,
219 const struct dc_dcc_surface_param *input,
220 struct dc_surface_dcc_cap *output)
221 {
222 struct dc *dc = hubbub->ctx->dc;
223 /* implement section 1.6.2.1 of DCN1_Programming_Guide.docx */
224 enum dcc_control dcc_control;
225 unsigned int bpe;
226 enum segment_order segment_order_horz, segment_order_vert;
227 bool req128_horz_wc, req128_vert_wc;
228
229 memset(output, 0, sizeof(*output));
230
231 if (dc->debug.disable_dcc == DCC_DISABLE)
232 return false;
233
234 if (!hubbub->funcs->dcc_support_pixel_format(input->format,
235 &bpe))
236 return false;
237
238 if (!hubbub->funcs->dcc_support_swizzle(input->swizzle_mode, bpe,
239 &segment_order_horz, &segment_order_vert))
240 return false;
241
242 hubbub2_det_request_size(TO_DCN20_HUBBUB(hubbub)->detile_buf_size,
243 input->surface_size.height, input->surface_size.width,
244 bpe, &req128_horz_wc, &req128_vert_wc);
245
246 if (!req128_horz_wc && !req128_vert_wc) {
247 dcc_control = dcc_control__256_256_xxx;
248 } else if (input->scan == SCAN_DIRECTION_HORIZONTAL) {
249 if (!req128_horz_wc)
250 dcc_control = dcc_control__256_256_xxx;
251 else if (segment_order_horz == segment_order__contiguous)
252 dcc_control = dcc_control__128_128_xxx;
253 else
254 dcc_control = dcc_control__256_64_64;
255 } else if (input->scan == SCAN_DIRECTION_VERTICAL) {
256 if (!req128_vert_wc)
257 dcc_control = dcc_control__256_256_xxx;
258 else if (segment_order_vert == segment_order__contiguous)
259 dcc_control = dcc_control__128_128_xxx;
260 else
261 dcc_control = dcc_control__256_64_64;
262 } else {
263 if ((req128_horz_wc &&
264 segment_order_horz == segment_order__non_contiguous) ||
265 (req128_vert_wc &&
266 segment_order_vert == segment_order__non_contiguous))
267 /* access_dir not known, must use most constraining */
268 dcc_control = dcc_control__256_64_64;
269 else
270 /* reg128 is true for either horz and vert
271 * but segment_order is contiguous
272 */
273 dcc_control = dcc_control__128_128_xxx;
274 }
275
276 /* Exception for 64KB_R_X */
277 if ((bpe == 2) && (input->swizzle_mode == DC_SW_64KB_R_X))
278 dcc_control = dcc_control__128_128_xxx;
279
280 if (dc->debug.disable_dcc == DCC_HALF_REQ_DISALBE &&
281 dcc_control != dcc_control__256_256_xxx)
282 return false;
283
284 switch (dcc_control) {
285 case dcc_control__256_256_xxx:
286 output->grph.rgb.max_uncompressed_blk_size = 256;
287 output->grph.rgb.max_compressed_blk_size = 256;
288 output->grph.rgb.independent_64b_blks = false;
289 break;
290 case dcc_control__128_128_xxx:
291 output->grph.rgb.max_uncompressed_blk_size = 128;
292 output->grph.rgb.max_compressed_blk_size = 128;
293 output->grph.rgb.independent_64b_blks = false;
294 break;
295 case dcc_control__256_64_64:
296 output->grph.rgb.max_uncompressed_blk_size = 256;
297 output->grph.rgb.max_compressed_blk_size = 64;
298 output->grph.rgb.independent_64b_blks = true;
299 break;
300 default:
301 ASSERT(false);
302 break;
303 }
304 output->capable = true;
305 output->const_color_support = true;
306
307 return true;
308 }
309
page_table_depth_to_hw(unsigned int page_table_depth)310 static enum dcn_hubbub_page_table_depth page_table_depth_to_hw(unsigned int page_table_depth)
311 {
312 enum dcn_hubbub_page_table_depth depth = 0;
313
314 switch (page_table_depth) {
315 case 1:
316 depth = DCN_PAGE_TABLE_DEPTH_1_LEVEL;
317 break;
318 case 2:
319 depth = DCN_PAGE_TABLE_DEPTH_2_LEVEL;
320 break;
321 case 3:
322 depth = DCN_PAGE_TABLE_DEPTH_3_LEVEL;
323 break;
324 case 4:
325 depth = DCN_PAGE_TABLE_DEPTH_4_LEVEL;
326 break;
327 default:
328 ASSERT(false);
329 break;
330 }
331
332 return depth;
333 }
334
page_table_block_size_to_hw(unsigned int page_table_block_size)335 static enum dcn_hubbub_page_table_block_size page_table_block_size_to_hw(unsigned int page_table_block_size)
336 {
337 enum dcn_hubbub_page_table_block_size block_size = 0;
338
339 switch (page_table_block_size) {
340 case 4096:
341 block_size = DCN_PAGE_TABLE_BLOCK_SIZE_4KB;
342 break;
343 case 65536:
344 block_size = DCN_PAGE_TABLE_BLOCK_SIZE_64KB;
345 break;
346 #if defined(CONFIG_DRM_AMD_DC_DCN3_0)
347 case 32768:
348 block_size = DCN_PAGE_TABLE_BLOCK_SIZE_32KB;
349 break;
350 #endif
351 default:
352 ASSERT(false);
353 block_size = page_table_block_size;
354 break;
355 }
356
357 return block_size;
358 }
359
hubbub2_init_vm_ctx(struct hubbub * hubbub,struct dcn_hubbub_virt_addr_config * va_config,int vmid)360 void hubbub2_init_vm_ctx(struct hubbub *hubbub,
361 struct dcn_hubbub_virt_addr_config *va_config,
362 int vmid)
363 {
364 struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub);
365 struct dcn_vmid_page_table_config virt_config;
366
367 virt_config.page_table_start_addr = va_config->page_table_start_addr >> 12;
368 virt_config.page_table_end_addr = va_config->page_table_end_addr >> 12;
369 virt_config.depth = page_table_depth_to_hw(va_config->page_table_depth);
370 virt_config.block_size = page_table_block_size_to_hw(va_config->page_table_block_size);
371 virt_config.page_table_base_addr = va_config->page_table_base_addr;
372
373 dcn20_vmid_setup(&hubbub1->vmid[vmid], &virt_config);
374 }
375
hubbub2_init_dchub_sys_ctx(struct hubbub * hubbub,struct dcn_hubbub_phys_addr_config * pa_config)376 int hubbub2_init_dchub_sys_ctx(struct hubbub *hubbub,
377 struct dcn_hubbub_phys_addr_config *pa_config)
378 {
379 struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub);
380 struct dcn_vmid_page_table_config phys_config;
381
382 REG_SET(DCN_VM_FB_LOCATION_BASE, 0,
383 FB_BASE, pa_config->system_aperture.fb_base >> 24);
384 REG_SET(DCN_VM_FB_LOCATION_TOP, 0,
385 FB_TOP, pa_config->system_aperture.fb_top >> 24);
386 REG_SET(DCN_VM_FB_OFFSET, 0,
387 FB_OFFSET, pa_config->system_aperture.fb_offset >> 24);
388 REG_SET(DCN_VM_AGP_BOT, 0,
389 AGP_BOT, pa_config->system_aperture.agp_bot >> 24);
390 REG_SET(DCN_VM_AGP_TOP, 0,
391 AGP_TOP, pa_config->system_aperture.agp_top >> 24);
392 REG_SET(DCN_VM_AGP_BASE, 0,
393 AGP_BASE, pa_config->system_aperture.agp_base >> 24);
394
395 REG_SET(DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB, 0,
396 DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB, (pa_config->page_table_default_page_addr >> 44) & 0xF);
397 REG_SET(DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB, 0,
398 DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB, (pa_config->page_table_default_page_addr >> 12) & 0xFFFFFFFF);
399
400 if (pa_config->gart_config.page_table_start_addr != pa_config->gart_config.page_table_end_addr) {
401 phys_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr >> 12;
402 phys_config.page_table_end_addr = pa_config->gart_config.page_table_end_addr >> 12;
403 phys_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr;
404 phys_config.depth = 0;
405 phys_config.block_size = 0;
406 // Init VMID 0 based on PA config
407 dcn20_vmid_setup(&hubbub1->vmid[0], &phys_config);
408 }
409
410 return NUM_VMID;
411 }
412
hubbub2_update_dchub(struct hubbub * hubbub,struct dchub_init_data * dh_data)413 void hubbub2_update_dchub(struct hubbub *hubbub,
414 struct dchub_init_data *dh_data)
415 {
416 struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub);
417
418 if (REG(DCN_VM_FB_LOCATION_TOP) == 0)
419 return;
420
421 switch (dh_data->fb_mode) {
422 case FRAME_BUFFER_MODE_ZFB_ONLY:
423 /*For ZFB case need to put DCHUB FB BASE and TOP upside down to indicate ZFB mode*/
424 REG_UPDATE(DCN_VM_FB_LOCATION_TOP,
425 FB_TOP, 0);
426
427 REG_UPDATE(DCN_VM_FB_LOCATION_BASE,
428 FB_BASE, 0xFFFFFF);
429
430 /*This field defines the 24 MSBs, bits [47:24] of the 48 bit AGP Base*/
431 REG_UPDATE(DCN_VM_AGP_BASE,
432 AGP_BASE, dh_data->zfb_phys_addr_base >> 24);
433
434 /*This field defines the bottom range of the AGP aperture and represents the 24*/
435 /*MSBs, bits [47:24] of the 48 address bits*/
436 REG_UPDATE(DCN_VM_AGP_BOT,
437 AGP_BOT, dh_data->zfb_mc_base_addr >> 24);
438
439 /*This field defines the top range of the AGP aperture and represents the 24*/
440 /*MSBs, bits [47:24] of the 48 address bits*/
441 REG_UPDATE(DCN_VM_AGP_TOP,
442 AGP_TOP, (dh_data->zfb_mc_base_addr +
443 dh_data->zfb_size_in_byte - 1) >> 24);
444 break;
445 case FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL:
446 /*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/
447
448 /*This field defines the 24 MSBs, bits [47:24] of the 48 bit AGP Base*/
449 REG_UPDATE(DCN_VM_AGP_BASE,
450 AGP_BASE, dh_data->zfb_phys_addr_base >> 24);
451
452 /*This field defines the bottom range of the AGP aperture and represents the 24*/
453 /*MSBs, bits [47:24] of the 48 address bits*/
454 REG_UPDATE(DCN_VM_AGP_BOT,
455 AGP_BOT, dh_data->zfb_mc_base_addr >> 24);
456
457 /*This field defines the top range of the AGP aperture and represents the 24*/
458 /*MSBs, bits [47:24] of the 48 address bits*/
459 REG_UPDATE(DCN_VM_AGP_TOP,
460 AGP_TOP, (dh_data->zfb_mc_base_addr +
461 dh_data->zfb_size_in_byte - 1) >> 24);
462 break;
463 case FRAME_BUFFER_MODE_LOCAL_ONLY:
464 /*Should not touch FB LOCATION (should be done by VBIOS)*/
465
466 /*This field defines the 24 MSBs, bits [47:24] of the 48 bit AGP Base*/
467 REG_UPDATE(DCN_VM_AGP_BASE,
468 AGP_BASE, 0);
469
470 /*This field defines the bottom range of the AGP aperture and represents the 24*/
471 /*MSBs, bits [47:24] of the 48 address bits*/
472 REG_UPDATE(DCN_VM_AGP_BOT,
473 AGP_BOT, 0xFFFFFF);
474
475 /*This field defines the top range of the AGP aperture and represents the 24*/
476 /*MSBs, bits [47:24] of the 48 address bits*/
477 REG_UPDATE(DCN_VM_AGP_TOP,
478 AGP_TOP, 0);
479 break;
480 default:
481 break;
482 }
483
484 dh_data->dchub_initialzied = true;
485 dh_data->dchub_info_valid = false;
486 }
487
hubbub2_wm_read_state(struct hubbub * hubbub,struct dcn_hubbub_wm * wm)488 void hubbub2_wm_read_state(struct hubbub *hubbub,
489 struct dcn_hubbub_wm *wm)
490 {
491 struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub);
492
493 struct dcn_hubbub_wm_set *s;
494
495 memset(wm, 0, sizeof(struct dcn_hubbub_wm));
496
497 s = &wm->sets[0];
498 s->wm_set = 0;
499 s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A);
500 if (REG(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A))
501 s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A);
502 if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A)) {
503 s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A);
504 s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A);
505 }
506 s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A);
507
508 s = &wm->sets[1];
509 s->wm_set = 1;
510 s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B);
511 if (REG(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B))
512 s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B);
513 if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B)) {
514 s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B);
515 s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B);
516 }
517 s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B);
518
519 s = &wm->sets[2];
520 s->wm_set = 2;
521 s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C);
522 if (REG(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C))
523 s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C);
524 if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C)) {
525 s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C);
526 s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C);
527 }
528 s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C);
529
530 s = &wm->sets[3];
531 s->wm_set = 3;
532 s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D);
533 if (REG(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D))
534 s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D);
535 if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D)) {
536 s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D);
537 s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D);
538 }
539 s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D);
540 }
541
hubbub2_get_dchub_ref_freq(struct hubbub * hubbub,unsigned int dccg_ref_freq_inKhz,unsigned int * dchub_ref_freq_inKhz)542 void hubbub2_get_dchub_ref_freq(struct hubbub *hubbub,
543 unsigned int dccg_ref_freq_inKhz,
544 unsigned int *dchub_ref_freq_inKhz)
545 {
546 struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub);
547 uint32_t ref_div = 0;
548 uint32_t ref_en = 0;
549
550 REG_GET_2(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, &ref_div,
551 DCHUBBUB_GLOBAL_TIMER_ENABLE, &ref_en);
552
553 if (ref_en) {
554 if (ref_div == 2)
555 *dchub_ref_freq_inKhz = dccg_ref_freq_inKhz / 2;
556 else
557 *dchub_ref_freq_inKhz = dccg_ref_freq_inKhz;
558
559 // DC hub reference frequency must be around 50Mhz, otherwise there may be
560 // overflow/underflow issues when doing HUBBUB programming
561 if (*dchub_ref_freq_inKhz < 40000 || *dchub_ref_freq_inKhz > 60000)
562 ASSERT_CRITICAL(false);
563
564 return;
565 } else {
566 *dchub_ref_freq_inKhz = dccg_ref_freq_inKhz;
567
568 // HUBBUB global timer must be enabled.
569 ASSERT_CRITICAL(false);
570 return;
571 }
572 }
573
hubbub2_program_watermarks(struct hubbub * hubbub,struct dcn_watermark_set * watermarks,unsigned int refclk_mhz,bool safe_to_lower)574 static bool hubbub2_program_watermarks(
575 struct hubbub *hubbub,
576 struct dcn_watermark_set *watermarks,
577 unsigned int refclk_mhz,
578 bool safe_to_lower)
579 {
580 struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub);
581 bool wm_pending = false;
582 /*
583 * Need to clamp to max of the register values (i.e. no wrap)
584 * for dcn1, all wm registers are 21-bit wide
585 */
586 if (hubbub1_program_urgent_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower))
587 wm_pending = true;
588
589 if (hubbub1_program_stutter_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower))
590 wm_pending = true;
591
592 /*
593 * There's a special case when going from p-state support to p-state unsupported
594 * here we are going to LOWER watermarks to go to dummy p-state only, but this has
595 * to be done prepare_bandwidth, not optimize
596 */
597 if (hubbub1->base.ctx->dc->clk_mgr->clks.prev_p_state_change_support == true &&
598 hubbub1->base.ctx->dc->clk_mgr->clks.p_state_change_support == false)
599 safe_to_lower = true;
600
601 hubbub1_program_pstate_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower);
602
603 REG_SET(DCHUBBUB_ARB_SAT_LEVEL, 0,
604 DCHUBBUB_ARB_SAT_LEVEL, 60 * refclk_mhz);
605 REG_UPDATE(DCHUBBUB_ARB_DF_REQ_OUTSTAND, DCHUBBUB_ARB_MIN_REQ_OUTSTAND, 180);
606
607 hubbub->funcs->allow_self_refresh_control(hubbub, !hubbub->ctx->dc->debug.disable_stutter);
608 return wm_pending;
609 }
610
611 static const struct hubbub_funcs hubbub2_funcs = {
612 .update_dchub = hubbub2_update_dchub,
613 .init_dchub_sys_ctx = hubbub2_init_dchub_sys_ctx,
614 .init_vm_ctx = hubbub2_init_vm_ctx,
615 .dcc_support_swizzle = hubbub2_dcc_support_swizzle,
616 .dcc_support_pixel_format = hubbub2_dcc_support_pixel_format,
617 .get_dcc_compression_cap = hubbub2_get_dcc_compression_cap,
618 .wm_read_state = hubbub2_wm_read_state,
619 .get_dchub_ref_freq = hubbub2_get_dchub_ref_freq,
620 .program_watermarks = hubbub2_program_watermarks,
621 .is_allow_self_refresh_enabled = hubbub1_is_allow_self_refresh_enabled,
622 .allow_self_refresh_control = hubbub1_allow_self_refresh_control,
623 };
624
hubbub2_construct(struct dcn20_hubbub * hubbub,struct dc_context * ctx,const struct dcn_hubbub_registers * hubbub_regs,const struct dcn_hubbub_shift * hubbub_shift,const struct dcn_hubbub_mask * hubbub_mask)625 void hubbub2_construct(struct dcn20_hubbub *hubbub,
626 struct dc_context *ctx,
627 const struct dcn_hubbub_registers *hubbub_regs,
628 const struct dcn_hubbub_shift *hubbub_shift,
629 const struct dcn_hubbub_mask *hubbub_mask)
630 {
631 hubbub->base.ctx = ctx;
632
633 hubbub->base.funcs = &hubbub2_funcs;
634
635 hubbub->regs = hubbub_regs;
636 hubbub->shifts = hubbub_shift;
637 hubbub->masks = hubbub_mask;
638
639 hubbub->debug_test_index_pstate = 0xB;
640 hubbub->detile_buf_size = 164 * 1024; /* 164KB for DCN2.0 */
641 }
642