1 /*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include <linux/ratelimit.h>
25 #include <linux/printk.h>
26 #include <linux/slab.h>
27 #include <linux/list.h>
28 #include <linux/types.h>
29 #include <linux/bitops.h>
30 #include <linux/sched.h>
31 #include "kfd_priv.h"
32 #include "kfd_device_queue_manager.h"
33 #include "kfd_mqd_manager.h"
34 #include "cik_regs.h"
35 #include "kfd_kernel_queue.h"
36 #include "amdgpu_amdkfd.h"
37
38 /* Size of the per-pipe EOP queue */
39 #define CIK_HPD_EOP_BYTES_LOG2 11
40 #define CIK_HPD_EOP_BYTES (1U << CIK_HPD_EOP_BYTES_LOG2)
41
42 static int set_pasid_vmid_mapping(struct device_queue_manager *dqm,
43 u32 pasid, unsigned int vmid);
44
45 static int execute_queues_cpsch(struct device_queue_manager *dqm,
46 enum kfd_unmap_queues_filter filter,
47 uint32_t filter_param);
48 static int unmap_queues_cpsch(struct device_queue_manager *dqm,
49 enum kfd_unmap_queues_filter filter,
50 uint32_t filter_param);
51
52 static int map_queues_cpsch(struct device_queue_manager *dqm);
53
54 static void deallocate_sdma_queue(struct device_queue_manager *dqm,
55 struct queue *q);
56
57 static inline void deallocate_hqd(struct device_queue_manager *dqm,
58 struct queue *q);
59 static int allocate_hqd(struct device_queue_manager *dqm, struct queue *q);
60 static int allocate_sdma_queue(struct device_queue_manager *dqm,
61 struct queue *q);
62 static void kfd_process_hw_exception(struct work_struct *work);
63
64 static inline
get_mqd_type_from_queue_type(enum kfd_queue_type type)65 enum KFD_MQD_TYPE get_mqd_type_from_queue_type(enum kfd_queue_type type)
66 {
67 if (type == KFD_QUEUE_TYPE_SDMA || type == KFD_QUEUE_TYPE_SDMA_XGMI)
68 return KFD_MQD_TYPE_SDMA;
69 return KFD_MQD_TYPE_CP;
70 }
71
is_pipe_enabled(struct device_queue_manager * dqm,int mec,int pipe)72 static bool is_pipe_enabled(struct device_queue_manager *dqm, int mec, int pipe)
73 {
74 int i;
75 int pipe_offset = mec * dqm->dev->shared_resources.num_pipe_per_mec
76 + pipe * dqm->dev->shared_resources.num_queue_per_pipe;
77
78 /* queue is available for KFD usage if bit is 1 */
79 for (i = 0; i < dqm->dev->shared_resources.num_queue_per_pipe; ++i)
80 if (test_bit(pipe_offset + i,
81 dqm->dev->shared_resources.cp_queue_bitmap))
82 return true;
83 return false;
84 }
85
get_cp_queues_num(struct device_queue_manager * dqm)86 unsigned int get_cp_queues_num(struct device_queue_manager *dqm)
87 {
88 return bitmap_weight(dqm->dev->shared_resources.cp_queue_bitmap,
89 KGD_MAX_QUEUES);
90 }
91
get_queues_per_pipe(struct device_queue_manager * dqm)92 unsigned int get_queues_per_pipe(struct device_queue_manager *dqm)
93 {
94 return dqm->dev->shared_resources.num_queue_per_pipe;
95 }
96
get_pipes_per_mec(struct device_queue_manager * dqm)97 unsigned int get_pipes_per_mec(struct device_queue_manager *dqm)
98 {
99 return dqm->dev->shared_resources.num_pipe_per_mec;
100 }
101
get_num_sdma_engines(struct device_queue_manager * dqm)102 static unsigned int get_num_sdma_engines(struct device_queue_manager *dqm)
103 {
104 return dqm->dev->device_info->num_sdma_engines;
105 }
106
get_num_xgmi_sdma_engines(struct device_queue_manager * dqm)107 static unsigned int get_num_xgmi_sdma_engines(struct device_queue_manager *dqm)
108 {
109 return dqm->dev->device_info->num_xgmi_sdma_engines;
110 }
111
get_num_all_sdma_engines(struct device_queue_manager * dqm)112 static unsigned int get_num_all_sdma_engines(struct device_queue_manager *dqm)
113 {
114 return get_num_sdma_engines(dqm) + get_num_xgmi_sdma_engines(dqm);
115 }
116
get_num_sdma_queues(struct device_queue_manager * dqm)117 unsigned int get_num_sdma_queues(struct device_queue_manager *dqm)
118 {
119 return dqm->dev->device_info->num_sdma_engines
120 * dqm->dev->device_info->num_sdma_queues_per_engine;
121 }
122
get_num_xgmi_sdma_queues(struct device_queue_manager * dqm)123 unsigned int get_num_xgmi_sdma_queues(struct device_queue_manager *dqm)
124 {
125 return dqm->dev->device_info->num_xgmi_sdma_engines
126 * dqm->dev->device_info->num_sdma_queues_per_engine;
127 }
128
program_sh_mem_settings(struct device_queue_manager * dqm,struct qcm_process_device * qpd)129 void program_sh_mem_settings(struct device_queue_manager *dqm,
130 struct qcm_process_device *qpd)
131 {
132 return dqm->dev->kfd2kgd->program_sh_mem_settings(
133 dqm->dev->kgd, qpd->vmid,
134 qpd->sh_mem_config,
135 qpd->sh_mem_ape1_base,
136 qpd->sh_mem_ape1_limit,
137 qpd->sh_mem_bases);
138 }
139
increment_queue_count(struct device_queue_manager * dqm,struct qcm_process_device * qpd,struct queue * q)140 static void increment_queue_count(struct device_queue_manager *dqm,
141 struct qcm_process_device *qpd,
142 struct queue *q)
143 {
144 dqm->active_queue_count++;
145 if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE ||
146 q->properties.type == KFD_QUEUE_TYPE_DIQ)
147 dqm->active_cp_queue_count++;
148
149 if (q->properties.is_gws) {
150 dqm->gws_queue_count++;
151 qpd->mapped_gws_queue = true;
152 }
153 }
154
decrement_queue_count(struct device_queue_manager * dqm,struct qcm_process_device * qpd,struct queue * q)155 static void decrement_queue_count(struct device_queue_manager *dqm,
156 struct qcm_process_device *qpd,
157 struct queue *q)
158 {
159 dqm->active_queue_count--;
160 if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE ||
161 q->properties.type == KFD_QUEUE_TYPE_DIQ)
162 dqm->active_cp_queue_count--;
163
164 if (q->properties.is_gws) {
165 dqm->gws_queue_count--;
166 qpd->mapped_gws_queue = false;
167 }
168 }
169
allocate_doorbell(struct qcm_process_device * qpd,struct queue * q)170 static int allocate_doorbell(struct qcm_process_device *qpd, struct queue *q)
171 {
172 struct kfd_dev *dev = qpd->dqm->dev;
173
174 if (!KFD_IS_SOC15(dev->device_info->asic_family)) {
175 /* On pre-SOC15 chips we need to use the queue ID to
176 * preserve the user mode ABI.
177 */
178 q->doorbell_id = q->properties.queue_id;
179 } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA ||
180 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) {
181 /* For SDMA queues on SOC15 with 8-byte doorbell, use static
182 * doorbell assignments based on the engine and queue id.
183 * The doobell index distance between RLC (2*i) and (2*i+1)
184 * for a SDMA engine is 512.
185 */
186 uint32_t *idx_offset =
187 dev->shared_resources.sdma_doorbell_idx;
188
189 q->doorbell_id = idx_offset[q->properties.sdma_engine_id]
190 + (q->properties.sdma_queue_id & 1)
191 * KFD_QUEUE_DOORBELL_MIRROR_OFFSET
192 + (q->properties.sdma_queue_id >> 1);
193 } else {
194 /* For CP queues on SOC15 reserve a free doorbell ID */
195 unsigned int found;
196
197 found = find_first_zero_bit(qpd->doorbell_bitmap,
198 KFD_MAX_NUM_OF_QUEUES_PER_PROCESS);
199 if (found >= KFD_MAX_NUM_OF_QUEUES_PER_PROCESS) {
200 pr_debug("No doorbells available");
201 return -EBUSY;
202 }
203 set_bit(found, qpd->doorbell_bitmap);
204 q->doorbell_id = found;
205 }
206
207 q->properties.doorbell_off =
208 kfd_get_doorbell_dw_offset_in_bar(dev, qpd_to_pdd(qpd),
209 q->doorbell_id);
210 return 0;
211 }
212
deallocate_doorbell(struct qcm_process_device * qpd,struct queue * q)213 static void deallocate_doorbell(struct qcm_process_device *qpd,
214 struct queue *q)
215 {
216 unsigned int old;
217 struct kfd_dev *dev = qpd->dqm->dev;
218
219 if (!KFD_IS_SOC15(dev->device_info->asic_family) ||
220 q->properties.type == KFD_QUEUE_TYPE_SDMA ||
221 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)
222 return;
223
224 old = test_and_clear_bit(q->doorbell_id, qpd->doorbell_bitmap);
225 WARN_ON(!old);
226 }
227
allocate_vmid(struct device_queue_manager * dqm,struct qcm_process_device * qpd,struct queue * q)228 static int allocate_vmid(struct device_queue_manager *dqm,
229 struct qcm_process_device *qpd,
230 struct queue *q)
231 {
232 int allocated_vmid = -1, i;
233
234 for (i = dqm->dev->vm_info.first_vmid_kfd;
235 i <= dqm->dev->vm_info.last_vmid_kfd; i++) {
236 if (!dqm->vmid_pasid[i]) {
237 allocated_vmid = i;
238 break;
239 }
240 }
241
242 if (allocated_vmid < 0) {
243 pr_err("no more vmid to allocate\n");
244 return -ENOSPC;
245 }
246
247 pr_debug("vmid allocated: %d\n", allocated_vmid);
248
249 dqm->vmid_pasid[allocated_vmid] = q->process->pasid;
250
251 set_pasid_vmid_mapping(dqm, q->process->pasid, allocated_vmid);
252
253 qpd->vmid = allocated_vmid;
254 q->properties.vmid = allocated_vmid;
255
256 program_sh_mem_settings(dqm, qpd);
257
258 /* qpd->page_table_base is set earlier when register_process()
259 * is called, i.e. when the first queue is created.
260 */
261 dqm->dev->kfd2kgd->set_vm_context_page_table_base(dqm->dev->kgd,
262 qpd->vmid,
263 qpd->page_table_base);
264 /* invalidate the VM context after pasid and vmid mapping is set up */
265 kfd_flush_tlb(qpd_to_pdd(qpd));
266
267 if (dqm->dev->kfd2kgd->set_scratch_backing_va)
268 dqm->dev->kfd2kgd->set_scratch_backing_va(dqm->dev->kgd,
269 qpd->sh_hidden_private_base, qpd->vmid);
270
271 return 0;
272 }
273
flush_texture_cache_nocpsch(struct kfd_dev * kdev,struct qcm_process_device * qpd)274 static int flush_texture_cache_nocpsch(struct kfd_dev *kdev,
275 struct qcm_process_device *qpd)
276 {
277 const struct packet_manager_funcs *pmf = qpd->dqm->packets.pmf;
278 int ret;
279
280 if (!qpd->ib_kaddr)
281 return -ENOMEM;
282
283 ret = pmf->release_mem(qpd->ib_base, (uint32_t *)qpd->ib_kaddr);
284 if (ret)
285 return ret;
286
287 return amdgpu_amdkfd_submit_ib(kdev->kgd, KGD_ENGINE_MEC1, qpd->vmid,
288 qpd->ib_base, (uint32_t *)qpd->ib_kaddr,
289 pmf->release_mem_size / sizeof(uint32_t));
290 }
291
deallocate_vmid(struct device_queue_manager * dqm,struct qcm_process_device * qpd,struct queue * q)292 static void deallocate_vmid(struct device_queue_manager *dqm,
293 struct qcm_process_device *qpd,
294 struct queue *q)
295 {
296 /* On GFX v7, CP doesn't flush TC at dequeue */
297 if (q->device->device_info->asic_family == CHIP_HAWAII)
298 if (flush_texture_cache_nocpsch(q->device, qpd))
299 pr_err("Failed to flush TC\n");
300
301 kfd_flush_tlb(qpd_to_pdd(qpd));
302
303 /* Release the vmid mapping */
304 set_pasid_vmid_mapping(dqm, 0, qpd->vmid);
305 dqm->vmid_pasid[qpd->vmid] = 0;
306
307 qpd->vmid = 0;
308 q->properties.vmid = 0;
309 }
310
create_queue_nocpsch(struct device_queue_manager * dqm,struct queue * q,struct qcm_process_device * qpd)311 static int create_queue_nocpsch(struct device_queue_manager *dqm,
312 struct queue *q,
313 struct qcm_process_device *qpd)
314 {
315 struct mqd_manager *mqd_mgr;
316 int retval;
317
318 dqm_lock(dqm);
319
320 if (dqm->total_queue_count >= max_num_of_queues_per_device) {
321 pr_warn("Can't create new usermode queue because %d queues were already created\n",
322 dqm->total_queue_count);
323 retval = -EPERM;
324 goto out_unlock;
325 }
326
327 if (list_empty(&qpd->queues_list)) {
328 retval = allocate_vmid(dqm, qpd, q);
329 if (retval)
330 goto out_unlock;
331 }
332 q->properties.vmid = qpd->vmid;
333 /*
334 * Eviction state logic: mark all queues as evicted, even ones
335 * not currently active. Restoring inactive queues later only
336 * updates the is_evicted flag but is a no-op otherwise.
337 */
338 q->properties.is_evicted = !!qpd->evicted;
339
340 q->properties.tba_addr = qpd->tba_addr;
341 q->properties.tma_addr = qpd->tma_addr;
342
343 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
344 q->properties.type)];
345 if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE) {
346 retval = allocate_hqd(dqm, q);
347 if (retval)
348 goto deallocate_vmid;
349 pr_debug("Loading mqd to hqd on pipe %d, queue %d\n",
350 q->pipe, q->queue);
351 } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA ||
352 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) {
353 retval = allocate_sdma_queue(dqm, q);
354 if (retval)
355 goto deallocate_vmid;
356 dqm->asic_ops.init_sdma_vm(dqm, q, qpd);
357 }
358
359 retval = allocate_doorbell(qpd, q);
360 if (retval)
361 goto out_deallocate_hqd;
362
363 /* Temporarily release dqm lock to avoid a circular lock dependency */
364 dqm_unlock(dqm);
365 q->mqd_mem_obj = mqd_mgr->allocate_mqd(mqd_mgr->dev, &q->properties);
366 dqm_lock(dqm);
367
368 if (!q->mqd_mem_obj) {
369 retval = -ENOMEM;
370 goto out_deallocate_doorbell;
371 }
372 mqd_mgr->init_mqd(mqd_mgr, &q->mqd, q->mqd_mem_obj,
373 &q->gart_mqd_addr, &q->properties);
374 if (q->properties.is_active) {
375 if (!dqm->sched_running) {
376 WARN_ONCE(1, "Load non-HWS mqd while stopped\n");
377 goto add_queue_to_list;
378 }
379
380 if (WARN(q->process->mm != current->mm,
381 "should only run in user thread"))
382 retval = -EFAULT;
383 else
384 retval = mqd_mgr->load_mqd(mqd_mgr, q->mqd, q->pipe,
385 q->queue, &q->properties, current->mm);
386 if (retval)
387 goto out_free_mqd;
388 }
389
390 add_queue_to_list:
391 list_add(&q->list, &qpd->queues_list);
392 qpd->queue_count++;
393 if (q->properties.is_active)
394 increment_queue_count(dqm, qpd, q);
395
396 /*
397 * Unconditionally increment this counter, regardless of the queue's
398 * type or whether the queue is active.
399 */
400 dqm->total_queue_count++;
401 pr_debug("Total of %d queues are accountable so far\n",
402 dqm->total_queue_count);
403 goto out_unlock;
404
405 out_free_mqd:
406 mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj);
407 out_deallocate_doorbell:
408 deallocate_doorbell(qpd, q);
409 out_deallocate_hqd:
410 if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE)
411 deallocate_hqd(dqm, q);
412 else if (q->properties.type == KFD_QUEUE_TYPE_SDMA ||
413 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)
414 deallocate_sdma_queue(dqm, q);
415 deallocate_vmid:
416 if (list_empty(&qpd->queues_list))
417 deallocate_vmid(dqm, qpd, q);
418 out_unlock:
419 dqm_unlock(dqm);
420 return retval;
421 }
422
allocate_hqd(struct device_queue_manager * dqm,struct queue * q)423 static int allocate_hqd(struct device_queue_manager *dqm, struct queue *q)
424 {
425 bool set;
426 int pipe, bit, i;
427
428 set = false;
429
430 for (pipe = dqm->next_pipe_to_allocate, i = 0;
431 i < get_pipes_per_mec(dqm);
432 pipe = ((pipe + 1) % get_pipes_per_mec(dqm)), ++i) {
433
434 if (!is_pipe_enabled(dqm, 0, pipe))
435 continue;
436
437 if (dqm->allocated_queues[pipe] != 0) {
438 bit = ffs(dqm->allocated_queues[pipe]) - 1;
439 dqm->allocated_queues[pipe] &= ~(1 << bit);
440 q->pipe = pipe;
441 q->queue = bit;
442 set = true;
443 break;
444 }
445 }
446
447 if (!set)
448 return -EBUSY;
449
450 pr_debug("hqd slot - pipe %d, queue %d\n", q->pipe, q->queue);
451 /* horizontal hqd allocation */
452 dqm->next_pipe_to_allocate = (pipe + 1) % get_pipes_per_mec(dqm);
453
454 return 0;
455 }
456
deallocate_hqd(struct device_queue_manager * dqm,struct queue * q)457 static inline void deallocate_hqd(struct device_queue_manager *dqm,
458 struct queue *q)
459 {
460 dqm->allocated_queues[q->pipe] |= (1 << q->queue);
461 }
462
463 /* Access to DQM has to be locked before calling destroy_queue_nocpsch_locked
464 * to avoid asynchronized access
465 */
destroy_queue_nocpsch_locked(struct device_queue_manager * dqm,struct qcm_process_device * qpd,struct queue * q)466 static int destroy_queue_nocpsch_locked(struct device_queue_manager *dqm,
467 struct qcm_process_device *qpd,
468 struct queue *q)
469 {
470 int retval;
471 struct mqd_manager *mqd_mgr;
472
473 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
474 q->properties.type)];
475
476 if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE)
477 deallocate_hqd(dqm, q);
478 else if (q->properties.type == KFD_QUEUE_TYPE_SDMA)
479 deallocate_sdma_queue(dqm, q);
480 else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)
481 deallocate_sdma_queue(dqm, q);
482 else {
483 pr_debug("q->properties.type %d is invalid\n",
484 q->properties.type);
485 return -EINVAL;
486 }
487 dqm->total_queue_count--;
488
489 deallocate_doorbell(qpd, q);
490
491 if (!dqm->sched_running) {
492 WARN_ONCE(1, "Destroy non-HWS queue while stopped\n");
493 return 0;
494 }
495
496 retval = mqd_mgr->destroy_mqd(mqd_mgr, q->mqd,
497 KFD_PREEMPT_TYPE_WAVEFRONT_RESET,
498 KFD_UNMAP_LATENCY_MS,
499 q->pipe, q->queue);
500 if (retval == -ETIME)
501 qpd->reset_wavefronts = true;
502
503 list_del(&q->list);
504 if (list_empty(&qpd->queues_list)) {
505 if (qpd->reset_wavefronts) {
506 pr_warn("Resetting wave fronts (nocpsch) on dev %p\n",
507 dqm->dev);
508 /* dbgdev_wave_reset_wavefronts has to be called before
509 * deallocate_vmid(), i.e. when vmid is still in use.
510 */
511 dbgdev_wave_reset_wavefronts(dqm->dev,
512 qpd->pqm->process);
513 qpd->reset_wavefronts = false;
514 }
515
516 deallocate_vmid(dqm, qpd, q);
517 }
518 qpd->queue_count--;
519 if (q->properties.is_active)
520 decrement_queue_count(dqm, qpd, q);
521
522 return retval;
523 }
524
destroy_queue_nocpsch(struct device_queue_manager * dqm,struct qcm_process_device * qpd,struct queue * q)525 static int destroy_queue_nocpsch(struct device_queue_manager *dqm,
526 struct qcm_process_device *qpd,
527 struct queue *q)
528 {
529 int retval;
530 uint64_t sdma_val = 0;
531 struct kfd_process_device *pdd = qpd_to_pdd(qpd);
532 struct mqd_manager *mqd_mgr =
533 dqm->mqd_mgrs[get_mqd_type_from_queue_type(q->properties.type)];
534
535 /* Get the SDMA queue stats */
536 if ((q->properties.type == KFD_QUEUE_TYPE_SDMA) ||
537 (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)) {
538 retval = read_sdma_queue_counter((uint64_t __user *)q->properties.read_ptr,
539 &sdma_val);
540 if (retval)
541 pr_err("Failed to read SDMA queue counter for queue: %d\n",
542 q->properties.queue_id);
543 }
544
545 dqm_lock(dqm);
546 retval = destroy_queue_nocpsch_locked(dqm, qpd, q);
547 if (!retval)
548 pdd->sdma_past_activity_counter += sdma_val;
549 dqm_unlock(dqm);
550
551 mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj);
552
553 return retval;
554 }
555
update_queue(struct device_queue_manager * dqm,struct queue * q)556 static int update_queue(struct device_queue_manager *dqm, struct queue *q)
557 {
558 int retval = 0;
559 struct mqd_manager *mqd_mgr;
560 struct kfd_process_device *pdd;
561 bool prev_active = false;
562
563 dqm_lock(dqm);
564 pdd = kfd_get_process_device_data(q->device, q->process);
565 if (!pdd) {
566 retval = -ENODEV;
567 goto out_unlock;
568 }
569 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
570 q->properties.type)];
571
572 /* Save previous activity state for counters */
573 prev_active = q->properties.is_active;
574
575 /* Make sure the queue is unmapped before updating the MQD */
576 if (dqm->sched_policy != KFD_SCHED_POLICY_NO_HWS) {
577 retval = unmap_queues_cpsch(dqm,
578 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0);
579 if (retval) {
580 pr_err("unmap queue failed\n");
581 goto out_unlock;
582 }
583 } else if (prev_active &&
584 (q->properties.type == KFD_QUEUE_TYPE_COMPUTE ||
585 q->properties.type == KFD_QUEUE_TYPE_SDMA ||
586 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)) {
587
588 if (!dqm->sched_running) {
589 WARN_ONCE(1, "Update non-HWS queue while stopped\n");
590 goto out_unlock;
591 }
592
593 retval = mqd_mgr->destroy_mqd(mqd_mgr, q->mqd,
594 KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN,
595 KFD_UNMAP_LATENCY_MS, q->pipe, q->queue);
596 if (retval) {
597 pr_err("destroy mqd failed\n");
598 goto out_unlock;
599 }
600 }
601
602 mqd_mgr->update_mqd(mqd_mgr, q->mqd, &q->properties);
603
604 /*
605 * check active state vs. the previous state and modify
606 * counter accordingly. map_queues_cpsch uses the
607 * dqm->active_queue_count to determine whether a new runlist must be
608 * uploaded.
609 */
610 if (q->properties.is_active && !prev_active) {
611 increment_queue_count(dqm, &pdd->qpd, q);
612 } else if (!q->properties.is_active && prev_active) {
613 decrement_queue_count(dqm, &pdd->qpd, q);
614 } else if (q->gws && !q->properties.is_gws) {
615 if (q->properties.is_active) {
616 dqm->gws_queue_count++;
617 pdd->qpd.mapped_gws_queue = true;
618 }
619 q->properties.is_gws = true;
620 } else if (!q->gws && q->properties.is_gws) {
621 if (q->properties.is_active) {
622 dqm->gws_queue_count--;
623 pdd->qpd.mapped_gws_queue = false;
624 }
625 q->properties.is_gws = false;
626 }
627
628 if (dqm->sched_policy != KFD_SCHED_POLICY_NO_HWS)
629 retval = map_queues_cpsch(dqm);
630 else if (q->properties.is_active &&
631 (q->properties.type == KFD_QUEUE_TYPE_COMPUTE ||
632 q->properties.type == KFD_QUEUE_TYPE_SDMA ||
633 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)) {
634 if (WARN(q->process->mm != current->mm,
635 "should only run in user thread"))
636 retval = -EFAULT;
637 else
638 retval = mqd_mgr->load_mqd(mqd_mgr, q->mqd,
639 q->pipe, q->queue,
640 &q->properties, current->mm);
641 }
642
643 out_unlock:
644 dqm_unlock(dqm);
645 return retval;
646 }
647
evict_process_queues_nocpsch(struct device_queue_manager * dqm,struct qcm_process_device * qpd)648 static int evict_process_queues_nocpsch(struct device_queue_manager *dqm,
649 struct qcm_process_device *qpd)
650 {
651 struct queue *q;
652 struct mqd_manager *mqd_mgr;
653 struct kfd_process_device *pdd;
654 int retval, ret = 0;
655
656 dqm_lock(dqm);
657 if (qpd->evicted++ > 0) /* already evicted, do nothing */
658 goto out;
659
660 pdd = qpd_to_pdd(qpd);
661 pr_debug_ratelimited("Evicting PASID 0x%x queues\n",
662 pdd->process->pasid);
663
664 pdd->last_evict_timestamp = get_jiffies_64();
665 /* Mark all queues as evicted. Deactivate all active queues on
666 * the qpd.
667 */
668 list_for_each_entry(q, &qpd->queues_list, list) {
669 q->properties.is_evicted = true;
670 if (!q->properties.is_active)
671 continue;
672
673 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
674 q->properties.type)];
675 q->properties.is_active = false;
676 decrement_queue_count(dqm, qpd, q);
677
678 if (WARN_ONCE(!dqm->sched_running, "Evict when stopped\n"))
679 continue;
680
681 retval = mqd_mgr->destroy_mqd(mqd_mgr, q->mqd,
682 KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN,
683 KFD_UNMAP_LATENCY_MS, q->pipe, q->queue);
684 if (retval && !ret)
685 /* Return the first error, but keep going to
686 * maintain a consistent eviction state
687 */
688 ret = retval;
689 }
690
691 out:
692 dqm_unlock(dqm);
693 return ret;
694 }
695
evict_process_queues_cpsch(struct device_queue_manager * dqm,struct qcm_process_device * qpd)696 static int evict_process_queues_cpsch(struct device_queue_manager *dqm,
697 struct qcm_process_device *qpd)
698 {
699 struct queue *q;
700 struct kfd_process_device *pdd;
701 int retval = 0;
702
703 dqm_lock(dqm);
704 if (qpd->evicted++ > 0) /* already evicted, do nothing */
705 goto out;
706
707 pdd = qpd_to_pdd(qpd);
708 pr_debug_ratelimited("Evicting PASID 0x%x queues\n",
709 pdd->process->pasid);
710
711 /* Mark all queues as evicted. Deactivate all active queues on
712 * the qpd.
713 */
714 list_for_each_entry(q, &qpd->queues_list, list) {
715 q->properties.is_evicted = true;
716 if (!q->properties.is_active)
717 continue;
718
719 q->properties.is_active = false;
720 decrement_queue_count(dqm, qpd, q);
721 }
722 pdd->last_evict_timestamp = get_jiffies_64();
723 retval = execute_queues_cpsch(dqm,
724 qpd->is_debug ?
725 KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES :
726 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0);
727
728 out:
729 dqm_unlock(dqm);
730 return retval;
731 }
732
restore_process_queues_nocpsch(struct device_queue_manager * dqm,struct qcm_process_device * qpd)733 static int restore_process_queues_nocpsch(struct device_queue_manager *dqm,
734 struct qcm_process_device *qpd)
735 {
736 struct mm_struct *mm = NULL;
737 struct queue *q;
738 struct mqd_manager *mqd_mgr;
739 struct kfd_process_device *pdd;
740 uint64_t pd_base;
741 uint64_t eviction_duration;
742 int retval, ret = 0;
743
744 pdd = qpd_to_pdd(qpd);
745 /* Retrieve PD base */
746 pd_base = amdgpu_amdkfd_gpuvm_get_process_page_dir(pdd->vm);
747
748 dqm_lock(dqm);
749 if (WARN_ON_ONCE(!qpd->evicted)) /* already restored, do nothing */
750 goto out;
751 if (qpd->evicted > 1) { /* ref count still > 0, decrement & quit */
752 qpd->evicted--;
753 goto out;
754 }
755
756 pr_debug_ratelimited("Restoring PASID 0x%x queues\n",
757 pdd->process->pasid);
758
759 /* Update PD Base in QPD */
760 qpd->page_table_base = pd_base;
761 pr_debug("Updated PD address to 0x%llx\n", pd_base);
762
763 if (!list_empty(&qpd->queues_list)) {
764 dqm->dev->kfd2kgd->set_vm_context_page_table_base(
765 dqm->dev->kgd,
766 qpd->vmid,
767 qpd->page_table_base);
768 kfd_flush_tlb(pdd);
769 }
770
771 /* Take a safe reference to the mm_struct, which may otherwise
772 * disappear even while the kfd_process is still referenced.
773 */
774 mm = get_task_mm(pdd->process->lead_thread);
775 if (!mm) {
776 ret = -EFAULT;
777 goto out;
778 }
779
780 /* Remove the eviction flags. Activate queues that are not
781 * inactive for other reasons.
782 */
783 list_for_each_entry(q, &qpd->queues_list, list) {
784 q->properties.is_evicted = false;
785 if (!QUEUE_IS_ACTIVE(q->properties))
786 continue;
787
788 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
789 q->properties.type)];
790 q->properties.is_active = true;
791 increment_queue_count(dqm, qpd, q);
792
793 if (WARN_ONCE(!dqm->sched_running, "Restore when stopped\n"))
794 continue;
795
796 retval = mqd_mgr->load_mqd(mqd_mgr, q->mqd, q->pipe,
797 q->queue, &q->properties, mm);
798 if (retval && !ret)
799 /* Return the first error, but keep going to
800 * maintain a consistent eviction state
801 */
802 ret = retval;
803 }
804 qpd->evicted = 0;
805 eviction_duration = get_jiffies_64() - pdd->last_evict_timestamp;
806 atomic64_add(eviction_duration, &pdd->evict_duration_counter);
807 out:
808 if (mm)
809 mmput(mm);
810 dqm_unlock(dqm);
811 return ret;
812 }
813
restore_process_queues_cpsch(struct device_queue_manager * dqm,struct qcm_process_device * qpd)814 static int restore_process_queues_cpsch(struct device_queue_manager *dqm,
815 struct qcm_process_device *qpd)
816 {
817 struct queue *q;
818 struct kfd_process_device *pdd;
819 uint64_t pd_base;
820 uint64_t eviction_duration;
821 int retval = 0;
822
823 pdd = qpd_to_pdd(qpd);
824 /* Retrieve PD base */
825 pd_base = amdgpu_amdkfd_gpuvm_get_process_page_dir(pdd->vm);
826
827 dqm_lock(dqm);
828 if (WARN_ON_ONCE(!qpd->evicted)) /* already restored, do nothing */
829 goto out;
830 if (qpd->evicted > 1) { /* ref count still > 0, decrement & quit */
831 qpd->evicted--;
832 goto out;
833 }
834
835 pr_debug_ratelimited("Restoring PASID 0x%x queues\n",
836 pdd->process->pasid);
837
838 /* Update PD Base in QPD */
839 qpd->page_table_base = pd_base;
840 pr_debug("Updated PD address to 0x%llx\n", pd_base);
841
842 /* activate all active queues on the qpd */
843 list_for_each_entry(q, &qpd->queues_list, list) {
844 q->properties.is_evicted = false;
845 if (!QUEUE_IS_ACTIVE(q->properties))
846 continue;
847
848 q->properties.is_active = true;
849 increment_queue_count(dqm, &pdd->qpd, q);
850 }
851 retval = execute_queues_cpsch(dqm,
852 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0);
853 qpd->evicted = 0;
854 eviction_duration = get_jiffies_64() - pdd->last_evict_timestamp;
855 atomic64_add(eviction_duration, &pdd->evict_duration_counter);
856 out:
857 dqm_unlock(dqm);
858 return retval;
859 }
860
register_process(struct device_queue_manager * dqm,struct qcm_process_device * qpd)861 static int register_process(struct device_queue_manager *dqm,
862 struct qcm_process_device *qpd)
863 {
864 struct device_process_node *n;
865 struct kfd_process_device *pdd;
866 uint64_t pd_base;
867 int retval;
868
869 n = kzalloc(sizeof(*n), GFP_KERNEL);
870 if (!n)
871 return -ENOMEM;
872
873 n->qpd = qpd;
874
875 pdd = qpd_to_pdd(qpd);
876 /* Retrieve PD base */
877 pd_base = amdgpu_amdkfd_gpuvm_get_process_page_dir(pdd->vm);
878
879 dqm_lock(dqm);
880 list_add(&n->list, &dqm->queues);
881
882 /* Update PD Base in QPD */
883 qpd->page_table_base = pd_base;
884 pr_debug("Updated PD address to 0x%llx\n", pd_base);
885
886 retval = dqm->asic_ops.update_qpd(dqm, qpd);
887
888 dqm->processes_count++;
889
890 dqm_unlock(dqm);
891
892 /* Outside the DQM lock because under the DQM lock we can't do
893 * reclaim or take other locks that others hold while reclaiming.
894 */
895 kfd_inc_compute_active(dqm->dev);
896
897 return retval;
898 }
899
unregister_process(struct device_queue_manager * dqm,struct qcm_process_device * qpd)900 static int unregister_process(struct device_queue_manager *dqm,
901 struct qcm_process_device *qpd)
902 {
903 int retval;
904 struct device_process_node *cur, *next;
905
906 pr_debug("qpd->queues_list is %s\n",
907 list_empty(&qpd->queues_list) ? "empty" : "not empty");
908
909 retval = 0;
910 dqm_lock(dqm);
911
912 list_for_each_entry_safe(cur, next, &dqm->queues, list) {
913 if (qpd == cur->qpd) {
914 list_del(&cur->list);
915 kfree(cur);
916 dqm->processes_count--;
917 goto out;
918 }
919 }
920 /* qpd not found in dqm list */
921 retval = 1;
922 out:
923 dqm_unlock(dqm);
924
925 /* Outside the DQM lock because under the DQM lock we can't do
926 * reclaim or take other locks that others hold while reclaiming.
927 */
928 if (!retval)
929 kfd_dec_compute_active(dqm->dev);
930
931 return retval;
932 }
933
934 static int
set_pasid_vmid_mapping(struct device_queue_manager * dqm,u32 pasid,unsigned int vmid)935 set_pasid_vmid_mapping(struct device_queue_manager *dqm, u32 pasid,
936 unsigned int vmid)
937 {
938 return dqm->dev->kfd2kgd->set_pasid_vmid_mapping(
939 dqm->dev->kgd, pasid, vmid);
940 }
941
init_interrupts(struct device_queue_manager * dqm)942 static void init_interrupts(struct device_queue_manager *dqm)
943 {
944 unsigned int i;
945
946 for (i = 0 ; i < get_pipes_per_mec(dqm) ; i++)
947 if (is_pipe_enabled(dqm, 0, i))
948 dqm->dev->kfd2kgd->init_interrupts(dqm->dev->kgd, i);
949 }
950
initialize_nocpsch(struct device_queue_manager * dqm)951 static int initialize_nocpsch(struct device_queue_manager *dqm)
952 {
953 int pipe, queue;
954
955 pr_debug("num of pipes: %d\n", get_pipes_per_mec(dqm));
956
957 dqm->allocated_queues = kcalloc(get_pipes_per_mec(dqm),
958 sizeof(unsigned int), GFP_KERNEL);
959 if (!dqm->allocated_queues)
960 return -ENOMEM;
961
962 mutex_init(&dqm->lock_hidden);
963 INIT_LIST_HEAD(&dqm->queues);
964 dqm->active_queue_count = dqm->next_pipe_to_allocate = 0;
965 dqm->active_cp_queue_count = 0;
966 dqm->gws_queue_count = 0;
967
968 for (pipe = 0; pipe < get_pipes_per_mec(dqm); pipe++) {
969 int pipe_offset = pipe * get_queues_per_pipe(dqm);
970
971 for (queue = 0; queue < get_queues_per_pipe(dqm); queue++)
972 if (test_bit(pipe_offset + queue,
973 dqm->dev->shared_resources.cp_queue_bitmap))
974 dqm->allocated_queues[pipe] |= 1 << queue;
975 }
976
977 memset(dqm->vmid_pasid, 0, sizeof(dqm->vmid_pasid));
978
979 dqm->sdma_bitmap = ~0ULL >> (64 - get_num_sdma_queues(dqm));
980 dqm->xgmi_sdma_bitmap = ~0ULL >> (64 - get_num_xgmi_sdma_queues(dqm));
981
982 return 0;
983 }
984
uninitialize(struct device_queue_manager * dqm)985 static void uninitialize(struct device_queue_manager *dqm)
986 {
987 int i;
988
989 WARN_ON(dqm->active_queue_count > 0 || dqm->processes_count > 0);
990
991 kfree(dqm->allocated_queues);
992 for (i = 0 ; i < KFD_MQD_TYPE_MAX ; i++)
993 kfree(dqm->mqd_mgrs[i]);
994 mutex_destroy(&dqm->lock_hidden);
995 }
996
start_nocpsch(struct device_queue_manager * dqm)997 static int start_nocpsch(struct device_queue_manager *dqm)
998 {
999 pr_info("SW scheduler is used");
1000 init_interrupts(dqm);
1001
1002 if (dqm->dev->device_info->asic_family == CHIP_HAWAII)
1003 return pm_init(&dqm->packets, dqm);
1004 dqm->sched_running = true;
1005
1006 return 0;
1007 }
1008
stop_nocpsch(struct device_queue_manager * dqm)1009 static int stop_nocpsch(struct device_queue_manager *dqm)
1010 {
1011 if (dqm->dev->device_info->asic_family == CHIP_HAWAII)
1012 pm_uninit(&dqm->packets, false);
1013 dqm->sched_running = false;
1014
1015 return 0;
1016 }
1017
pre_reset(struct device_queue_manager * dqm)1018 static void pre_reset(struct device_queue_manager *dqm)
1019 {
1020 dqm_lock(dqm);
1021 dqm->is_resetting = true;
1022 dqm_unlock(dqm);
1023 }
1024
allocate_sdma_queue(struct device_queue_manager * dqm,struct queue * q)1025 static int allocate_sdma_queue(struct device_queue_manager *dqm,
1026 struct queue *q)
1027 {
1028 int bit;
1029
1030 if (q->properties.type == KFD_QUEUE_TYPE_SDMA) {
1031 if (dqm->sdma_bitmap == 0) {
1032 pr_err("No more SDMA queue to allocate\n");
1033 return -ENOMEM;
1034 }
1035
1036 bit = __ffs64(dqm->sdma_bitmap);
1037 dqm->sdma_bitmap &= ~(1ULL << bit);
1038 q->sdma_id = bit;
1039 q->properties.sdma_engine_id = q->sdma_id %
1040 get_num_sdma_engines(dqm);
1041 q->properties.sdma_queue_id = q->sdma_id /
1042 get_num_sdma_engines(dqm);
1043 } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) {
1044 if (dqm->xgmi_sdma_bitmap == 0) {
1045 pr_err("No more XGMI SDMA queue to allocate\n");
1046 return -ENOMEM;
1047 }
1048 bit = __ffs64(dqm->xgmi_sdma_bitmap);
1049 dqm->xgmi_sdma_bitmap &= ~(1ULL << bit);
1050 q->sdma_id = bit;
1051 /* sdma_engine_id is sdma id including
1052 * both PCIe-optimized SDMAs and XGMI-
1053 * optimized SDMAs. The calculation below
1054 * assumes the first N engines are always
1055 * PCIe-optimized ones
1056 */
1057 q->properties.sdma_engine_id = get_num_sdma_engines(dqm) +
1058 q->sdma_id % get_num_xgmi_sdma_engines(dqm);
1059 q->properties.sdma_queue_id = q->sdma_id /
1060 get_num_xgmi_sdma_engines(dqm);
1061 }
1062
1063 pr_debug("SDMA engine id: %d\n", q->properties.sdma_engine_id);
1064 pr_debug("SDMA queue id: %d\n", q->properties.sdma_queue_id);
1065
1066 return 0;
1067 }
1068
deallocate_sdma_queue(struct device_queue_manager * dqm,struct queue * q)1069 static void deallocate_sdma_queue(struct device_queue_manager *dqm,
1070 struct queue *q)
1071 {
1072 if (q->properties.type == KFD_QUEUE_TYPE_SDMA) {
1073 if (q->sdma_id >= get_num_sdma_queues(dqm))
1074 return;
1075 dqm->sdma_bitmap |= (1ULL << q->sdma_id);
1076 } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) {
1077 if (q->sdma_id >= get_num_xgmi_sdma_queues(dqm))
1078 return;
1079 dqm->xgmi_sdma_bitmap |= (1ULL << q->sdma_id);
1080 }
1081 }
1082
1083 /*
1084 * Device Queue Manager implementation for cp scheduler
1085 */
1086
set_sched_resources(struct device_queue_manager * dqm)1087 static int set_sched_resources(struct device_queue_manager *dqm)
1088 {
1089 int i, mec;
1090 struct scheduling_resources res;
1091
1092 res.vmid_mask = dqm->dev->shared_resources.compute_vmid_bitmap;
1093
1094 res.queue_mask = 0;
1095 for (i = 0; i < KGD_MAX_QUEUES; ++i) {
1096 mec = (i / dqm->dev->shared_resources.num_queue_per_pipe)
1097 / dqm->dev->shared_resources.num_pipe_per_mec;
1098
1099 if (!test_bit(i, dqm->dev->shared_resources.cp_queue_bitmap))
1100 continue;
1101
1102 /* only acquire queues from the first MEC */
1103 if (mec > 0)
1104 continue;
1105
1106 /* This situation may be hit in the future if a new HW
1107 * generation exposes more than 64 queues. If so, the
1108 * definition of res.queue_mask needs updating
1109 */
1110 if (WARN_ON(i >= (sizeof(res.queue_mask)*8))) {
1111 pr_err("Invalid queue enabled by amdgpu: %d\n", i);
1112 break;
1113 }
1114
1115 res.queue_mask |= 1ull
1116 << amdgpu_queue_mask_bit_to_set_resource_bit(
1117 (struct amdgpu_device *)dqm->dev->kgd, i);
1118 }
1119 res.gws_mask = ~0ull;
1120 res.oac_mask = res.gds_heap_base = res.gds_heap_size = 0;
1121
1122 pr_debug("Scheduling resources:\n"
1123 "vmid mask: 0x%8X\n"
1124 "queue mask: 0x%8llX\n",
1125 res.vmid_mask, res.queue_mask);
1126
1127 return pm_send_set_resources(&dqm->packets, &res);
1128 }
1129
initialize_cpsch(struct device_queue_manager * dqm)1130 static int initialize_cpsch(struct device_queue_manager *dqm)
1131 {
1132 uint64_t num_sdma_queues;
1133 uint64_t num_xgmi_sdma_queues;
1134
1135 pr_debug("num of pipes: %d\n", get_pipes_per_mec(dqm));
1136
1137 mutex_init(&dqm->lock_hidden);
1138 INIT_LIST_HEAD(&dqm->queues);
1139 dqm->active_queue_count = dqm->processes_count = 0;
1140 dqm->active_cp_queue_count = 0;
1141 dqm->gws_queue_count = 0;
1142 dqm->active_runlist = false;
1143
1144 num_sdma_queues = get_num_sdma_queues(dqm);
1145 if (num_sdma_queues >= BITS_PER_TYPE(dqm->sdma_bitmap))
1146 dqm->sdma_bitmap = ULLONG_MAX;
1147 else
1148 dqm->sdma_bitmap = (BIT_ULL(num_sdma_queues) - 1);
1149
1150 num_xgmi_sdma_queues = get_num_xgmi_sdma_queues(dqm);
1151 if (num_xgmi_sdma_queues >= BITS_PER_TYPE(dqm->xgmi_sdma_bitmap))
1152 dqm->xgmi_sdma_bitmap = ULLONG_MAX;
1153 else
1154 dqm->xgmi_sdma_bitmap = (BIT_ULL(num_xgmi_sdma_queues) - 1);
1155
1156 INIT_WORK(&dqm->hw_exception_work, kfd_process_hw_exception);
1157
1158 return 0;
1159 }
1160
start_cpsch(struct device_queue_manager * dqm)1161 static int start_cpsch(struct device_queue_manager *dqm)
1162 {
1163 int retval;
1164
1165 retval = 0;
1166
1167 retval = pm_init(&dqm->packets, dqm);
1168 if (retval)
1169 goto fail_packet_manager_init;
1170
1171 retval = set_sched_resources(dqm);
1172 if (retval)
1173 goto fail_set_sched_resources;
1174
1175 pr_debug("Allocating fence memory\n");
1176
1177 /* allocate fence memory on the gart */
1178 retval = kfd_gtt_sa_allocate(dqm->dev, sizeof(*dqm->fence_addr),
1179 &dqm->fence_mem);
1180
1181 if (retval)
1182 goto fail_allocate_vidmem;
1183
1184 dqm->fence_addr = (uint64_t *)dqm->fence_mem->cpu_ptr;
1185 dqm->fence_gpu_addr = dqm->fence_mem->gpu_addr;
1186
1187 init_interrupts(dqm);
1188
1189 dqm_lock(dqm);
1190 /* clear hang status when driver try to start the hw scheduler */
1191 dqm->is_hws_hang = false;
1192 dqm->is_resetting = false;
1193 dqm->sched_running = true;
1194 execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0);
1195 dqm_unlock(dqm);
1196
1197 return 0;
1198 fail_allocate_vidmem:
1199 fail_set_sched_resources:
1200 pm_uninit(&dqm->packets, false);
1201 fail_packet_manager_init:
1202 return retval;
1203 }
1204
stop_cpsch(struct device_queue_manager * dqm)1205 static int stop_cpsch(struct device_queue_manager *dqm)
1206 {
1207 bool hanging;
1208
1209 dqm_lock(dqm);
1210 if (!dqm->sched_running) {
1211 dqm_unlock(dqm);
1212 return 0;
1213 }
1214
1215 if (!dqm->is_hws_hang)
1216 unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0);
1217 hanging = dqm->is_hws_hang || dqm->is_resetting;
1218 dqm->sched_running = false;
1219 dqm_unlock(dqm);
1220
1221 pm_release_ib(&dqm->packets);
1222
1223 kfd_gtt_sa_free(dqm->dev, dqm->fence_mem);
1224 pm_uninit(&dqm->packets, hanging);
1225
1226 return 0;
1227 }
1228
create_kernel_queue_cpsch(struct device_queue_manager * dqm,struct kernel_queue * kq,struct qcm_process_device * qpd)1229 static int create_kernel_queue_cpsch(struct device_queue_manager *dqm,
1230 struct kernel_queue *kq,
1231 struct qcm_process_device *qpd)
1232 {
1233 dqm_lock(dqm);
1234 if (dqm->total_queue_count >= max_num_of_queues_per_device) {
1235 pr_warn("Can't create new kernel queue because %d queues were already created\n",
1236 dqm->total_queue_count);
1237 dqm_unlock(dqm);
1238 return -EPERM;
1239 }
1240
1241 /*
1242 * Unconditionally increment this counter, regardless of the queue's
1243 * type or whether the queue is active.
1244 */
1245 dqm->total_queue_count++;
1246 pr_debug("Total of %d queues are accountable so far\n",
1247 dqm->total_queue_count);
1248
1249 list_add(&kq->list, &qpd->priv_queue_list);
1250 increment_queue_count(dqm, qpd, kq->queue);
1251 qpd->is_debug = true;
1252 execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0);
1253 dqm_unlock(dqm);
1254
1255 return 0;
1256 }
1257
destroy_kernel_queue_cpsch(struct device_queue_manager * dqm,struct kernel_queue * kq,struct qcm_process_device * qpd)1258 static void destroy_kernel_queue_cpsch(struct device_queue_manager *dqm,
1259 struct kernel_queue *kq,
1260 struct qcm_process_device *qpd)
1261 {
1262 dqm_lock(dqm);
1263 list_del(&kq->list);
1264 decrement_queue_count(dqm, qpd, kq->queue);
1265 qpd->is_debug = false;
1266 execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0);
1267 /*
1268 * Unconditionally decrement this counter, regardless of the queue's
1269 * type.
1270 */
1271 dqm->total_queue_count--;
1272 pr_debug("Total of %d queues are accountable so far\n",
1273 dqm->total_queue_count);
1274 dqm_unlock(dqm);
1275 }
1276
create_queue_cpsch(struct device_queue_manager * dqm,struct queue * q,struct qcm_process_device * qpd)1277 static int create_queue_cpsch(struct device_queue_manager *dqm, struct queue *q,
1278 struct qcm_process_device *qpd)
1279 {
1280 int retval;
1281 struct mqd_manager *mqd_mgr;
1282
1283 if (dqm->total_queue_count >= max_num_of_queues_per_device) {
1284 pr_warn("Can't create new usermode queue because %d queues were already created\n",
1285 dqm->total_queue_count);
1286 retval = -EPERM;
1287 goto out;
1288 }
1289
1290 if (q->properties.type == KFD_QUEUE_TYPE_SDMA ||
1291 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) {
1292 dqm_lock(dqm);
1293 retval = allocate_sdma_queue(dqm, q);
1294 dqm_unlock(dqm);
1295 if (retval)
1296 goto out;
1297 }
1298
1299 retval = allocate_doorbell(qpd, q);
1300 if (retval)
1301 goto out_deallocate_sdma_queue;
1302
1303 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
1304 q->properties.type)];
1305
1306 if (q->properties.type == KFD_QUEUE_TYPE_SDMA ||
1307 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)
1308 dqm->asic_ops.init_sdma_vm(dqm, q, qpd);
1309 q->properties.tba_addr = qpd->tba_addr;
1310 q->properties.tma_addr = qpd->tma_addr;
1311 q->mqd_mem_obj = mqd_mgr->allocate_mqd(mqd_mgr->dev, &q->properties);
1312 if (!q->mqd_mem_obj) {
1313 retval = -ENOMEM;
1314 goto out_deallocate_doorbell;
1315 }
1316
1317 dqm_lock(dqm);
1318 /*
1319 * Eviction state logic: mark all queues as evicted, even ones
1320 * not currently active. Restoring inactive queues later only
1321 * updates the is_evicted flag but is a no-op otherwise.
1322 */
1323 q->properties.is_evicted = !!qpd->evicted;
1324 mqd_mgr->init_mqd(mqd_mgr, &q->mqd, q->mqd_mem_obj,
1325 &q->gart_mqd_addr, &q->properties);
1326
1327 list_add(&q->list, &qpd->queues_list);
1328 qpd->queue_count++;
1329
1330 if (q->properties.is_active) {
1331 increment_queue_count(dqm, qpd, q);
1332
1333 execute_queues_cpsch(dqm,
1334 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0);
1335 }
1336
1337 /*
1338 * Unconditionally increment this counter, regardless of the queue's
1339 * type or whether the queue is active.
1340 */
1341 dqm->total_queue_count++;
1342
1343 pr_debug("Total of %d queues are accountable so far\n",
1344 dqm->total_queue_count);
1345
1346 dqm_unlock(dqm);
1347 return retval;
1348
1349 out_deallocate_doorbell:
1350 deallocate_doorbell(qpd, q);
1351 out_deallocate_sdma_queue:
1352 if (q->properties.type == KFD_QUEUE_TYPE_SDMA ||
1353 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) {
1354 dqm_lock(dqm);
1355 deallocate_sdma_queue(dqm, q);
1356 dqm_unlock(dqm);
1357 }
1358 out:
1359 return retval;
1360 }
1361
amdkfd_fence_wait_timeout(uint64_t * fence_addr,uint64_t fence_value,unsigned int timeout_ms)1362 int amdkfd_fence_wait_timeout(uint64_t *fence_addr,
1363 uint64_t fence_value,
1364 unsigned int timeout_ms)
1365 {
1366 unsigned long end_jiffies = msecs_to_jiffies(timeout_ms) + jiffies;
1367
1368 while (*fence_addr != fence_value) {
1369 if (time_after(jiffies, end_jiffies)) {
1370 pr_err("qcm fence wait loop timeout expired\n");
1371 /* In HWS case, this is used to halt the driver thread
1372 * in order not to mess up CP states before doing
1373 * scandumps for FW debugging.
1374 */
1375 while (halt_if_hws_hang)
1376 schedule();
1377
1378 return -ETIME;
1379 }
1380 schedule();
1381 }
1382
1383 return 0;
1384 }
1385
1386 /* dqm->lock mutex has to be locked before calling this function */
map_queues_cpsch(struct device_queue_manager * dqm)1387 static int map_queues_cpsch(struct device_queue_manager *dqm)
1388 {
1389 int retval;
1390
1391 if (!dqm->sched_running)
1392 return 0;
1393 if (dqm->active_queue_count <= 0 || dqm->processes_count <= 0)
1394 return 0;
1395 if (dqm->active_runlist)
1396 return 0;
1397
1398 retval = pm_send_runlist(&dqm->packets, &dqm->queues);
1399 pr_debug("%s sent runlist\n", __func__);
1400 if (retval) {
1401 pr_err("failed to execute runlist\n");
1402 return retval;
1403 }
1404 dqm->active_runlist = true;
1405
1406 return retval;
1407 }
1408
1409 /* dqm->lock mutex has to be locked before calling this function */
unmap_queues_cpsch(struct device_queue_manager * dqm,enum kfd_unmap_queues_filter filter,uint32_t filter_param)1410 static int unmap_queues_cpsch(struct device_queue_manager *dqm,
1411 enum kfd_unmap_queues_filter filter,
1412 uint32_t filter_param)
1413 {
1414 int retval = 0;
1415
1416 if (!dqm->sched_running)
1417 return 0;
1418 if (dqm->is_hws_hang)
1419 return -EIO;
1420 if (!dqm->active_runlist)
1421 return retval;
1422
1423 retval = pm_send_unmap_queue(&dqm->packets, KFD_QUEUE_TYPE_COMPUTE,
1424 filter, filter_param, false, 0);
1425 if (retval)
1426 return retval;
1427
1428 *dqm->fence_addr = KFD_FENCE_INIT;
1429 pm_send_query_status(&dqm->packets, dqm->fence_gpu_addr,
1430 KFD_FENCE_COMPLETED);
1431 /* should be timed out */
1432 retval = amdkfd_fence_wait_timeout(dqm->fence_addr, KFD_FENCE_COMPLETED,
1433 queue_preemption_timeout_ms);
1434 if (retval) {
1435 pr_err("The cp might be in an unrecoverable state due to an unsuccessful queues preemption\n");
1436 dqm->is_hws_hang = true;
1437 /* It's possible we're detecting a HWS hang in the
1438 * middle of a GPU reset. No need to schedule another
1439 * reset in this case.
1440 */
1441 if (!dqm->is_resetting)
1442 schedule_work(&dqm->hw_exception_work);
1443 return retval;
1444 }
1445
1446 pm_release_ib(&dqm->packets);
1447 dqm->active_runlist = false;
1448
1449 return retval;
1450 }
1451
1452 /* dqm->lock mutex has to be locked before calling this function */
execute_queues_cpsch(struct device_queue_manager * dqm,enum kfd_unmap_queues_filter filter,uint32_t filter_param)1453 static int execute_queues_cpsch(struct device_queue_manager *dqm,
1454 enum kfd_unmap_queues_filter filter,
1455 uint32_t filter_param)
1456 {
1457 int retval;
1458
1459 if (dqm->is_hws_hang)
1460 return -EIO;
1461 retval = unmap_queues_cpsch(dqm, filter, filter_param);
1462 if (retval)
1463 return retval;
1464
1465 return map_queues_cpsch(dqm);
1466 }
1467
destroy_queue_cpsch(struct device_queue_manager * dqm,struct qcm_process_device * qpd,struct queue * q)1468 static int destroy_queue_cpsch(struct device_queue_manager *dqm,
1469 struct qcm_process_device *qpd,
1470 struct queue *q)
1471 {
1472 int retval;
1473 struct mqd_manager *mqd_mgr;
1474 uint64_t sdma_val = 0;
1475 struct kfd_process_device *pdd = qpd_to_pdd(qpd);
1476
1477 /* Get the SDMA queue stats */
1478 if ((q->properties.type == KFD_QUEUE_TYPE_SDMA) ||
1479 (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)) {
1480 retval = read_sdma_queue_counter((uint64_t __user *)q->properties.read_ptr,
1481 &sdma_val);
1482 if (retval)
1483 pr_err("Failed to read SDMA queue counter for queue: %d\n",
1484 q->properties.queue_id);
1485 }
1486
1487 retval = 0;
1488
1489 /* remove queue from list to prevent rescheduling after preemption */
1490 dqm_lock(dqm);
1491
1492 if (qpd->is_debug) {
1493 /*
1494 * error, currently we do not allow to destroy a queue
1495 * of a currently debugged process
1496 */
1497 retval = -EBUSY;
1498 goto failed_try_destroy_debugged_queue;
1499
1500 }
1501
1502 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
1503 q->properties.type)];
1504
1505 deallocate_doorbell(qpd, q);
1506
1507 if ((q->properties.type == KFD_QUEUE_TYPE_SDMA) ||
1508 (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)) {
1509 deallocate_sdma_queue(dqm, q);
1510 pdd->sdma_past_activity_counter += sdma_val;
1511 }
1512
1513 list_del(&q->list);
1514 qpd->queue_count--;
1515 if (q->properties.is_active) {
1516 decrement_queue_count(dqm, qpd, q);
1517 retval = execute_queues_cpsch(dqm,
1518 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0);
1519 if (retval == -ETIME)
1520 qpd->reset_wavefronts = true;
1521 }
1522
1523 /*
1524 * Unconditionally decrement this counter, regardless of the queue's
1525 * type
1526 */
1527 dqm->total_queue_count--;
1528 pr_debug("Total of %d queues are accountable so far\n",
1529 dqm->total_queue_count);
1530
1531 dqm_unlock(dqm);
1532
1533 /* Do free_mqd after dqm_unlock(dqm) to avoid circular locking */
1534 mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj);
1535
1536 return retval;
1537
1538 failed_try_destroy_debugged_queue:
1539
1540 dqm_unlock(dqm);
1541 return retval;
1542 }
1543
1544 /*
1545 * Low bits must be 0000/FFFF as required by HW, high bits must be 0 to
1546 * stay in user mode.
1547 */
1548 #define APE1_FIXED_BITS_MASK 0xFFFF80000000FFFFULL
1549 /* APE1 limit is inclusive and 64K aligned. */
1550 #define APE1_LIMIT_ALIGNMENT 0xFFFF
1551
set_cache_memory_policy(struct device_queue_manager * dqm,struct qcm_process_device * qpd,enum cache_policy default_policy,enum cache_policy alternate_policy,void __user * alternate_aperture_base,uint64_t alternate_aperture_size)1552 static bool set_cache_memory_policy(struct device_queue_manager *dqm,
1553 struct qcm_process_device *qpd,
1554 enum cache_policy default_policy,
1555 enum cache_policy alternate_policy,
1556 void __user *alternate_aperture_base,
1557 uint64_t alternate_aperture_size)
1558 {
1559 bool retval = true;
1560
1561 if (!dqm->asic_ops.set_cache_memory_policy)
1562 return retval;
1563
1564 dqm_lock(dqm);
1565
1566 if (alternate_aperture_size == 0) {
1567 /* base > limit disables APE1 */
1568 qpd->sh_mem_ape1_base = 1;
1569 qpd->sh_mem_ape1_limit = 0;
1570 } else {
1571 /*
1572 * In FSA64, APE1_Base[63:0] = { 16{SH_MEM_APE1_BASE[31]},
1573 * SH_MEM_APE1_BASE[31:0], 0x0000 }
1574 * APE1_Limit[63:0] = { 16{SH_MEM_APE1_LIMIT[31]},
1575 * SH_MEM_APE1_LIMIT[31:0], 0xFFFF }
1576 * Verify that the base and size parameters can be
1577 * represented in this format and convert them.
1578 * Additionally restrict APE1 to user-mode addresses.
1579 */
1580
1581 uint64_t base = (uintptr_t)alternate_aperture_base;
1582 uint64_t limit = base + alternate_aperture_size - 1;
1583
1584 if (limit <= base || (base & APE1_FIXED_BITS_MASK) != 0 ||
1585 (limit & APE1_FIXED_BITS_MASK) != APE1_LIMIT_ALIGNMENT) {
1586 retval = false;
1587 goto out;
1588 }
1589
1590 qpd->sh_mem_ape1_base = base >> 16;
1591 qpd->sh_mem_ape1_limit = limit >> 16;
1592 }
1593
1594 retval = dqm->asic_ops.set_cache_memory_policy(
1595 dqm,
1596 qpd,
1597 default_policy,
1598 alternate_policy,
1599 alternate_aperture_base,
1600 alternate_aperture_size);
1601
1602 if ((dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) && (qpd->vmid != 0))
1603 program_sh_mem_settings(dqm, qpd);
1604
1605 pr_debug("sh_mem_config: 0x%x, ape1_base: 0x%x, ape1_limit: 0x%x\n",
1606 qpd->sh_mem_config, qpd->sh_mem_ape1_base,
1607 qpd->sh_mem_ape1_limit);
1608
1609 out:
1610 dqm_unlock(dqm);
1611 return retval;
1612 }
1613
set_trap_handler(struct device_queue_manager * dqm,struct qcm_process_device * qpd,uint64_t tba_addr,uint64_t tma_addr)1614 static int set_trap_handler(struct device_queue_manager *dqm,
1615 struct qcm_process_device *qpd,
1616 uint64_t tba_addr,
1617 uint64_t tma_addr)
1618 {
1619 uint64_t *tma;
1620
1621 if (dqm->dev->cwsr_enabled) {
1622 /* Jump from CWSR trap handler to user trap */
1623 tma = (uint64_t *)(qpd->cwsr_kaddr + KFD_CWSR_TMA_OFFSET);
1624 tma[0] = tba_addr;
1625 tma[1] = tma_addr;
1626 } else {
1627 qpd->tba_addr = tba_addr;
1628 qpd->tma_addr = tma_addr;
1629 }
1630
1631 return 0;
1632 }
1633
process_termination_nocpsch(struct device_queue_manager * dqm,struct qcm_process_device * qpd)1634 static int process_termination_nocpsch(struct device_queue_manager *dqm,
1635 struct qcm_process_device *qpd)
1636 {
1637 struct queue *q;
1638 struct device_process_node *cur, *next_dpn;
1639 int retval = 0;
1640 bool found = false;
1641
1642 dqm_lock(dqm);
1643
1644 /* Clear all user mode queues */
1645 while (!list_empty(&qpd->queues_list)) {
1646 struct mqd_manager *mqd_mgr;
1647 int ret;
1648
1649 q = list_first_entry(&qpd->queues_list, struct queue, list);
1650 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
1651 q->properties.type)];
1652 ret = destroy_queue_nocpsch_locked(dqm, qpd, q);
1653 if (ret)
1654 retval = ret;
1655 dqm_unlock(dqm);
1656 mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj);
1657 dqm_lock(dqm);
1658 }
1659
1660 /* Unregister process */
1661 list_for_each_entry_safe(cur, next_dpn, &dqm->queues, list) {
1662 if (qpd == cur->qpd) {
1663 list_del(&cur->list);
1664 kfree(cur);
1665 dqm->processes_count--;
1666 found = true;
1667 break;
1668 }
1669 }
1670
1671 dqm_unlock(dqm);
1672
1673 /* Outside the DQM lock because under the DQM lock we can't do
1674 * reclaim or take other locks that others hold while reclaiming.
1675 */
1676 if (found)
1677 kfd_dec_compute_active(dqm->dev);
1678
1679 return retval;
1680 }
1681
get_wave_state(struct device_queue_manager * dqm,struct queue * q,void __user * ctl_stack,u32 * ctl_stack_used_size,u32 * save_area_used_size)1682 static int get_wave_state(struct device_queue_manager *dqm,
1683 struct queue *q,
1684 void __user *ctl_stack,
1685 u32 *ctl_stack_used_size,
1686 u32 *save_area_used_size)
1687 {
1688 struct mqd_manager *mqd_mgr;
1689
1690 dqm_lock(dqm);
1691
1692 mqd_mgr = dqm->mqd_mgrs[KFD_MQD_TYPE_CP];
1693
1694 if (q->properties.type != KFD_QUEUE_TYPE_COMPUTE ||
1695 q->properties.is_active || !q->device->cwsr_enabled ||
1696 !mqd_mgr->get_wave_state) {
1697 dqm_unlock(dqm);
1698 return -EINVAL;
1699 }
1700
1701 dqm_unlock(dqm);
1702
1703 /*
1704 * get_wave_state is outside the dqm lock to prevent circular locking
1705 * and the queue should be protected against destruction by the process
1706 * lock.
1707 */
1708 return mqd_mgr->get_wave_state(mqd_mgr, q->mqd, ctl_stack,
1709 ctl_stack_used_size, save_area_used_size);
1710 }
1711
process_termination_cpsch(struct device_queue_manager * dqm,struct qcm_process_device * qpd)1712 static int process_termination_cpsch(struct device_queue_manager *dqm,
1713 struct qcm_process_device *qpd)
1714 {
1715 int retval;
1716 struct queue *q;
1717 struct kernel_queue *kq, *kq_next;
1718 struct mqd_manager *mqd_mgr;
1719 struct device_process_node *cur, *next_dpn;
1720 enum kfd_unmap_queues_filter filter =
1721 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES;
1722 bool found = false;
1723
1724 retval = 0;
1725
1726 dqm_lock(dqm);
1727
1728 /* Clean all kernel queues */
1729 list_for_each_entry_safe(kq, kq_next, &qpd->priv_queue_list, list) {
1730 list_del(&kq->list);
1731 decrement_queue_count(dqm, qpd, kq->queue);
1732 qpd->is_debug = false;
1733 dqm->total_queue_count--;
1734 filter = KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES;
1735 }
1736
1737 /* Clear all user mode queues */
1738 list_for_each_entry(q, &qpd->queues_list, list) {
1739 if (q->properties.type == KFD_QUEUE_TYPE_SDMA)
1740 deallocate_sdma_queue(dqm, q);
1741 else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)
1742 deallocate_sdma_queue(dqm, q);
1743
1744 if (q->properties.is_active)
1745 decrement_queue_count(dqm, qpd, q);
1746
1747 dqm->total_queue_count--;
1748 }
1749
1750 /* Unregister process */
1751 list_for_each_entry_safe(cur, next_dpn, &dqm->queues, list) {
1752 if (qpd == cur->qpd) {
1753 list_del(&cur->list);
1754 kfree(cur);
1755 dqm->processes_count--;
1756 found = true;
1757 break;
1758 }
1759 }
1760
1761 retval = execute_queues_cpsch(dqm, filter, 0);
1762 if ((!dqm->is_hws_hang) && (retval || qpd->reset_wavefronts)) {
1763 pr_warn("Resetting wave fronts (cpsch) on dev %p\n", dqm->dev);
1764 dbgdev_wave_reset_wavefronts(dqm->dev, qpd->pqm->process);
1765 qpd->reset_wavefronts = false;
1766 }
1767
1768 /* Lastly, free mqd resources.
1769 * Do free_mqd() after dqm_unlock to avoid circular locking.
1770 */
1771 while (!list_empty(&qpd->queues_list)) {
1772 q = list_first_entry(&qpd->queues_list, struct queue, list);
1773 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
1774 q->properties.type)];
1775 list_del(&q->list);
1776 qpd->queue_count--;
1777 dqm_unlock(dqm);
1778 mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj);
1779 dqm_lock(dqm);
1780 }
1781 dqm_unlock(dqm);
1782
1783 /* Outside the DQM lock because under the DQM lock we can't do
1784 * reclaim or take other locks that others hold while reclaiming.
1785 */
1786 if (found)
1787 kfd_dec_compute_active(dqm->dev);
1788
1789 return retval;
1790 }
1791
init_mqd_managers(struct device_queue_manager * dqm)1792 static int init_mqd_managers(struct device_queue_manager *dqm)
1793 {
1794 int i, j;
1795 struct mqd_manager *mqd_mgr;
1796
1797 for (i = 0; i < KFD_MQD_TYPE_MAX; i++) {
1798 mqd_mgr = dqm->asic_ops.mqd_manager_init(i, dqm->dev);
1799 if (!mqd_mgr) {
1800 pr_err("mqd manager [%d] initialization failed\n", i);
1801 goto out_free;
1802 }
1803 dqm->mqd_mgrs[i] = mqd_mgr;
1804 }
1805
1806 return 0;
1807
1808 out_free:
1809 for (j = 0; j < i; j++) {
1810 kfree(dqm->mqd_mgrs[j]);
1811 dqm->mqd_mgrs[j] = NULL;
1812 }
1813
1814 return -ENOMEM;
1815 }
1816
1817 /* Allocate one hiq mqd (HWS) and all SDMA mqd in a continuous trunk*/
allocate_hiq_sdma_mqd(struct device_queue_manager * dqm)1818 static int allocate_hiq_sdma_mqd(struct device_queue_manager *dqm)
1819 {
1820 int retval;
1821 struct kfd_dev *dev = dqm->dev;
1822 struct kfd_mem_obj *mem_obj = &dqm->hiq_sdma_mqd;
1823 uint32_t size = dqm->mqd_mgrs[KFD_MQD_TYPE_SDMA]->mqd_size *
1824 get_num_all_sdma_engines(dqm) *
1825 dev->device_info->num_sdma_queues_per_engine +
1826 dqm->mqd_mgrs[KFD_MQD_TYPE_HIQ]->mqd_size;
1827
1828 retval = amdgpu_amdkfd_alloc_gtt_mem(dev->kgd, size,
1829 &(mem_obj->gtt_mem), &(mem_obj->gpu_addr),
1830 (void *)&(mem_obj->cpu_ptr), false);
1831
1832 return retval;
1833 }
1834
device_queue_manager_init(struct kfd_dev * dev)1835 struct device_queue_manager *device_queue_manager_init(struct kfd_dev *dev)
1836 {
1837 struct device_queue_manager *dqm;
1838
1839 pr_debug("Loading device queue manager\n");
1840
1841 dqm = kzalloc(sizeof(*dqm), GFP_KERNEL);
1842 if (!dqm)
1843 return NULL;
1844
1845 switch (dev->device_info->asic_family) {
1846 /* HWS is not available on Hawaii. */
1847 case CHIP_HAWAII:
1848 /* HWS depends on CWSR for timely dequeue. CWSR is not
1849 * available on Tonga.
1850 *
1851 * FIXME: This argument also applies to Kaveri.
1852 */
1853 case CHIP_TONGA:
1854 dqm->sched_policy = KFD_SCHED_POLICY_NO_HWS;
1855 break;
1856 default:
1857 dqm->sched_policy = sched_policy;
1858 break;
1859 }
1860
1861 dqm->dev = dev;
1862 switch (dqm->sched_policy) {
1863 case KFD_SCHED_POLICY_HWS:
1864 case KFD_SCHED_POLICY_HWS_NO_OVERSUBSCRIPTION:
1865 /* initialize dqm for cp scheduling */
1866 dqm->ops.create_queue = create_queue_cpsch;
1867 dqm->ops.initialize = initialize_cpsch;
1868 dqm->ops.start = start_cpsch;
1869 dqm->ops.stop = stop_cpsch;
1870 dqm->ops.pre_reset = pre_reset;
1871 dqm->ops.destroy_queue = destroy_queue_cpsch;
1872 dqm->ops.update_queue = update_queue;
1873 dqm->ops.register_process = register_process;
1874 dqm->ops.unregister_process = unregister_process;
1875 dqm->ops.uninitialize = uninitialize;
1876 dqm->ops.create_kernel_queue = create_kernel_queue_cpsch;
1877 dqm->ops.destroy_kernel_queue = destroy_kernel_queue_cpsch;
1878 dqm->ops.set_cache_memory_policy = set_cache_memory_policy;
1879 dqm->ops.set_trap_handler = set_trap_handler;
1880 dqm->ops.process_termination = process_termination_cpsch;
1881 dqm->ops.evict_process_queues = evict_process_queues_cpsch;
1882 dqm->ops.restore_process_queues = restore_process_queues_cpsch;
1883 dqm->ops.get_wave_state = get_wave_state;
1884 break;
1885 case KFD_SCHED_POLICY_NO_HWS:
1886 /* initialize dqm for no cp scheduling */
1887 dqm->ops.start = start_nocpsch;
1888 dqm->ops.stop = stop_nocpsch;
1889 dqm->ops.pre_reset = pre_reset;
1890 dqm->ops.create_queue = create_queue_nocpsch;
1891 dqm->ops.destroy_queue = destroy_queue_nocpsch;
1892 dqm->ops.update_queue = update_queue;
1893 dqm->ops.register_process = register_process;
1894 dqm->ops.unregister_process = unregister_process;
1895 dqm->ops.initialize = initialize_nocpsch;
1896 dqm->ops.uninitialize = uninitialize;
1897 dqm->ops.set_cache_memory_policy = set_cache_memory_policy;
1898 dqm->ops.set_trap_handler = set_trap_handler;
1899 dqm->ops.process_termination = process_termination_nocpsch;
1900 dqm->ops.evict_process_queues = evict_process_queues_nocpsch;
1901 dqm->ops.restore_process_queues =
1902 restore_process_queues_nocpsch;
1903 dqm->ops.get_wave_state = get_wave_state;
1904 break;
1905 default:
1906 pr_err("Invalid scheduling policy %d\n", dqm->sched_policy);
1907 goto out_free;
1908 }
1909
1910 switch (dev->device_info->asic_family) {
1911 case CHIP_CARRIZO:
1912 device_queue_manager_init_vi(&dqm->asic_ops);
1913 break;
1914
1915 case CHIP_KAVERI:
1916 device_queue_manager_init_cik(&dqm->asic_ops);
1917 break;
1918
1919 case CHIP_HAWAII:
1920 device_queue_manager_init_cik_hawaii(&dqm->asic_ops);
1921 break;
1922
1923 case CHIP_TONGA:
1924 case CHIP_FIJI:
1925 case CHIP_POLARIS10:
1926 case CHIP_POLARIS11:
1927 case CHIP_POLARIS12:
1928 case CHIP_VEGAM:
1929 device_queue_manager_init_vi_tonga(&dqm->asic_ops);
1930 break;
1931
1932 case CHIP_VEGA10:
1933 case CHIP_VEGA12:
1934 case CHIP_VEGA20:
1935 case CHIP_RAVEN:
1936 case CHIP_RENOIR:
1937 case CHIP_ARCTURUS:
1938 device_queue_manager_init_v9(&dqm->asic_ops);
1939 break;
1940 case CHIP_NAVI10:
1941 case CHIP_NAVI12:
1942 case CHIP_NAVI14:
1943 case CHIP_SIENNA_CICHLID:
1944 case CHIP_NAVY_FLOUNDER:
1945 device_queue_manager_init_v10_navi10(&dqm->asic_ops);
1946 break;
1947 default:
1948 WARN(1, "Unexpected ASIC family %u",
1949 dev->device_info->asic_family);
1950 goto out_free;
1951 }
1952
1953 if (init_mqd_managers(dqm))
1954 goto out_free;
1955
1956 if (allocate_hiq_sdma_mqd(dqm)) {
1957 pr_err("Failed to allocate hiq sdma mqd trunk buffer\n");
1958 goto out_free;
1959 }
1960
1961 if (!dqm->ops.initialize(dqm))
1962 return dqm;
1963
1964 out_free:
1965 kfree(dqm);
1966 return NULL;
1967 }
1968
deallocate_hiq_sdma_mqd(struct kfd_dev * dev,struct kfd_mem_obj * mqd)1969 static void deallocate_hiq_sdma_mqd(struct kfd_dev *dev,
1970 struct kfd_mem_obj *mqd)
1971 {
1972 WARN(!mqd, "No hiq sdma mqd trunk to free");
1973
1974 amdgpu_amdkfd_free_gtt_mem(dev->kgd, mqd->gtt_mem);
1975 }
1976
device_queue_manager_uninit(struct device_queue_manager * dqm)1977 void device_queue_manager_uninit(struct device_queue_manager *dqm)
1978 {
1979 dqm->ops.uninitialize(dqm);
1980 deallocate_hiq_sdma_mqd(dqm->dev, &dqm->hiq_sdma_mqd);
1981 kfree(dqm);
1982 }
1983
kfd_process_vm_fault(struct device_queue_manager * dqm,u32 pasid)1984 int kfd_process_vm_fault(struct device_queue_manager *dqm, u32 pasid)
1985 {
1986 struct kfd_process_device *pdd;
1987 struct kfd_process *p = kfd_lookup_process_by_pasid(pasid);
1988 int ret = 0;
1989
1990 if (!p)
1991 return -EINVAL;
1992 WARN(debug_evictions, "Evicting pid %d", p->lead_thread->pid);
1993 pdd = kfd_get_process_device_data(dqm->dev, p);
1994 if (pdd)
1995 ret = dqm->ops.evict_process_queues(dqm, &pdd->qpd);
1996 kfd_unref_process(p);
1997
1998 return ret;
1999 }
2000
kfd_process_hw_exception(struct work_struct * work)2001 static void kfd_process_hw_exception(struct work_struct *work)
2002 {
2003 struct device_queue_manager *dqm = container_of(work,
2004 struct device_queue_manager, hw_exception_work);
2005 amdgpu_amdkfd_gpu_reset(dqm->dev->kgd);
2006 }
2007
2008 #if defined(CONFIG_DEBUG_FS)
2009
seq_reg_dump(struct seq_file * m,uint32_t (* dump)[2],uint32_t n_regs)2010 static void seq_reg_dump(struct seq_file *m,
2011 uint32_t (*dump)[2], uint32_t n_regs)
2012 {
2013 uint32_t i, count;
2014
2015 for (i = 0, count = 0; i < n_regs; i++) {
2016 if (count == 0 ||
2017 dump[i-1][0] + sizeof(uint32_t) != dump[i][0]) {
2018 seq_printf(m, "%s %08x: %08x",
2019 i ? "\n" : "",
2020 dump[i][0], dump[i][1]);
2021 count = 7;
2022 } else {
2023 seq_printf(m, " %08x", dump[i][1]);
2024 count--;
2025 }
2026 }
2027
2028 seq_puts(m, "\n");
2029 }
2030
dqm_debugfs_hqds(struct seq_file * m,void * data)2031 int dqm_debugfs_hqds(struct seq_file *m, void *data)
2032 {
2033 struct device_queue_manager *dqm = data;
2034 uint32_t (*dump)[2], n_regs;
2035 int pipe, queue;
2036 int r = 0;
2037
2038 if (!dqm->sched_running) {
2039 seq_printf(m, " Device is stopped\n");
2040
2041 return 0;
2042 }
2043
2044 r = dqm->dev->kfd2kgd->hqd_dump(dqm->dev->kgd,
2045 KFD_CIK_HIQ_PIPE, KFD_CIK_HIQ_QUEUE,
2046 &dump, &n_regs);
2047 if (!r) {
2048 seq_printf(m, " HIQ on MEC %d Pipe %d Queue %d\n",
2049 KFD_CIK_HIQ_PIPE/get_pipes_per_mec(dqm)+1,
2050 KFD_CIK_HIQ_PIPE%get_pipes_per_mec(dqm),
2051 KFD_CIK_HIQ_QUEUE);
2052 seq_reg_dump(m, dump, n_regs);
2053
2054 kfree(dump);
2055 }
2056
2057 for (pipe = 0; pipe < get_pipes_per_mec(dqm); pipe++) {
2058 int pipe_offset = pipe * get_queues_per_pipe(dqm);
2059
2060 for (queue = 0; queue < get_queues_per_pipe(dqm); queue++) {
2061 if (!test_bit(pipe_offset + queue,
2062 dqm->dev->shared_resources.cp_queue_bitmap))
2063 continue;
2064
2065 r = dqm->dev->kfd2kgd->hqd_dump(
2066 dqm->dev->kgd, pipe, queue, &dump, &n_regs);
2067 if (r)
2068 break;
2069
2070 seq_printf(m, " CP Pipe %d, Queue %d\n",
2071 pipe, queue);
2072 seq_reg_dump(m, dump, n_regs);
2073
2074 kfree(dump);
2075 }
2076 }
2077
2078 for (pipe = 0; pipe < get_num_all_sdma_engines(dqm); pipe++) {
2079 for (queue = 0;
2080 queue < dqm->dev->device_info->num_sdma_queues_per_engine;
2081 queue++) {
2082 r = dqm->dev->kfd2kgd->hqd_sdma_dump(
2083 dqm->dev->kgd, pipe, queue, &dump, &n_regs);
2084 if (r)
2085 break;
2086
2087 seq_printf(m, " SDMA Engine %d, RLC %d\n",
2088 pipe, queue);
2089 seq_reg_dump(m, dump, n_regs);
2090
2091 kfree(dump);
2092 }
2093 }
2094
2095 return r;
2096 }
2097
dqm_debugfs_execute_queues(struct device_queue_manager * dqm)2098 int dqm_debugfs_execute_queues(struct device_queue_manager *dqm)
2099 {
2100 int r = 0;
2101
2102 dqm_lock(dqm);
2103 dqm->active_runlist = true;
2104 r = execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0);
2105 dqm_unlock(dqm);
2106
2107 return r;
2108 }
2109
2110 #endif
2111