1 /*
2 * Copyright (c) 2006 Luc Verhaegen (quirks list)
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 * Copyright 2010 Red Hat, Inc.
6 *
7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
8 * FB layer.
9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com>
10 *
11 * Permission is hereby granted, free of charge, to any person obtaining a
12 * copy of this software and associated documentation files (the "Software"),
13 * to deal in the Software without restriction, including without limitation
14 * the rights to use, copy, modify, merge, publish, distribute, sub license,
15 * and/or sell copies of the Software, and to permit persons to whom the
16 * Software is furnished to do so, subject to the following conditions:
17 *
18 * The above copyright notice and this permission notice (including the
19 * next paragraph) shall be included in all copies or substantial portions
20 * of the Software.
21 *
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
28 * DEALINGS IN THE SOFTWARE.
29 */
30
31 #include <linux/hdmi.h>
32 #include <linux/i2c.h>
33 #include <linux/kernel.h>
34 #include <linux/module.h>
35 #include <linux/slab.h>
36 #include <linux/vga_switcheroo.h>
37
38 #include <drm/drm_displayid.h>
39 #include <drm/drm_drv.h>
40 #include <drm/drm_edid.h>
41 #include <drm/drm_encoder.h>
42 #include <drm/drm_print.h>
43 #include <drm/drm_scdc_helper.h>
44
45 #include "drm_crtc_internal.h"
46
47 #define version_greater(edid, maj, min) \
48 (((edid)->version > (maj)) || \
49 ((edid)->version == (maj) && (edid)->revision > (min)))
50
51 #define EDID_EST_TIMINGS 16
52 #define EDID_STD_TIMINGS 8
53 #define EDID_DETAILED_TIMINGS 4
54
55 /*
56 * EDID blocks out in the wild have a variety of bugs, try to collect
57 * them here (note that userspace may work around broken monitors first,
58 * but fixes should make their way here so that the kernel "just works"
59 * on as many displays as possible).
60 */
61
62 /* First detailed mode wrong, use largest 60Hz mode */
63 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0)
64 /* Reported 135MHz pixel clock is too high, needs adjustment */
65 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1)
66 /* Prefer the largest mode at 75 Hz */
67 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2)
68 /* Detail timing is in cm not mm */
69 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3)
70 /* Detailed timing descriptors have bogus size values, so just take the
71 * maximum size and use that.
72 */
73 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4)
74 /* use +hsync +vsync for detailed mode */
75 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
76 /* Force reduced-blanking timings for detailed modes */
77 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7)
78 /* Force 8bpc */
79 #define EDID_QUIRK_FORCE_8BPC (1 << 8)
80 /* Force 12bpc */
81 #define EDID_QUIRK_FORCE_12BPC (1 << 9)
82 /* Force 6bpc */
83 #define EDID_QUIRK_FORCE_6BPC (1 << 10)
84 /* Force 10bpc */
85 #define EDID_QUIRK_FORCE_10BPC (1 << 11)
86 /* Non desktop display (i.e. HMD) */
87 #define EDID_QUIRK_NON_DESKTOP (1 << 12)
88
89 struct detailed_mode_closure {
90 struct drm_connector *connector;
91 struct edid *edid;
92 bool preferred;
93 u32 quirks;
94 int modes;
95 };
96
97 #define LEVEL_DMT 0
98 #define LEVEL_GTF 1
99 #define LEVEL_GTF2 2
100 #define LEVEL_CVT 3
101
102 static const struct edid_quirk {
103 char vendor[4];
104 int product_id;
105 u32 quirks;
106 } edid_quirk_list[] = {
107 /* Acer AL1706 */
108 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 },
109 /* Acer F51 */
110 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 },
111
112 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */
113 { "AEO", 0, EDID_QUIRK_FORCE_6BPC },
114
115 /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */
116 { "BOE", 0x78b, EDID_QUIRK_FORCE_6BPC },
117
118 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */
119 { "CPT", 0x17df, EDID_QUIRK_FORCE_6BPC },
120
121 /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */
122 { "SDC", 0x3652, EDID_QUIRK_FORCE_6BPC },
123
124 /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */
125 { "BOE", 0x0771, EDID_QUIRK_FORCE_6BPC },
126
127 /* Belinea 10 15 55 */
128 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 },
129 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 },
130
131 /* Envision Peripherals, Inc. EN-7100e */
132 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH },
133 /* Envision EN2028 */
134 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 },
135
136 /* Funai Electronics PM36B */
137 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 |
138 EDID_QUIRK_DETAILED_IN_CM },
139
140 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */
141 { "LGD", 764, EDID_QUIRK_FORCE_10BPC },
142
143 /* LG Philips LCD LP154W01-A5 */
144 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
145 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
146
147 /* Samsung SyncMaster 205BW. Note: irony */
148 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP },
149 /* Samsung SyncMaster 22[5-6]BW */
150 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 },
151 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 },
152
153 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */
154 { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC },
155
156 /* ViewSonic VA2026w */
157 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING },
158
159 /* Medion MD 30217 PG */
160 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 },
161
162 /* Lenovo G50 */
163 { "SDC", 18514, EDID_QUIRK_FORCE_6BPC },
164
165 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */
166 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC },
167
168 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/
169 { "ETR", 13896, EDID_QUIRK_FORCE_8BPC },
170
171 /* Valve Index Headset */
172 { "VLV", 0x91a8, EDID_QUIRK_NON_DESKTOP },
173 { "VLV", 0x91b0, EDID_QUIRK_NON_DESKTOP },
174 { "VLV", 0x91b1, EDID_QUIRK_NON_DESKTOP },
175 { "VLV", 0x91b2, EDID_QUIRK_NON_DESKTOP },
176 { "VLV", 0x91b3, EDID_QUIRK_NON_DESKTOP },
177 { "VLV", 0x91b4, EDID_QUIRK_NON_DESKTOP },
178 { "VLV", 0x91b5, EDID_QUIRK_NON_DESKTOP },
179 { "VLV", 0x91b6, EDID_QUIRK_NON_DESKTOP },
180 { "VLV", 0x91b7, EDID_QUIRK_NON_DESKTOP },
181 { "VLV", 0x91b8, EDID_QUIRK_NON_DESKTOP },
182 { "VLV", 0x91b9, EDID_QUIRK_NON_DESKTOP },
183 { "VLV", 0x91ba, EDID_QUIRK_NON_DESKTOP },
184 { "VLV", 0x91bb, EDID_QUIRK_NON_DESKTOP },
185 { "VLV", 0x91bc, EDID_QUIRK_NON_DESKTOP },
186 { "VLV", 0x91bd, EDID_QUIRK_NON_DESKTOP },
187 { "VLV", 0x91be, EDID_QUIRK_NON_DESKTOP },
188 { "VLV", 0x91bf, EDID_QUIRK_NON_DESKTOP },
189
190 /* HTC Vive and Vive Pro VR Headsets */
191 { "HVR", 0xaa01, EDID_QUIRK_NON_DESKTOP },
192 { "HVR", 0xaa02, EDID_QUIRK_NON_DESKTOP },
193
194 /* Oculus Rift DK1, DK2, CV1 and Rift S VR Headsets */
195 { "OVR", 0x0001, EDID_QUIRK_NON_DESKTOP },
196 { "OVR", 0x0003, EDID_QUIRK_NON_DESKTOP },
197 { "OVR", 0x0004, EDID_QUIRK_NON_DESKTOP },
198 { "OVR", 0x0012, EDID_QUIRK_NON_DESKTOP },
199
200 /* Windows Mixed Reality Headsets */
201 { "ACR", 0x7fce, EDID_QUIRK_NON_DESKTOP },
202 { "HPN", 0x3515, EDID_QUIRK_NON_DESKTOP },
203 { "LEN", 0x0408, EDID_QUIRK_NON_DESKTOP },
204 { "LEN", 0xb800, EDID_QUIRK_NON_DESKTOP },
205 { "FUJ", 0x1970, EDID_QUIRK_NON_DESKTOP },
206 { "DEL", 0x7fce, EDID_QUIRK_NON_DESKTOP },
207 { "SEC", 0x144a, EDID_QUIRK_NON_DESKTOP },
208 { "AUS", 0xc102, EDID_QUIRK_NON_DESKTOP },
209
210 /* Sony PlayStation VR Headset */
211 { "SNY", 0x0704, EDID_QUIRK_NON_DESKTOP },
212
213 /* Sensics VR Headsets */
214 { "SEN", 0x1019, EDID_QUIRK_NON_DESKTOP },
215
216 /* OSVR HDK and HDK2 VR Headsets */
217 { "SVR", 0x1019, EDID_QUIRK_NON_DESKTOP },
218 };
219
220 /*
221 * Autogenerated from the DMT spec.
222 * This table is copied from xfree86/modes/xf86EdidModes.c.
223 */
224 static const struct drm_display_mode drm_dmt_modes[] = {
225 /* 0x01 - 640x350@85Hz */
226 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
227 736, 832, 0, 350, 382, 385, 445, 0,
228 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
229 /* 0x02 - 640x400@85Hz */
230 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
231 736, 832, 0, 400, 401, 404, 445, 0,
232 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
233 /* 0x03 - 720x400@85Hz */
234 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
235 828, 936, 0, 400, 401, 404, 446, 0,
236 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
237 /* 0x04 - 640x480@60Hz */
238 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
239 752, 800, 0, 480, 490, 492, 525, 0,
240 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
241 /* 0x05 - 640x480@72Hz */
242 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
243 704, 832, 0, 480, 489, 492, 520, 0,
244 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
245 /* 0x06 - 640x480@75Hz */
246 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
247 720, 840, 0, 480, 481, 484, 500, 0,
248 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
249 /* 0x07 - 640x480@85Hz */
250 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
251 752, 832, 0, 480, 481, 484, 509, 0,
252 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
253 /* 0x08 - 800x600@56Hz */
254 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
255 896, 1024, 0, 600, 601, 603, 625, 0,
256 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
257 /* 0x09 - 800x600@60Hz */
258 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
259 968, 1056, 0, 600, 601, 605, 628, 0,
260 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
261 /* 0x0a - 800x600@72Hz */
262 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
263 976, 1040, 0, 600, 637, 643, 666, 0,
264 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
265 /* 0x0b - 800x600@75Hz */
266 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
267 896, 1056, 0, 600, 601, 604, 625, 0,
268 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
269 /* 0x0c - 800x600@85Hz */
270 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
271 896, 1048, 0, 600, 601, 604, 631, 0,
272 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
273 /* 0x0d - 800x600@120Hz RB */
274 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848,
275 880, 960, 0, 600, 603, 607, 636, 0,
276 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
277 /* 0x0e - 848x480@60Hz */
278 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
279 976, 1088, 0, 480, 486, 494, 517, 0,
280 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
281 /* 0x0f - 1024x768@43Hz, interlace */
282 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
283 1208, 1264, 0, 768, 768, 776, 817, 0,
284 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
285 DRM_MODE_FLAG_INTERLACE) },
286 /* 0x10 - 1024x768@60Hz */
287 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
288 1184, 1344, 0, 768, 771, 777, 806, 0,
289 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
290 /* 0x11 - 1024x768@70Hz */
291 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
292 1184, 1328, 0, 768, 771, 777, 806, 0,
293 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
294 /* 0x12 - 1024x768@75Hz */
295 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
296 1136, 1312, 0, 768, 769, 772, 800, 0,
297 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
298 /* 0x13 - 1024x768@85Hz */
299 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
300 1168, 1376, 0, 768, 769, 772, 808, 0,
301 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
302 /* 0x14 - 1024x768@120Hz RB */
303 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072,
304 1104, 1184, 0, 768, 771, 775, 813, 0,
305 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
306 /* 0x15 - 1152x864@75Hz */
307 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
308 1344, 1600, 0, 864, 865, 868, 900, 0,
309 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
310 /* 0x55 - 1280x720@60Hz */
311 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
312 1430, 1650, 0, 720, 725, 730, 750, 0,
313 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
314 /* 0x16 - 1280x768@60Hz RB */
315 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328,
316 1360, 1440, 0, 768, 771, 778, 790, 0,
317 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
318 /* 0x17 - 1280x768@60Hz */
319 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
320 1472, 1664, 0, 768, 771, 778, 798, 0,
321 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
322 /* 0x18 - 1280x768@75Hz */
323 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
324 1488, 1696, 0, 768, 771, 778, 805, 0,
325 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
326 /* 0x19 - 1280x768@85Hz */
327 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
328 1496, 1712, 0, 768, 771, 778, 809, 0,
329 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
330 /* 0x1a - 1280x768@120Hz RB */
331 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328,
332 1360, 1440, 0, 768, 771, 778, 813, 0,
333 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
334 /* 0x1b - 1280x800@60Hz RB */
335 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328,
336 1360, 1440, 0, 800, 803, 809, 823, 0,
337 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
338 /* 0x1c - 1280x800@60Hz */
339 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
340 1480, 1680, 0, 800, 803, 809, 831, 0,
341 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
342 /* 0x1d - 1280x800@75Hz */
343 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
344 1488, 1696, 0, 800, 803, 809, 838, 0,
345 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
346 /* 0x1e - 1280x800@85Hz */
347 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
348 1496, 1712, 0, 800, 803, 809, 843, 0,
349 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
350 /* 0x1f - 1280x800@120Hz RB */
351 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328,
352 1360, 1440, 0, 800, 803, 809, 847, 0,
353 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
354 /* 0x20 - 1280x960@60Hz */
355 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
356 1488, 1800, 0, 960, 961, 964, 1000, 0,
357 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
358 /* 0x21 - 1280x960@85Hz */
359 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
360 1504, 1728, 0, 960, 961, 964, 1011, 0,
361 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
362 /* 0x22 - 1280x960@120Hz RB */
363 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328,
364 1360, 1440, 0, 960, 963, 967, 1017, 0,
365 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
366 /* 0x23 - 1280x1024@60Hz */
367 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
368 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
369 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
370 /* 0x24 - 1280x1024@75Hz */
371 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
372 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
373 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
374 /* 0x25 - 1280x1024@85Hz */
375 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
376 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
377 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
378 /* 0x26 - 1280x1024@120Hz RB */
379 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328,
380 1360, 1440, 0, 1024, 1027, 1034, 1084, 0,
381 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
382 /* 0x27 - 1360x768@60Hz */
383 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
384 1536, 1792, 0, 768, 771, 777, 795, 0,
385 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
386 /* 0x28 - 1360x768@120Hz RB */
387 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408,
388 1440, 1520, 0, 768, 771, 776, 813, 0,
389 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
390 /* 0x51 - 1366x768@60Hz */
391 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436,
392 1579, 1792, 0, 768, 771, 774, 798, 0,
393 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
394 /* 0x56 - 1366x768@60Hz */
395 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380,
396 1436, 1500, 0, 768, 769, 772, 800, 0,
397 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
398 /* 0x29 - 1400x1050@60Hz RB */
399 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448,
400 1480, 1560, 0, 1050, 1053, 1057, 1080, 0,
401 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
402 /* 0x2a - 1400x1050@60Hz */
403 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
404 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
405 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
406 /* 0x2b - 1400x1050@75Hz */
407 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
408 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
409 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
410 /* 0x2c - 1400x1050@85Hz */
411 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
412 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
413 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
414 /* 0x2d - 1400x1050@120Hz RB */
415 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448,
416 1480, 1560, 0, 1050, 1053, 1057, 1112, 0,
417 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
418 /* 0x2e - 1440x900@60Hz RB */
419 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488,
420 1520, 1600, 0, 900, 903, 909, 926, 0,
421 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
422 /* 0x2f - 1440x900@60Hz */
423 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
424 1672, 1904, 0, 900, 903, 909, 934, 0,
425 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
426 /* 0x30 - 1440x900@75Hz */
427 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
428 1688, 1936, 0, 900, 903, 909, 942, 0,
429 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
430 /* 0x31 - 1440x900@85Hz */
431 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
432 1696, 1952, 0, 900, 903, 909, 948, 0,
433 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
434 /* 0x32 - 1440x900@120Hz RB */
435 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488,
436 1520, 1600, 0, 900, 903, 909, 953, 0,
437 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
438 /* 0x53 - 1600x900@60Hz */
439 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624,
440 1704, 1800, 0, 900, 901, 904, 1000, 0,
441 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
442 /* 0x33 - 1600x1200@60Hz */
443 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
444 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
445 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
446 /* 0x34 - 1600x1200@65Hz */
447 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
448 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
449 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
450 /* 0x35 - 1600x1200@70Hz */
451 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
452 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
453 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
454 /* 0x36 - 1600x1200@75Hz */
455 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,
456 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
457 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
458 /* 0x37 - 1600x1200@85Hz */
459 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
460 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
461 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
462 /* 0x38 - 1600x1200@120Hz RB */
463 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648,
464 1680, 1760, 0, 1200, 1203, 1207, 1271, 0,
465 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
466 /* 0x39 - 1680x1050@60Hz RB */
467 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728,
468 1760, 1840, 0, 1050, 1053, 1059, 1080, 0,
469 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
470 /* 0x3a - 1680x1050@60Hz */
471 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
472 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
473 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
474 /* 0x3b - 1680x1050@75Hz */
475 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
476 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
477 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
478 /* 0x3c - 1680x1050@85Hz */
479 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
480 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
481 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
482 /* 0x3d - 1680x1050@120Hz RB */
483 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728,
484 1760, 1840, 0, 1050, 1053, 1059, 1112, 0,
485 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
486 /* 0x3e - 1792x1344@60Hz */
487 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
488 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
489 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
490 /* 0x3f - 1792x1344@75Hz */
491 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
492 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
493 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
494 /* 0x40 - 1792x1344@120Hz RB */
495 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840,
496 1872, 1952, 0, 1344, 1347, 1351, 1423, 0,
497 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
498 /* 0x41 - 1856x1392@60Hz */
499 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
500 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
501 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
502 /* 0x42 - 1856x1392@75Hz */
503 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
504 2208, 2560, 0, 1392, 1393, 1396, 1500, 0,
505 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
506 /* 0x43 - 1856x1392@120Hz RB */
507 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904,
508 1936, 2016, 0, 1392, 1395, 1399, 1474, 0,
509 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
510 /* 0x52 - 1920x1080@60Hz */
511 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
512 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
513 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
514 /* 0x44 - 1920x1200@60Hz RB */
515 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968,
516 2000, 2080, 0, 1200, 1203, 1209, 1235, 0,
517 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
518 /* 0x45 - 1920x1200@60Hz */
519 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
520 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
521 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
522 /* 0x46 - 1920x1200@75Hz */
523 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
524 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
525 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
526 /* 0x47 - 1920x1200@85Hz */
527 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
528 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
529 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
530 /* 0x48 - 1920x1200@120Hz RB */
531 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968,
532 2000, 2080, 0, 1200, 1203, 1209, 1271, 0,
533 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
534 /* 0x49 - 1920x1440@60Hz */
535 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
536 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
537 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
538 /* 0x4a - 1920x1440@75Hz */
539 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
540 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
541 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
542 /* 0x4b - 1920x1440@120Hz RB */
543 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968,
544 2000, 2080, 0, 1440, 1443, 1447, 1525, 0,
545 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
546 /* 0x54 - 2048x1152@60Hz */
547 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074,
548 2154, 2250, 0, 1152, 1153, 1156, 1200, 0,
549 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
550 /* 0x4c - 2560x1600@60Hz RB */
551 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608,
552 2640, 2720, 0, 1600, 1603, 1609, 1646, 0,
553 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
554 /* 0x4d - 2560x1600@60Hz */
555 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
556 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
557 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
558 /* 0x4e - 2560x1600@75Hz */
559 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
560 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
561 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
562 /* 0x4f - 2560x1600@85Hz */
563 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
564 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
565 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
566 /* 0x50 - 2560x1600@120Hz RB */
567 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608,
568 2640, 2720, 0, 1600, 1603, 1609, 1694, 0,
569 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
570 /* 0x57 - 4096x2160@60Hz RB */
571 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104,
572 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
573 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
574 /* 0x58 - 4096x2160@59.94Hz RB */
575 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104,
576 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
577 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
578 };
579
580 /*
581 * These more or less come from the DMT spec. The 720x400 modes are
582 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75
583 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode
584 * should be 1152x870, again for the Mac, but instead we use the x864 DMT
585 * mode.
586 *
587 * The DMT modes have been fact-checked; the rest are mild guesses.
588 */
589 static const struct drm_display_mode edid_est_modes[] = {
590 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
591 968, 1056, 0, 600, 601, 605, 628, 0,
592 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
593 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
594 896, 1024, 0, 600, 601, 603, 625, 0,
595 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
596 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
597 720, 840, 0, 480, 481, 484, 500, 0,
598 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
599 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
600 704, 832, 0, 480, 489, 492, 520, 0,
601 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
602 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
603 768, 864, 0, 480, 483, 486, 525, 0,
604 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
605 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
606 752, 800, 0, 480, 490, 492, 525, 0,
607 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
608 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
609 846, 900, 0, 400, 421, 423, 449, 0,
610 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
611 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
612 846, 900, 0, 400, 412, 414, 449, 0,
613 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
614 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
615 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
616 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
617 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
618 1136, 1312, 0, 768, 769, 772, 800, 0,
619 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
620 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
621 1184, 1328, 0, 768, 771, 777, 806, 0,
622 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
623 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
624 1184, 1344, 0, 768, 771, 777, 806, 0,
625 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
626 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
627 1208, 1264, 0, 768, 768, 776, 817, 0,
628 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
629 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
630 928, 1152, 0, 624, 625, 628, 667, 0,
631 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
632 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
633 896, 1056, 0, 600, 601, 604, 625, 0,
634 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
635 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
636 976, 1040, 0, 600, 637, 643, 666, 0,
637 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
638 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
639 1344, 1600, 0, 864, 865, 868, 900, 0,
640 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
641 };
642
643 struct minimode {
644 short w;
645 short h;
646 short r;
647 short rb;
648 };
649
650 static const struct minimode est3_modes[] = {
651 /* byte 6 */
652 { 640, 350, 85, 0 },
653 { 640, 400, 85, 0 },
654 { 720, 400, 85, 0 },
655 { 640, 480, 85, 0 },
656 { 848, 480, 60, 0 },
657 { 800, 600, 85, 0 },
658 { 1024, 768, 85, 0 },
659 { 1152, 864, 75, 0 },
660 /* byte 7 */
661 { 1280, 768, 60, 1 },
662 { 1280, 768, 60, 0 },
663 { 1280, 768, 75, 0 },
664 { 1280, 768, 85, 0 },
665 { 1280, 960, 60, 0 },
666 { 1280, 960, 85, 0 },
667 { 1280, 1024, 60, 0 },
668 { 1280, 1024, 85, 0 },
669 /* byte 8 */
670 { 1360, 768, 60, 0 },
671 { 1440, 900, 60, 1 },
672 { 1440, 900, 60, 0 },
673 { 1440, 900, 75, 0 },
674 { 1440, 900, 85, 0 },
675 { 1400, 1050, 60, 1 },
676 { 1400, 1050, 60, 0 },
677 { 1400, 1050, 75, 0 },
678 /* byte 9 */
679 { 1400, 1050, 85, 0 },
680 { 1680, 1050, 60, 1 },
681 { 1680, 1050, 60, 0 },
682 { 1680, 1050, 75, 0 },
683 { 1680, 1050, 85, 0 },
684 { 1600, 1200, 60, 0 },
685 { 1600, 1200, 65, 0 },
686 { 1600, 1200, 70, 0 },
687 /* byte 10 */
688 { 1600, 1200, 75, 0 },
689 { 1600, 1200, 85, 0 },
690 { 1792, 1344, 60, 0 },
691 { 1792, 1344, 75, 0 },
692 { 1856, 1392, 60, 0 },
693 { 1856, 1392, 75, 0 },
694 { 1920, 1200, 60, 1 },
695 { 1920, 1200, 60, 0 },
696 /* byte 11 */
697 { 1920, 1200, 75, 0 },
698 { 1920, 1200, 85, 0 },
699 { 1920, 1440, 60, 0 },
700 { 1920, 1440, 75, 0 },
701 };
702
703 static const struct minimode extra_modes[] = {
704 { 1024, 576, 60, 0 },
705 { 1366, 768, 60, 0 },
706 { 1600, 900, 60, 0 },
707 { 1680, 945, 60, 0 },
708 { 1920, 1080, 60, 0 },
709 { 2048, 1152, 60, 0 },
710 { 2048, 1536, 60, 0 },
711 };
712
713 /*
714 * From CEA/CTA-861 spec.
715 *
716 * Do not access directly, instead always use cea_mode_for_vic().
717 */
718 static const struct drm_display_mode edid_cea_modes_1[] = {
719 /* 1 - 640x480@60Hz 4:3 */
720 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
721 752, 800, 0, 480, 490, 492, 525, 0,
722 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
723 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
724 /* 2 - 720x480@60Hz 4:3 */
725 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
726 798, 858, 0, 480, 489, 495, 525, 0,
727 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
728 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
729 /* 3 - 720x480@60Hz 16:9 */
730 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
731 798, 858, 0, 480, 489, 495, 525, 0,
732 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
733 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
734 /* 4 - 1280x720@60Hz 16:9 */
735 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
736 1430, 1650, 0, 720, 725, 730, 750, 0,
737 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
738 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
739 /* 5 - 1920x1080i@60Hz 16:9 */
740 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
741 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
742 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
743 DRM_MODE_FLAG_INTERLACE),
744 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
745 /* 6 - 720(1440)x480i@60Hz 4:3 */
746 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
747 801, 858, 0, 480, 488, 494, 525, 0,
748 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
749 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
750 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
751 /* 7 - 720(1440)x480i@60Hz 16:9 */
752 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
753 801, 858, 0, 480, 488, 494, 525, 0,
754 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
755 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
756 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
757 /* 8 - 720(1440)x240@60Hz 4:3 */
758 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
759 801, 858, 0, 240, 244, 247, 262, 0,
760 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
761 DRM_MODE_FLAG_DBLCLK),
762 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
763 /* 9 - 720(1440)x240@60Hz 16:9 */
764 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
765 801, 858, 0, 240, 244, 247, 262, 0,
766 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
767 DRM_MODE_FLAG_DBLCLK),
768 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
769 /* 10 - 2880x480i@60Hz 4:3 */
770 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
771 3204, 3432, 0, 480, 488, 494, 525, 0,
772 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
773 DRM_MODE_FLAG_INTERLACE),
774 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
775 /* 11 - 2880x480i@60Hz 16:9 */
776 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
777 3204, 3432, 0, 480, 488, 494, 525, 0,
778 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
779 DRM_MODE_FLAG_INTERLACE),
780 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
781 /* 12 - 2880x240@60Hz 4:3 */
782 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
783 3204, 3432, 0, 240, 244, 247, 262, 0,
784 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
785 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
786 /* 13 - 2880x240@60Hz 16:9 */
787 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
788 3204, 3432, 0, 240, 244, 247, 262, 0,
789 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
790 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
791 /* 14 - 1440x480@60Hz 4:3 */
792 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
793 1596, 1716, 0, 480, 489, 495, 525, 0,
794 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
795 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
796 /* 15 - 1440x480@60Hz 16:9 */
797 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
798 1596, 1716, 0, 480, 489, 495, 525, 0,
799 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
800 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
801 /* 16 - 1920x1080@60Hz 16:9 */
802 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
803 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
804 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
805 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
806 /* 17 - 720x576@50Hz 4:3 */
807 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
808 796, 864, 0, 576, 581, 586, 625, 0,
809 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
810 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
811 /* 18 - 720x576@50Hz 16:9 */
812 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
813 796, 864, 0, 576, 581, 586, 625, 0,
814 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
815 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
816 /* 19 - 1280x720@50Hz 16:9 */
817 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
818 1760, 1980, 0, 720, 725, 730, 750, 0,
819 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
820 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
821 /* 20 - 1920x1080i@50Hz 16:9 */
822 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
823 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
824 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
825 DRM_MODE_FLAG_INTERLACE),
826 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
827 /* 21 - 720(1440)x576i@50Hz 4:3 */
828 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
829 795, 864, 0, 576, 580, 586, 625, 0,
830 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
831 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
832 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
833 /* 22 - 720(1440)x576i@50Hz 16:9 */
834 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
835 795, 864, 0, 576, 580, 586, 625, 0,
836 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
837 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
838 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
839 /* 23 - 720(1440)x288@50Hz 4:3 */
840 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
841 795, 864, 0, 288, 290, 293, 312, 0,
842 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
843 DRM_MODE_FLAG_DBLCLK),
844 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
845 /* 24 - 720(1440)x288@50Hz 16:9 */
846 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
847 795, 864, 0, 288, 290, 293, 312, 0,
848 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
849 DRM_MODE_FLAG_DBLCLK),
850 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
851 /* 25 - 2880x576i@50Hz 4:3 */
852 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
853 3180, 3456, 0, 576, 580, 586, 625, 0,
854 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
855 DRM_MODE_FLAG_INTERLACE),
856 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
857 /* 26 - 2880x576i@50Hz 16:9 */
858 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
859 3180, 3456, 0, 576, 580, 586, 625, 0,
860 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
861 DRM_MODE_FLAG_INTERLACE),
862 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
863 /* 27 - 2880x288@50Hz 4:3 */
864 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
865 3180, 3456, 0, 288, 290, 293, 312, 0,
866 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
867 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
868 /* 28 - 2880x288@50Hz 16:9 */
869 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
870 3180, 3456, 0, 288, 290, 293, 312, 0,
871 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
872 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
873 /* 29 - 1440x576@50Hz 4:3 */
874 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
875 1592, 1728, 0, 576, 581, 586, 625, 0,
876 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
877 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
878 /* 30 - 1440x576@50Hz 16:9 */
879 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
880 1592, 1728, 0, 576, 581, 586, 625, 0,
881 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
882 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
883 /* 31 - 1920x1080@50Hz 16:9 */
884 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
885 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
886 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
887 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
888 /* 32 - 1920x1080@24Hz 16:9 */
889 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
890 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
891 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
892 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
893 /* 33 - 1920x1080@25Hz 16:9 */
894 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
895 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
896 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
897 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
898 /* 34 - 1920x1080@30Hz 16:9 */
899 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
900 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
901 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
902 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
903 /* 35 - 2880x480@60Hz 4:3 */
904 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
905 3192, 3432, 0, 480, 489, 495, 525, 0,
906 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
907 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
908 /* 36 - 2880x480@60Hz 16:9 */
909 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
910 3192, 3432, 0, 480, 489, 495, 525, 0,
911 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
912 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
913 /* 37 - 2880x576@50Hz 4:3 */
914 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
915 3184, 3456, 0, 576, 581, 586, 625, 0,
916 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
917 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
918 /* 38 - 2880x576@50Hz 16:9 */
919 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
920 3184, 3456, 0, 576, 581, 586, 625, 0,
921 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
922 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
923 /* 39 - 1920x1080i@50Hz 16:9 */
924 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952,
925 2120, 2304, 0, 1080, 1126, 1136, 1250, 0,
926 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC |
927 DRM_MODE_FLAG_INTERLACE),
928 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
929 /* 40 - 1920x1080i@100Hz 16:9 */
930 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
931 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
932 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
933 DRM_MODE_FLAG_INTERLACE),
934 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
935 /* 41 - 1280x720@100Hz 16:9 */
936 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
937 1760, 1980, 0, 720, 725, 730, 750, 0,
938 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
939 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
940 /* 42 - 720x576@100Hz 4:3 */
941 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
942 796, 864, 0, 576, 581, 586, 625, 0,
943 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
944 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
945 /* 43 - 720x576@100Hz 16:9 */
946 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
947 796, 864, 0, 576, 581, 586, 625, 0,
948 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
949 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
950 /* 44 - 720(1440)x576i@100Hz 4:3 */
951 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
952 795, 864, 0, 576, 580, 586, 625, 0,
953 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
954 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
955 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
956 /* 45 - 720(1440)x576i@100Hz 16:9 */
957 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
958 795, 864, 0, 576, 580, 586, 625, 0,
959 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
960 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
961 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
962 /* 46 - 1920x1080i@120Hz 16:9 */
963 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
964 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
965 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
966 DRM_MODE_FLAG_INTERLACE),
967 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
968 /* 47 - 1280x720@120Hz 16:9 */
969 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
970 1430, 1650, 0, 720, 725, 730, 750, 0,
971 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
972 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
973 /* 48 - 720x480@120Hz 4:3 */
974 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
975 798, 858, 0, 480, 489, 495, 525, 0,
976 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
977 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
978 /* 49 - 720x480@120Hz 16:9 */
979 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
980 798, 858, 0, 480, 489, 495, 525, 0,
981 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
982 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
983 /* 50 - 720(1440)x480i@120Hz 4:3 */
984 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
985 801, 858, 0, 480, 488, 494, 525, 0,
986 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
987 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
988 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
989 /* 51 - 720(1440)x480i@120Hz 16:9 */
990 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
991 801, 858, 0, 480, 488, 494, 525, 0,
992 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
993 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
994 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
995 /* 52 - 720x576@200Hz 4:3 */
996 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
997 796, 864, 0, 576, 581, 586, 625, 0,
998 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
999 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1000 /* 53 - 720x576@200Hz 16:9 */
1001 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
1002 796, 864, 0, 576, 581, 586, 625, 0,
1003 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1004 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1005 /* 54 - 720(1440)x576i@200Hz 4:3 */
1006 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1007 795, 864, 0, 576, 580, 586, 625, 0,
1008 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1009 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1010 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1011 /* 55 - 720(1440)x576i@200Hz 16:9 */
1012 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1013 795, 864, 0, 576, 580, 586, 625, 0,
1014 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1015 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1016 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1017 /* 56 - 720x480@240Hz 4:3 */
1018 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1019 798, 858, 0, 480, 489, 495, 525, 0,
1020 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1021 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1022 /* 57 - 720x480@240Hz 16:9 */
1023 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1024 798, 858, 0, 480, 489, 495, 525, 0,
1025 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1026 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1027 /* 58 - 720(1440)x480i@240Hz 4:3 */
1028 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1029 801, 858, 0, 480, 488, 494, 525, 0,
1030 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1031 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1032 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1033 /* 59 - 720(1440)x480i@240Hz 16:9 */
1034 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1035 801, 858, 0, 480, 488, 494, 525, 0,
1036 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1037 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1038 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1039 /* 60 - 1280x720@24Hz 16:9 */
1040 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1041 3080, 3300, 0, 720, 725, 730, 750, 0,
1042 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1043 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1044 /* 61 - 1280x720@25Hz 16:9 */
1045 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1046 3740, 3960, 0, 720, 725, 730, 750, 0,
1047 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1048 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1049 /* 62 - 1280x720@30Hz 16:9 */
1050 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1051 3080, 3300, 0, 720, 725, 730, 750, 0,
1052 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1053 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1054 /* 63 - 1920x1080@120Hz 16:9 */
1055 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1056 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1057 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1058 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1059 /* 64 - 1920x1080@100Hz 16:9 */
1060 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1061 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1062 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1063 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1064 /* 65 - 1280x720@24Hz 64:27 */
1065 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1066 3080, 3300, 0, 720, 725, 730, 750, 0,
1067 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1068 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1069 /* 66 - 1280x720@25Hz 64:27 */
1070 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1071 3740, 3960, 0, 720, 725, 730, 750, 0,
1072 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1073 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1074 /* 67 - 1280x720@30Hz 64:27 */
1075 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1076 3080, 3300, 0, 720, 725, 730, 750, 0,
1077 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1078 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1079 /* 68 - 1280x720@50Hz 64:27 */
1080 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
1081 1760, 1980, 0, 720, 725, 730, 750, 0,
1082 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1083 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1084 /* 69 - 1280x720@60Hz 64:27 */
1085 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
1086 1430, 1650, 0, 720, 725, 730, 750, 0,
1087 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1088 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1089 /* 70 - 1280x720@100Hz 64:27 */
1090 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
1091 1760, 1980, 0, 720, 725, 730, 750, 0,
1092 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1093 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1094 /* 71 - 1280x720@120Hz 64:27 */
1095 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
1096 1430, 1650, 0, 720, 725, 730, 750, 0,
1097 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1098 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1099 /* 72 - 1920x1080@24Hz 64:27 */
1100 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
1101 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1102 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1103 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1104 /* 73 - 1920x1080@25Hz 64:27 */
1105 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
1106 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1107 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1108 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1109 /* 74 - 1920x1080@30Hz 64:27 */
1110 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
1111 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1112 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1113 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1114 /* 75 - 1920x1080@50Hz 64:27 */
1115 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
1116 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1117 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1118 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1119 /* 76 - 1920x1080@60Hz 64:27 */
1120 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
1121 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1122 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1123 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1124 /* 77 - 1920x1080@100Hz 64:27 */
1125 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1126 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1127 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1128 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1129 /* 78 - 1920x1080@120Hz 64:27 */
1130 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1131 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1132 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1133 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1134 /* 79 - 1680x720@24Hz 64:27 */
1135 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040,
1136 3080, 3300, 0, 720, 725, 730, 750, 0,
1137 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1138 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1139 /* 80 - 1680x720@25Hz 64:27 */
1140 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908,
1141 2948, 3168, 0, 720, 725, 730, 750, 0,
1142 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1143 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1144 /* 81 - 1680x720@30Hz 64:27 */
1145 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380,
1146 2420, 2640, 0, 720, 725, 730, 750, 0,
1147 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1148 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1149 /* 82 - 1680x720@50Hz 64:27 */
1150 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940,
1151 1980, 2200, 0, 720, 725, 730, 750, 0,
1152 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1153 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1154 /* 83 - 1680x720@60Hz 64:27 */
1155 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940,
1156 1980, 2200, 0, 720, 725, 730, 750, 0,
1157 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1158 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1159 /* 84 - 1680x720@100Hz 64:27 */
1160 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740,
1161 1780, 2000, 0, 720, 725, 730, 825, 0,
1162 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1163 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1164 /* 85 - 1680x720@120Hz 64:27 */
1165 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740,
1166 1780, 2000, 0, 720, 725, 730, 825, 0,
1167 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1168 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1169 /* 86 - 2560x1080@24Hz 64:27 */
1170 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558,
1171 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1172 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1173 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1174 /* 87 - 2560x1080@25Hz 64:27 */
1175 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008,
1176 3052, 3200, 0, 1080, 1084, 1089, 1125, 0,
1177 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1178 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1179 /* 88 - 2560x1080@30Hz 64:27 */
1180 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328,
1181 3372, 3520, 0, 1080, 1084, 1089, 1125, 0,
1182 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1183 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1184 /* 89 - 2560x1080@50Hz 64:27 */
1185 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108,
1186 3152, 3300, 0, 1080, 1084, 1089, 1125, 0,
1187 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1188 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1189 /* 90 - 2560x1080@60Hz 64:27 */
1190 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808,
1191 2852, 3000, 0, 1080, 1084, 1089, 1100, 0,
1192 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1193 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1194 /* 91 - 2560x1080@100Hz 64:27 */
1195 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778,
1196 2822, 2970, 0, 1080, 1084, 1089, 1250, 0,
1197 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1198 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1199 /* 92 - 2560x1080@120Hz 64:27 */
1200 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108,
1201 3152, 3300, 0, 1080, 1084, 1089, 1250, 0,
1202 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1203 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1204 /* 93 - 3840x2160@24Hz 16:9 */
1205 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1206 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1207 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1208 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1209 /* 94 - 3840x2160@25Hz 16:9 */
1210 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1211 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1212 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1213 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1214 /* 95 - 3840x2160@30Hz 16:9 */
1215 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1216 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1217 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1218 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1219 /* 96 - 3840x2160@50Hz 16:9 */
1220 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1221 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1222 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1223 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1224 /* 97 - 3840x2160@60Hz 16:9 */
1225 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1226 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1227 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1228 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1229 /* 98 - 4096x2160@24Hz 256:135 */
1230 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116,
1231 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1232 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1233 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1234 /* 99 - 4096x2160@25Hz 256:135 */
1235 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064,
1236 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1237 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1238 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1239 /* 100 - 4096x2160@30Hz 256:135 */
1240 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184,
1241 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1242 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1243 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1244 /* 101 - 4096x2160@50Hz 256:135 */
1245 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064,
1246 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1247 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1248 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1249 /* 102 - 4096x2160@60Hz 256:135 */
1250 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184,
1251 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1252 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1253 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1254 /* 103 - 3840x2160@24Hz 64:27 */
1255 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1256 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1257 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1258 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1259 /* 104 - 3840x2160@25Hz 64:27 */
1260 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1261 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1262 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1263 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1264 /* 105 - 3840x2160@30Hz 64:27 */
1265 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1266 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1267 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1268 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1269 /* 106 - 3840x2160@50Hz 64:27 */
1270 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1271 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1272 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1273 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1274 /* 107 - 3840x2160@60Hz 64:27 */
1275 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1276 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1277 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1278 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1279 /* 108 - 1280x720@48Hz 16:9 */
1280 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,
1281 2280, 2500, 0, 720, 725, 730, 750, 0,
1282 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1283 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1284 /* 109 - 1280x720@48Hz 64:27 */
1285 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,
1286 2280, 2500, 0, 720, 725, 730, 750, 0,
1287 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1288 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1289 /* 110 - 1680x720@48Hz 64:27 */
1290 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 2490,
1291 2530, 2750, 0, 720, 725, 730, 750, 0,
1292 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1293 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1294 /* 111 - 1920x1080@48Hz 16:9 */
1295 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
1296 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1297 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1298 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1299 /* 112 - 1920x1080@48Hz 64:27 */
1300 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
1301 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1302 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1303 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1304 /* 113 - 2560x1080@48Hz 64:27 */
1305 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 3558,
1306 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1307 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1308 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1309 /* 114 - 3840x2160@48Hz 16:9 */
1310 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
1311 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1312 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1313 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1314 /* 115 - 4096x2160@48Hz 256:135 */
1315 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5116,
1316 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1317 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1318 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1319 /* 116 - 3840x2160@48Hz 64:27 */
1320 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
1321 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1322 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1323 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1324 /* 117 - 3840x2160@100Hz 16:9 */
1325 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
1326 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1327 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1328 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1329 /* 118 - 3840x2160@120Hz 16:9 */
1330 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
1331 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1332 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1333 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1334 /* 119 - 3840x2160@100Hz 64:27 */
1335 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
1336 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1337 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1338 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1339 /* 120 - 3840x2160@120Hz 64:27 */
1340 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
1341 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1342 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1343 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1344 /* 121 - 5120x2160@24Hz 64:27 */
1345 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 7116,
1346 7204, 7500, 0, 2160, 2168, 2178, 2200, 0,
1347 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1348 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1349 /* 122 - 5120x2160@25Hz 64:27 */
1350 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 6816,
1351 6904, 7200, 0, 2160, 2168, 2178, 2200, 0,
1352 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1353 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1354 /* 123 - 5120x2160@30Hz 64:27 */
1355 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 5784,
1356 5872, 6000, 0, 2160, 2168, 2178, 2200, 0,
1357 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1358 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1359 /* 124 - 5120x2160@48Hz 64:27 */
1360 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5866,
1361 5954, 6250, 0, 2160, 2168, 2178, 2475, 0,
1362 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1363 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1364 /* 125 - 5120x2160@50Hz 64:27 */
1365 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 6216,
1366 6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
1367 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1368 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1369 /* 126 - 5120x2160@60Hz 64:27 */
1370 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5284,
1371 5372, 5500, 0, 2160, 2168, 2178, 2250, 0,
1372 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1373 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1374 /* 127 - 5120x2160@100Hz 64:27 */
1375 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 6216,
1376 6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
1377 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1378 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1379 };
1380
1381 /*
1382 * From CEA/CTA-861 spec.
1383 *
1384 * Do not access directly, instead always use cea_mode_for_vic().
1385 */
1386 static const struct drm_display_mode edid_cea_modes_193[] = {
1387 /* 193 - 5120x2160@120Hz 64:27 */
1388 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 5284,
1389 5372, 5500, 0, 2160, 2168, 2178, 2250, 0,
1390 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1391 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1392 /* 194 - 7680x4320@24Hz 16:9 */
1393 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,
1394 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1395 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1396 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1397 /* 195 - 7680x4320@25Hz 16:9 */
1398 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,
1399 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1400 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1401 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1402 /* 196 - 7680x4320@30Hz 16:9 */
1403 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,
1404 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1405 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1406 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1407 /* 197 - 7680x4320@48Hz 16:9 */
1408 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,
1409 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1410 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1411 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1412 /* 198 - 7680x4320@50Hz 16:9 */
1413 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032,
1414 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1415 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1416 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1417 /* 199 - 7680x4320@60Hz 16:9 */
1418 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232,
1419 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1420 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1421 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1422 /* 200 - 7680x4320@100Hz 16:9 */
1423 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792,
1424 9968, 10560, 0, 4320, 4336, 4356, 4500, 0,
1425 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1426 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1427 /* 201 - 7680x4320@120Hz 16:9 */
1428 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032,
1429 8208, 8800, 0, 4320, 4336, 4356, 4500, 0,
1430 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1431 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1432 /* 202 - 7680x4320@24Hz 64:27 */
1433 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,
1434 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1435 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1436 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1437 /* 203 - 7680x4320@25Hz 64:27 */
1438 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,
1439 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1440 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1441 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1442 /* 204 - 7680x4320@30Hz 64:27 */
1443 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,
1444 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1445 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1446 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1447 /* 205 - 7680x4320@48Hz 64:27 */
1448 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,
1449 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1450 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1451 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1452 /* 206 - 7680x4320@50Hz 64:27 */
1453 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032,
1454 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1455 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1456 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1457 /* 207 - 7680x4320@60Hz 64:27 */
1458 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232,
1459 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1460 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1461 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1462 /* 208 - 7680x4320@100Hz 64:27 */
1463 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792,
1464 9968, 10560, 0, 4320, 4336, 4356, 4500, 0,
1465 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1466 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1467 /* 209 - 7680x4320@120Hz 64:27 */
1468 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032,
1469 8208, 8800, 0, 4320, 4336, 4356, 4500, 0,
1470 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1471 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1472 /* 210 - 10240x4320@24Hz 64:27 */
1473 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 11732,
1474 11908, 12500, 0, 4320, 4336, 4356, 4950, 0,
1475 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1476 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1477 /* 211 - 10240x4320@25Hz 64:27 */
1478 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 12732,
1479 12908, 13500, 0, 4320, 4336, 4356, 4400, 0,
1480 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1481 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1482 /* 212 - 10240x4320@30Hz 64:27 */
1483 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 10528,
1484 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1485 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1486 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1487 /* 213 - 10240x4320@48Hz 64:27 */
1488 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 11732,
1489 11908, 12500, 0, 4320, 4336, 4356, 4950, 0,
1490 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1491 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1492 /* 214 - 10240x4320@50Hz 64:27 */
1493 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 12732,
1494 12908, 13500, 0, 4320, 4336, 4356, 4400, 0,
1495 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1496 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1497 /* 215 - 10240x4320@60Hz 64:27 */
1498 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 10528,
1499 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1500 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1501 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1502 /* 216 - 10240x4320@100Hz 64:27 */
1503 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 12432,
1504 12608, 13200, 0, 4320, 4336, 4356, 4500, 0,
1505 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1506 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1507 /* 217 - 10240x4320@120Hz 64:27 */
1508 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 10528,
1509 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1510 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1511 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1512 /* 218 - 4096x2160@100Hz 256:135 */
1513 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4896,
1514 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1515 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1516 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1517 /* 219 - 4096x2160@120Hz 256:135 */
1518 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4184,
1519 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1520 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1521 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1522 };
1523
1524 /*
1525 * HDMI 1.4 4k modes. Index using the VIC.
1526 */
1527 static const struct drm_display_mode edid_4k_modes[] = {
1528 /* 0 - dummy, VICs start at 1 */
1529 { },
1530 /* 1 - 3840x2160@30Hz */
1531 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1532 3840, 4016, 4104, 4400, 0,
1533 2160, 2168, 2178, 2250, 0,
1534 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1535 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1536 /* 2 - 3840x2160@25Hz */
1537 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1538 3840, 4896, 4984, 5280, 0,
1539 2160, 2168, 2178, 2250, 0,
1540 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1541 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1542 /* 3 - 3840x2160@24Hz */
1543 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1544 3840, 5116, 5204, 5500, 0,
1545 2160, 2168, 2178, 2250, 0,
1546 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1547 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1548 /* 4 - 4096x2160@24Hz (SMPTE) */
1549 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000,
1550 4096, 5116, 5204, 5500, 0,
1551 2160, 2168, 2178, 2250, 0,
1552 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1553 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1554 };
1555
1556 /*** DDC fetch and block validation ***/
1557
1558 static const u8 edid_header[] = {
1559 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
1560 };
1561
1562 /**
1563 * drm_edid_header_is_valid - sanity check the header of the base EDID block
1564 * @raw_edid: pointer to raw base EDID block
1565 *
1566 * Sanity check the header of the base EDID block.
1567 *
1568 * Return: 8 if the header is perfect, down to 0 if it's totally wrong.
1569 */
drm_edid_header_is_valid(const u8 * raw_edid)1570 int drm_edid_header_is_valid(const u8 *raw_edid)
1571 {
1572 int i, score = 0;
1573
1574 for (i = 0; i < sizeof(edid_header); i++)
1575 if (raw_edid[i] == edid_header[i])
1576 score++;
1577
1578 return score;
1579 }
1580 EXPORT_SYMBOL(drm_edid_header_is_valid);
1581
1582 static int edid_fixup __read_mostly = 6;
1583 module_param_named(edid_fixup, edid_fixup, int, 0400);
1584 MODULE_PARM_DESC(edid_fixup,
1585 "Minimum number of valid EDID header bytes (0-8, default 6)");
1586
1587 static int validate_displayid(u8 *displayid, int length, int idx);
1588
drm_edid_block_checksum(const u8 * raw_edid)1589 static int drm_edid_block_checksum(const u8 *raw_edid)
1590 {
1591 int i;
1592 u8 csum = 0, crc = 0;
1593
1594 for (i = 0; i < EDID_LENGTH - 1; i++)
1595 csum += raw_edid[i];
1596
1597 crc = 0x100 - csum;
1598
1599 return crc;
1600 }
1601
drm_edid_block_checksum_diff(const u8 * raw_edid,u8 real_checksum)1602 static bool drm_edid_block_checksum_diff(const u8 *raw_edid, u8 real_checksum)
1603 {
1604 if (raw_edid[EDID_LENGTH - 1] != real_checksum)
1605 return true;
1606 else
1607 return false;
1608 }
1609
drm_edid_is_zero(const u8 * in_edid,int length)1610 static bool drm_edid_is_zero(const u8 *in_edid, int length)
1611 {
1612 if (memchr_inv(in_edid, 0, length))
1613 return false;
1614
1615 return true;
1616 }
1617
1618 /**
1619 * drm_edid_are_equal - compare two edid blobs.
1620 * @edid1: pointer to first blob
1621 * @edid2: pointer to second blob
1622 * This helper can be used during probing to determine if
1623 * edid had changed.
1624 */
drm_edid_are_equal(const struct edid * edid1,const struct edid * edid2)1625 bool drm_edid_are_equal(const struct edid *edid1, const struct edid *edid2)
1626 {
1627 int edid1_len, edid2_len;
1628 bool edid1_present = edid1 != NULL;
1629 bool edid2_present = edid2 != NULL;
1630
1631 if (edid1_present != edid2_present)
1632 return false;
1633
1634 if (edid1) {
1635 edid1_len = EDID_LENGTH * (1 + edid1->extensions);
1636 edid2_len = EDID_LENGTH * (1 + edid2->extensions);
1637
1638 if (edid1_len != edid2_len)
1639 return false;
1640
1641 if (memcmp(edid1, edid2, edid1_len))
1642 return false;
1643 }
1644
1645 return true;
1646 }
1647 EXPORT_SYMBOL(drm_edid_are_equal);
1648
1649 /**
1650 * drm_edid_block_valid - Sanity check the EDID block (base or extension)
1651 * @raw_edid: pointer to raw EDID block
1652 * @block: type of block to validate (0 for base, extension otherwise)
1653 * @print_bad_edid: if true, dump bad EDID blocks to the console
1654 * @edid_corrupt: if true, the header or checksum is invalid
1655 *
1656 * Validate a base or extension EDID block and optionally dump bad blocks to
1657 * the console.
1658 *
1659 * Return: True if the block is valid, false otherwise.
1660 */
drm_edid_block_valid(u8 * raw_edid,int block,bool print_bad_edid,bool * edid_corrupt)1661 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid,
1662 bool *edid_corrupt)
1663 {
1664 u8 csum;
1665 struct edid *edid = (struct edid *)raw_edid;
1666
1667 if (WARN_ON(!raw_edid))
1668 return false;
1669
1670 if (edid_fixup > 8 || edid_fixup < 0)
1671 edid_fixup = 6;
1672
1673 if (block == 0) {
1674 int score = drm_edid_header_is_valid(raw_edid);
1675
1676 if (score == 8) {
1677 if (edid_corrupt)
1678 *edid_corrupt = false;
1679 } else if (score >= edid_fixup) {
1680 /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6
1681 * The corrupt flag needs to be set here otherwise, the
1682 * fix-up code here will correct the problem, the
1683 * checksum is correct and the test fails
1684 */
1685 if (edid_corrupt)
1686 *edid_corrupt = true;
1687 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n");
1688 memcpy(raw_edid, edid_header, sizeof(edid_header));
1689 } else {
1690 if (edid_corrupt)
1691 *edid_corrupt = true;
1692 goto bad;
1693 }
1694 }
1695
1696 csum = drm_edid_block_checksum(raw_edid);
1697 if (drm_edid_block_checksum_diff(raw_edid, csum)) {
1698 if (edid_corrupt)
1699 *edid_corrupt = true;
1700
1701 /* allow CEA to slide through, switches mangle this */
1702 if (raw_edid[0] == CEA_EXT) {
1703 DRM_DEBUG("EDID checksum is invalid, remainder is %d\n", csum);
1704 DRM_DEBUG("Assuming a KVM switch modified the CEA block but left the original checksum\n");
1705 } else {
1706 if (print_bad_edid)
1707 DRM_NOTE("EDID checksum is invalid, remainder is %d\n", csum);
1708
1709 goto bad;
1710 }
1711 }
1712
1713 /* per-block-type checks */
1714 switch (raw_edid[0]) {
1715 case 0: /* base */
1716 if (edid->version != 1) {
1717 DRM_NOTE("EDID has major version %d, instead of 1\n", edid->version);
1718 goto bad;
1719 }
1720
1721 if (edid->revision > 4)
1722 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n");
1723 break;
1724
1725 default:
1726 break;
1727 }
1728
1729 return true;
1730
1731 bad:
1732 if (print_bad_edid) {
1733 if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) {
1734 pr_notice("EDID block is all zeroes\n");
1735 } else {
1736 pr_notice("Raw EDID:\n");
1737 print_hex_dump(KERN_NOTICE,
1738 " \t", DUMP_PREFIX_NONE, 16, 1,
1739 raw_edid, EDID_LENGTH, false);
1740 }
1741 }
1742 return false;
1743 }
1744 EXPORT_SYMBOL(drm_edid_block_valid);
1745
1746 /**
1747 * drm_edid_is_valid - sanity check EDID data
1748 * @edid: EDID data
1749 *
1750 * Sanity-check an entire EDID record (including extensions)
1751 *
1752 * Return: True if the EDID data is valid, false otherwise.
1753 */
drm_edid_is_valid(struct edid * edid)1754 bool drm_edid_is_valid(struct edid *edid)
1755 {
1756 int i;
1757 u8 *raw = (u8 *)edid;
1758
1759 if (!edid)
1760 return false;
1761
1762 for (i = 0; i <= edid->extensions; i++)
1763 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL))
1764 return false;
1765
1766 return true;
1767 }
1768 EXPORT_SYMBOL(drm_edid_is_valid);
1769
1770 #define DDC_SEGMENT_ADDR 0x30
1771 /**
1772 * drm_do_probe_ddc_edid() - get EDID information via I2C
1773 * @data: I2C device adapter
1774 * @buf: EDID data buffer to be filled
1775 * @block: 128 byte EDID block to start fetching from
1776 * @len: EDID data buffer length to fetch
1777 *
1778 * Try to fetch EDID information by calling I2C driver functions.
1779 *
1780 * Return: 0 on success or -1 on failure.
1781 */
1782 static int
drm_do_probe_ddc_edid(void * data,u8 * buf,unsigned int block,size_t len)1783 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len)
1784 {
1785 struct i2c_adapter *adapter = data;
1786 unsigned char start = block * EDID_LENGTH;
1787 unsigned char segment = block >> 1;
1788 unsigned char xfers = segment ? 3 : 2;
1789 int ret, retries = 5;
1790
1791 /*
1792 * The core I2C driver will automatically retry the transfer if the
1793 * adapter reports EAGAIN. However, we find that bit-banging transfers
1794 * are susceptible to errors under a heavily loaded machine and
1795 * generate spurious NAKs and timeouts. Retrying the transfer
1796 * of the individual block a few times seems to overcome this.
1797 */
1798 do {
1799 struct i2c_msg msgs[] = {
1800 {
1801 .addr = DDC_SEGMENT_ADDR,
1802 .flags = 0,
1803 .len = 1,
1804 .buf = &segment,
1805 }, {
1806 .addr = DDC_ADDR,
1807 .flags = 0,
1808 .len = 1,
1809 .buf = &start,
1810 }, {
1811 .addr = DDC_ADDR,
1812 .flags = I2C_M_RD,
1813 .len = len,
1814 .buf = buf,
1815 }
1816 };
1817
1818 /*
1819 * Avoid sending the segment addr to not upset non-compliant
1820 * DDC monitors.
1821 */
1822 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers);
1823
1824 if (ret == -ENXIO) {
1825 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n",
1826 adapter->name);
1827 break;
1828 }
1829 } while (ret != xfers && --retries);
1830
1831 return ret == xfers ? 0 : -1;
1832 }
1833
connector_bad_edid(struct drm_connector * connector,u8 * edid,int num_blocks)1834 static void connector_bad_edid(struct drm_connector *connector,
1835 u8 *edid, int num_blocks)
1836 {
1837 int i;
1838 u8 last_block;
1839
1840 /*
1841 * 0x7e in the EDID is the number of extension blocks. The EDID
1842 * is 1 (base block) + num_ext_blocks big. That means we can think
1843 * of 0x7e in the EDID of the _index_ of the last block in the
1844 * combined chunk of memory.
1845 */
1846 last_block = edid[0x7e];
1847
1848 /* Calculate real checksum for the last edid extension block data */
1849 if (last_block < num_blocks)
1850 connector->real_edid_checksum =
1851 drm_edid_block_checksum(edid + last_block * EDID_LENGTH);
1852
1853 if (connector->bad_edid_counter++ && !drm_debug_enabled(DRM_UT_KMS))
1854 return;
1855
1856 drm_warn(connector->dev, "%s: EDID is invalid:\n", connector->name);
1857 for (i = 0; i < num_blocks; i++) {
1858 u8 *block = edid + i * EDID_LENGTH;
1859 char prefix[20];
1860
1861 if (drm_edid_is_zero(block, EDID_LENGTH))
1862 sprintf(prefix, "\t[%02x] ZERO ", i);
1863 else if (!drm_edid_block_valid(block, i, false, NULL))
1864 sprintf(prefix, "\t[%02x] BAD ", i);
1865 else
1866 sprintf(prefix, "\t[%02x] GOOD ", i);
1867
1868 print_hex_dump(KERN_WARNING,
1869 prefix, DUMP_PREFIX_NONE, 16, 1,
1870 block, EDID_LENGTH, false);
1871 }
1872 }
1873
1874 /* Get override or firmware EDID */
drm_get_override_edid(struct drm_connector * connector)1875 static struct edid *drm_get_override_edid(struct drm_connector *connector)
1876 {
1877 struct edid *override = NULL;
1878
1879 if (connector->override_edid)
1880 override = drm_edid_duplicate(connector->edid_blob_ptr->data);
1881
1882 if (!override)
1883 override = drm_load_edid_firmware(connector);
1884
1885 return IS_ERR(override) ? NULL : override;
1886 }
1887
1888 /**
1889 * drm_add_override_edid_modes - add modes from override/firmware EDID
1890 * @connector: connector we're probing
1891 *
1892 * Add modes from the override/firmware EDID, if available. Only to be used from
1893 * drm_helper_probe_single_connector_modes() as a fallback for when DDC probe
1894 * failed during drm_get_edid() and caused the override/firmware EDID to be
1895 * skipped.
1896 *
1897 * Return: The number of modes added or 0 if we couldn't find any.
1898 */
drm_add_override_edid_modes(struct drm_connector * connector)1899 int drm_add_override_edid_modes(struct drm_connector *connector)
1900 {
1901 struct edid *override;
1902 int num_modes = 0;
1903
1904 override = drm_get_override_edid(connector);
1905 if (override) {
1906 drm_connector_update_edid_property(connector, override);
1907 num_modes = drm_add_edid_modes(connector, override);
1908 kfree(override);
1909
1910 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n",
1911 connector->base.id, connector->name, num_modes);
1912 }
1913
1914 return num_modes;
1915 }
1916 EXPORT_SYMBOL(drm_add_override_edid_modes);
1917
1918 /**
1919 * drm_do_get_edid - get EDID data using a custom EDID block read function
1920 * @connector: connector we're probing
1921 * @get_edid_block: EDID block read function
1922 * @data: private data passed to the block read function
1923 *
1924 * When the I2C adapter connected to the DDC bus is hidden behind a device that
1925 * exposes a different interface to read EDID blocks this function can be used
1926 * to get EDID data using a custom block read function.
1927 *
1928 * As in the general case the DDC bus is accessible by the kernel at the I2C
1929 * level, drivers must make all reasonable efforts to expose it as an I2C
1930 * adapter and use drm_get_edid() instead of abusing this function.
1931 *
1932 * The EDID may be overridden using debugfs override_edid or firmare EDID
1933 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority
1934 * order. Having either of them bypasses actual EDID reads.
1935 *
1936 * Return: Pointer to valid EDID or NULL if we couldn't find any.
1937 */
drm_do_get_edid(struct drm_connector * connector,int (* get_edid_block)(void * data,u8 * buf,unsigned int block,size_t len),void * data)1938 struct edid *drm_do_get_edid(struct drm_connector *connector,
1939 int (*get_edid_block)(void *data, u8 *buf, unsigned int block,
1940 size_t len),
1941 void *data)
1942 {
1943 int i, j = 0, valid_extensions = 0;
1944 u8 *edid, *new;
1945 struct edid *override;
1946
1947 override = drm_get_override_edid(connector);
1948 if (override)
1949 return override;
1950
1951 if ((edid = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL)
1952 return NULL;
1953
1954 /* base block fetch */
1955 for (i = 0; i < 4; i++) {
1956 if (get_edid_block(data, edid, 0, EDID_LENGTH))
1957 goto out;
1958 if (drm_edid_block_valid(edid, 0, false,
1959 &connector->edid_corrupt))
1960 break;
1961 if (i == 0 && drm_edid_is_zero(edid, EDID_LENGTH)) {
1962 connector->null_edid_counter++;
1963 goto carp;
1964 }
1965 }
1966 if (i == 4)
1967 goto carp;
1968
1969 /* if there's no extensions, we're done */
1970 valid_extensions = edid[0x7e];
1971 if (valid_extensions == 0)
1972 return (struct edid *)edid;
1973
1974 new = krealloc(edid, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1975 if (!new)
1976 goto out;
1977 edid = new;
1978
1979 for (j = 1; j <= edid[0x7e]; j++) {
1980 u8 *block = edid + j * EDID_LENGTH;
1981
1982 for (i = 0; i < 4; i++) {
1983 if (get_edid_block(data, block, j, EDID_LENGTH))
1984 goto out;
1985 if (drm_edid_block_valid(block, j, false, NULL))
1986 break;
1987 }
1988
1989 if (i == 4)
1990 valid_extensions--;
1991 }
1992
1993 if (valid_extensions != edid[0x7e]) {
1994 u8 *base;
1995
1996 connector_bad_edid(connector, edid, edid[0x7e] + 1);
1997
1998 new = kmalloc_array(valid_extensions + 1, EDID_LENGTH,
1999 GFP_KERNEL);
2000 if (!new)
2001 goto out;
2002
2003 base = new;
2004 for (i = 0; i <= edid[0x7e]; i++) {
2005 u8 *block = edid + i * EDID_LENGTH;
2006
2007 if (!drm_edid_block_valid(block, i, false, NULL))
2008 continue;
2009
2010 memcpy(base, block, EDID_LENGTH);
2011 base += EDID_LENGTH;
2012 }
2013
2014 new[EDID_LENGTH - 1] += new[0x7e] - valid_extensions;
2015 new[0x7e] = valid_extensions;
2016
2017 kfree(edid);
2018 edid = new;
2019 }
2020
2021 return (struct edid *)edid;
2022
2023 carp:
2024 connector_bad_edid(connector, edid, 1);
2025 out:
2026 kfree(edid);
2027 return NULL;
2028 }
2029 EXPORT_SYMBOL_GPL(drm_do_get_edid);
2030
2031 /**
2032 * drm_probe_ddc() - probe DDC presence
2033 * @adapter: I2C adapter to probe
2034 *
2035 * Return: True on success, false on failure.
2036 */
2037 bool
drm_probe_ddc(struct i2c_adapter * adapter)2038 drm_probe_ddc(struct i2c_adapter *adapter)
2039 {
2040 unsigned char out;
2041
2042 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
2043 }
2044 EXPORT_SYMBOL(drm_probe_ddc);
2045
2046 /**
2047 * drm_get_edid - get EDID data, if available
2048 * @connector: connector we're probing
2049 * @adapter: I2C adapter to use for DDC
2050 *
2051 * Poke the given I2C channel to grab EDID data if possible. If found,
2052 * attach it to the connector.
2053 *
2054 * Return: Pointer to valid EDID or NULL if we couldn't find any.
2055 */
drm_get_edid(struct drm_connector * connector,struct i2c_adapter * adapter)2056 struct edid *drm_get_edid(struct drm_connector *connector,
2057 struct i2c_adapter *adapter)
2058 {
2059 struct edid *edid;
2060
2061 if (connector->force == DRM_FORCE_OFF)
2062 return NULL;
2063
2064 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
2065 return NULL;
2066
2067 edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter);
2068 drm_connector_update_edid_property(connector, edid);
2069 return edid;
2070 }
2071 EXPORT_SYMBOL(drm_get_edid);
2072
2073 /**
2074 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output
2075 * @connector: connector we're probing
2076 * @adapter: I2C adapter to use for DDC
2077 *
2078 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of
2079 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily
2080 * switch DDC to the GPU which is retrieving EDID.
2081 *
2082 * Return: Pointer to valid EDID or %NULL if we couldn't find any.
2083 */
drm_get_edid_switcheroo(struct drm_connector * connector,struct i2c_adapter * adapter)2084 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector,
2085 struct i2c_adapter *adapter)
2086 {
2087 struct pci_dev *pdev = connector->dev->pdev;
2088 struct edid *edid;
2089
2090 vga_switcheroo_lock_ddc(pdev);
2091 edid = drm_get_edid(connector, adapter);
2092 vga_switcheroo_unlock_ddc(pdev);
2093
2094 return edid;
2095 }
2096 EXPORT_SYMBOL(drm_get_edid_switcheroo);
2097
2098 /**
2099 * drm_edid_duplicate - duplicate an EDID and the extensions
2100 * @edid: EDID to duplicate
2101 *
2102 * Return: Pointer to duplicated EDID or NULL on allocation failure.
2103 */
drm_edid_duplicate(const struct edid * edid)2104 struct edid *drm_edid_duplicate(const struct edid *edid)
2105 {
2106 return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL);
2107 }
2108 EXPORT_SYMBOL(drm_edid_duplicate);
2109
2110 /*** EDID parsing ***/
2111
2112 /**
2113 * edid_vendor - match a string against EDID's obfuscated vendor field
2114 * @edid: EDID to match
2115 * @vendor: vendor string
2116 *
2117 * Returns true if @vendor is in @edid, false otherwise
2118 */
edid_vendor(const struct edid * edid,const char * vendor)2119 static bool edid_vendor(const struct edid *edid, const char *vendor)
2120 {
2121 char edid_vendor[3];
2122
2123 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@';
2124 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) |
2125 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@';
2126 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@';
2127
2128 return !strncmp(edid_vendor, vendor, 3);
2129 }
2130
2131 /**
2132 * edid_get_quirks - return quirk flags for a given EDID
2133 * @edid: EDID to process
2134 *
2135 * This tells subsequent routines what fixes they need to apply.
2136 */
edid_get_quirks(const struct edid * edid)2137 static u32 edid_get_quirks(const struct edid *edid)
2138 {
2139 const struct edid_quirk *quirk;
2140 int i;
2141
2142 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
2143 quirk = &edid_quirk_list[i];
2144
2145 if (edid_vendor(edid, quirk->vendor) &&
2146 (EDID_PRODUCT_ID(edid) == quirk->product_id))
2147 return quirk->quirks;
2148 }
2149
2150 return 0;
2151 }
2152
2153 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
2154 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t)))
2155
2156 /**
2157 * edid_fixup_preferred - set preferred modes based on quirk list
2158 * @connector: has mode list to fix up
2159 * @quirks: quirks list
2160 *
2161 * Walk the mode list for @connector, clearing the preferred status
2162 * on existing modes and setting it anew for the right mode ala @quirks.
2163 */
edid_fixup_preferred(struct drm_connector * connector,u32 quirks)2164 static void edid_fixup_preferred(struct drm_connector *connector,
2165 u32 quirks)
2166 {
2167 struct drm_display_mode *t, *cur_mode, *preferred_mode;
2168 int target_refresh = 0;
2169 int cur_vrefresh, preferred_vrefresh;
2170
2171 if (list_empty(&connector->probed_modes))
2172 return;
2173
2174 if (quirks & EDID_QUIRK_PREFER_LARGE_60)
2175 target_refresh = 60;
2176 if (quirks & EDID_QUIRK_PREFER_LARGE_75)
2177 target_refresh = 75;
2178
2179 preferred_mode = list_first_entry(&connector->probed_modes,
2180 struct drm_display_mode, head);
2181
2182 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) {
2183 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
2184
2185 if (cur_mode == preferred_mode)
2186 continue;
2187
2188 /* Largest mode is preferred */
2189 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode))
2190 preferred_mode = cur_mode;
2191
2192 cur_vrefresh = drm_mode_vrefresh(cur_mode);
2193 preferred_vrefresh = drm_mode_vrefresh(preferred_mode);
2194 /* At a given size, try to get closest to target refresh */
2195 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
2196 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) <
2197 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) {
2198 preferred_mode = cur_mode;
2199 }
2200 }
2201
2202 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
2203 }
2204
2205 static bool
mode_is_rb(const struct drm_display_mode * mode)2206 mode_is_rb(const struct drm_display_mode *mode)
2207 {
2208 return (mode->htotal - mode->hdisplay == 160) &&
2209 (mode->hsync_end - mode->hdisplay == 80) &&
2210 (mode->hsync_end - mode->hsync_start == 32) &&
2211 (mode->vsync_start - mode->vdisplay == 3);
2212 }
2213
2214 /*
2215 * drm_mode_find_dmt - Create a copy of a mode if present in DMT
2216 * @dev: Device to duplicate against
2217 * @hsize: Mode width
2218 * @vsize: Mode height
2219 * @fresh: Mode refresh rate
2220 * @rb: Mode reduced-blanking-ness
2221 *
2222 * Walk the DMT mode list looking for a match for the given parameters.
2223 *
2224 * Return: A newly allocated copy of the mode, or NULL if not found.
2225 */
drm_mode_find_dmt(struct drm_device * dev,int hsize,int vsize,int fresh,bool rb)2226 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
2227 int hsize, int vsize, int fresh,
2228 bool rb)
2229 {
2230 int i;
2231
2232 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
2233 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
2234
2235 if (hsize != ptr->hdisplay)
2236 continue;
2237 if (vsize != ptr->vdisplay)
2238 continue;
2239 if (fresh != drm_mode_vrefresh(ptr))
2240 continue;
2241 if (rb != mode_is_rb(ptr))
2242 continue;
2243
2244 return drm_mode_duplicate(dev, ptr);
2245 }
2246
2247 return NULL;
2248 }
2249 EXPORT_SYMBOL(drm_mode_find_dmt);
2250
is_display_descriptor(const u8 d[18],u8 tag)2251 static bool is_display_descriptor(const u8 d[18], u8 tag)
2252 {
2253 return d[0] == 0x00 && d[1] == 0x00 &&
2254 d[2] == 0x00 && d[3] == tag;
2255 }
2256
is_detailed_timing_descriptor(const u8 d[18])2257 static bool is_detailed_timing_descriptor(const u8 d[18])
2258 {
2259 return d[0] != 0x00 || d[1] != 0x00;
2260 }
2261
2262 typedef void detailed_cb(struct detailed_timing *timing, void *closure);
2263
2264 static void
cea_for_each_detailed_block(u8 * ext,detailed_cb * cb,void * closure)2265 cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
2266 {
2267 int i, n;
2268 u8 d = ext[0x02];
2269 u8 *det_base = ext + d;
2270
2271 if (d < 4 || d > 127)
2272 return;
2273
2274 n = (127 - d) / 18;
2275 for (i = 0; i < n; i++)
2276 cb((struct detailed_timing *)(det_base + 18 * i), closure);
2277 }
2278
2279 static void
vtb_for_each_detailed_block(u8 * ext,detailed_cb * cb,void * closure)2280 vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
2281 {
2282 unsigned int i, n = min((int)ext[0x02], 6);
2283 u8 *det_base = ext + 5;
2284
2285 if (ext[0x01] != 1)
2286 return; /* unknown version */
2287
2288 for (i = 0; i < n; i++)
2289 cb((struct detailed_timing *)(det_base + 18 * i), closure);
2290 }
2291
2292 static void
drm_for_each_detailed_block(u8 * raw_edid,detailed_cb * cb,void * closure)2293 drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure)
2294 {
2295 int i;
2296 struct edid *edid = (struct edid *)raw_edid;
2297
2298 if (edid == NULL)
2299 return;
2300
2301 for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
2302 cb(&(edid->detailed_timings[i]), closure);
2303
2304 for (i = 1; i <= raw_edid[0x7e]; i++) {
2305 u8 *ext = raw_edid + (i * EDID_LENGTH);
2306
2307 switch (*ext) {
2308 case CEA_EXT:
2309 cea_for_each_detailed_block(ext, cb, closure);
2310 break;
2311 case VTB_EXT:
2312 vtb_for_each_detailed_block(ext, cb, closure);
2313 break;
2314 default:
2315 break;
2316 }
2317 }
2318 }
2319
2320 static void
is_rb(struct detailed_timing * t,void * data)2321 is_rb(struct detailed_timing *t, void *data)
2322 {
2323 u8 *r = (u8 *)t;
2324
2325 if (!is_display_descriptor(r, EDID_DETAIL_MONITOR_RANGE))
2326 return;
2327
2328 if (r[15] & 0x10)
2329 *(bool *)data = true;
2330 }
2331
2332 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */
2333 static bool
drm_monitor_supports_rb(struct edid * edid)2334 drm_monitor_supports_rb(struct edid *edid)
2335 {
2336 if (edid->revision >= 4) {
2337 bool ret = false;
2338
2339 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret);
2340 return ret;
2341 }
2342
2343 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0);
2344 }
2345
2346 static void
find_gtf2(struct detailed_timing * t,void * data)2347 find_gtf2(struct detailed_timing *t, void *data)
2348 {
2349 u8 *r = (u8 *)t;
2350
2351 if (!is_display_descriptor(r, EDID_DETAIL_MONITOR_RANGE))
2352 return;
2353
2354 if (r[10] == 0x02)
2355 *(u8 **)data = r;
2356 }
2357
2358 /* Secondary GTF curve kicks in above some break frequency */
2359 static int
drm_gtf2_hbreak(struct edid * edid)2360 drm_gtf2_hbreak(struct edid *edid)
2361 {
2362 u8 *r = NULL;
2363
2364 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2365 return r ? (r[12] * 2) : 0;
2366 }
2367
2368 static int
drm_gtf2_2c(struct edid * edid)2369 drm_gtf2_2c(struct edid *edid)
2370 {
2371 u8 *r = NULL;
2372
2373 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2374 return r ? r[13] : 0;
2375 }
2376
2377 static int
drm_gtf2_m(struct edid * edid)2378 drm_gtf2_m(struct edid *edid)
2379 {
2380 u8 *r = NULL;
2381
2382 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2383 return r ? (r[15] << 8) + r[14] : 0;
2384 }
2385
2386 static int
drm_gtf2_k(struct edid * edid)2387 drm_gtf2_k(struct edid *edid)
2388 {
2389 u8 *r = NULL;
2390
2391 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2392 return r ? r[16] : 0;
2393 }
2394
2395 static int
drm_gtf2_2j(struct edid * edid)2396 drm_gtf2_2j(struct edid *edid)
2397 {
2398 u8 *r = NULL;
2399
2400 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2401 return r ? r[17] : 0;
2402 }
2403
2404 /**
2405 * standard_timing_level - get std. timing level(CVT/GTF/DMT)
2406 * @edid: EDID block to scan
2407 */
standard_timing_level(struct edid * edid)2408 static int standard_timing_level(struct edid *edid)
2409 {
2410 if (edid->revision >= 2) {
2411 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF))
2412 return LEVEL_CVT;
2413 if (drm_gtf2_hbreak(edid))
2414 return LEVEL_GTF2;
2415 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
2416 return LEVEL_GTF;
2417 }
2418 return LEVEL_DMT;
2419 }
2420
2421 /*
2422 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old
2423 * monitors fill with ascii space (0x20) instead.
2424 */
2425 static int
bad_std_timing(u8 a,u8 b)2426 bad_std_timing(u8 a, u8 b)
2427 {
2428 return (a == 0x00 && b == 0x00) ||
2429 (a == 0x01 && b == 0x01) ||
2430 (a == 0x20 && b == 0x20);
2431 }
2432
drm_mode_hsync(const struct drm_display_mode * mode)2433 static int drm_mode_hsync(const struct drm_display_mode *mode)
2434 {
2435 if (mode->htotal <= 0)
2436 return 0;
2437
2438 return DIV_ROUND_CLOSEST(mode->clock, mode->htotal);
2439 }
2440
2441 /**
2442 * drm_mode_std - convert standard mode info (width, height, refresh) into mode
2443 * @connector: connector of for the EDID block
2444 * @edid: EDID block to scan
2445 * @t: standard timing params
2446 *
2447 * Take the standard timing params (in this case width, aspect, and refresh)
2448 * and convert them into a real mode using CVT/GTF/DMT.
2449 */
2450 static struct drm_display_mode *
drm_mode_std(struct drm_connector * connector,struct edid * edid,struct std_timing * t)2451 drm_mode_std(struct drm_connector *connector, struct edid *edid,
2452 struct std_timing *t)
2453 {
2454 struct drm_device *dev = connector->dev;
2455 struct drm_display_mode *m, *mode = NULL;
2456 int hsize, vsize;
2457 int vrefresh_rate;
2458 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
2459 >> EDID_TIMING_ASPECT_SHIFT;
2460 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
2461 >> EDID_TIMING_VFREQ_SHIFT;
2462 int timing_level = standard_timing_level(edid);
2463
2464 if (bad_std_timing(t->hsize, t->vfreq_aspect))
2465 return NULL;
2466
2467 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
2468 hsize = t->hsize * 8 + 248;
2469 /* vrefresh_rate = vfreq + 60 */
2470 vrefresh_rate = vfreq + 60;
2471 /* the vdisplay is calculated based on the aspect ratio */
2472 if (aspect_ratio == 0) {
2473 if (edid->revision < 3)
2474 vsize = hsize;
2475 else
2476 vsize = (hsize * 10) / 16;
2477 } else if (aspect_ratio == 1)
2478 vsize = (hsize * 3) / 4;
2479 else if (aspect_ratio == 2)
2480 vsize = (hsize * 4) / 5;
2481 else
2482 vsize = (hsize * 9) / 16;
2483
2484 /* HDTV hack, part 1 */
2485 if (vrefresh_rate == 60 &&
2486 ((hsize == 1360 && vsize == 765) ||
2487 (hsize == 1368 && vsize == 769))) {
2488 hsize = 1366;
2489 vsize = 768;
2490 }
2491
2492 /*
2493 * If this connector already has a mode for this size and refresh
2494 * rate (because it came from detailed or CVT info), use that
2495 * instead. This way we don't have to guess at interlace or
2496 * reduced blanking.
2497 */
2498 list_for_each_entry(m, &connector->probed_modes, head)
2499 if (m->hdisplay == hsize && m->vdisplay == vsize &&
2500 drm_mode_vrefresh(m) == vrefresh_rate)
2501 return NULL;
2502
2503 /* HDTV hack, part 2 */
2504 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
2505 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
2506 false);
2507 if (!mode)
2508 return NULL;
2509 mode->hdisplay = 1366;
2510 mode->hsync_start = mode->hsync_start - 1;
2511 mode->hsync_end = mode->hsync_end - 1;
2512 return mode;
2513 }
2514
2515 /* check whether it can be found in default mode table */
2516 if (drm_monitor_supports_rb(edid)) {
2517 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate,
2518 true);
2519 if (mode)
2520 return mode;
2521 }
2522 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false);
2523 if (mode)
2524 return mode;
2525
2526 /* okay, generate it */
2527 switch (timing_level) {
2528 case LEVEL_DMT:
2529 break;
2530 case LEVEL_GTF:
2531 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
2532 break;
2533 case LEVEL_GTF2:
2534 /*
2535 * This is potentially wrong if there's ever a monitor with
2536 * more than one ranges section, each claiming a different
2537 * secondary GTF curve. Please don't do that.
2538 */
2539 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
2540 if (!mode)
2541 return NULL;
2542 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) {
2543 drm_mode_destroy(dev, mode);
2544 mode = drm_gtf_mode_complex(dev, hsize, vsize,
2545 vrefresh_rate, 0, 0,
2546 drm_gtf2_m(edid),
2547 drm_gtf2_2c(edid),
2548 drm_gtf2_k(edid),
2549 drm_gtf2_2j(edid));
2550 }
2551 break;
2552 case LEVEL_CVT:
2553 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
2554 false);
2555 break;
2556 }
2557 return mode;
2558 }
2559
2560 /*
2561 * EDID is delightfully ambiguous about how interlaced modes are to be
2562 * encoded. Our internal representation is of frame height, but some
2563 * HDTV detailed timings are encoded as field height.
2564 *
2565 * The format list here is from CEA, in frame size. Technically we
2566 * should be checking refresh rate too. Whatever.
2567 */
2568 static void
drm_mode_do_interlace_quirk(struct drm_display_mode * mode,struct detailed_pixel_timing * pt)2569 drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
2570 struct detailed_pixel_timing *pt)
2571 {
2572 int i;
2573 static const struct {
2574 int w, h;
2575 } cea_interlaced[] = {
2576 { 1920, 1080 },
2577 { 720, 480 },
2578 { 1440, 480 },
2579 { 2880, 480 },
2580 { 720, 576 },
2581 { 1440, 576 },
2582 { 2880, 576 },
2583 };
2584
2585 if (!(pt->misc & DRM_EDID_PT_INTERLACED))
2586 return;
2587
2588 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) {
2589 if ((mode->hdisplay == cea_interlaced[i].w) &&
2590 (mode->vdisplay == cea_interlaced[i].h / 2)) {
2591 mode->vdisplay *= 2;
2592 mode->vsync_start *= 2;
2593 mode->vsync_end *= 2;
2594 mode->vtotal *= 2;
2595 mode->vtotal |= 1;
2596 }
2597 }
2598
2599 mode->flags |= DRM_MODE_FLAG_INTERLACE;
2600 }
2601
2602 /**
2603 * drm_mode_detailed - create a new mode from an EDID detailed timing section
2604 * @dev: DRM device (needed to create new mode)
2605 * @edid: EDID block
2606 * @timing: EDID detailed timing info
2607 * @quirks: quirks to apply
2608 *
2609 * An EDID detailed timing block contains enough info for us to create and
2610 * return a new struct drm_display_mode.
2611 */
drm_mode_detailed(struct drm_device * dev,struct edid * edid,struct detailed_timing * timing,u32 quirks)2612 static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
2613 struct edid *edid,
2614 struct detailed_timing *timing,
2615 u32 quirks)
2616 {
2617 struct drm_display_mode *mode;
2618 struct detailed_pixel_timing *pt = &timing->data.pixel_data;
2619 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
2620 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
2621 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
2622 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
2623 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
2624 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
2625 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4;
2626 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
2627
2628 /* ignore tiny modes */
2629 if (hactive < 64 || vactive < 64)
2630 return NULL;
2631
2632 if (pt->misc & DRM_EDID_PT_STEREO) {
2633 DRM_DEBUG_KMS("stereo mode not supported\n");
2634 return NULL;
2635 }
2636 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
2637 DRM_DEBUG_KMS("composite sync not supported\n");
2638 }
2639
2640 /* it is incorrect if hsync/vsync width is zero */
2641 if (!hsync_pulse_width || !vsync_pulse_width) {
2642 DRM_DEBUG_KMS("Incorrect Detailed timing. "
2643 "Wrong Hsync/Vsync pulse width\n");
2644 return NULL;
2645 }
2646
2647 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) {
2648 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false);
2649 if (!mode)
2650 return NULL;
2651
2652 goto set_size;
2653 }
2654
2655 mode = drm_mode_create(dev);
2656 if (!mode)
2657 return NULL;
2658
2659 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
2660 timing->pixel_clock = cpu_to_le16(1088);
2661
2662 mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
2663
2664 mode->hdisplay = hactive;
2665 mode->hsync_start = mode->hdisplay + hsync_offset;
2666 mode->hsync_end = mode->hsync_start + hsync_pulse_width;
2667 mode->htotal = mode->hdisplay + hblank;
2668
2669 mode->vdisplay = vactive;
2670 mode->vsync_start = mode->vdisplay + vsync_offset;
2671 mode->vsync_end = mode->vsync_start + vsync_pulse_width;
2672 mode->vtotal = mode->vdisplay + vblank;
2673
2674 /* Some EDIDs have bogus h/vtotal values */
2675 if (mode->hsync_end > mode->htotal)
2676 mode->htotal = mode->hsync_end + 1;
2677 if (mode->vsync_end > mode->vtotal)
2678 mode->vtotal = mode->vsync_end + 1;
2679
2680 drm_mode_do_interlace_quirk(mode, pt);
2681
2682 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
2683 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE;
2684 }
2685
2686 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
2687 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
2688 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
2689 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
2690
2691 set_size:
2692 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
2693 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
2694
2695 if (quirks & EDID_QUIRK_DETAILED_IN_CM) {
2696 mode->width_mm *= 10;
2697 mode->height_mm *= 10;
2698 }
2699
2700 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
2701 mode->width_mm = edid->width_cm * 10;
2702 mode->height_mm = edid->height_cm * 10;
2703 }
2704
2705 mode->type = DRM_MODE_TYPE_DRIVER;
2706 drm_mode_set_name(mode);
2707
2708 return mode;
2709 }
2710
2711 static bool
mode_in_hsync_range(const struct drm_display_mode * mode,struct edid * edid,u8 * t)2712 mode_in_hsync_range(const struct drm_display_mode *mode,
2713 struct edid *edid, u8 *t)
2714 {
2715 int hsync, hmin, hmax;
2716
2717 hmin = t[7];
2718 if (edid->revision >= 4)
2719 hmin += ((t[4] & 0x04) ? 255 : 0);
2720 hmax = t[8];
2721 if (edid->revision >= 4)
2722 hmax += ((t[4] & 0x08) ? 255 : 0);
2723 hsync = drm_mode_hsync(mode);
2724
2725 return (hsync <= hmax && hsync >= hmin);
2726 }
2727
2728 static bool
mode_in_vsync_range(const struct drm_display_mode * mode,struct edid * edid,u8 * t)2729 mode_in_vsync_range(const struct drm_display_mode *mode,
2730 struct edid *edid, u8 *t)
2731 {
2732 int vsync, vmin, vmax;
2733
2734 vmin = t[5];
2735 if (edid->revision >= 4)
2736 vmin += ((t[4] & 0x01) ? 255 : 0);
2737 vmax = t[6];
2738 if (edid->revision >= 4)
2739 vmax += ((t[4] & 0x02) ? 255 : 0);
2740 vsync = drm_mode_vrefresh(mode);
2741
2742 return (vsync <= vmax && vsync >= vmin);
2743 }
2744
2745 static u32
range_pixel_clock(struct edid * edid,u8 * t)2746 range_pixel_clock(struct edid *edid, u8 *t)
2747 {
2748 /* unspecified */
2749 if (t[9] == 0 || t[9] == 255)
2750 return 0;
2751
2752 /* 1.4 with CVT support gives us real precision, yay */
2753 if (edid->revision >= 4 && t[10] == 0x04)
2754 return (t[9] * 10000) - ((t[12] >> 2) * 250);
2755
2756 /* 1.3 is pathetic, so fuzz up a bit */
2757 return t[9] * 10000 + 5001;
2758 }
2759
2760 static bool
mode_in_range(const struct drm_display_mode * mode,struct edid * edid,struct detailed_timing * timing)2761 mode_in_range(const struct drm_display_mode *mode, struct edid *edid,
2762 struct detailed_timing *timing)
2763 {
2764 u32 max_clock;
2765 u8 *t = (u8 *)timing;
2766
2767 if (!mode_in_hsync_range(mode, edid, t))
2768 return false;
2769
2770 if (!mode_in_vsync_range(mode, edid, t))
2771 return false;
2772
2773 if ((max_clock = range_pixel_clock(edid, t)))
2774 if (mode->clock > max_clock)
2775 return false;
2776
2777 /* 1.4 max horizontal check */
2778 if (edid->revision >= 4 && t[10] == 0x04)
2779 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3))))
2780 return false;
2781
2782 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid))
2783 return false;
2784
2785 return true;
2786 }
2787
valid_inferred_mode(const struct drm_connector * connector,const struct drm_display_mode * mode)2788 static bool valid_inferred_mode(const struct drm_connector *connector,
2789 const struct drm_display_mode *mode)
2790 {
2791 const struct drm_display_mode *m;
2792 bool ok = false;
2793
2794 list_for_each_entry(m, &connector->probed_modes, head) {
2795 if (mode->hdisplay == m->hdisplay &&
2796 mode->vdisplay == m->vdisplay &&
2797 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m))
2798 return false; /* duplicated */
2799 if (mode->hdisplay <= m->hdisplay &&
2800 mode->vdisplay <= m->vdisplay)
2801 ok = true;
2802 }
2803 return ok;
2804 }
2805
2806 static int
drm_dmt_modes_for_range(struct drm_connector * connector,struct edid * edid,struct detailed_timing * timing)2807 drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid,
2808 struct detailed_timing *timing)
2809 {
2810 int i, modes = 0;
2811 struct drm_display_mode *newmode;
2812 struct drm_device *dev = connector->dev;
2813
2814 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
2815 if (mode_in_range(drm_dmt_modes + i, edid, timing) &&
2816 valid_inferred_mode(connector, drm_dmt_modes + i)) {
2817 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
2818 if (newmode) {
2819 drm_mode_probed_add(connector, newmode);
2820 modes++;
2821 }
2822 }
2823 }
2824
2825 return modes;
2826 }
2827
2828 /* fix up 1366x768 mode from 1368x768;
2829 * GFT/CVT can't express 1366 width which isn't dividable by 8
2830 */
drm_mode_fixup_1366x768(struct drm_display_mode * mode)2831 void drm_mode_fixup_1366x768(struct drm_display_mode *mode)
2832 {
2833 if (mode->hdisplay == 1368 && mode->vdisplay == 768) {
2834 mode->hdisplay = 1366;
2835 mode->hsync_start--;
2836 mode->hsync_end--;
2837 drm_mode_set_name(mode);
2838 }
2839 }
2840
2841 static int
drm_gtf_modes_for_range(struct drm_connector * connector,struct edid * edid,struct detailed_timing * timing)2842 drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid,
2843 struct detailed_timing *timing)
2844 {
2845 int i, modes = 0;
2846 struct drm_display_mode *newmode;
2847 struct drm_device *dev = connector->dev;
2848
2849 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
2850 const struct minimode *m = &extra_modes[i];
2851
2852 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0);
2853 if (!newmode)
2854 return modes;
2855
2856 drm_mode_fixup_1366x768(newmode);
2857 if (!mode_in_range(newmode, edid, timing) ||
2858 !valid_inferred_mode(connector, newmode)) {
2859 drm_mode_destroy(dev, newmode);
2860 continue;
2861 }
2862
2863 drm_mode_probed_add(connector, newmode);
2864 modes++;
2865 }
2866
2867 return modes;
2868 }
2869
2870 static int
drm_cvt_modes_for_range(struct drm_connector * connector,struct edid * edid,struct detailed_timing * timing)2871 drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid,
2872 struct detailed_timing *timing)
2873 {
2874 int i, modes = 0;
2875 struct drm_display_mode *newmode;
2876 struct drm_device *dev = connector->dev;
2877 bool rb = drm_monitor_supports_rb(edid);
2878
2879 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
2880 const struct minimode *m = &extra_modes[i];
2881
2882 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0);
2883 if (!newmode)
2884 return modes;
2885
2886 drm_mode_fixup_1366x768(newmode);
2887 if (!mode_in_range(newmode, edid, timing) ||
2888 !valid_inferred_mode(connector, newmode)) {
2889 drm_mode_destroy(dev, newmode);
2890 continue;
2891 }
2892
2893 drm_mode_probed_add(connector, newmode);
2894 modes++;
2895 }
2896
2897 return modes;
2898 }
2899
2900 static void
do_inferred_modes(struct detailed_timing * timing,void * c)2901 do_inferred_modes(struct detailed_timing *timing, void *c)
2902 {
2903 struct detailed_mode_closure *closure = c;
2904 struct detailed_non_pixel *data = &timing->data.other_data;
2905 struct detailed_data_monitor_range *range = &data->data.range;
2906
2907 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_MONITOR_RANGE))
2908 return;
2909
2910 closure->modes += drm_dmt_modes_for_range(closure->connector,
2911 closure->edid,
2912 timing);
2913
2914 if (!version_greater(closure->edid, 1, 1))
2915 return; /* GTF not defined yet */
2916
2917 switch (range->flags) {
2918 case 0x02: /* secondary gtf, XXX could do more */
2919 case 0x00: /* default gtf */
2920 closure->modes += drm_gtf_modes_for_range(closure->connector,
2921 closure->edid,
2922 timing);
2923 break;
2924 case 0x04: /* cvt, only in 1.4+ */
2925 if (!version_greater(closure->edid, 1, 3))
2926 break;
2927
2928 closure->modes += drm_cvt_modes_for_range(closure->connector,
2929 closure->edid,
2930 timing);
2931 break;
2932 case 0x01: /* just the ranges, no formula */
2933 default:
2934 break;
2935 }
2936 }
2937
2938 static int
add_inferred_modes(struct drm_connector * connector,struct edid * edid)2939 add_inferred_modes(struct drm_connector *connector, struct edid *edid)
2940 {
2941 struct detailed_mode_closure closure = {
2942 .connector = connector,
2943 .edid = edid,
2944 };
2945
2946 if (version_greater(edid, 1, 0))
2947 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes,
2948 &closure);
2949
2950 return closure.modes;
2951 }
2952
2953 static int
drm_est3_modes(struct drm_connector * connector,struct detailed_timing * timing)2954 drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing)
2955 {
2956 int i, j, m, modes = 0;
2957 struct drm_display_mode *mode;
2958 u8 *est = ((u8 *)timing) + 6;
2959
2960 for (i = 0; i < 6; i++) {
2961 for (j = 7; j >= 0; j--) {
2962 m = (i * 8) + (7 - j);
2963 if (m >= ARRAY_SIZE(est3_modes))
2964 break;
2965 if (est[i] & (1 << j)) {
2966 mode = drm_mode_find_dmt(connector->dev,
2967 est3_modes[m].w,
2968 est3_modes[m].h,
2969 est3_modes[m].r,
2970 est3_modes[m].rb);
2971 if (mode) {
2972 drm_mode_probed_add(connector, mode);
2973 modes++;
2974 }
2975 }
2976 }
2977 }
2978
2979 return modes;
2980 }
2981
2982 static void
do_established_modes(struct detailed_timing * timing,void * c)2983 do_established_modes(struct detailed_timing *timing, void *c)
2984 {
2985 struct detailed_mode_closure *closure = c;
2986
2987 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_EST_TIMINGS))
2988 return;
2989
2990 closure->modes += drm_est3_modes(closure->connector, timing);
2991 }
2992
2993 /**
2994 * add_established_modes - get est. modes from EDID and add them
2995 * @connector: connector to add mode(s) to
2996 * @edid: EDID block to scan
2997 *
2998 * Each EDID block contains a bitmap of the supported "established modes" list
2999 * (defined above). Tease them out and add them to the global modes list.
3000 */
3001 static int
add_established_modes(struct drm_connector * connector,struct edid * edid)3002 add_established_modes(struct drm_connector *connector, struct edid *edid)
3003 {
3004 struct drm_device *dev = connector->dev;
3005 unsigned long est_bits = edid->established_timings.t1 |
3006 (edid->established_timings.t2 << 8) |
3007 ((edid->established_timings.mfg_rsvd & 0x80) << 9);
3008 int i, modes = 0;
3009 struct detailed_mode_closure closure = {
3010 .connector = connector,
3011 .edid = edid,
3012 };
3013
3014 for (i = 0; i <= EDID_EST_TIMINGS; i++) {
3015 if (est_bits & (1<<i)) {
3016 struct drm_display_mode *newmode;
3017
3018 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
3019 if (newmode) {
3020 drm_mode_probed_add(connector, newmode);
3021 modes++;
3022 }
3023 }
3024 }
3025
3026 if (version_greater(edid, 1, 0))
3027 drm_for_each_detailed_block((u8 *)edid,
3028 do_established_modes, &closure);
3029
3030 return modes + closure.modes;
3031 }
3032
3033 static void
do_standard_modes(struct detailed_timing * timing,void * c)3034 do_standard_modes(struct detailed_timing *timing, void *c)
3035 {
3036 struct detailed_mode_closure *closure = c;
3037 struct detailed_non_pixel *data = &timing->data.other_data;
3038 struct drm_connector *connector = closure->connector;
3039 struct edid *edid = closure->edid;
3040 int i;
3041
3042 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_STD_MODES))
3043 return;
3044
3045 for (i = 0; i < 6; i++) {
3046 struct std_timing *std = &data->data.timings[i];
3047 struct drm_display_mode *newmode;
3048
3049 newmode = drm_mode_std(connector, edid, std);
3050 if (newmode) {
3051 drm_mode_probed_add(connector, newmode);
3052 closure->modes++;
3053 }
3054 }
3055 }
3056
3057 /**
3058 * add_standard_modes - get std. modes from EDID and add them
3059 * @connector: connector to add mode(s) to
3060 * @edid: EDID block to scan
3061 *
3062 * Standard modes can be calculated using the appropriate standard (DMT,
3063 * GTF or CVT. Grab them from @edid and add them to the list.
3064 */
3065 static int
add_standard_modes(struct drm_connector * connector,struct edid * edid)3066 add_standard_modes(struct drm_connector *connector, struct edid *edid)
3067 {
3068 int i, modes = 0;
3069 struct detailed_mode_closure closure = {
3070 .connector = connector,
3071 .edid = edid,
3072 };
3073
3074 for (i = 0; i < EDID_STD_TIMINGS; i++) {
3075 struct drm_display_mode *newmode;
3076
3077 newmode = drm_mode_std(connector, edid,
3078 &edid->standard_timings[i]);
3079 if (newmode) {
3080 drm_mode_probed_add(connector, newmode);
3081 modes++;
3082 }
3083 }
3084
3085 if (version_greater(edid, 1, 0))
3086 drm_for_each_detailed_block((u8 *)edid, do_standard_modes,
3087 &closure);
3088
3089 /* XXX should also look for standard codes in VTB blocks */
3090
3091 return modes + closure.modes;
3092 }
3093
drm_cvt_modes(struct drm_connector * connector,struct detailed_timing * timing)3094 static int drm_cvt_modes(struct drm_connector *connector,
3095 struct detailed_timing *timing)
3096 {
3097 int i, j, modes = 0;
3098 struct drm_display_mode *newmode;
3099 struct drm_device *dev = connector->dev;
3100 struct cvt_timing *cvt;
3101 const int rates[] = { 60, 85, 75, 60, 50 };
3102 const u8 empty[3] = { 0, 0, 0 };
3103
3104 for (i = 0; i < 4; i++) {
3105 int width, height;
3106
3107 cvt = &(timing->data.other_data.data.cvt[i]);
3108
3109 if (!memcmp(cvt->code, empty, 3))
3110 continue;
3111
3112 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
3113 switch (cvt->code[1] & 0x0c) {
3114 /* default - because compiler doesn't see that we've enumerated all cases */
3115 default:
3116 case 0x00:
3117 width = height * 4 / 3;
3118 break;
3119 case 0x04:
3120 width = height * 16 / 9;
3121 break;
3122 case 0x08:
3123 width = height * 16 / 10;
3124 break;
3125 case 0x0c:
3126 width = height * 15 / 9;
3127 break;
3128 }
3129
3130 for (j = 1; j < 5; j++) {
3131 if (cvt->code[2] & (1 << j)) {
3132 newmode = drm_cvt_mode(dev, width, height,
3133 rates[j], j == 0,
3134 false, false);
3135 if (newmode) {
3136 drm_mode_probed_add(connector, newmode);
3137 modes++;
3138 }
3139 }
3140 }
3141 }
3142
3143 return modes;
3144 }
3145
3146 static void
do_cvt_mode(struct detailed_timing * timing,void * c)3147 do_cvt_mode(struct detailed_timing *timing, void *c)
3148 {
3149 struct detailed_mode_closure *closure = c;
3150
3151 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_CVT_3BYTE))
3152 return;
3153
3154 closure->modes += drm_cvt_modes(closure->connector, timing);
3155 }
3156
3157 static int
add_cvt_modes(struct drm_connector * connector,struct edid * edid)3158 add_cvt_modes(struct drm_connector *connector, struct edid *edid)
3159 {
3160 struct detailed_mode_closure closure = {
3161 .connector = connector,
3162 .edid = edid,
3163 };
3164
3165 if (version_greater(edid, 1, 2))
3166 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure);
3167
3168 /* XXX should also look for CVT codes in VTB blocks */
3169
3170 return closure.modes;
3171 }
3172
3173 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode);
3174
3175 static void
do_detailed_mode(struct detailed_timing * timing,void * c)3176 do_detailed_mode(struct detailed_timing *timing, void *c)
3177 {
3178 struct detailed_mode_closure *closure = c;
3179 struct drm_display_mode *newmode;
3180
3181 if (!is_detailed_timing_descriptor((const u8 *)timing))
3182 return;
3183
3184 newmode = drm_mode_detailed(closure->connector->dev,
3185 closure->edid, timing,
3186 closure->quirks);
3187 if (!newmode)
3188 return;
3189
3190 if (closure->preferred)
3191 newmode->type |= DRM_MODE_TYPE_PREFERRED;
3192
3193 /*
3194 * Detailed modes are limited to 10kHz pixel clock resolution,
3195 * so fix up anything that looks like CEA/HDMI mode, but the clock
3196 * is just slightly off.
3197 */
3198 fixup_detailed_cea_mode_clock(newmode);
3199
3200 drm_mode_probed_add(closure->connector, newmode);
3201 closure->modes++;
3202 closure->preferred = false;
3203 }
3204
3205 /*
3206 * add_detailed_modes - Add modes from detailed timings
3207 * @connector: attached connector
3208 * @edid: EDID block to scan
3209 * @quirks: quirks to apply
3210 */
3211 static int
add_detailed_modes(struct drm_connector * connector,struct edid * edid,u32 quirks)3212 add_detailed_modes(struct drm_connector *connector, struct edid *edid,
3213 u32 quirks)
3214 {
3215 struct detailed_mode_closure closure = {
3216 .connector = connector,
3217 .edid = edid,
3218 .preferred = true,
3219 .quirks = quirks,
3220 };
3221
3222 if (closure.preferred && !version_greater(edid, 1, 3))
3223 closure.preferred =
3224 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING);
3225
3226 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure);
3227
3228 return closure.modes;
3229 }
3230
3231 #define AUDIO_BLOCK 0x01
3232 #define VIDEO_BLOCK 0x02
3233 #define VENDOR_BLOCK 0x03
3234 #define SPEAKER_BLOCK 0x04
3235 #define HDR_STATIC_METADATA_BLOCK 0x6
3236 #define USE_EXTENDED_TAG 0x07
3237 #define EXT_VIDEO_CAPABILITY_BLOCK 0x00
3238 #define EXT_VIDEO_DATA_BLOCK_420 0x0E
3239 #define EXT_VIDEO_CAP_BLOCK_Y420CMDB 0x0F
3240 #define EXT_VIDEO_HF_SCDB_DATA_BLOCK 0x79
3241 #define EDID_BASIC_AUDIO (1 << 6)
3242 #define EDID_CEA_YCRCB444 (1 << 5)
3243 #define EDID_CEA_YCRCB422 (1 << 4)
3244 #define EDID_CEA_VCDB_QS (1 << 6)
3245
3246 /*
3247 * Search EDID for CEA extension block.
3248 */
drm_find_edid_extension(const struct edid * edid,int ext_id,int * ext_index)3249 static u8 *drm_find_edid_extension(const struct edid *edid,
3250 int ext_id, int *ext_index)
3251 {
3252 u8 *edid_ext = NULL;
3253 int i;
3254
3255 /* No EDID or EDID extensions */
3256 if (edid == NULL || edid->extensions == 0)
3257 return NULL;
3258
3259 /* Find CEA extension */
3260 for (i = *ext_index; i < edid->extensions; i++) {
3261 edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1);
3262 if (edid_ext[0] == ext_id)
3263 break;
3264 }
3265
3266 if (i >= edid->extensions)
3267 return NULL;
3268
3269 *ext_index = i + 1;
3270
3271 return edid_ext;
3272 }
3273
3274
drm_find_displayid_extension(const struct edid * edid,int * length,int * idx,int * ext_index)3275 static u8 *drm_find_displayid_extension(const struct edid *edid,
3276 int *length, int *idx,
3277 int *ext_index)
3278 {
3279 u8 *displayid = drm_find_edid_extension(edid, DISPLAYID_EXT, ext_index);
3280 struct displayid_hdr *base;
3281 int ret;
3282
3283 if (!displayid)
3284 return NULL;
3285
3286 /* EDID extensions block checksum isn't for us */
3287 *length = EDID_LENGTH - 1;
3288 *idx = 1;
3289
3290 ret = validate_displayid(displayid, *length, *idx);
3291 if (ret)
3292 return NULL;
3293
3294 base = (struct displayid_hdr *)&displayid[*idx];
3295 *length = *idx + sizeof(*base) + base->bytes;
3296
3297 return displayid;
3298 }
3299
drm_find_cea_extension(const struct edid * edid)3300 static u8 *drm_find_cea_extension(const struct edid *edid)
3301 {
3302 int length, idx;
3303 struct displayid_block *block;
3304 u8 *cea;
3305 u8 *displayid;
3306 int ext_index;
3307
3308 /* Look for a top level CEA extension block */
3309 /* FIXME: make callers iterate through multiple CEA ext blocks? */
3310 ext_index = 0;
3311 cea = drm_find_edid_extension(edid, CEA_EXT, &ext_index);
3312 if (cea)
3313 return cea;
3314
3315 /* CEA blocks can also be found embedded in a DisplayID block */
3316 ext_index = 0;
3317 for (;;) {
3318 displayid = drm_find_displayid_extension(edid, &length, &idx,
3319 &ext_index);
3320 if (!displayid)
3321 return NULL;
3322
3323 idx += sizeof(struct displayid_hdr);
3324 for_each_displayid_db(displayid, block, idx, length) {
3325 if (block->tag == DATA_BLOCK_CTA)
3326 return (u8 *)block;
3327 }
3328 }
3329
3330 return NULL;
3331 }
3332
cea_mode_for_vic(u8 vic)3333 static __always_inline const struct drm_display_mode *cea_mode_for_vic(u8 vic)
3334 {
3335 BUILD_BUG_ON(1 + ARRAY_SIZE(edid_cea_modes_1) - 1 != 127);
3336 BUILD_BUG_ON(193 + ARRAY_SIZE(edid_cea_modes_193) - 1 != 219);
3337
3338 if (vic >= 1 && vic < 1 + ARRAY_SIZE(edid_cea_modes_1))
3339 return &edid_cea_modes_1[vic - 1];
3340 if (vic >= 193 && vic < 193 + ARRAY_SIZE(edid_cea_modes_193))
3341 return &edid_cea_modes_193[vic - 193];
3342 return NULL;
3343 }
3344
cea_num_vics(void)3345 static u8 cea_num_vics(void)
3346 {
3347 return 193 + ARRAY_SIZE(edid_cea_modes_193);
3348 }
3349
cea_next_vic(u8 vic)3350 static u8 cea_next_vic(u8 vic)
3351 {
3352 if (++vic == 1 + ARRAY_SIZE(edid_cea_modes_1))
3353 vic = 193;
3354 return vic;
3355 }
3356
3357 /*
3358 * Calculate the alternate clock for the CEA mode
3359 * (60Hz vs. 59.94Hz etc.)
3360 */
3361 static unsigned int
cea_mode_alternate_clock(const struct drm_display_mode * cea_mode)3362 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode)
3363 {
3364 unsigned int clock = cea_mode->clock;
3365
3366 if (drm_mode_vrefresh(cea_mode) % 6 != 0)
3367 return clock;
3368
3369 /*
3370 * edid_cea_modes contains the 59.94Hz
3371 * variant for 240 and 480 line modes,
3372 * and the 60Hz variant otherwise.
3373 */
3374 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480)
3375 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000);
3376 else
3377 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001);
3378
3379 return clock;
3380 }
3381
3382 static bool
cea_mode_alternate_timings(u8 vic,struct drm_display_mode * mode)3383 cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode)
3384 {
3385 /*
3386 * For certain VICs the spec allows the vertical
3387 * front porch to vary by one or two lines.
3388 *
3389 * cea_modes[] stores the variant with the shortest
3390 * vertical front porch. We can adjust the mode to
3391 * get the other variants by simply increasing the
3392 * vertical front porch length.
3393 */
3394 BUILD_BUG_ON(cea_mode_for_vic(8)->vtotal != 262 ||
3395 cea_mode_for_vic(9)->vtotal != 262 ||
3396 cea_mode_for_vic(12)->vtotal != 262 ||
3397 cea_mode_for_vic(13)->vtotal != 262 ||
3398 cea_mode_for_vic(23)->vtotal != 312 ||
3399 cea_mode_for_vic(24)->vtotal != 312 ||
3400 cea_mode_for_vic(27)->vtotal != 312 ||
3401 cea_mode_for_vic(28)->vtotal != 312);
3402
3403 if (((vic == 8 || vic == 9 ||
3404 vic == 12 || vic == 13) && mode->vtotal < 263) ||
3405 ((vic == 23 || vic == 24 ||
3406 vic == 27 || vic == 28) && mode->vtotal < 314)) {
3407 mode->vsync_start++;
3408 mode->vsync_end++;
3409 mode->vtotal++;
3410
3411 return true;
3412 }
3413
3414 return false;
3415 }
3416
drm_match_cea_mode_clock_tolerance(const struct drm_display_mode * to_match,unsigned int clock_tolerance)3417 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match,
3418 unsigned int clock_tolerance)
3419 {
3420 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
3421 u8 vic;
3422
3423 if (!to_match->clock)
3424 return 0;
3425
3426 if (to_match->picture_aspect_ratio)
3427 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
3428
3429 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
3430 struct drm_display_mode cea_mode = *cea_mode_for_vic(vic);
3431 unsigned int clock1, clock2;
3432
3433 /* Check both 60Hz and 59.94Hz */
3434 clock1 = cea_mode.clock;
3435 clock2 = cea_mode_alternate_clock(&cea_mode);
3436
3437 if (abs(to_match->clock - clock1) > clock_tolerance &&
3438 abs(to_match->clock - clock2) > clock_tolerance)
3439 continue;
3440
3441 do {
3442 if (drm_mode_match(to_match, &cea_mode, match_flags))
3443 return vic;
3444 } while (cea_mode_alternate_timings(vic, &cea_mode));
3445 }
3446
3447 return 0;
3448 }
3449
3450 /**
3451 * drm_match_cea_mode - look for a CEA mode matching given mode
3452 * @to_match: display mode
3453 *
3454 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861
3455 * mode.
3456 */
drm_match_cea_mode(const struct drm_display_mode * to_match)3457 u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
3458 {
3459 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
3460 u8 vic;
3461
3462 if (!to_match->clock)
3463 return 0;
3464
3465 if (to_match->picture_aspect_ratio)
3466 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
3467
3468 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
3469 struct drm_display_mode cea_mode = *cea_mode_for_vic(vic);
3470 unsigned int clock1, clock2;
3471
3472 /* Check both 60Hz and 59.94Hz */
3473 clock1 = cea_mode.clock;
3474 clock2 = cea_mode_alternate_clock(&cea_mode);
3475
3476 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) &&
3477 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2))
3478 continue;
3479
3480 do {
3481 if (drm_mode_match(to_match, &cea_mode, match_flags))
3482 return vic;
3483 } while (cea_mode_alternate_timings(vic, &cea_mode));
3484 }
3485
3486 return 0;
3487 }
3488 EXPORT_SYMBOL(drm_match_cea_mode);
3489
drm_valid_cea_vic(u8 vic)3490 static bool drm_valid_cea_vic(u8 vic)
3491 {
3492 return cea_mode_for_vic(vic) != NULL;
3493 }
3494
drm_get_cea_aspect_ratio(const u8 video_code)3495 static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
3496 {
3497 const struct drm_display_mode *mode = cea_mode_for_vic(video_code);
3498
3499 if (mode)
3500 return mode->picture_aspect_ratio;
3501
3502 return HDMI_PICTURE_ASPECT_NONE;
3503 }
3504
drm_get_hdmi_aspect_ratio(const u8 video_code)3505 static enum hdmi_picture_aspect drm_get_hdmi_aspect_ratio(const u8 video_code)
3506 {
3507 return edid_4k_modes[video_code].picture_aspect_ratio;
3508 }
3509
3510 /*
3511 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor
3512 * specific block).
3513 */
3514 static unsigned int
hdmi_mode_alternate_clock(const struct drm_display_mode * hdmi_mode)3515 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode)
3516 {
3517 return cea_mode_alternate_clock(hdmi_mode);
3518 }
3519
drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode * to_match,unsigned int clock_tolerance)3520 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match,
3521 unsigned int clock_tolerance)
3522 {
3523 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
3524 u8 vic;
3525
3526 if (!to_match->clock)
3527 return 0;
3528
3529 if (to_match->picture_aspect_ratio)
3530 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
3531
3532 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
3533 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
3534 unsigned int clock1, clock2;
3535
3536 /* Make sure to also match alternate clocks */
3537 clock1 = hdmi_mode->clock;
3538 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
3539
3540 if (abs(to_match->clock - clock1) > clock_tolerance &&
3541 abs(to_match->clock - clock2) > clock_tolerance)
3542 continue;
3543
3544 if (drm_mode_match(to_match, hdmi_mode, match_flags))
3545 return vic;
3546 }
3547
3548 return 0;
3549 }
3550
3551 /*
3552 * drm_match_hdmi_mode - look for a HDMI mode matching given mode
3553 * @to_match: display mode
3554 *
3555 * An HDMI mode is one defined in the HDMI vendor specific block.
3556 *
3557 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one.
3558 */
drm_match_hdmi_mode(const struct drm_display_mode * to_match)3559 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match)
3560 {
3561 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
3562 u8 vic;
3563
3564 if (!to_match->clock)
3565 return 0;
3566
3567 if (to_match->picture_aspect_ratio)
3568 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
3569
3570 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
3571 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
3572 unsigned int clock1, clock2;
3573
3574 /* Make sure to also match alternate clocks */
3575 clock1 = hdmi_mode->clock;
3576 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
3577
3578 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
3579 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
3580 drm_mode_match(to_match, hdmi_mode, match_flags))
3581 return vic;
3582 }
3583 return 0;
3584 }
3585
drm_valid_hdmi_vic(u8 vic)3586 static bool drm_valid_hdmi_vic(u8 vic)
3587 {
3588 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes);
3589 }
3590
3591 static int
add_alternate_cea_modes(struct drm_connector * connector,struct edid * edid)3592 add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid)
3593 {
3594 struct drm_device *dev = connector->dev;
3595 struct drm_display_mode *mode, *tmp;
3596 LIST_HEAD(list);
3597 int modes = 0;
3598
3599 /* Don't add CEA modes if the CEA extension block is missing */
3600 if (!drm_find_cea_extension(edid))
3601 return 0;
3602
3603 /*
3604 * Go through all probed modes and create a new mode
3605 * with the alternate clock for certain CEA modes.
3606 */
3607 list_for_each_entry(mode, &connector->probed_modes, head) {
3608 const struct drm_display_mode *cea_mode = NULL;
3609 struct drm_display_mode *newmode;
3610 u8 vic = drm_match_cea_mode(mode);
3611 unsigned int clock1, clock2;
3612
3613 if (drm_valid_cea_vic(vic)) {
3614 cea_mode = cea_mode_for_vic(vic);
3615 clock2 = cea_mode_alternate_clock(cea_mode);
3616 } else {
3617 vic = drm_match_hdmi_mode(mode);
3618 if (drm_valid_hdmi_vic(vic)) {
3619 cea_mode = &edid_4k_modes[vic];
3620 clock2 = hdmi_mode_alternate_clock(cea_mode);
3621 }
3622 }
3623
3624 if (!cea_mode)
3625 continue;
3626
3627 clock1 = cea_mode->clock;
3628
3629 if (clock1 == clock2)
3630 continue;
3631
3632 if (mode->clock != clock1 && mode->clock != clock2)
3633 continue;
3634
3635 newmode = drm_mode_duplicate(dev, cea_mode);
3636 if (!newmode)
3637 continue;
3638
3639 /* Carry over the stereo flags */
3640 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK;
3641
3642 /*
3643 * The current mode could be either variant. Make
3644 * sure to pick the "other" clock for the new mode.
3645 */
3646 if (mode->clock != clock1)
3647 newmode->clock = clock1;
3648 else
3649 newmode->clock = clock2;
3650
3651 list_add_tail(&newmode->head, &list);
3652 }
3653
3654 list_for_each_entry_safe(mode, tmp, &list, head) {
3655 list_del(&mode->head);
3656 drm_mode_probed_add(connector, mode);
3657 modes++;
3658 }
3659
3660 return modes;
3661 }
3662
svd_to_vic(u8 svd)3663 static u8 svd_to_vic(u8 svd)
3664 {
3665 /* 0-6 bit vic, 7th bit native mode indicator */
3666 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192))
3667 return svd & 127;
3668
3669 return svd;
3670 }
3671
3672 static struct drm_display_mode *
drm_display_mode_from_vic_index(struct drm_connector * connector,const u8 * video_db,u8 video_len,u8 video_index)3673 drm_display_mode_from_vic_index(struct drm_connector *connector,
3674 const u8 *video_db, u8 video_len,
3675 u8 video_index)
3676 {
3677 struct drm_device *dev = connector->dev;
3678 struct drm_display_mode *newmode;
3679 u8 vic;
3680
3681 if (video_db == NULL || video_index >= video_len)
3682 return NULL;
3683
3684 /* CEA modes are numbered 1..127 */
3685 vic = svd_to_vic(video_db[video_index]);
3686 if (!drm_valid_cea_vic(vic))
3687 return NULL;
3688
3689 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic));
3690 if (!newmode)
3691 return NULL;
3692
3693 return newmode;
3694 }
3695
3696 /*
3697 * do_y420vdb_modes - Parse YCBCR 420 only modes
3698 * @connector: connector corresponding to the HDMI sink
3699 * @svds: start of the data block of CEA YCBCR 420 VDB
3700 * @len: length of the CEA YCBCR 420 VDB
3701 *
3702 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB)
3703 * which contains modes which can be supported in YCBCR 420
3704 * output format only.
3705 */
do_y420vdb_modes(struct drm_connector * connector,const u8 * svds,u8 svds_len)3706 static int do_y420vdb_modes(struct drm_connector *connector,
3707 const u8 *svds, u8 svds_len)
3708 {
3709 int modes = 0, i;
3710 struct drm_device *dev = connector->dev;
3711 struct drm_display_info *info = &connector->display_info;
3712 struct drm_hdmi_info *hdmi = &info->hdmi;
3713
3714 for (i = 0; i < svds_len; i++) {
3715 u8 vic = svd_to_vic(svds[i]);
3716 struct drm_display_mode *newmode;
3717
3718 if (!drm_valid_cea_vic(vic))
3719 continue;
3720
3721 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic));
3722 if (!newmode)
3723 break;
3724 bitmap_set(hdmi->y420_vdb_modes, vic, 1);
3725 drm_mode_probed_add(connector, newmode);
3726 modes++;
3727 }
3728
3729 if (modes > 0)
3730 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
3731 return modes;
3732 }
3733
3734 /*
3735 * drm_add_cmdb_modes - Add a YCBCR 420 mode into bitmap
3736 * @connector: connector corresponding to the HDMI sink
3737 * @vic: CEA vic for the video mode to be added in the map
3738 *
3739 * Makes an entry for a videomode in the YCBCR 420 bitmap
3740 */
3741 static void
drm_add_cmdb_modes(struct drm_connector * connector,u8 svd)3742 drm_add_cmdb_modes(struct drm_connector *connector, u8 svd)
3743 {
3744 u8 vic = svd_to_vic(svd);
3745 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
3746
3747 if (!drm_valid_cea_vic(vic))
3748 return;
3749
3750 bitmap_set(hdmi->y420_cmdb_modes, vic, 1);
3751 }
3752
3753 /**
3754 * drm_display_mode_from_cea_vic() - return a mode for CEA VIC
3755 * @dev: DRM device
3756 * @video_code: CEA VIC of the mode
3757 *
3758 * Creates a new mode matching the specified CEA VIC.
3759 *
3760 * Returns: A new drm_display_mode on success or NULL on failure
3761 */
3762 struct drm_display_mode *
drm_display_mode_from_cea_vic(struct drm_device * dev,u8 video_code)3763 drm_display_mode_from_cea_vic(struct drm_device *dev,
3764 u8 video_code)
3765 {
3766 const struct drm_display_mode *cea_mode;
3767 struct drm_display_mode *newmode;
3768
3769 cea_mode = cea_mode_for_vic(video_code);
3770 if (!cea_mode)
3771 return NULL;
3772
3773 newmode = drm_mode_duplicate(dev, cea_mode);
3774 if (!newmode)
3775 return NULL;
3776
3777 return newmode;
3778 }
3779 EXPORT_SYMBOL(drm_display_mode_from_cea_vic);
3780
3781 static int
do_cea_modes(struct drm_connector * connector,const u8 * db,u8 len)3782 do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len)
3783 {
3784 int i, modes = 0;
3785 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
3786
3787 for (i = 0; i < len; i++) {
3788 struct drm_display_mode *mode;
3789
3790 mode = drm_display_mode_from_vic_index(connector, db, len, i);
3791 if (mode) {
3792 /*
3793 * YCBCR420 capability block contains a bitmap which
3794 * gives the index of CEA modes from CEA VDB, which
3795 * can support YCBCR 420 sampling output also (apart
3796 * from RGB/YCBCR444 etc).
3797 * For example, if the bit 0 in bitmap is set,
3798 * first mode in VDB can support YCBCR420 output too.
3799 * Add YCBCR420 modes only if sink is HDMI 2.0 capable.
3800 */
3801 if (i < 64 && hdmi->y420_cmdb_map & (1ULL << i))
3802 drm_add_cmdb_modes(connector, db[i]);
3803
3804 drm_mode_probed_add(connector, mode);
3805 modes++;
3806 }
3807 }
3808
3809 return modes;
3810 }
3811
3812 struct stereo_mandatory_mode {
3813 int width, height, vrefresh;
3814 unsigned int flags;
3815 };
3816
3817 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = {
3818 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3819 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING },
3820 { 1920, 1080, 50,
3821 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
3822 { 1920, 1080, 60,
3823 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
3824 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3825 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING },
3826 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3827 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING }
3828 };
3829
3830 static bool
stereo_match_mandatory(const struct drm_display_mode * mode,const struct stereo_mandatory_mode * stereo_mode)3831 stereo_match_mandatory(const struct drm_display_mode *mode,
3832 const struct stereo_mandatory_mode *stereo_mode)
3833 {
3834 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
3835
3836 return mode->hdisplay == stereo_mode->width &&
3837 mode->vdisplay == stereo_mode->height &&
3838 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) &&
3839 drm_mode_vrefresh(mode) == stereo_mode->vrefresh;
3840 }
3841
add_hdmi_mandatory_stereo_modes(struct drm_connector * connector)3842 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector)
3843 {
3844 struct drm_device *dev = connector->dev;
3845 const struct drm_display_mode *mode;
3846 struct list_head stereo_modes;
3847 int modes = 0, i;
3848
3849 INIT_LIST_HEAD(&stereo_modes);
3850
3851 list_for_each_entry(mode, &connector->probed_modes, head) {
3852 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) {
3853 const struct stereo_mandatory_mode *mandatory;
3854 struct drm_display_mode *new_mode;
3855
3856 if (!stereo_match_mandatory(mode,
3857 &stereo_mandatory_modes[i]))
3858 continue;
3859
3860 mandatory = &stereo_mandatory_modes[i];
3861 new_mode = drm_mode_duplicate(dev, mode);
3862 if (!new_mode)
3863 continue;
3864
3865 new_mode->flags |= mandatory->flags;
3866 list_add_tail(&new_mode->head, &stereo_modes);
3867 modes++;
3868 }
3869 }
3870
3871 list_splice_tail(&stereo_modes, &connector->probed_modes);
3872
3873 return modes;
3874 }
3875
add_hdmi_mode(struct drm_connector * connector,u8 vic)3876 static int add_hdmi_mode(struct drm_connector *connector, u8 vic)
3877 {
3878 struct drm_device *dev = connector->dev;
3879 struct drm_display_mode *newmode;
3880
3881 if (!drm_valid_hdmi_vic(vic)) {
3882 DRM_ERROR("Unknown HDMI VIC: %d\n", vic);
3883 return 0;
3884 }
3885
3886 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]);
3887 if (!newmode)
3888 return 0;
3889
3890 drm_mode_probed_add(connector, newmode);
3891
3892 return 1;
3893 }
3894
add_3d_struct_modes(struct drm_connector * connector,u16 structure,const u8 * video_db,u8 video_len,u8 video_index)3895 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure,
3896 const u8 *video_db, u8 video_len, u8 video_index)
3897 {
3898 struct drm_display_mode *newmode;
3899 int modes = 0;
3900
3901 if (structure & (1 << 0)) {
3902 newmode = drm_display_mode_from_vic_index(connector, video_db,
3903 video_len,
3904 video_index);
3905 if (newmode) {
3906 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING;
3907 drm_mode_probed_add(connector, newmode);
3908 modes++;
3909 }
3910 }
3911 if (structure & (1 << 6)) {
3912 newmode = drm_display_mode_from_vic_index(connector, video_db,
3913 video_len,
3914 video_index);
3915 if (newmode) {
3916 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
3917 drm_mode_probed_add(connector, newmode);
3918 modes++;
3919 }
3920 }
3921 if (structure & (1 << 8)) {
3922 newmode = drm_display_mode_from_vic_index(connector, video_db,
3923 video_len,
3924 video_index);
3925 if (newmode) {
3926 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
3927 drm_mode_probed_add(connector, newmode);
3928 modes++;
3929 }
3930 }
3931
3932 return modes;
3933 }
3934
3935 /*
3936 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block
3937 * @connector: connector corresponding to the HDMI sink
3938 * @db: start of the CEA vendor specific block
3939 * @len: length of the CEA block payload, ie. one can access up to db[len]
3940 *
3941 * Parses the HDMI VSDB looking for modes to add to @connector. This function
3942 * also adds the stereo 3d modes when applicable.
3943 */
3944 static int
do_hdmi_vsdb_modes(struct drm_connector * connector,const u8 * db,u8 len,const u8 * video_db,u8 video_len)3945 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len,
3946 const u8 *video_db, u8 video_len)
3947 {
3948 struct drm_display_info *info = &connector->display_info;
3949 int modes = 0, offset = 0, i, multi_present = 0, multi_len;
3950 u8 vic_len, hdmi_3d_len = 0;
3951 u16 mask;
3952 u16 structure_all;
3953
3954 if (len < 8)
3955 goto out;
3956
3957 /* no HDMI_Video_Present */
3958 if (!(db[8] & (1 << 5)))
3959 goto out;
3960
3961 /* Latency_Fields_Present */
3962 if (db[8] & (1 << 7))
3963 offset += 2;
3964
3965 /* I_Latency_Fields_Present */
3966 if (db[8] & (1 << 6))
3967 offset += 2;
3968
3969 /* the declared length is not long enough for the 2 first bytes
3970 * of additional video format capabilities */
3971 if (len < (8 + offset + 2))
3972 goto out;
3973
3974 /* 3D_Present */
3975 offset++;
3976 if (db[8 + offset] & (1 << 7)) {
3977 modes += add_hdmi_mandatory_stereo_modes(connector);
3978
3979 /* 3D_Multi_present */
3980 multi_present = (db[8 + offset] & 0x60) >> 5;
3981 }
3982
3983 offset++;
3984 vic_len = db[8 + offset] >> 5;
3985 hdmi_3d_len = db[8 + offset] & 0x1f;
3986
3987 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) {
3988 u8 vic;
3989
3990 vic = db[9 + offset + i];
3991 modes += add_hdmi_mode(connector, vic);
3992 }
3993 offset += 1 + vic_len;
3994
3995 if (multi_present == 1)
3996 multi_len = 2;
3997 else if (multi_present == 2)
3998 multi_len = 4;
3999 else
4000 multi_len = 0;
4001
4002 if (len < (8 + offset + hdmi_3d_len - 1))
4003 goto out;
4004
4005 if (hdmi_3d_len < multi_len)
4006 goto out;
4007
4008 if (multi_present == 1 || multi_present == 2) {
4009 /* 3D_Structure_ALL */
4010 structure_all = (db[8 + offset] << 8) | db[9 + offset];
4011
4012 /* check if 3D_MASK is present */
4013 if (multi_present == 2)
4014 mask = (db[10 + offset] << 8) | db[11 + offset];
4015 else
4016 mask = 0xffff;
4017
4018 for (i = 0; i < 16; i++) {
4019 if (mask & (1 << i))
4020 modes += add_3d_struct_modes(connector,
4021 structure_all,
4022 video_db,
4023 video_len, i);
4024 }
4025 }
4026
4027 offset += multi_len;
4028
4029 for (i = 0; i < (hdmi_3d_len - multi_len); i++) {
4030 int vic_index;
4031 struct drm_display_mode *newmode = NULL;
4032 unsigned int newflag = 0;
4033 bool detail_present;
4034
4035 detail_present = ((db[8 + offset + i] & 0x0f) > 7);
4036
4037 if (detail_present && (i + 1 == hdmi_3d_len - multi_len))
4038 break;
4039
4040 /* 2D_VIC_order_X */
4041 vic_index = db[8 + offset + i] >> 4;
4042
4043 /* 3D_Structure_X */
4044 switch (db[8 + offset + i] & 0x0f) {
4045 case 0:
4046 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING;
4047 break;
4048 case 6:
4049 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
4050 break;
4051 case 8:
4052 /* 3D_Detail_X */
4053 if ((db[9 + offset + i] >> 4) == 1)
4054 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
4055 break;
4056 }
4057
4058 if (newflag != 0) {
4059 newmode = drm_display_mode_from_vic_index(connector,
4060 video_db,
4061 video_len,
4062 vic_index);
4063
4064 if (newmode) {
4065 newmode->flags |= newflag;
4066 drm_mode_probed_add(connector, newmode);
4067 modes++;
4068 }
4069 }
4070
4071 if (detail_present)
4072 i++;
4073 }
4074
4075 out:
4076 if (modes > 0)
4077 info->has_hdmi_infoframe = true;
4078 return modes;
4079 }
4080
4081 static int
cea_db_payload_len(const u8 * db)4082 cea_db_payload_len(const u8 *db)
4083 {
4084 return db[0] & 0x1f;
4085 }
4086
4087 static int
cea_db_extended_tag(const u8 * db)4088 cea_db_extended_tag(const u8 *db)
4089 {
4090 return db[1];
4091 }
4092
4093 static int
cea_db_tag(const u8 * db)4094 cea_db_tag(const u8 *db)
4095 {
4096 return db[0] >> 5;
4097 }
4098
4099 static int
cea_revision(const u8 * cea)4100 cea_revision(const u8 *cea)
4101 {
4102 /*
4103 * FIXME is this correct for the DispID variant?
4104 * The DispID spec doesn't really specify whether
4105 * this is the revision of the CEA extension or
4106 * the DispID CEA data block. And the only value
4107 * given as an example is 0.
4108 */
4109 return cea[1];
4110 }
4111
4112 static int
cea_db_offsets(const u8 * cea,int * start,int * end)4113 cea_db_offsets(const u8 *cea, int *start, int *end)
4114 {
4115 /* DisplayID CTA extension blocks and top-level CEA EDID
4116 * block header definitions differ in the following bytes:
4117 * 1) Byte 2 of the header specifies length differently,
4118 * 2) Byte 3 is only present in the CEA top level block.
4119 *
4120 * The different definitions for byte 2 follow.
4121 *
4122 * DisplayID CTA extension block defines byte 2 as:
4123 * Number of payload bytes
4124 *
4125 * CEA EDID block defines byte 2 as:
4126 * Byte number (decimal) within this block where the 18-byte
4127 * DTDs begin. If no non-DTD data is present in this extension
4128 * block, the value should be set to 04h (the byte after next).
4129 * If set to 00h, there are no DTDs present in this block and
4130 * no non-DTD data.
4131 */
4132 if (cea[0] == DATA_BLOCK_CTA) {
4133 /*
4134 * for_each_displayid_db() has already verified
4135 * that these stay within expected bounds.
4136 */
4137 *start = 3;
4138 *end = *start + cea[2];
4139 } else if (cea[0] == CEA_EXT) {
4140 /* Data block offset in CEA extension block */
4141 *start = 4;
4142 *end = cea[2];
4143 if (*end == 0)
4144 *end = 127;
4145 if (*end < 4 || *end > 127)
4146 return -ERANGE;
4147 } else {
4148 return -EOPNOTSUPP;
4149 }
4150
4151 return 0;
4152 }
4153
cea_db_is_hdmi_vsdb(const u8 * db)4154 static bool cea_db_is_hdmi_vsdb(const u8 *db)
4155 {
4156 int hdmi_id;
4157
4158 if (cea_db_tag(db) != VENDOR_BLOCK)
4159 return false;
4160
4161 if (cea_db_payload_len(db) < 5)
4162 return false;
4163
4164 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16);
4165
4166 return hdmi_id == HDMI_IEEE_OUI;
4167 }
4168
cea_db_is_hdmi_forum_vsdb(const u8 * db)4169 static bool cea_db_is_hdmi_forum_vsdb(const u8 *db)
4170 {
4171 unsigned int oui;
4172
4173 if (cea_db_tag(db) != VENDOR_BLOCK)
4174 return false;
4175
4176 if (cea_db_payload_len(db) < 7)
4177 return false;
4178
4179 oui = db[3] << 16 | db[2] << 8 | db[1];
4180
4181 return oui == HDMI_FORUM_IEEE_OUI;
4182 }
4183
cea_db_is_vcdb(const u8 * db)4184 static bool cea_db_is_vcdb(const u8 *db)
4185 {
4186 if (cea_db_tag(db) != USE_EXTENDED_TAG)
4187 return false;
4188
4189 if (cea_db_payload_len(db) != 2)
4190 return false;
4191
4192 if (cea_db_extended_tag(db) != EXT_VIDEO_CAPABILITY_BLOCK)
4193 return false;
4194
4195 return true;
4196 }
4197
cea_db_is_hdmi_forum_scdb(const u8 * db)4198 static bool cea_db_is_hdmi_forum_scdb(const u8 *db)
4199 {
4200 if (cea_db_tag(db) != USE_EXTENDED_TAG)
4201 return false;
4202
4203 if (cea_db_payload_len(db) < 7)
4204 return false;
4205
4206 if (cea_db_extended_tag(db) != EXT_VIDEO_HF_SCDB_DATA_BLOCK)
4207 return false;
4208
4209 return true;
4210 }
4211
cea_db_is_y420cmdb(const u8 * db)4212 static bool cea_db_is_y420cmdb(const u8 *db)
4213 {
4214 if (cea_db_tag(db) != USE_EXTENDED_TAG)
4215 return false;
4216
4217 if (!cea_db_payload_len(db))
4218 return false;
4219
4220 if (cea_db_extended_tag(db) != EXT_VIDEO_CAP_BLOCK_Y420CMDB)
4221 return false;
4222
4223 return true;
4224 }
4225
cea_db_is_y420vdb(const u8 * db)4226 static bool cea_db_is_y420vdb(const u8 *db)
4227 {
4228 if (cea_db_tag(db) != USE_EXTENDED_TAG)
4229 return false;
4230
4231 if (!cea_db_payload_len(db))
4232 return false;
4233
4234 if (cea_db_extended_tag(db) != EXT_VIDEO_DATA_BLOCK_420)
4235 return false;
4236
4237 return true;
4238 }
4239
4240 #define for_each_cea_db(cea, i, start, end) \
4241 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1)
4242
drm_parse_y420cmdb_bitmap(struct drm_connector * connector,const u8 * db)4243 static void drm_parse_y420cmdb_bitmap(struct drm_connector *connector,
4244 const u8 *db)
4245 {
4246 struct drm_display_info *info = &connector->display_info;
4247 struct drm_hdmi_info *hdmi = &info->hdmi;
4248 u8 map_len = cea_db_payload_len(db) - 1;
4249 u8 count;
4250 u64 map = 0;
4251
4252 if (map_len == 0) {
4253 /* All CEA modes support ycbcr420 sampling also.*/
4254 hdmi->y420_cmdb_map = U64_MAX;
4255 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
4256 return;
4257 }
4258
4259 /*
4260 * This map indicates which of the existing CEA block modes
4261 * from VDB can support YCBCR420 output too. So if bit=0 is
4262 * set, first mode from VDB can support YCBCR420 output too.
4263 * We will parse and keep this map, before parsing VDB itself
4264 * to avoid going through the same block again and again.
4265 *
4266 * Spec is not clear about max possible size of this block.
4267 * Clamping max bitmap block size at 8 bytes. Every byte can
4268 * address 8 CEA modes, in this way this map can address
4269 * 8*8 = first 64 SVDs.
4270 */
4271 if (WARN_ON_ONCE(map_len > 8))
4272 map_len = 8;
4273
4274 for (count = 0; count < map_len; count++)
4275 map |= (u64)db[2 + count] << (8 * count);
4276
4277 if (map)
4278 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
4279
4280 hdmi->y420_cmdb_map = map;
4281 }
4282
4283 static int
add_cea_modes(struct drm_connector * connector,struct edid * edid)4284 add_cea_modes(struct drm_connector *connector, struct edid *edid)
4285 {
4286 const u8 *cea = drm_find_cea_extension(edid);
4287 const u8 *db, *hdmi = NULL, *video = NULL;
4288 u8 dbl, hdmi_len, video_len = 0;
4289 int modes = 0;
4290
4291 if (cea && cea_revision(cea) >= 3) {
4292 int i, start, end;
4293
4294 if (cea_db_offsets(cea, &start, &end))
4295 return 0;
4296
4297 for_each_cea_db(cea, i, start, end) {
4298 db = &cea[i];
4299 dbl = cea_db_payload_len(db);
4300
4301 if (cea_db_tag(db) == VIDEO_BLOCK) {
4302 video = db + 1;
4303 video_len = dbl;
4304 modes += do_cea_modes(connector, video, dbl);
4305 } else if (cea_db_is_hdmi_vsdb(db)) {
4306 hdmi = db;
4307 hdmi_len = dbl;
4308 } else if (cea_db_is_y420vdb(db)) {
4309 const u8 *vdb420 = &db[2];
4310
4311 /* Add 4:2:0(only) modes present in EDID */
4312 modes += do_y420vdb_modes(connector,
4313 vdb420,
4314 dbl - 1);
4315 }
4316 }
4317 }
4318
4319 /*
4320 * We parse the HDMI VSDB after having added the cea modes as we will
4321 * be patching their flags when the sink supports stereo 3D.
4322 */
4323 if (hdmi)
4324 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video,
4325 video_len);
4326
4327 return modes;
4328 }
4329
fixup_detailed_cea_mode_clock(struct drm_display_mode * mode)4330 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode)
4331 {
4332 const struct drm_display_mode *cea_mode;
4333 int clock1, clock2, clock;
4334 u8 vic;
4335 const char *type;
4336
4337 /*
4338 * allow 5kHz clock difference either way to account for
4339 * the 10kHz clock resolution limit of detailed timings.
4340 */
4341 vic = drm_match_cea_mode_clock_tolerance(mode, 5);
4342 if (drm_valid_cea_vic(vic)) {
4343 type = "CEA";
4344 cea_mode = cea_mode_for_vic(vic);
4345 clock1 = cea_mode->clock;
4346 clock2 = cea_mode_alternate_clock(cea_mode);
4347 } else {
4348 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5);
4349 if (drm_valid_hdmi_vic(vic)) {
4350 type = "HDMI";
4351 cea_mode = &edid_4k_modes[vic];
4352 clock1 = cea_mode->clock;
4353 clock2 = hdmi_mode_alternate_clock(cea_mode);
4354 } else {
4355 return;
4356 }
4357 }
4358
4359 /* pick whichever is closest */
4360 if (abs(mode->clock - clock1) < abs(mode->clock - clock2))
4361 clock = clock1;
4362 else
4363 clock = clock2;
4364
4365 if (mode->clock == clock)
4366 return;
4367
4368 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n",
4369 type, vic, mode->clock, clock);
4370 mode->clock = clock;
4371 }
4372
cea_db_is_hdmi_hdr_metadata_block(const u8 * db)4373 static bool cea_db_is_hdmi_hdr_metadata_block(const u8 *db)
4374 {
4375 if (cea_db_tag(db) != USE_EXTENDED_TAG)
4376 return false;
4377
4378 if (db[1] != HDR_STATIC_METADATA_BLOCK)
4379 return false;
4380
4381 if (cea_db_payload_len(db) < 3)
4382 return false;
4383
4384 return true;
4385 }
4386
eotf_supported(const u8 * edid_ext)4387 static uint8_t eotf_supported(const u8 *edid_ext)
4388 {
4389 return edid_ext[2] &
4390 (BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) |
4391 BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) |
4392 BIT(HDMI_EOTF_SMPTE_ST2084) |
4393 BIT(HDMI_EOTF_BT_2100_HLG));
4394 }
4395
hdr_metadata_type(const u8 * edid_ext)4396 static uint8_t hdr_metadata_type(const u8 *edid_ext)
4397 {
4398 return edid_ext[3] &
4399 BIT(HDMI_STATIC_METADATA_TYPE1);
4400 }
4401
4402 static void
drm_parse_hdr_metadata_block(struct drm_connector * connector,const u8 * db)4403 drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db)
4404 {
4405 u16 len;
4406
4407 len = cea_db_payload_len(db);
4408
4409 connector->hdr_sink_metadata.hdmi_type1.eotf =
4410 eotf_supported(db);
4411 connector->hdr_sink_metadata.hdmi_type1.metadata_type =
4412 hdr_metadata_type(db);
4413
4414 if (len >= 4)
4415 connector->hdr_sink_metadata.hdmi_type1.max_cll = db[4];
4416 if (len >= 5)
4417 connector->hdr_sink_metadata.hdmi_type1.max_fall = db[5];
4418 if (len >= 6)
4419 connector->hdr_sink_metadata.hdmi_type1.min_cll = db[6];
4420 }
4421
4422 static void
drm_parse_hdmi_vsdb_audio(struct drm_connector * connector,const u8 * db)4423 drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db)
4424 {
4425 u8 len = cea_db_payload_len(db);
4426
4427 if (len >= 6 && (db[6] & (1 << 7)))
4428 connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI;
4429 if (len >= 8) {
4430 connector->latency_present[0] = db[8] >> 7;
4431 connector->latency_present[1] = (db[8] >> 6) & 1;
4432 }
4433 if (len >= 9)
4434 connector->video_latency[0] = db[9];
4435 if (len >= 10)
4436 connector->audio_latency[0] = db[10];
4437 if (len >= 11)
4438 connector->video_latency[1] = db[11];
4439 if (len >= 12)
4440 connector->audio_latency[1] = db[12];
4441
4442 DRM_DEBUG_KMS("HDMI: latency present %d %d, "
4443 "video latency %d %d, "
4444 "audio latency %d %d\n",
4445 connector->latency_present[0],
4446 connector->latency_present[1],
4447 connector->video_latency[0],
4448 connector->video_latency[1],
4449 connector->audio_latency[0],
4450 connector->audio_latency[1]);
4451 }
4452
4453 static void
monitor_name(struct detailed_timing * t,void * data)4454 monitor_name(struct detailed_timing *t, void *data)
4455 {
4456 if (!is_display_descriptor((const u8 *)t, EDID_DETAIL_MONITOR_NAME))
4457 return;
4458
4459 *(u8 **)data = t->data.other_data.data.str.str;
4460 }
4461
get_monitor_name(struct edid * edid,char name[13])4462 static int get_monitor_name(struct edid *edid, char name[13])
4463 {
4464 char *edid_name = NULL;
4465 int mnl;
4466
4467 if (!edid || !name)
4468 return 0;
4469
4470 drm_for_each_detailed_block((u8 *)edid, monitor_name, &edid_name);
4471 for (mnl = 0; edid_name && mnl < 13; mnl++) {
4472 if (edid_name[mnl] == 0x0a)
4473 break;
4474
4475 name[mnl] = edid_name[mnl];
4476 }
4477
4478 return mnl;
4479 }
4480
4481 /**
4482 * drm_edid_get_monitor_name - fetch the monitor name from the edid
4483 * @edid: monitor EDID information
4484 * @name: pointer to a character array to hold the name of the monitor
4485 * @bufsize: The size of the name buffer (should be at least 14 chars.)
4486 *
4487 */
drm_edid_get_monitor_name(struct edid * edid,char * name,int bufsize)4488 void drm_edid_get_monitor_name(struct edid *edid, char *name, int bufsize)
4489 {
4490 int name_length;
4491 char buf[13];
4492
4493 if (bufsize <= 0)
4494 return;
4495
4496 name_length = min(get_monitor_name(edid, buf), bufsize - 1);
4497 memcpy(name, buf, name_length);
4498 name[name_length] = '\0';
4499 }
4500 EXPORT_SYMBOL(drm_edid_get_monitor_name);
4501
clear_eld(struct drm_connector * connector)4502 static void clear_eld(struct drm_connector *connector)
4503 {
4504 memset(connector->eld, 0, sizeof(connector->eld));
4505
4506 connector->latency_present[0] = false;
4507 connector->latency_present[1] = false;
4508 connector->video_latency[0] = 0;
4509 connector->audio_latency[0] = 0;
4510 connector->video_latency[1] = 0;
4511 connector->audio_latency[1] = 0;
4512 }
4513
4514 /*
4515 * drm_edid_to_eld - build ELD from EDID
4516 * @connector: connector corresponding to the HDMI/DP sink
4517 * @edid: EDID to parse
4518 *
4519 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The
4520 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in.
4521 */
drm_edid_to_eld(struct drm_connector * connector,struct edid * edid)4522 static void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid)
4523 {
4524 uint8_t *eld = connector->eld;
4525 u8 *cea;
4526 u8 *db;
4527 int total_sad_count = 0;
4528 int mnl;
4529 int dbl;
4530
4531 clear_eld(connector);
4532
4533 if (!edid)
4534 return;
4535
4536 cea = drm_find_cea_extension(edid);
4537 if (!cea) {
4538 DRM_DEBUG_KMS("ELD: no CEA Extension found\n");
4539 return;
4540 }
4541
4542 mnl = get_monitor_name(edid, &eld[DRM_ELD_MONITOR_NAME_STRING]);
4543 DRM_DEBUG_KMS("ELD monitor %s\n", &eld[DRM_ELD_MONITOR_NAME_STRING]);
4544
4545 eld[DRM_ELD_CEA_EDID_VER_MNL] = cea[1] << DRM_ELD_CEA_EDID_VER_SHIFT;
4546 eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl;
4547
4548 eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D;
4549
4550 eld[DRM_ELD_MANUFACTURER_NAME0] = edid->mfg_id[0];
4551 eld[DRM_ELD_MANUFACTURER_NAME1] = edid->mfg_id[1];
4552 eld[DRM_ELD_PRODUCT_CODE0] = edid->prod_code[0];
4553 eld[DRM_ELD_PRODUCT_CODE1] = edid->prod_code[1];
4554
4555 if (cea_revision(cea) >= 3) {
4556 int i, start, end;
4557 int sad_count;
4558
4559 if (cea_db_offsets(cea, &start, &end)) {
4560 start = 0;
4561 end = 0;
4562 }
4563
4564 for_each_cea_db(cea, i, start, end) {
4565 db = &cea[i];
4566 dbl = cea_db_payload_len(db);
4567
4568 switch (cea_db_tag(db)) {
4569 case AUDIO_BLOCK:
4570 /* Audio Data Block, contains SADs */
4571 sad_count = min(dbl / 3, 15 - total_sad_count);
4572 if (sad_count >= 1)
4573 memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)],
4574 &db[1], sad_count * 3);
4575 total_sad_count += sad_count;
4576 break;
4577 case SPEAKER_BLOCK:
4578 /* Speaker Allocation Data Block */
4579 if (dbl >= 1)
4580 eld[DRM_ELD_SPEAKER] = db[1];
4581 break;
4582 case VENDOR_BLOCK:
4583 /* HDMI Vendor-Specific Data Block */
4584 if (cea_db_is_hdmi_vsdb(db))
4585 drm_parse_hdmi_vsdb_audio(connector, db);
4586 break;
4587 default:
4588 break;
4589 }
4590 }
4591 }
4592 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT;
4593
4594 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
4595 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4596 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP;
4597 else
4598 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI;
4599
4600 eld[DRM_ELD_BASELINE_ELD_LEN] =
4601 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4);
4602
4603 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n",
4604 drm_eld_size(eld), total_sad_count);
4605 }
4606
4607 /**
4608 * drm_edid_to_sad - extracts SADs from EDID
4609 * @edid: EDID to parse
4610 * @sads: pointer that will be set to the extracted SADs
4611 *
4612 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it.
4613 *
4614 * Note: The returned pointer needs to be freed using kfree().
4615 *
4616 * Return: The number of found SADs or negative number on error.
4617 */
drm_edid_to_sad(struct edid * edid,struct cea_sad ** sads)4618 int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads)
4619 {
4620 int count = 0;
4621 int i, start, end, dbl;
4622 u8 *cea;
4623
4624 cea = drm_find_cea_extension(edid);
4625 if (!cea) {
4626 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
4627 return 0;
4628 }
4629
4630 if (cea_revision(cea) < 3) {
4631 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
4632 return 0;
4633 }
4634
4635 if (cea_db_offsets(cea, &start, &end)) {
4636 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
4637 return -EPROTO;
4638 }
4639
4640 for_each_cea_db(cea, i, start, end) {
4641 u8 *db = &cea[i];
4642
4643 if (cea_db_tag(db) == AUDIO_BLOCK) {
4644 int j;
4645
4646 dbl = cea_db_payload_len(db);
4647
4648 count = dbl / 3; /* SAD is 3B */
4649 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL);
4650 if (!*sads)
4651 return -ENOMEM;
4652 for (j = 0; j < count; j++) {
4653 u8 *sad = &db[1 + j * 3];
4654
4655 (*sads)[j].format = (sad[0] & 0x78) >> 3;
4656 (*sads)[j].channels = sad[0] & 0x7;
4657 (*sads)[j].freq = sad[1] & 0x7F;
4658 (*sads)[j].byte2 = sad[2];
4659 }
4660 break;
4661 }
4662 }
4663
4664 return count;
4665 }
4666 EXPORT_SYMBOL(drm_edid_to_sad);
4667
4668 /**
4669 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID
4670 * @edid: EDID to parse
4671 * @sadb: pointer to the speaker block
4672 *
4673 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it.
4674 *
4675 * Note: The returned pointer needs to be freed using kfree().
4676 *
4677 * Return: The number of found Speaker Allocation Blocks or negative number on
4678 * error.
4679 */
drm_edid_to_speaker_allocation(struct edid * edid,u8 ** sadb)4680 int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb)
4681 {
4682 int count = 0;
4683 int i, start, end, dbl;
4684 const u8 *cea;
4685
4686 cea = drm_find_cea_extension(edid);
4687 if (!cea) {
4688 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
4689 return 0;
4690 }
4691
4692 if (cea_revision(cea) < 3) {
4693 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
4694 return 0;
4695 }
4696
4697 if (cea_db_offsets(cea, &start, &end)) {
4698 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
4699 return -EPROTO;
4700 }
4701
4702 for_each_cea_db(cea, i, start, end) {
4703 const u8 *db = &cea[i];
4704
4705 if (cea_db_tag(db) == SPEAKER_BLOCK) {
4706 dbl = cea_db_payload_len(db);
4707
4708 /* Speaker Allocation Data Block */
4709 if (dbl == 3) {
4710 *sadb = kmemdup(&db[1], dbl, GFP_KERNEL);
4711 if (!*sadb)
4712 return -ENOMEM;
4713 count = dbl;
4714 break;
4715 }
4716 }
4717 }
4718
4719 return count;
4720 }
4721 EXPORT_SYMBOL(drm_edid_to_speaker_allocation);
4722
4723 /**
4724 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay
4725 * @connector: connector associated with the HDMI/DP sink
4726 * @mode: the display mode
4727 *
4728 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if
4729 * the sink doesn't support audio or video.
4730 */
drm_av_sync_delay(struct drm_connector * connector,const struct drm_display_mode * mode)4731 int drm_av_sync_delay(struct drm_connector *connector,
4732 const struct drm_display_mode *mode)
4733 {
4734 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
4735 int a, v;
4736
4737 if (!connector->latency_present[0])
4738 return 0;
4739 if (!connector->latency_present[1])
4740 i = 0;
4741
4742 a = connector->audio_latency[i];
4743 v = connector->video_latency[i];
4744
4745 /*
4746 * HDMI/DP sink doesn't support audio or video?
4747 */
4748 if (a == 255 || v == 255)
4749 return 0;
4750
4751 /*
4752 * Convert raw EDID values to millisecond.
4753 * Treat unknown latency as 0ms.
4754 */
4755 if (a)
4756 a = min(2 * (a - 1), 500);
4757 if (v)
4758 v = min(2 * (v - 1), 500);
4759
4760 return max(v - a, 0);
4761 }
4762 EXPORT_SYMBOL(drm_av_sync_delay);
4763
4764 /**
4765 * drm_detect_hdmi_monitor - detect whether monitor is HDMI
4766 * @edid: monitor EDID information
4767 *
4768 * Parse the CEA extension according to CEA-861-B.
4769 *
4770 * Drivers that have added the modes parsed from EDID to drm_display_info
4771 * should use &drm_display_info.is_hdmi instead of calling this function.
4772 *
4773 * Return: True if the monitor is HDMI, false if not or unknown.
4774 */
drm_detect_hdmi_monitor(struct edid * edid)4775 bool drm_detect_hdmi_monitor(struct edid *edid)
4776 {
4777 u8 *edid_ext;
4778 int i;
4779 int start_offset, end_offset;
4780
4781 edid_ext = drm_find_cea_extension(edid);
4782 if (!edid_ext)
4783 return false;
4784
4785 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
4786 return false;
4787
4788 /*
4789 * Because HDMI identifier is in Vendor Specific Block,
4790 * search it from all data blocks of CEA extension.
4791 */
4792 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
4793 if (cea_db_is_hdmi_vsdb(&edid_ext[i]))
4794 return true;
4795 }
4796
4797 return false;
4798 }
4799 EXPORT_SYMBOL(drm_detect_hdmi_monitor);
4800
4801 /**
4802 * drm_detect_monitor_audio - check monitor audio capability
4803 * @edid: EDID block to scan
4804 *
4805 * Monitor should have CEA extension block.
4806 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic
4807 * audio' only. If there is any audio extension block and supported
4808 * audio format, assume at least 'basic audio' support, even if 'basic
4809 * audio' is not defined in EDID.
4810 *
4811 * Return: True if the monitor supports audio, false otherwise.
4812 */
drm_detect_monitor_audio(struct edid * edid)4813 bool drm_detect_monitor_audio(struct edid *edid)
4814 {
4815 u8 *edid_ext;
4816 int i, j;
4817 bool has_audio = false;
4818 int start_offset, end_offset;
4819
4820 edid_ext = drm_find_cea_extension(edid);
4821 if (!edid_ext)
4822 goto end;
4823
4824 has_audio = (edid_ext[0] == CEA_EXT &&
4825 (edid_ext[3] & EDID_BASIC_AUDIO) != 0);
4826
4827 if (has_audio) {
4828 DRM_DEBUG_KMS("Monitor has basic audio support\n");
4829 goto end;
4830 }
4831
4832 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
4833 goto end;
4834
4835 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
4836 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) {
4837 has_audio = true;
4838 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3)
4839 DRM_DEBUG_KMS("CEA audio format %d\n",
4840 (edid_ext[i + j] >> 3) & 0xf);
4841 goto end;
4842 }
4843 }
4844 end:
4845 return has_audio;
4846 }
4847 EXPORT_SYMBOL(drm_detect_monitor_audio);
4848
4849
4850 /**
4851 * drm_default_rgb_quant_range - default RGB quantization range
4852 * @mode: display mode
4853 *
4854 * Determine the default RGB quantization range for the mode,
4855 * as specified in CEA-861.
4856 *
4857 * Return: The default RGB quantization range for the mode
4858 */
4859 enum hdmi_quantization_range
drm_default_rgb_quant_range(const struct drm_display_mode * mode)4860 drm_default_rgb_quant_range(const struct drm_display_mode *mode)
4861 {
4862 /* All CEA modes other than VIC 1 use limited quantization range. */
4863 return drm_match_cea_mode(mode) > 1 ?
4864 HDMI_QUANTIZATION_RANGE_LIMITED :
4865 HDMI_QUANTIZATION_RANGE_FULL;
4866 }
4867 EXPORT_SYMBOL(drm_default_rgb_quant_range);
4868
drm_parse_vcdb(struct drm_connector * connector,const u8 * db)4869 static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db)
4870 {
4871 struct drm_display_info *info = &connector->display_info;
4872
4873 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", db[2]);
4874
4875 if (db[2] & EDID_CEA_VCDB_QS)
4876 info->rgb_quant_range_selectable = true;
4877 }
4878
drm_parse_ycbcr420_deep_color_info(struct drm_connector * connector,const u8 * db)4879 static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector,
4880 const u8 *db)
4881 {
4882 u8 dc_mask;
4883 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
4884
4885 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK;
4886 hdmi->y420_dc_modes = dc_mask;
4887 }
4888
drm_parse_hdmi_forum_vsdb(struct drm_connector * connector,const u8 * hf_vsdb)4889 static void drm_parse_hdmi_forum_vsdb(struct drm_connector *connector,
4890 const u8 *hf_vsdb)
4891 {
4892 struct drm_display_info *display = &connector->display_info;
4893 struct drm_hdmi_info *hdmi = &display->hdmi;
4894
4895 display->has_hdmi_infoframe = true;
4896
4897 if (hf_vsdb[6] & 0x80) {
4898 hdmi->scdc.supported = true;
4899 if (hf_vsdb[6] & 0x40)
4900 hdmi->scdc.read_request = true;
4901 }
4902
4903 /*
4904 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz.
4905 * And as per the spec, three factors confirm this:
4906 * * Availability of a HF-VSDB block in EDID (check)
4907 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check)
4908 * * SCDC support available (let's check)
4909 * Lets check it out.
4910 */
4911
4912 if (hf_vsdb[5]) {
4913 /* max clock is 5000 KHz times block value */
4914 u32 max_tmds_clock = hf_vsdb[5] * 5000;
4915 struct drm_scdc *scdc = &hdmi->scdc;
4916
4917 if (max_tmds_clock > 340000) {
4918 display->max_tmds_clock = max_tmds_clock;
4919 DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n",
4920 display->max_tmds_clock);
4921 }
4922
4923 if (scdc->supported) {
4924 scdc->scrambling.supported = true;
4925
4926 /* Few sinks support scrambling for clocks < 340M */
4927 if ((hf_vsdb[6] & 0x8))
4928 scdc->scrambling.low_rates = true;
4929 }
4930 }
4931
4932 drm_parse_ycbcr420_deep_color_info(connector, hf_vsdb);
4933 }
4934
drm_parse_hdmi_deep_color_info(struct drm_connector * connector,const u8 * hdmi)4935 static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector,
4936 const u8 *hdmi)
4937 {
4938 struct drm_display_info *info = &connector->display_info;
4939 unsigned int dc_bpc = 0;
4940
4941 /* HDMI supports at least 8 bpc */
4942 info->bpc = 8;
4943
4944 if (cea_db_payload_len(hdmi) < 6)
4945 return;
4946
4947 if (hdmi[6] & DRM_EDID_HDMI_DC_30) {
4948 dc_bpc = 10;
4949 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30;
4950 DRM_DEBUG("%s: HDMI sink does deep color 30.\n",
4951 connector->name);
4952 }
4953
4954 if (hdmi[6] & DRM_EDID_HDMI_DC_36) {
4955 dc_bpc = 12;
4956 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36;
4957 DRM_DEBUG("%s: HDMI sink does deep color 36.\n",
4958 connector->name);
4959 }
4960
4961 if (hdmi[6] & DRM_EDID_HDMI_DC_48) {
4962 dc_bpc = 16;
4963 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48;
4964 DRM_DEBUG("%s: HDMI sink does deep color 48.\n",
4965 connector->name);
4966 }
4967
4968 if (dc_bpc == 0) {
4969 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n",
4970 connector->name);
4971 return;
4972 }
4973
4974 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n",
4975 connector->name, dc_bpc);
4976 info->bpc = dc_bpc;
4977
4978 /* YCRCB444 is optional according to spec. */
4979 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) {
4980 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n",
4981 connector->name);
4982 }
4983
4984 /*
4985 * Spec says that if any deep color mode is supported at all,
4986 * then deep color 36 bit must be supported.
4987 */
4988 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) {
4989 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n",
4990 connector->name);
4991 }
4992 }
4993
4994 static void
drm_parse_hdmi_vsdb_video(struct drm_connector * connector,const u8 * db)4995 drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db)
4996 {
4997 struct drm_display_info *info = &connector->display_info;
4998 u8 len = cea_db_payload_len(db);
4999
5000 info->is_hdmi = true;
5001
5002 if (len >= 6)
5003 info->dvi_dual = db[6] & 1;
5004 if (len >= 7)
5005 info->max_tmds_clock = db[7] * 5000;
5006
5007 DRM_DEBUG_KMS("HDMI: DVI dual %d, "
5008 "max TMDS clock %d kHz\n",
5009 info->dvi_dual,
5010 info->max_tmds_clock);
5011
5012 drm_parse_hdmi_deep_color_info(connector, db);
5013 }
5014
drm_parse_cea_ext(struct drm_connector * connector,const struct edid * edid)5015 static void drm_parse_cea_ext(struct drm_connector *connector,
5016 const struct edid *edid)
5017 {
5018 struct drm_display_info *info = &connector->display_info;
5019 const u8 *edid_ext;
5020 int i, start, end;
5021
5022 edid_ext = drm_find_cea_extension(edid);
5023 if (!edid_ext)
5024 return;
5025
5026 info->cea_rev = edid_ext[1];
5027
5028 /* The existence of a CEA block should imply RGB support */
5029 info->color_formats = DRM_COLOR_FORMAT_RGB444;
5030 if (edid_ext[3] & EDID_CEA_YCRCB444)
5031 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
5032 if (edid_ext[3] & EDID_CEA_YCRCB422)
5033 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
5034
5035 if (cea_db_offsets(edid_ext, &start, &end))
5036 return;
5037
5038 for_each_cea_db(edid_ext, i, start, end) {
5039 const u8 *db = &edid_ext[i];
5040
5041 if (cea_db_is_hdmi_vsdb(db))
5042 drm_parse_hdmi_vsdb_video(connector, db);
5043 if (cea_db_is_hdmi_forum_vsdb(db) ||
5044 cea_db_is_hdmi_forum_scdb(db))
5045 drm_parse_hdmi_forum_vsdb(connector, db);
5046 if (cea_db_is_y420cmdb(db))
5047 drm_parse_y420cmdb_bitmap(connector, db);
5048 if (cea_db_is_vcdb(db))
5049 drm_parse_vcdb(connector, db);
5050 if (cea_db_is_hdmi_hdr_metadata_block(db))
5051 drm_parse_hdr_metadata_block(connector, db);
5052 }
5053 }
5054
5055 static
get_monitor_range(struct detailed_timing * timing,void * info_monitor_range)5056 void get_monitor_range(struct detailed_timing *timing,
5057 void *info_monitor_range)
5058 {
5059 struct drm_monitor_range_info *monitor_range = info_monitor_range;
5060 const struct detailed_non_pixel *data = &timing->data.other_data;
5061 const struct detailed_data_monitor_range *range = &data->data.range;
5062
5063 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_MONITOR_RANGE))
5064 return;
5065
5066 /*
5067 * Check for flag range limits only. If flag == 1 then
5068 * no additional timing information provided.
5069 * Default GTF, GTF Secondary curve and CVT are not
5070 * supported
5071 */
5072 if (range->flags != DRM_EDID_RANGE_LIMITS_ONLY_FLAG)
5073 return;
5074
5075 monitor_range->min_vfreq = range->min_vfreq;
5076 monitor_range->max_vfreq = range->max_vfreq;
5077 }
5078
5079 static
drm_get_monitor_range(struct drm_connector * connector,const struct edid * edid)5080 void drm_get_monitor_range(struct drm_connector *connector,
5081 const struct edid *edid)
5082 {
5083 struct drm_display_info *info = &connector->display_info;
5084
5085 if (!version_greater(edid, 1, 1))
5086 return;
5087
5088 drm_for_each_detailed_block((u8 *)edid, get_monitor_range,
5089 &info->monitor_range);
5090
5091 DRM_DEBUG_KMS("Supported Monitor Refresh rate range is %d Hz - %d Hz\n",
5092 info->monitor_range.min_vfreq,
5093 info->monitor_range.max_vfreq);
5094 }
5095
5096 /* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset
5097 * all of the values which would have been set from EDID
5098 */
5099 void
drm_reset_display_info(struct drm_connector * connector)5100 drm_reset_display_info(struct drm_connector *connector)
5101 {
5102 struct drm_display_info *info = &connector->display_info;
5103
5104 info->width_mm = 0;
5105 info->height_mm = 0;
5106
5107 info->bpc = 0;
5108 info->color_formats = 0;
5109 info->cea_rev = 0;
5110 info->max_tmds_clock = 0;
5111 info->dvi_dual = false;
5112 info->is_hdmi = false;
5113 info->has_hdmi_infoframe = false;
5114 info->rgb_quant_range_selectable = false;
5115 memset(&info->hdmi, 0, sizeof(info->hdmi));
5116
5117 info->non_desktop = 0;
5118 memset(&info->monitor_range, 0, sizeof(info->monitor_range));
5119 }
5120
drm_add_display_info(struct drm_connector * connector,const struct edid * edid)5121 u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edid)
5122 {
5123 struct drm_display_info *info = &connector->display_info;
5124
5125 u32 quirks = edid_get_quirks(edid);
5126
5127 drm_reset_display_info(connector);
5128
5129 info->width_mm = edid->width_cm * 10;
5130 info->height_mm = edid->height_cm * 10;
5131
5132 info->non_desktop = !!(quirks & EDID_QUIRK_NON_DESKTOP);
5133
5134 drm_get_monitor_range(connector, edid);
5135
5136 DRM_DEBUG_KMS("non_desktop set to %d\n", info->non_desktop);
5137
5138 if (edid->revision < 3)
5139 return quirks;
5140
5141 if (!(edid->input & DRM_EDID_INPUT_DIGITAL))
5142 return quirks;
5143
5144 info->color_formats |= DRM_COLOR_FORMAT_RGB444;
5145 drm_parse_cea_ext(connector, edid);
5146
5147 /*
5148 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3?
5149 *
5150 * For such displays, the DFP spec 1.0, section 3.10 "EDID support"
5151 * tells us to assume 8 bpc color depth if the EDID doesn't have
5152 * extensions which tell otherwise.
5153 */
5154 if (info->bpc == 0 && edid->revision == 3 &&
5155 edid->input & DRM_EDID_DIGITAL_DFP_1_X) {
5156 info->bpc = 8;
5157 DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n",
5158 connector->name, info->bpc);
5159 }
5160
5161 /* Only defined for 1.4 with digital displays */
5162 if (edid->revision < 4)
5163 return quirks;
5164
5165 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) {
5166 case DRM_EDID_DIGITAL_DEPTH_6:
5167 info->bpc = 6;
5168 break;
5169 case DRM_EDID_DIGITAL_DEPTH_8:
5170 info->bpc = 8;
5171 break;
5172 case DRM_EDID_DIGITAL_DEPTH_10:
5173 info->bpc = 10;
5174 break;
5175 case DRM_EDID_DIGITAL_DEPTH_12:
5176 info->bpc = 12;
5177 break;
5178 case DRM_EDID_DIGITAL_DEPTH_14:
5179 info->bpc = 14;
5180 break;
5181 case DRM_EDID_DIGITAL_DEPTH_16:
5182 info->bpc = 16;
5183 break;
5184 case DRM_EDID_DIGITAL_DEPTH_UNDEF:
5185 default:
5186 info->bpc = 0;
5187 break;
5188 }
5189
5190 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n",
5191 connector->name, info->bpc);
5192
5193 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444)
5194 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
5195 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
5196 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
5197 return quirks;
5198 }
5199
validate_displayid(u8 * displayid,int length,int idx)5200 static int validate_displayid(u8 *displayid, int length, int idx)
5201 {
5202 int i, dispid_length;
5203 u8 csum = 0;
5204 struct displayid_hdr *base;
5205
5206 base = (struct displayid_hdr *)&displayid[idx];
5207
5208 DRM_DEBUG_KMS("base revision 0x%x, length %d, %d %d\n",
5209 base->rev, base->bytes, base->prod_id, base->ext_count);
5210
5211 /* +1 for DispID checksum */
5212 dispid_length = sizeof(*base) + base->bytes + 1;
5213 if (dispid_length > length - idx)
5214 return -EINVAL;
5215
5216 for (i = 0; i < dispid_length; i++)
5217 csum += displayid[idx + i];
5218 if (csum) {
5219 DRM_NOTE("DisplayID checksum invalid, remainder is %d\n", csum);
5220 return -EINVAL;
5221 }
5222
5223 return 0;
5224 }
5225
drm_mode_displayid_detailed(struct drm_device * dev,struct displayid_detailed_timings_1 * timings)5226 static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev,
5227 struct displayid_detailed_timings_1 *timings)
5228 {
5229 struct drm_display_mode *mode;
5230 unsigned pixel_clock = (timings->pixel_clock[0] |
5231 (timings->pixel_clock[1] << 8) |
5232 (timings->pixel_clock[2] << 16)) + 1;
5233 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1;
5234 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1;
5235 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1;
5236 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1;
5237 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1;
5238 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1;
5239 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1;
5240 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1;
5241 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1;
5242 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1;
5243
5244 mode = drm_mode_create(dev);
5245 if (!mode)
5246 return NULL;
5247
5248 mode->clock = pixel_clock * 10;
5249 mode->hdisplay = hactive;
5250 mode->hsync_start = mode->hdisplay + hsync;
5251 mode->hsync_end = mode->hsync_start + hsync_width;
5252 mode->htotal = mode->hdisplay + hblank;
5253
5254 mode->vdisplay = vactive;
5255 mode->vsync_start = mode->vdisplay + vsync;
5256 mode->vsync_end = mode->vsync_start + vsync_width;
5257 mode->vtotal = mode->vdisplay + vblank;
5258
5259 mode->flags = 0;
5260 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
5261 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
5262 mode->type = DRM_MODE_TYPE_DRIVER;
5263
5264 if (timings->flags & 0x80)
5265 mode->type |= DRM_MODE_TYPE_PREFERRED;
5266 drm_mode_set_name(mode);
5267
5268 return mode;
5269 }
5270
add_displayid_detailed_1_modes(struct drm_connector * connector,struct displayid_block * block)5271 static int add_displayid_detailed_1_modes(struct drm_connector *connector,
5272 struct displayid_block *block)
5273 {
5274 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block;
5275 int i;
5276 int num_timings;
5277 struct drm_display_mode *newmode;
5278 int num_modes = 0;
5279 /* blocks must be multiple of 20 bytes length */
5280 if (block->num_bytes % 20)
5281 return 0;
5282
5283 num_timings = block->num_bytes / 20;
5284 for (i = 0; i < num_timings; i++) {
5285 struct displayid_detailed_timings_1 *timings = &det->timings[i];
5286
5287 newmode = drm_mode_displayid_detailed(connector->dev, timings);
5288 if (!newmode)
5289 continue;
5290
5291 drm_mode_probed_add(connector, newmode);
5292 num_modes++;
5293 }
5294 return num_modes;
5295 }
5296
add_displayid_detailed_modes(struct drm_connector * connector,struct edid * edid)5297 static int add_displayid_detailed_modes(struct drm_connector *connector,
5298 struct edid *edid)
5299 {
5300 u8 *displayid;
5301 int length, idx;
5302 struct displayid_block *block;
5303 int num_modes = 0;
5304 int ext_index = 0;
5305
5306 for (;;) {
5307 displayid = drm_find_displayid_extension(edid, &length, &idx,
5308 &ext_index);
5309 if (!displayid)
5310 break;
5311
5312 idx += sizeof(struct displayid_hdr);
5313 for_each_displayid_db(displayid, block, idx, length) {
5314 switch (block->tag) {
5315 case DATA_BLOCK_TYPE_1_DETAILED_TIMING:
5316 num_modes += add_displayid_detailed_1_modes(connector, block);
5317 break;
5318 }
5319 }
5320 }
5321
5322 return num_modes;
5323 }
5324
5325 /**
5326 * drm_add_edid_modes - add modes from EDID data, if available
5327 * @connector: connector we're probing
5328 * @edid: EDID data
5329 *
5330 * Add the specified modes to the connector's mode list. Also fills out the
5331 * &drm_display_info structure and ELD in @connector with any information which
5332 * can be derived from the edid.
5333 *
5334 * Return: The number of modes added or 0 if we couldn't find any.
5335 */
drm_add_edid_modes(struct drm_connector * connector,struct edid * edid)5336 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
5337 {
5338 int num_modes = 0;
5339 u32 quirks;
5340
5341 if (edid == NULL) {
5342 clear_eld(connector);
5343 return 0;
5344 }
5345 if (!drm_edid_is_valid(edid)) {
5346 clear_eld(connector);
5347 drm_warn(connector->dev, "%s: EDID invalid.\n",
5348 connector->name);
5349 return 0;
5350 }
5351
5352 drm_edid_to_eld(connector, edid);
5353
5354 /*
5355 * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks.
5356 * To avoid multiple parsing of same block, lets parse that map
5357 * from sink info, before parsing CEA modes.
5358 */
5359 quirks = drm_add_display_info(connector, edid);
5360
5361 /*
5362 * EDID spec says modes should be preferred in this order:
5363 * - preferred detailed mode
5364 * - other detailed modes from base block
5365 * - detailed modes from extension blocks
5366 * - CVT 3-byte code modes
5367 * - standard timing codes
5368 * - established timing codes
5369 * - modes inferred from GTF or CVT range information
5370 *
5371 * We get this pretty much right.
5372 *
5373 * XXX order for additional mode types in extension blocks?
5374 */
5375 num_modes += add_detailed_modes(connector, edid, quirks);
5376 num_modes += add_cvt_modes(connector, edid);
5377 num_modes += add_standard_modes(connector, edid);
5378 num_modes += add_established_modes(connector, edid);
5379 num_modes += add_cea_modes(connector, edid);
5380 num_modes += add_alternate_cea_modes(connector, edid);
5381 num_modes += add_displayid_detailed_modes(connector, edid);
5382 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
5383 num_modes += add_inferred_modes(connector, edid);
5384
5385 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
5386 edid_fixup_preferred(connector, quirks);
5387
5388 if (quirks & EDID_QUIRK_FORCE_6BPC)
5389 connector->display_info.bpc = 6;
5390
5391 if (quirks & EDID_QUIRK_FORCE_8BPC)
5392 connector->display_info.bpc = 8;
5393
5394 if (quirks & EDID_QUIRK_FORCE_10BPC)
5395 connector->display_info.bpc = 10;
5396
5397 if (quirks & EDID_QUIRK_FORCE_12BPC)
5398 connector->display_info.bpc = 12;
5399
5400 return num_modes;
5401 }
5402 EXPORT_SYMBOL(drm_add_edid_modes);
5403
5404 /**
5405 * drm_add_modes_noedid - add modes for the connectors without EDID
5406 * @connector: connector we're probing
5407 * @hdisplay: the horizontal display limit
5408 * @vdisplay: the vertical display limit
5409 *
5410 * Add the specified modes to the connector's mode list. Only when the
5411 * hdisplay/vdisplay is not beyond the given limit, it will be added.
5412 *
5413 * Return: The number of modes added or 0 if we couldn't find any.
5414 */
drm_add_modes_noedid(struct drm_connector * connector,int hdisplay,int vdisplay)5415 int drm_add_modes_noedid(struct drm_connector *connector,
5416 int hdisplay, int vdisplay)
5417 {
5418 int i, count, num_modes = 0;
5419 struct drm_display_mode *mode;
5420 struct drm_device *dev = connector->dev;
5421
5422 count = ARRAY_SIZE(drm_dmt_modes);
5423 if (hdisplay < 0)
5424 hdisplay = 0;
5425 if (vdisplay < 0)
5426 vdisplay = 0;
5427
5428 for (i = 0; i < count; i++) {
5429 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
5430
5431 if (hdisplay && vdisplay) {
5432 /*
5433 * Only when two are valid, they will be used to check
5434 * whether the mode should be added to the mode list of
5435 * the connector.
5436 */
5437 if (ptr->hdisplay > hdisplay ||
5438 ptr->vdisplay > vdisplay)
5439 continue;
5440 }
5441 if (drm_mode_vrefresh(ptr) > 61)
5442 continue;
5443 mode = drm_mode_duplicate(dev, ptr);
5444 if (mode) {
5445 drm_mode_probed_add(connector, mode);
5446 num_modes++;
5447 }
5448 }
5449 return num_modes;
5450 }
5451 EXPORT_SYMBOL(drm_add_modes_noedid);
5452
5453 /**
5454 * drm_set_preferred_mode - Sets the preferred mode of a connector
5455 * @connector: connector whose mode list should be processed
5456 * @hpref: horizontal resolution of preferred mode
5457 * @vpref: vertical resolution of preferred mode
5458 *
5459 * Marks a mode as preferred if it matches the resolution specified by @hpref
5460 * and @vpref.
5461 */
drm_set_preferred_mode(struct drm_connector * connector,int hpref,int vpref)5462 void drm_set_preferred_mode(struct drm_connector *connector,
5463 int hpref, int vpref)
5464 {
5465 struct drm_display_mode *mode;
5466
5467 list_for_each_entry(mode, &connector->probed_modes, head) {
5468 if (mode->hdisplay == hpref &&
5469 mode->vdisplay == vpref)
5470 mode->type |= DRM_MODE_TYPE_PREFERRED;
5471 }
5472 }
5473 EXPORT_SYMBOL(drm_set_preferred_mode);
5474
is_hdmi2_sink(const struct drm_connector * connector)5475 static bool is_hdmi2_sink(const struct drm_connector *connector)
5476 {
5477 /*
5478 * FIXME: sil-sii8620 doesn't have a connector around when
5479 * we need one, so we have to be prepared for a NULL connector.
5480 */
5481 if (!connector)
5482 return true;
5483
5484 return connector->display_info.hdmi.scdc.supported ||
5485 connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB420;
5486 }
5487
is_eotf_supported(u8 output_eotf,u8 sink_eotf)5488 static inline bool is_eotf_supported(u8 output_eotf, u8 sink_eotf)
5489 {
5490 return sink_eotf & BIT(output_eotf);
5491 }
5492
5493 /**
5494 * drm_hdmi_infoframe_set_hdr_metadata() - fill an HDMI DRM infoframe with
5495 * HDR metadata from userspace
5496 * @frame: HDMI DRM infoframe
5497 * @conn_state: Connector state containing HDR metadata
5498 *
5499 * Return: 0 on success or a negative error code on failure.
5500 */
5501 int
drm_hdmi_infoframe_set_hdr_metadata(struct hdmi_drm_infoframe * frame,const struct drm_connector_state * conn_state)5502 drm_hdmi_infoframe_set_hdr_metadata(struct hdmi_drm_infoframe *frame,
5503 const struct drm_connector_state *conn_state)
5504 {
5505 struct drm_connector *connector;
5506 struct hdr_output_metadata *hdr_metadata;
5507 int err;
5508
5509 if (!frame || !conn_state)
5510 return -EINVAL;
5511
5512 connector = conn_state->connector;
5513
5514 if (!conn_state->hdr_output_metadata)
5515 return -EINVAL;
5516
5517 hdr_metadata = conn_state->hdr_output_metadata->data;
5518
5519 if (!hdr_metadata || !connector)
5520 return -EINVAL;
5521
5522 /* Sink EOTF is Bit map while infoframe is absolute values */
5523 if (!is_eotf_supported(hdr_metadata->hdmi_metadata_type1.eotf,
5524 connector->hdr_sink_metadata.hdmi_type1.eotf)) {
5525 DRM_DEBUG_KMS("EOTF Not Supported\n");
5526 return -EINVAL;
5527 }
5528
5529 err = hdmi_drm_infoframe_init(frame);
5530 if (err < 0)
5531 return err;
5532
5533 frame->eotf = hdr_metadata->hdmi_metadata_type1.eotf;
5534 frame->metadata_type = hdr_metadata->hdmi_metadata_type1.metadata_type;
5535
5536 BUILD_BUG_ON(sizeof(frame->display_primaries) !=
5537 sizeof(hdr_metadata->hdmi_metadata_type1.display_primaries));
5538 BUILD_BUG_ON(sizeof(frame->white_point) !=
5539 sizeof(hdr_metadata->hdmi_metadata_type1.white_point));
5540
5541 memcpy(&frame->display_primaries,
5542 &hdr_metadata->hdmi_metadata_type1.display_primaries,
5543 sizeof(frame->display_primaries));
5544
5545 memcpy(&frame->white_point,
5546 &hdr_metadata->hdmi_metadata_type1.white_point,
5547 sizeof(frame->white_point));
5548
5549 frame->max_display_mastering_luminance =
5550 hdr_metadata->hdmi_metadata_type1.max_display_mastering_luminance;
5551 frame->min_display_mastering_luminance =
5552 hdr_metadata->hdmi_metadata_type1.min_display_mastering_luminance;
5553 frame->max_fall = hdr_metadata->hdmi_metadata_type1.max_fall;
5554 frame->max_cll = hdr_metadata->hdmi_metadata_type1.max_cll;
5555
5556 return 0;
5557 }
5558 EXPORT_SYMBOL(drm_hdmi_infoframe_set_hdr_metadata);
5559
drm_mode_hdmi_vic(const struct drm_connector * connector,const struct drm_display_mode * mode)5560 static u8 drm_mode_hdmi_vic(const struct drm_connector *connector,
5561 const struct drm_display_mode *mode)
5562 {
5563 bool has_hdmi_infoframe = connector ?
5564 connector->display_info.has_hdmi_infoframe : false;
5565
5566 if (!has_hdmi_infoframe)
5567 return 0;
5568
5569 /* No HDMI VIC when signalling 3D video format */
5570 if (mode->flags & DRM_MODE_FLAG_3D_MASK)
5571 return 0;
5572
5573 return drm_match_hdmi_mode(mode);
5574 }
5575
drm_mode_cea_vic(const struct drm_connector * connector,const struct drm_display_mode * mode)5576 static u8 drm_mode_cea_vic(const struct drm_connector *connector,
5577 const struct drm_display_mode *mode)
5578 {
5579 /*
5580 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes
5581 * we should send its VIC in vendor infoframes, else send the
5582 * VIC in AVI infoframes. Lets check if this mode is present in
5583 * HDMI 1.4b 4K modes
5584 */
5585 if (drm_mode_hdmi_vic(connector, mode))
5586 return 0;
5587
5588 return drm_match_cea_mode(mode);
5589 }
5590
5591 /*
5592 * Avoid sending VICs defined in HDMI 2.0 in AVI infoframes to sinks that
5593 * conform to HDMI 1.4.
5594 *
5595 * HDMI 1.4 (CTA-861-D) VIC range: [1..64]
5596 * HDMI 2.0 (CTA-861-F) VIC range: [1..107]
5597 */
vic_for_avi_infoframe(const struct drm_connector * connector,u8 vic)5598 static u8 vic_for_avi_infoframe(const struct drm_connector *connector, u8 vic)
5599 {
5600 if (!is_hdmi2_sink(connector) && vic > 64)
5601 return 0;
5602
5603 return vic;
5604 }
5605
5606 /**
5607 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with
5608 * data from a DRM display mode
5609 * @frame: HDMI AVI infoframe
5610 * @connector: the connector
5611 * @mode: DRM display mode
5612 *
5613 * Return: 0 on success or a negative error code on failure.
5614 */
5615 int
drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe * frame,const struct drm_connector * connector,const struct drm_display_mode * mode)5616 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
5617 const struct drm_connector *connector,
5618 const struct drm_display_mode *mode)
5619 {
5620 enum hdmi_picture_aspect picture_aspect;
5621 u8 vic, hdmi_vic;
5622
5623 if (!frame || !mode)
5624 return -EINVAL;
5625
5626 hdmi_avi_infoframe_init(frame);
5627
5628 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
5629 frame->pixel_repeat = 1;
5630
5631 vic = drm_mode_cea_vic(connector, mode);
5632 hdmi_vic = drm_mode_hdmi_vic(connector, mode);
5633
5634 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
5635
5636 /*
5637 * As some drivers don't support atomic, we can't use connector state.
5638 * So just initialize the frame with default values, just the same way
5639 * as it's done with other properties here.
5640 */
5641 frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS;
5642 frame->itc = 0;
5643
5644 /*
5645 * Populate picture aspect ratio from either
5646 * user input (if specified) or from the CEA/HDMI mode lists.
5647 */
5648 picture_aspect = mode->picture_aspect_ratio;
5649 if (picture_aspect == HDMI_PICTURE_ASPECT_NONE) {
5650 if (vic)
5651 picture_aspect = drm_get_cea_aspect_ratio(vic);
5652 else if (hdmi_vic)
5653 picture_aspect = drm_get_hdmi_aspect_ratio(hdmi_vic);
5654 }
5655
5656 /*
5657 * The infoframe can't convey anything but none, 4:3
5658 * and 16:9, so if the user has asked for anything else
5659 * we can only satisfy it by specifying the right VIC.
5660 */
5661 if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) {
5662 if (vic) {
5663 if (picture_aspect != drm_get_cea_aspect_ratio(vic))
5664 return -EINVAL;
5665 } else if (hdmi_vic) {
5666 if (picture_aspect != drm_get_hdmi_aspect_ratio(hdmi_vic))
5667 return -EINVAL;
5668 } else {
5669 return -EINVAL;
5670 }
5671
5672 picture_aspect = HDMI_PICTURE_ASPECT_NONE;
5673 }
5674
5675 frame->video_code = vic_for_avi_infoframe(connector, vic);
5676 frame->picture_aspect = picture_aspect;
5677 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
5678 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
5679
5680 return 0;
5681 }
5682 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode);
5683
5684 /* HDMI Colorspace Spec Definitions */
5685 #define FULL_COLORIMETRY_MASK 0x1FF
5686 #define NORMAL_COLORIMETRY_MASK 0x3
5687 #define EXTENDED_COLORIMETRY_MASK 0x7
5688 #define EXTENDED_ACE_COLORIMETRY_MASK 0xF
5689
5690 #define C(x) ((x) << 0)
5691 #define EC(x) ((x) << 2)
5692 #define ACE(x) ((x) << 5)
5693
5694 #define HDMI_COLORIMETRY_NO_DATA 0x0
5695 #define HDMI_COLORIMETRY_SMPTE_170M_YCC (C(1) | EC(0) | ACE(0))
5696 #define HDMI_COLORIMETRY_BT709_YCC (C(2) | EC(0) | ACE(0))
5697 #define HDMI_COLORIMETRY_XVYCC_601 (C(3) | EC(0) | ACE(0))
5698 #define HDMI_COLORIMETRY_XVYCC_709 (C(3) | EC(1) | ACE(0))
5699 #define HDMI_COLORIMETRY_SYCC_601 (C(3) | EC(2) | ACE(0))
5700 #define HDMI_COLORIMETRY_OPYCC_601 (C(3) | EC(3) | ACE(0))
5701 #define HDMI_COLORIMETRY_OPRGB (C(3) | EC(4) | ACE(0))
5702 #define HDMI_COLORIMETRY_BT2020_CYCC (C(3) | EC(5) | ACE(0))
5703 #define HDMI_COLORIMETRY_BT2020_RGB (C(3) | EC(6) | ACE(0))
5704 #define HDMI_COLORIMETRY_BT2020_YCC (C(3) | EC(6) | ACE(0))
5705 #define HDMI_COLORIMETRY_DCI_P3_RGB_D65 (C(3) | EC(7) | ACE(0))
5706 #define HDMI_COLORIMETRY_DCI_P3_RGB_THEATER (C(3) | EC(7) | ACE(1))
5707
5708 static const u32 hdmi_colorimetry_val[] = {
5709 [DRM_MODE_COLORIMETRY_NO_DATA] = HDMI_COLORIMETRY_NO_DATA,
5710 [DRM_MODE_COLORIMETRY_SMPTE_170M_YCC] = HDMI_COLORIMETRY_SMPTE_170M_YCC,
5711 [DRM_MODE_COLORIMETRY_BT709_YCC] = HDMI_COLORIMETRY_BT709_YCC,
5712 [DRM_MODE_COLORIMETRY_XVYCC_601] = HDMI_COLORIMETRY_XVYCC_601,
5713 [DRM_MODE_COLORIMETRY_XVYCC_709] = HDMI_COLORIMETRY_XVYCC_709,
5714 [DRM_MODE_COLORIMETRY_SYCC_601] = HDMI_COLORIMETRY_SYCC_601,
5715 [DRM_MODE_COLORIMETRY_OPYCC_601] = HDMI_COLORIMETRY_OPYCC_601,
5716 [DRM_MODE_COLORIMETRY_OPRGB] = HDMI_COLORIMETRY_OPRGB,
5717 [DRM_MODE_COLORIMETRY_BT2020_CYCC] = HDMI_COLORIMETRY_BT2020_CYCC,
5718 [DRM_MODE_COLORIMETRY_BT2020_RGB] = HDMI_COLORIMETRY_BT2020_RGB,
5719 [DRM_MODE_COLORIMETRY_BT2020_YCC] = HDMI_COLORIMETRY_BT2020_YCC,
5720 };
5721
5722 #undef C
5723 #undef EC
5724 #undef ACE
5725
5726 /**
5727 * drm_hdmi_avi_infoframe_colorspace() - fill the HDMI AVI infoframe
5728 * colorspace information
5729 * @frame: HDMI AVI infoframe
5730 * @conn_state: connector state
5731 */
5732 void
drm_hdmi_avi_infoframe_colorspace(struct hdmi_avi_infoframe * frame,const struct drm_connector_state * conn_state)5733 drm_hdmi_avi_infoframe_colorspace(struct hdmi_avi_infoframe *frame,
5734 const struct drm_connector_state *conn_state)
5735 {
5736 u32 colorimetry_val;
5737 u32 colorimetry_index = conn_state->colorspace & FULL_COLORIMETRY_MASK;
5738
5739 if (colorimetry_index >= ARRAY_SIZE(hdmi_colorimetry_val))
5740 colorimetry_val = HDMI_COLORIMETRY_NO_DATA;
5741 else
5742 colorimetry_val = hdmi_colorimetry_val[colorimetry_index];
5743
5744 frame->colorimetry = colorimetry_val & NORMAL_COLORIMETRY_MASK;
5745 /*
5746 * ToDo: Extend it for ACE formats as well. Modify the infoframe
5747 * structure and extend it in drivers/video/hdmi
5748 */
5749 frame->extended_colorimetry = (colorimetry_val >> 2) &
5750 EXTENDED_COLORIMETRY_MASK;
5751 }
5752 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_colorspace);
5753
5754 /**
5755 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe
5756 * quantization range information
5757 * @frame: HDMI AVI infoframe
5758 * @connector: the connector
5759 * @mode: DRM display mode
5760 * @rgb_quant_range: RGB quantization range (Q)
5761 */
5762 void
drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe * frame,const struct drm_connector * connector,const struct drm_display_mode * mode,enum hdmi_quantization_range rgb_quant_range)5763 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame,
5764 const struct drm_connector *connector,
5765 const struct drm_display_mode *mode,
5766 enum hdmi_quantization_range rgb_quant_range)
5767 {
5768 const struct drm_display_info *info = &connector->display_info;
5769
5770 /*
5771 * CEA-861:
5772 * "A Source shall not send a non-zero Q value that does not correspond
5773 * to the default RGB Quantization Range for the transmitted Picture
5774 * unless the Sink indicates support for the Q bit in a Video
5775 * Capabilities Data Block."
5776 *
5777 * HDMI 2.0 recommends sending non-zero Q when it does match the
5778 * default RGB quantization range for the mode, even when QS=0.
5779 */
5780 if (info->rgb_quant_range_selectable ||
5781 rgb_quant_range == drm_default_rgb_quant_range(mode))
5782 frame->quantization_range = rgb_quant_range;
5783 else
5784 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
5785
5786 /*
5787 * CEA-861-F:
5788 * "When transmitting any RGB colorimetry, the Source should set the
5789 * YQ-field to match the RGB Quantization Range being transmitted
5790 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB,
5791 * set YQ=1) and the Sink shall ignore the YQ-field."
5792 *
5793 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused
5794 * by non-zero YQ when receiving RGB. There doesn't seem to be any
5795 * good way to tell which version of CEA-861 the sink supports, so
5796 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based
5797 * on on CEA-861-F.
5798 */
5799 if (!is_hdmi2_sink(connector) ||
5800 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED)
5801 frame->ycc_quantization_range =
5802 HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
5803 else
5804 frame->ycc_quantization_range =
5805 HDMI_YCC_QUANTIZATION_RANGE_FULL;
5806 }
5807 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range);
5808
5809 /**
5810 * drm_hdmi_avi_infoframe_bars() - fill the HDMI AVI infoframe
5811 * bar information
5812 * @frame: HDMI AVI infoframe
5813 * @conn_state: connector state
5814 */
5815 void
drm_hdmi_avi_infoframe_bars(struct hdmi_avi_infoframe * frame,const struct drm_connector_state * conn_state)5816 drm_hdmi_avi_infoframe_bars(struct hdmi_avi_infoframe *frame,
5817 const struct drm_connector_state *conn_state)
5818 {
5819 frame->right_bar = conn_state->tv.margins.right;
5820 frame->left_bar = conn_state->tv.margins.left;
5821 frame->top_bar = conn_state->tv.margins.top;
5822 frame->bottom_bar = conn_state->tv.margins.bottom;
5823 }
5824 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_bars);
5825
5826 static enum hdmi_3d_structure
s3d_structure_from_display_mode(const struct drm_display_mode * mode)5827 s3d_structure_from_display_mode(const struct drm_display_mode *mode)
5828 {
5829 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK;
5830
5831 switch (layout) {
5832 case DRM_MODE_FLAG_3D_FRAME_PACKING:
5833 return HDMI_3D_STRUCTURE_FRAME_PACKING;
5834 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE:
5835 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE;
5836 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE:
5837 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE;
5838 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL:
5839 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL;
5840 case DRM_MODE_FLAG_3D_L_DEPTH:
5841 return HDMI_3D_STRUCTURE_L_DEPTH;
5842 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH:
5843 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH;
5844 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM:
5845 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM;
5846 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF:
5847 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF;
5848 default:
5849 return HDMI_3D_STRUCTURE_INVALID;
5850 }
5851 }
5852
5853 /**
5854 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with
5855 * data from a DRM display mode
5856 * @frame: HDMI vendor infoframe
5857 * @connector: the connector
5858 * @mode: DRM display mode
5859 *
5860 * Note that there's is a need to send HDMI vendor infoframes only when using a
5861 * 4k or stereoscopic 3D mode. So when giving any other mode as input this
5862 * function will return -EINVAL, error that can be safely ignored.
5863 *
5864 * Return: 0 on success or a negative error code on failure.
5865 */
5866 int
drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe * frame,const struct drm_connector * connector,const struct drm_display_mode * mode)5867 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
5868 const struct drm_connector *connector,
5869 const struct drm_display_mode *mode)
5870 {
5871 /*
5872 * FIXME: sil-sii8620 doesn't have a connector around when
5873 * we need one, so we have to be prepared for a NULL connector.
5874 */
5875 bool has_hdmi_infoframe = connector ?
5876 connector->display_info.has_hdmi_infoframe : false;
5877 int err;
5878
5879 if (!frame || !mode)
5880 return -EINVAL;
5881
5882 if (!has_hdmi_infoframe)
5883 return -EINVAL;
5884
5885 err = hdmi_vendor_infoframe_init(frame);
5886 if (err < 0)
5887 return err;
5888
5889 /*
5890 * Even if it's not absolutely necessary to send the infoframe
5891 * (ie.vic==0 and s3d_struct==0) we will still send it if we
5892 * know that the sink can handle it. This is based on a
5893 * suggestion in HDMI 2.0 Appendix F. Apparently some sinks
5894 * have trouble realizing that they shuld switch from 3D to 2D
5895 * mode if the source simply stops sending the infoframe when
5896 * it wants to switch from 3D to 2D.
5897 */
5898 frame->vic = drm_mode_hdmi_vic(connector, mode);
5899 frame->s3d_struct = s3d_structure_from_display_mode(mode);
5900
5901 return 0;
5902 }
5903 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode);
5904
drm_parse_tiled_block(struct drm_connector * connector,const struct displayid_block * block)5905 static void drm_parse_tiled_block(struct drm_connector *connector,
5906 const struct displayid_block *block)
5907 {
5908 const struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block;
5909 u16 w, h;
5910 u8 tile_v_loc, tile_h_loc;
5911 u8 num_v_tile, num_h_tile;
5912 struct drm_tile_group *tg;
5913
5914 w = tile->tile_size[0] | tile->tile_size[1] << 8;
5915 h = tile->tile_size[2] | tile->tile_size[3] << 8;
5916
5917 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30);
5918 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30);
5919 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4);
5920 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4);
5921
5922 connector->has_tile = true;
5923 if (tile->tile_cap & 0x80)
5924 connector->tile_is_single_monitor = true;
5925
5926 connector->num_h_tile = num_h_tile + 1;
5927 connector->num_v_tile = num_v_tile + 1;
5928 connector->tile_h_loc = tile_h_loc;
5929 connector->tile_v_loc = tile_v_loc;
5930 connector->tile_h_size = w + 1;
5931 connector->tile_v_size = h + 1;
5932
5933 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap);
5934 DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1);
5935 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n",
5936 num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc);
5937 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]);
5938
5939 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id);
5940 if (!tg)
5941 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id);
5942 if (!tg)
5943 return;
5944
5945 if (connector->tile_group != tg) {
5946 /* if we haven't got a pointer,
5947 take the reference, drop ref to old tile group */
5948 if (connector->tile_group)
5949 drm_mode_put_tile_group(connector->dev, connector->tile_group);
5950 connector->tile_group = tg;
5951 } else {
5952 /* if same tile group, then release the ref we just took. */
5953 drm_mode_put_tile_group(connector->dev, tg);
5954 }
5955 }
5956
drm_displayid_parse_tiled(struct drm_connector * connector,const u8 * displayid,int length,int idx)5957 static void drm_displayid_parse_tiled(struct drm_connector *connector,
5958 const u8 *displayid, int length, int idx)
5959 {
5960 const struct displayid_block *block;
5961
5962 idx += sizeof(struct displayid_hdr);
5963 for_each_displayid_db(displayid, block, idx, length) {
5964 DRM_DEBUG_KMS("block id 0x%x, rev %d, len %d\n",
5965 block->tag, block->rev, block->num_bytes);
5966
5967 switch (block->tag) {
5968 case DATA_BLOCK_TILED_DISPLAY:
5969 drm_parse_tiled_block(connector, block);
5970 break;
5971 default:
5972 DRM_DEBUG_KMS("found DisplayID tag 0x%x, unhandled\n", block->tag);
5973 break;
5974 }
5975 }
5976 }
5977
drm_update_tile_info(struct drm_connector * connector,const struct edid * edid)5978 void drm_update_tile_info(struct drm_connector *connector,
5979 const struct edid *edid)
5980 {
5981 const void *displayid = NULL;
5982 int ext_index = 0;
5983 int length, idx;
5984
5985 connector->has_tile = false;
5986 for (;;) {
5987 displayid = drm_find_displayid_extension(edid, &length, &idx,
5988 &ext_index);
5989 if (!displayid)
5990 break;
5991
5992 drm_displayid_parse_tiled(connector, displayid, length, idx);
5993 }
5994
5995 if (!connector->has_tile && connector->tile_group) {
5996 drm_mode_put_tile_group(connector->dev, connector->tile_group);
5997 connector->tile_group = NULL;
5998 }
5999 }
6000