1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * core.c - DesignWare USB3 DRD Controller Core file
4 *
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
6 *
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 */
10
11 #include <linux/clk.h>
12 #include <linux/version.h>
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/slab.h>
16 #include <linux/spinlock.h>
17 #include <linux/platform_device.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/interrupt.h>
20 #include <linux/ioport.h>
21 #include <linux/io.h>
22 #include <linux/list.h>
23 #include <linux/delay.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/of.h>
26 #include <linux/acpi.h>
27 #include <linux/pinctrl/consumer.h>
28 #include <linux/reset.h>
29
30 #include <linux/usb/ch9.h>
31 #include <linux/usb/gadget.h>
32 #include <linux/usb/of.h>
33 #include <linux/usb/otg.h>
34
35 #include "core.h"
36 #include "gadget.h"
37 #include "io.h"
38
39 #include "debug.h"
40
41 #define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */
42
43 /**
44 * dwc3_get_dr_mode - Validates and sets dr_mode
45 * @dwc: pointer to our context structure
46 */
dwc3_get_dr_mode(struct dwc3 * dwc)47 static int dwc3_get_dr_mode(struct dwc3 *dwc)
48 {
49 enum usb_dr_mode mode;
50 struct device *dev = dwc->dev;
51 unsigned int hw_mode;
52
53 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
54 dwc->dr_mode = USB_DR_MODE_OTG;
55
56 mode = dwc->dr_mode;
57 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
58
59 switch (hw_mode) {
60 case DWC3_GHWPARAMS0_MODE_GADGET:
61 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) {
62 dev_err(dev,
63 "Controller does not support host mode.\n");
64 return -EINVAL;
65 }
66 mode = USB_DR_MODE_PERIPHERAL;
67 break;
68 case DWC3_GHWPARAMS0_MODE_HOST:
69 if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) {
70 dev_err(dev,
71 "Controller does not support device mode.\n");
72 return -EINVAL;
73 }
74 mode = USB_DR_MODE_HOST;
75 break;
76 default:
77 if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
78 mode = USB_DR_MODE_HOST;
79 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
80 mode = USB_DR_MODE_PERIPHERAL;
81
82 /*
83 * DWC_usb31 and DWC_usb3 v3.30a and higher do not support OTG
84 * mode. If the controller supports DRD but the dr_mode is not
85 * specified or set to OTG, then set the mode to peripheral.
86 */
87 if (mode == USB_DR_MODE_OTG &&
88 (!IS_ENABLED(CONFIG_USB_ROLE_SWITCH) ||
89 !device_property_read_bool(dwc->dev, "usb-role-switch")) &&
90 !DWC3_VER_IS_PRIOR(DWC3, 330A))
91 mode = USB_DR_MODE_PERIPHERAL;
92 }
93
94 if (mode != dwc->dr_mode) {
95 dev_warn(dev,
96 "Configuration mismatch. dr_mode forced to %s\n",
97 mode == USB_DR_MODE_HOST ? "host" : "gadget");
98
99 dwc->dr_mode = mode;
100 }
101
102 return 0;
103 }
104
dwc3_set_prtcap(struct dwc3 * dwc,u32 mode)105 void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode)
106 {
107 u32 reg;
108
109 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
110 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
111 reg |= DWC3_GCTL_PRTCAPDIR(mode);
112 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
113
114 dwc->current_dr_role = mode;
115 }
116
__dwc3_set_mode(struct work_struct * work)117 static void __dwc3_set_mode(struct work_struct *work)
118 {
119 struct dwc3 *dwc = work_to_dwc(work);
120 unsigned long flags;
121 int ret;
122 u32 reg;
123 u32 desired_dr_role;
124
125 mutex_lock(&dwc->mutex);
126 spin_lock_irqsave(&dwc->lock, flags);
127 desired_dr_role = dwc->desired_dr_role;
128 spin_unlock_irqrestore(&dwc->lock, flags);
129
130 pm_runtime_get_sync(dwc->dev);
131
132 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_OTG)
133 dwc3_otg_update(dwc, 0);
134
135 if (!desired_dr_role)
136 goto out;
137
138 if (desired_dr_role == dwc->current_dr_role)
139 goto out;
140
141 if (desired_dr_role == DWC3_GCTL_PRTCAP_OTG && dwc->edev)
142 goto out;
143
144 switch (dwc->current_dr_role) {
145 case DWC3_GCTL_PRTCAP_HOST:
146 dwc3_host_exit(dwc);
147 break;
148 case DWC3_GCTL_PRTCAP_DEVICE:
149 dwc3_gadget_exit(dwc);
150 dwc3_event_buffers_cleanup(dwc);
151 break;
152 case DWC3_GCTL_PRTCAP_OTG:
153 dwc3_otg_exit(dwc);
154 spin_lock_irqsave(&dwc->lock, flags);
155 dwc->desired_otg_role = DWC3_OTG_ROLE_IDLE;
156 spin_unlock_irqrestore(&dwc->lock, flags);
157 dwc3_otg_update(dwc, 1);
158 break;
159 default:
160 break;
161 }
162
163 /*
164 * When current_dr_role is not set, there's no role switching.
165 * Only perform GCTL.CoreSoftReset when there's DRD role switching.
166 */
167 if (dwc->current_dr_role && ((DWC3_IP_IS(DWC3) ||
168 DWC3_VER_IS_PRIOR(DWC31, 190A)) &&
169 desired_dr_role != DWC3_GCTL_PRTCAP_OTG)) {
170 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
171 reg |= DWC3_GCTL_CORESOFTRESET;
172 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
173
174 /*
175 * Wait for internal clocks to synchronized. DWC_usb31 and
176 * DWC_usb32 may need at least 50ms (less for DWC_usb3). To
177 * keep it consistent across different IPs, let's wait up to
178 * 100ms before clearing GCTL.CORESOFTRESET.
179 */
180 msleep(100);
181
182 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
183 reg &= ~DWC3_GCTL_CORESOFTRESET;
184 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
185 }
186
187 spin_lock_irqsave(&dwc->lock, flags);
188
189 dwc3_set_prtcap(dwc, desired_dr_role);
190
191 spin_unlock_irqrestore(&dwc->lock, flags);
192
193 switch (desired_dr_role) {
194 case DWC3_GCTL_PRTCAP_HOST:
195 ret = dwc3_host_init(dwc);
196 if (ret) {
197 dev_err(dwc->dev, "failed to initialize host\n");
198 } else {
199 if (dwc->usb2_phy)
200 otg_set_vbus(dwc->usb2_phy->otg, true);
201 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
202 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
203 if (dwc->dis_split_quirk) {
204 reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);
205 reg |= DWC3_GUCTL3_SPLITDISABLE;
206 dwc3_writel(dwc->regs, DWC3_GUCTL3, reg);
207 }
208 }
209 break;
210 case DWC3_GCTL_PRTCAP_DEVICE:
211 dwc3_core_soft_reset(dwc);
212
213 dwc3_event_buffers_setup(dwc);
214
215 if (dwc->usb2_phy)
216 otg_set_vbus(dwc->usb2_phy->otg, false);
217 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
218 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
219
220 ret = dwc3_gadget_init(dwc);
221 if (ret)
222 dev_err(dwc->dev, "failed to initialize peripheral\n");
223 break;
224 case DWC3_GCTL_PRTCAP_OTG:
225 dwc3_otg_init(dwc);
226 dwc3_otg_update(dwc, 0);
227 break;
228 default:
229 break;
230 }
231
232 out:
233 pm_runtime_mark_last_busy(dwc->dev);
234 pm_runtime_put_autosuspend(dwc->dev);
235 mutex_unlock(&dwc->mutex);
236 }
237
dwc3_set_mode(struct dwc3 * dwc,u32 mode)238 void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
239 {
240 unsigned long flags;
241
242 if (dwc->dr_mode != USB_DR_MODE_OTG)
243 return;
244
245 spin_lock_irqsave(&dwc->lock, flags);
246 dwc->desired_dr_role = mode;
247 spin_unlock_irqrestore(&dwc->lock, flags);
248
249 queue_work(system_freezable_wq, &dwc->drd_work);
250 }
251
dwc3_core_fifo_space(struct dwc3_ep * dep,u8 type)252 u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type)
253 {
254 struct dwc3 *dwc = dep->dwc;
255 u32 reg;
256
257 dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE,
258 DWC3_GDBGFIFOSPACE_NUM(dep->number) |
259 DWC3_GDBGFIFOSPACE_TYPE(type));
260
261 reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE);
262
263 return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg);
264 }
265
266 /**
267 * dwc3_core_soft_reset - Issues core soft reset and PHY reset
268 * @dwc: pointer to our context structure
269 */
dwc3_core_soft_reset(struct dwc3 * dwc)270 int dwc3_core_soft_reset(struct dwc3 *dwc)
271 {
272 u32 reg;
273 int retries = 1000;
274
275 /*
276 * We're resetting only the device side because, if we're in host mode,
277 * XHCI driver will reset the host block. If dwc3 was configured for
278 * host-only mode, then we can return early.
279 */
280 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST)
281 return 0;
282
283 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
284 reg |= DWC3_DCTL_CSFTRST;
285 reg &= ~DWC3_DCTL_RUN_STOP;
286 dwc3_gadget_dctl_write_safe(dwc, reg);
287
288 /*
289 * For DWC_usb31 controller 1.90a and later, the DCTL.CSFRST bit
290 * is cleared only after all the clocks are synchronized. This can
291 * take a little more than 50ms. Set the polling rate at 20ms
292 * for 10 times instead.
293 */
294 if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32))
295 retries = 10;
296
297 do {
298 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
299 if (!(reg & DWC3_DCTL_CSFTRST))
300 goto done;
301
302 if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32))
303 msleep(20);
304 else
305 udelay(1);
306 } while (--retries);
307
308 return -ETIMEDOUT;
309
310 done:
311 /*
312 * For DWC_usb31 controller 1.80a and prior, once DCTL.CSFRST bit
313 * is cleared, we must wait at least 50ms before accessing the PHY
314 * domain (synchronization delay).
315 */
316 if (DWC3_VER_IS_WITHIN(DWC31, ANY, 180A))
317 msleep(50);
318
319 return 0;
320 }
321
322 /*
323 * dwc3_frame_length_adjustment - Adjusts frame length if required
324 * @dwc3: Pointer to our controller context structure
325 */
dwc3_frame_length_adjustment(struct dwc3 * dwc)326 static void dwc3_frame_length_adjustment(struct dwc3 *dwc)
327 {
328 u32 reg;
329 u32 dft;
330
331 if (DWC3_VER_IS_PRIOR(DWC3, 250A))
332 return;
333
334 if (dwc->fladj == 0)
335 return;
336
337 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
338 dft = reg & DWC3_GFLADJ_30MHZ_MASK;
339 if (dft != dwc->fladj) {
340 reg &= ~DWC3_GFLADJ_30MHZ_MASK;
341 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj;
342 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
343 }
344 }
345
346 /**
347 * dwc3_free_one_event_buffer - Frees one event buffer
348 * @dwc: Pointer to our controller context structure
349 * @evt: Pointer to event buffer to be freed
350 */
dwc3_free_one_event_buffer(struct dwc3 * dwc,struct dwc3_event_buffer * evt)351 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
352 struct dwc3_event_buffer *evt)
353 {
354 dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma);
355 }
356
357 /**
358 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
359 * @dwc: Pointer to our controller context structure
360 * @length: size of the event buffer
361 *
362 * Returns a pointer to the allocated event buffer structure on success
363 * otherwise ERR_PTR(errno).
364 */
dwc3_alloc_one_event_buffer(struct dwc3 * dwc,unsigned length)365 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
366 unsigned length)
367 {
368 struct dwc3_event_buffer *evt;
369
370 evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
371 if (!evt)
372 return ERR_PTR(-ENOMEM);
373
374 evt->dwc = dwc;
375 evt->length = length;
376 evt->cache = devm_kzalloc(dwc->dev, length, GFP_KERNEL);
377 if (!evt->cache)
378 return ERR_PTR(-ENOMEM);
379
380 evt->buf = dma_alloc_coherent(dwc->sysdev, length,
381 &evt->dma, GFP_KERNEL);
382 if (!evt->buf)
383 return ERR_PTR(-ENOMEM);
384
385 return evt;
386 }
387
388 /**
389 * dwc3_free_event_buffers - frees all allocated event buffers
390 * @dwc: Pointer to our controller context structure
391 */
dwc3_free_event_buffers(struct dwc3 * dwc)392 static void dwc3_free_event_buffers(struct dwc3 *dwc)
393 {
394 struct dwc3_event_buffer *evt;
395
396 evt = dwc->ev_buf;
397 if (evt)
398 dwc3_free_one_event_buffer(dwc, evt);
399 }
400
401 /**
402 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
403 * @dwc: pointer to our controller context structure
404 * @length: size of event buffer
405 *
406 * Returns 0 on success otherwise negative errno. In the error case, dwc
407 * may contain some buffers allocated but not all which were requested.
408 */
dwc3_alloc_event_buffers(struct dwc3 * dwc,unsigned length)409 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
410 {
411 struct dwc3_event_buffer *evt;
412
413 evt = dwc3_alloc_one_event_buffer(dwc, length);
414 if (IS_ERR(evt)) {
415 dev_err(dwc->dev, "can't allocate event buffer\n");
416 return PTR_ERR(evt);
417 }
418 dwc->ev_buf = evt;
419
420 return 0;
421 }
422
423 /**
424 * dwc3_event_buffers_setup - setup our allocated event buffers
425 * @dwc: pointer to our controller context structure
426 *
427 * Returns 0 on success otherwise negative errno.
428 */
dwc3_event_buffers_setup(struct dwc3 * dwc)429 int dwc3_event_buffers_setup(struct dwc3 *dwc)
430 {
431 struct dwc3_event_buffer *evt;
432
433 evt = dwc->ev_buf;
434 evt->lpos = 0;
435 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0),
436 lower_32_bits(evt->dma));
437 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0),
438 upper_32_bits(evt->dma));
439 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
440 DWC3_GEVNTSIZ_SIZE(evt->length));
441 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
442
443 return 0;
444 }
445
dwc3_event_buffers_cleanup(struct dwc3 * dwc)446 void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
447 {
448 struct dwc3_event_buffer *evt;
449
450 evt = dwc->ev_buf;
451
452 evt->lpos = 0;
453
454 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0);
455 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0);
456 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK
457 | DWC3_GEVNTSIZ_SIZE(0));
458 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
459 }
460
dwc3_alloc_scratch_buffers(struct dwc3 * dwc)461 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
462 {
463 if (!dwc->has_hibernation)
464 return 0;
465
466 if (!dwc->nr_scratch)
467 return 0;
468
469 dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
470 DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
471 if (!dwc->scratchbuf)
472 return -ENOMEM;
473
474 return 0;
475 }
476
dwc3_setup_scratch_buffers(struct dwc3 * dwc)477 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
478 {
479 dma_addr_t scratch_addr;
480 u32 param;
481 int ret;
482
483 if (!dwc->has_hibernation)
484 return 0;
485
486 if (!dwc->nr_scratch)
487 return 0;
488
489 /* should never fall here */
490 if (!WARN_ON(dwc->scratchbuf))
491 return 0;
492
493 scratch_addr = dma_map_single(dwc->sysdev, dwc->scratchbuf,
494 dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
495 DMA_BIDIRECTIONAL);
496 if (dma_mapping_error(dwc->sysdev, scratch_addr)) {
497 dev_err(dwc->sysdev, "failed to map scratch buffer\n");
498 ret = -EFAULT;
499 goto err0;
500 }
501
502 dwc->scratch_addr = scratch_addr;
503
504 param = lower_32_bits(scratch_addr);
505
506 ret = dwc3_send_gadget_generic_command(dwc,
507 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
508 if (ret < 0)
509 goto err1;
510
511 param = upper_32_bits(scratch_addr);
512
513 ret = dwc3_send_gadget_generic_command(dwc,
514 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
515 if (ret < 0)
516 goto err1;
517
518 return 0;
519
520 err1:
521 dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
522 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
523
524 err0:
525 return ret;
526 }
527
dwc3_free_scratch_buffers(struct dwc3 * dwc)528 static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
529 {
530 if (!dwc->has_hibernation)
531 return;
532
533 if (!dwc->nr_scratch)
534 return;
535
536 /* should never fall here */
537 if (!WARN_ON(dwc->scratchbuf))
538 return;
539
540 dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
541 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
542 kfree(dwc->scratchbuf);
543 }
544
dwc3_core_num_eps(struct dwc3 * dwc)545 static void dwc3_core_num_eps(struct dwc3 *dwc)
546 {
547 struct dwc3_hwparams *parms = &dwc->hwparams;
548
549 dwc->num_eps = DWC3_NUM_EPS(parms);
550 }
551
dwc3_cache_hwparams(struct dwc3 * dwc)552 static void dwc3_cache_hwparams(struct dwc3 *dwc)
553 {
554 struct dwc3_hwparams *parms = &dwc->hwparams;
555
556 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
557 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
558 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
559 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
560 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
561 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
562 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
563 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
564 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
565
566 if (DWC3_IP_IS(DWC32))
567 parms->hwparams9 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS9);
568 }
569
dwc3_core_ulpi_init(struct dwc3 * dwc)570 static int dwc3_core_ulpi_init(struct dwc3 *dwc)
571 {
572 int intf;
573 int ret = 0;
574
575 intf = DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3);
576
577 if (intf == DWC3_GHWPARAMS3_HSPHY_IFC_ULPI ||
578 (intf == DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI &&
579 dwc->hsphy_interface &&
580 !strncmp(dwc->hsphy_interface, "ulpi", 4)))
581 ret = dwc3_ulpi_init(dwc);
582
583 return ret;
584 }
585
586 /**
587 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
588 * @dwc: Pointer to our controller context structure
589 *
590 * Returns 0 on success. The USB PHY interfaces are configured but not
591 * initialized. The PHY interfaces and the PHYs get initialized together with
592 * the core in dwc3_core_init.
593 */
dwc3_phy_setup(struct dwc3 * dwc)594 static int dwc3_phy_setup(struct dwc3 *dwc)
595 {
596 unsigned int hw_mode;
597 u32 reg;
598
599 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
600
601 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
602
603 /*
604 * Make sure UX_EXIT_PX is cleared as that causes issues with some
605 * PHYs. Also, this bit is not supposed to be used in normal operation.
606 */
607 reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX;
608
609 /*
610 * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
611 * to '0' during coreConsultant configuration. So default value
612 * will be '0' when the core is reset. Application needs to set it
613 * to '1' after the core initialization is completed.
614 */
615 if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A))
616 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
617
618 /*
619 * For DRD controllers, GUSB3PIPECTL.SUSPENDENABLE must be cleared after
620 * power-on reset, and it can be set after core initialization, which is
621 * after device soft-reset during initialization.
622 */
623 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD)
624 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
625
626 if (dwc->u2ss_inp3_quirk)
627 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
628
629 if (dwc->dis_rxdet_inp3_quirk)
630 reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3;
631
632 if (dwc->req_p1p2p3_quirk)
633 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
634
635 if (dwc->del_p1p2p3_quirk)
636 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
637
638 if (dwc->del_phy_power_chg_quirk)
639 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
640
641 if (dwc->lfps_filter_quirk)
642 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
643
644 if (dwc->rx_detect_poll_quirk)
645 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
646
647 if (dwc->tx_de_emphasis_quirk)
648 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
649
650 if (dwc->dis_u3_susphy_quirk)
651 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
652
653 if (dwc->dis_del_phy_power_chg_quirk)
654 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
655
656 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
657
658 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
659
660 /* Select the HS PHY interface */
661 switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
662 case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI:
663 if (dwc->hsphy_interface &&
664 !strncmp(dwc->hsphy_interface, "utmi", 4)) {
665 reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI;
666 break;
667 } else if (dwc->hsphy_interface &&
668 !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
669 reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
670 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
671 } else {
672 /* Relying on default value. */
673 if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
674 break;
675 }
676 fallthrough;
677 case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
678 default:
679 break;
680 }
681
682 switch (dwc->hsphy_mode) {
683 case USBPHY_INTERFACE_MODE_UTMI:
684 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
685 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
686 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
687 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
688 break;
689 case USBPHY_INTERFACE_MODE_UTMIW:
690 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
691 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
692 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
693 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
694 break;
695 default:
696 break;
697 }
698
699 /*
700 * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
701 * '0' during coreConsultant configuration. So default value will
702 * be '0' when the core is reset. Application needs to set it to
703 * '1' after the core initialization is completed.
704 */
705 if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A))
706 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
707
708 /*
709 * For DRD controllers, GUSB2PHYCFG.SUSPHY must be cleared after
710 * power-on reset, and it can be set after core initialization, which is
711 * after device soft-reset during initialization.
712 */
713 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD)
714 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
715
716 if (dwc->dis_u2_susphy_quirk)
717 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
718
719 if (dwc->dis_enblslpm_quirk)
720 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
721 else
722 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM;
723
724 if (dwc->dis_u2_freeclk_exists_quirk)
725 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
726
727 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
728
729 return 0;
730 }
731
dwc3_core_exit(struct dwc3 * dwc)732 static void dwc3_core_exit(struct dwc3 *dwc)
733 {
734 dwc3_event_buffers_cleanup(dwc);
735
736 usb_phy_set_suspend(dwc->usb2_phy, 1);
737 usb_phy_set_suspend(dwc->usb3_phy, 1);
738 phy_power_off(dwc->usb2_generic_phy);
739 phy_power_off(dwc->usb3_generic_phy);
740
741 usb_phy_shutdown(dwc->usb2_phy);
742 usb_phy_shutdown(dwc->usb3_phy);
743 phy_exit(dwc->usb2_generic_phy);
744 phy_exit(dwc->usb3_generic_phy);
745
746 clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks);
747 reset_control_assert(dwc->reset);
748 }
749
dwc3_core_is_valid(struct dwc3 * dwc)750 static bool dwc3_core_is_valid(struct dwc3 *dwc)
751 {
752 u32 reg;
753
754 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
755 dwc->ip = DWC3_GSNPS_ID(reg);
756
757 /* This should read as U3 followed by revision number */
758 if (DWC3_IP_IS(DWC3)) {
759 dwc->revision = reg;
760 } else if (DWC3_IP_IS(DWC31) || DWC3_IP_IS(DWC32)) {
761 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
762 dwc->version_type = dwc3_readl(dwc->regs, DWC3_VER_TYPE);
763 } else {
764 return false;
765 }
766
767 return true;
768 }
769
dwc3_core_setup_global_control(struct dwc3 * dwc)770 static void dwc3_core_setup_global_control(struct dwc3 *dwc)
771 {
772 u32 hwparams4 = dwc->hwparams.hwparams4;
773 u32 reg;
774
775 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
776 reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
777
778 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
779 case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
780 /**
781 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
782 * issue which would cause xHCI compliance tests to fail.
783 *
784 * Because of that we cannot enable clock gating on such
785 * configurations.
786 *
787 * Refers to:
788 *
789 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
790 * SOF/ITP Mode Used
791 */
792 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
793 dwc->dr_mode == USB_DR_MODE_OTG) &&
794 DWC3_VER_IS_WITHIN(DWC3, 210A, 250A))
795 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
796 else
797 reg &= ~DWC3_GCTL_DSBLCLKGTNG;
798 break;
799 case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
800 /* enable hibernation here */
801 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
802
803 /*
804 * REVISIT Enabling this bit so that host-mode hibernation
805 * will work. Device-mode hibernation is not yet implemented.
806 */
807 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
808 break;
809 default:
810 /* nothing */
811 break;
812 }
813
814 /* check if current dwc3 is on simulation board */
815 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
816 dev_info(dwc->dev, "Running with FPGA optimizations\n");
817 dwc->is_fpga = true;
818 }
819
820 WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
821 "disable_scramble cannot be used on non-FPGA builds\n");
822
823 if (dwc->disable_scramble_quirk && dwc->is_fpga)
824 reg |= DWC3_GCTL_DISSCRAMBLE;
825 else
826 reg &= ~DWC3_GCTL_DISSCRAMBLE;
827
828 if (dwc->u2exit_lfps_quirk)
829 reg |= DWC3_GCTL_U2EXIT_LFPS;
830
831 /*
832 * WORKAROUND: DWC3 revisions <1.90a have a bug
833 * where the device can fail to connect at SuperSpeed
834 * and falls back to high-speed mode which causes
835 * the device to enter a Connect/Disconnect loop
836 */
837 if (DWC3_VER_IS_PRIOR(DWC3, 190A))
838 reg |= DWC3_GCTL_U2RSTECN;
839
840 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
841 }
842
843 static int dwc3_core_get_phy(struct dwc3 *dwc);
844 static int dwc3_core_ulpi_init(struct dwc3 *dwc);
845
846 /* set global incr burst type configuration registers */
dwc3_set_incr_burst_type(struct dwc3 * dwc)847 static void dwc3_set_incr_burst_type(struct dwc3 *dwc)
848 {
849 struct device *dev = dwc->dev;
850 /* incrx_mode : for INCR burst type. */
851 bool incrx_mode;
852 /* incrx_size : for size of INCRX burst. */
853 u32 incrx_size;
854 u32 *vals;
855 u32 cfg;
856 int ntype;
857 int ret;
858 int i;
859
860 cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
861
862 /*
863 * Handle property "snps,incr-burst-type-adjustment".
864 * Get the number of value from this property:
865 * result <= 0, means this property is not supported.
866 * result = 1, means INCRx burst mode supported.
867 * result > 1, means undefined length burst mode supported.
868 */
869 ntype = device_property_count_u32(dev, "snps,incr-burst-type-adjustment");
870 if (ntype <= 0)
871 return;
872
873 vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL);
874 if (!vals) {
875 dev_err(dev, "Error to get memory\n");
876 return;
877 }
878
879 /* Get INCR burst type, and parse it */
880 ret = device_property_read_u32_array(dev,
881 "snps,incr-burst-type-adjustment", vals, ntype);
882 if (ret) {
883 kfree(vals);
884 dev_err(dev, "Error to get property\n");
885 return;
886 }
887
888 incrx_size = *vals;
889
890 if (ntype > 1) {
891 /* INCRX (undefined length) burst mode */
892 incrx_mode = INCRX_UNDEF_LENGTH_BURST_MODE;
893 for (i = 1; i < ntype; i++) {
894 if (vals[i] > incrx_size)
895 incrx_size = vals[i];
896 }
897 } else {
898 /* INCRX burst mode */
899 incrx_mode = INCRX_BURST_MODE;
900 }
901
902 kfree(vals);
903
904 /* Enable Undefined Length INCR Burst and Enable INCRx Burst */
905 cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK;
906 if (incrx_mode)
907 cfg |= DWC3_GSBUSCFG0_INCRBRSTENA;
908 switch (incrx_size) {
909 case 256:
910 cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA;
911 break;
912 case 128:
913 cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA;
914 break;
915 case 64:
916 cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA;
917 break;
918 case 32:
919 cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA;
920 break;
921 case 16:
922 cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA;
923 break;
924 case 8:
925 cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA;
926 break;
927 case 4:
928 cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA;
929 break;
930 case 1:
931 break;
932 default:
933 dev_err(dev, "Invalid property\n");
934 break;
935 }
936
937 dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg);
938 }
939
940 /**
941 * dwc3_core_init - Low-level initialization of DWC3 Core
942 * @dwc: Pointer to our controller context structure
943 *
944 * Returns 0 on success otherwise negative errno.
945 */
dwc3_core_init(struct dwc3 * dwc)946 static int dwc3_core_init(struct dwc3 *dwc)
947 {
948 unsigned int hw_mode;
949 u32 reg;
950 int ret;
951
952 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
953
954 /*
955 * Write Linux Version Code to our GUID register so it's easy to figure
956 * out which kernel version a bug was found.
957 */
958 dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
959
960 ret = dwc3_phy_setup(dwc);
961 if (ret)
962 goto err0;
963
964 if (!dwc->ulpi_ready) {
965 ret = dwc3_core_ulpi_init(dwc);
966 if (ret) {
967 if (ret == -ETIMEDOUT) {
968 dwc3_core_soft_reset(dwc);
969 ret = -EPROBE_DEFER;
970 }
971 goto err0;
972 }
973 dwc->ulpi_ready = true;
974 }
975
976 if (!dwc->phys_ready) {
977 ret = dwc3_core_get_phy(dwc);
978 if (ret)
979 goto err0a;
980 dwc->phys_ready = true;
981 }
982
983 usb_phy_init(dwc->usb2_phy);
984 usb_phy_init(dwc->usb3_phy);
985 ret = phy_init(dwc->usb2_generic_phy);
986 if (ret < 0)
987 goto err0a;
988
989 ret = phy_init(dwc->usb3_generic_phy);
990 if (ret < 0) {
991 phy_exit(dwc->usb2_generic_phy);
992 goto err0a;
993 }
994
995 ret = dwc3_core_soft_reset(dwc);
996 if (ret)
997 goto err1;
998
999 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD &&
1000 !DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) {
1001 if (!dwc->dis_u3_susphy_quirk) {
1002 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
1003 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
1004 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
1005 }
1006
1007 if (!dwc->dis_u2_susphy_quirk) {
1008 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1009 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
1010 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1011 }
1012 }
1013
1014 dwc3_core_setup_global_control(dwc);
1015 dwc3_core_num_eps(dwc);
1016
1017 ret = dwc3_setup_scratch_buffers(dwc);
1018 if (ret)
1019 goto err1;
1020
1021 /* Adjust Frame Length */
1022 dwc3_frame_length_adjustment(dwc);
1023
1024 dwc3_set_incr_burst_type(dwc);
1025
1026 usb_phy_set_suspend(dwc->usb2_phy, 0);
1027 usb_phy_set_suspend(dwc->usb3_phy, 0);
1028 ret = phy_power_on(dwc->usb2_generic_phy);
1029 if (ret < 0)
1030 goto err2;
1031
1032 ret = phy_power_on(dwc->usb3_generic_phy);
1033 if (ret < 0)
1034 goto err3;
1035
1036 ret = dwc3_event_buffers_setup(dwc);
1037 if (ret) {
1038 dev_err(dwc->dev, "failed to setup event buffers\n");
1039 goto err4;
1040 }
1041
1042 /*
1043 * ENDXFER polling is available on version 3.10a and later of
1044 * the DWC_usb3 controller. It is NOT available in the
1045 * DWC_usb31 controller.
1046 */
1047 if (DWC3_VER_IS_WITHIN(DWC3, 310A, ANY)) {
1048 reg = dwc3_readl(dwc->regs, DWC3_GUCTL2);
1049 reg |= DWC3_GUCTL2_RST_ACTBITLATER;
1050 dwc3_writel(dwc->regs, DWC3_GUCTL2, reg);
1051 }
1052
1053 if (!DWC3_VER_IS_PRIOR(DWC3, 250A)) {
1054 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
1055
1056 /*
1057 * Enable hardware control of sending remote wakeup
1058 * in HS when the device is in the L1 state.
1059 */
1060 if (!DWC3_VER_IS_PRIOR(DWC3, 290A))
1061 reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW;
1062
1063 /*
1064 * Decouple USB 2.0 L1 & L2 events which will allow for
1065 * gadget driver to only receive U3/L2 suspend & wakeup
1066 * events and prevent the more frequent L1 LPM transitions
1067 * from interrupting the driver.
1068 */
1069 if (!DWC3_VER_IS_PRIOR(DWC3, 300A))
1070 reg |= DWC3_GUCTL1_DEV_DECOUPLE_L1L2_EVT;
1071
1072 if (dwc->dis_tx_ipgap_linecheck_quirk)
1073 reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS;
1074
1075 if (dwc->parkmode_disable_ss_quirk)
1076 reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS;
1077
1078 if (DWC3_VER_IS_WITHIN(DWC3, 290A, ANY) &&
1079 (dwc->maximum_speed == USB_SPEED_HIGH ||
1080 dwc->maximum_speed == USB_SPEED_FULL))
1081 reg |= DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK;
1082
1083 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
1084 }
1085
1086 /*
1087 * Must config both number of packets and max burst settings to enable
1088 * RX and/or TX threshold.
1089 */
1090 if (!DWC3_IP_IS(DWC3) && dwc->dr_mode == USB_DR_MODE_HOST) {
1091 u8 rx_thr_num = dwc->rx_thr_num_pkt_prd;
1092 u8 rx_maxburst = dwc->rx_max_burst_prd;
1093 u8 tx_thr_num = dwc->tx_thr_num_pkt_prd;
1094 u8 tx_maxburst = dwc->tx_max_burst_prd;
1095
1096 if (rx_thr_num && rx_maxburst) {
1097 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1098 reg |= DWC31_RXTHRNUMPKTSEL_PRD;
1099
1100 reg &= ~DWC31_RXTHRNUMPKT_PRD(~0);
1101 reg |= DWC31_RXTHRNUMPKT_PRD(rx_thr_num);
1102
1103 reg &= ~DWC31_MAXRXBURSTSIZE_PRD(~0);
1104 reg |= DWC31_MAXRXBURSTSIZE_PRD(rx_maxburst);
1105
1106 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1107 }
1108
1109 if (tx_thr_num && tx_maxburst) {
1110 reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG);
1111 reg |= DWC31_TXTHRNUMPKTSEL_PRD;
1112
1113 reg &= ~DWC31_TXTHRNUMPKT_PRD(~0);
1114 reg |= DWC31_TXTHRNUMPKT_PRD(tx_thr_num);
1115
1116 reg &= ~DWC31_MAXTXBURSTSIZE_PRD(~0);
1117 reg |= DWC31_MAXTXBURSTSIZE_PRD(tx_maxburst);
1118
1119 dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg);
1120 }
1121 }
1122
1123 return 0;
1124
1125 err4:
1126 phy_power_off(dwc->usb3_generic_phy);
1127
1128 err3:
1129 phy_power_off(dwc->usb2_generic_phy);
1130
1131 err2:
1132 usb_phy_set_suspend(dwc->usb2_phy, 1);
1133 usb_phy_set_suspend(dwc->usb3_phy, 1);
1134
1135 err1:
1136 usb_phy_shutdown(dwc->usb2_phy);
1137 usb_phy_shutdown(dwc->usb3_phy);
1138 phy_exit(dwc->usb2_generic_phy);
1139 phy_exit(dwc->usb3_generic_phy);
1140
1141 err0a:
1142 dwc3_ulpi_exit(dwc);
1143
1144 err0:
1145 return ret;
1146 }
1147
dwc3_core_get_phy(struct dwc3 * dwc)1148 static int dwc3_core_get_phy(struct dwc3 *dwc)
1149 {
1150 struct device *dev = dwc->dev;
1151 struct device_node *node = dev->of_node;
1152 int ret;
1153
1154 if (node) {
1155 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
1156 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
1157 } else {
1158 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
1159 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
1160 }
1161
1162 if (IS_ERR(dwc->usb2_phy)) {
1163 ret = PTR_ERR(dwc->usb2_phy);
1164 if (ret == -ENXIO || ret == -ENODEV) {
1165 dwc->usb2_phy = NULL;
1166 } else {
1167 return dev_err_probe(dev, ret, "no usb2 phy configured\n");
1168 }
1169 }
1170
1171 if (IS_ERR(dwc->usb3_phy)) {
1172 ret = PTR_ERR(dwc->usb3_phy);
1173 if (ret == -ENXIO || ret == -ENODEV) {
1174 dwc->usb3_phy = NULL;
1175 } else {
1176 return dev_err_probe(dev, ret, "no usb3 phy configured\n");
1177 }
1178 }
1179
1180 dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
1181 if (IS_ERR(dwc->usb2_generic_phy)) {
1182 ret = PTR_ERR(dwc->usb2_generic_phy);
1183 if (ret == -ENOSYS || ret == -ENODEV) {
1184 dwc->usb2_generic_phy = NULL;
1185 } else {
1186 return dev_err_probe(dev, ret, "no usb2 phy configured\n");
1187 }
1188 }
1189
1190 dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
1191 if (IS_ERR(dwc->usb3_generic_phy)) {
1192 ret = PTR_ERR(dwc->usb3_generic_phy);
1193 if (ret == -ENOSYS || ret == -ENODEV) {
1194 dwc->usb3_generic_phy = NULL;
1195 } else {
1196 return dev_err_probe(dev, ret, "no usb3 phy configured\n");
1197 }
1198 }
1199
1200 return 0;
1201 }
1202
dwc3_core_init_mode(struct dwc3 * dwc)1203 static int dwc3_core_init_mode(struct dwc3 *dwc)
1204 {
1205 struct device *dev = dwc->dev;
1206 int ret;
1207
1208 switch (dwc->dr_mode) {
1209 case USB_DR_MODE_PERIPHERAL:
1210 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1211
1212 if (dwc->usb2_phy)
1213 otg_set_vbus(dwc->usb2_phy->otg, false);
1214 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
1215 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
1216
1217 ret = dwc3_gadget_init(dwc);
1218 if (ret)
1219 return dev_err_probe(dev, ret, "failed to initialize gadget\n");
1220 break;
1221 case USB_DR_MODE_HOST:
1222 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
1223
1224 if (dwc->usb2_phy)
1225 otg_set_vbus(dwc->usb2_phy->otg, true);
1226 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
1227 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
1228
1229 ret = dwc3_host_init(dwc);
1230 if (ret)
1231 return dev_err_probe(dev, ret, "failed to initialize host\n");
1232 break;
1233 case USB_DR_MODE_OTG:
1234 INIT_WORK(&dwc->drd_work, __dwc3_set_mode);
1235 ret = dwc3_drd_init(dwc);
1236 if (ret)
1237 return dev_err_probe(dev, ret, "failed to initialize dual-role\n");
1238 break;
1239 default:
1240 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
1241 return -EINVAL;
1242 }
1243
1244 return 0;
1245 }
1246
dwc3_core_exit_mode(struct dwc3 * dwc)1247 static void dwc3_core_exit_mode(struct dwc3 *dwc)
1248 {
1249 switch (dwc->dr_mode) {
1250 case USB_DR_MODE_PERIPHERAL:
1251 dwc3_gadget_exit(dwc);
1252 break;
1253 case USB_DR_MODE_HOST:
1254 dwc3_host_exit(dwc);
1255 break;
1256 case USB_DR_MODE_OTG:
1257 dwc3_drd_exit(dwc);
1258 break;
1259 default:
1260 /* do nothing */
1261 break;
1262 }
1263
1264 /* de-assert DRVVBUS for HOST and OTG mode */
1265 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1266 }
1267
dwc3_get_properties(struct dwc3 * dwc)1268 static void dwc3_get_properties(struct dwc3 *dwc)
1269 {
1270 struct device *dev = dwc->dev;
1271 u8 lpm_nyet_threshold;
1272 u8 tx_de_emphasis;
1273 u8 hird_threshold;
1274 u8 rx_thr_num_pkt_prd = 0;
1275 u8 rx_max_burst_prd = 0;
1276 u8 tx_thr_num_pkt_prd = 0;
1277 u8 tx_max_burst_prd = 0;
1278 u8 tx_fifo_resize_max_num;
1279 const char *usb_psy_name;
1280 int ret;
1281
1282 /* default to highest possible threshold */
1283 lpm_nyet_threshold = 0xf;
1284
1285 /* default to -3.5dB de-emphasis */
1286 tx_de_emphasis = 1;
1287
1288 /*
1289 * default to assert utmi_sleep_n and use maximum allowed HIRD
1290 * threshold value of 0b1100
1291 */
1292 hird_threshold = 12;
1293
1294 /*
1295 * default to a TXFIFO size large enough to fit 6 max packets. This
1296 * allows for systems with larger bus latencies to have some headroom
1297 * for endpoints that have a large bMaxBurst value.
1298 */
1299 tx_fifo_resize_max_num = 6;
1300
1301 dwc->maximum_speed = usb_get_maximum_speed(dev);
1302 dwc->max_ssp_rate = usb_get_maximum_ssp_rate(dev);
1303 dwc->dr_mode = usb_get_dr_mode(dev);
1304 dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node);
1305
1306 dwc->sysdev_is_parent = device_property_read_bool(dev,
1307 "linux,sysdev_is_parent");
1308 if (dwc->sysdev_is_parent)
1309 dwc->sysdev = dwc->dev->parent;
1310 else
1311 dwc->sysdev = dwc->dev;
1312
1313 ret = device_property_read_string(dev, "usb-psy-name", &usb_psy_name);
1314 if (ret >= 0) {
1315 dwc->usb_psy = power_supply_get_by_name(usb_psy_name);
1316 if (!dwc->usb_psy)
1317 dev_err(dev, "couldn't get usb power supply\n");
1318 }
1319
1320 dwc->has_lpm_erratum = device_property_read_bool(dev,
1321 "snps,has-lpm-erratum");
1322 device_property_read_u8(dev, "snps,lpm-nyet-threshold",
1323 &lpm_nyet_threshold);
1324 dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
1325 "snps,is-utmi-l1-suspend");
1326 device_property_read_u8(dev, "snps,hird-threshold",
1327 &hird_threshold);
1328 dwc->dis_start_transfer_quirk = device_property_read_bool(dev,
1329 "snps,dis-start-transfer-quirk");
1330 dwc->usb3_lpm_capable = device_property_read_bool(dev,
1331 "snps,usb3_lpm_capable");
1332 dwc->usb2_lpm_disable = device_property_read_bool(dev,
1333 "snps,usb2-lpm-disable");
1334 dwc->usb2_gadget_lpm_disable = device_property_read_bool(dev,
1335 "snps,usb2-gadget-lpm-disable");
1336 device_property_read_u8(dev, "snps,rx-thr-num-pkt-prd",
1337 &rx_thr_num_pkt_prd);
1338 device_property_read_u8(dev, "snps,rx-max-burst-prd",
1339 &rx_max_burst_prd);
1340 device_property_read_u8(dev, "snps,tx-thr-num-pkt-prd",
1341 &tx_thr_num_pkt_prd);
1342 device_property_read_u8(dev, "snps,tx-max-burst-prd",
1343 &tx_max_burst_prd);
1344 dwc->do_fifo_resize = device_property_read_bool(dev,
1345 "tx-fifo-resize");
1346 if (dwc->do_fifo_resize)
1347 device_property_read_u8(dev, "tx-fifo-max-num",
1348 &tx_fifo_resize_max_num);
1349
1350 dwc->disable_scramble_quirk = device_property_read_bool(dev,
1351 "snps,disable_scramble_quirk");
1352 dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
1353 "snps,u2exit_lfps_quirk");
1354 dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
1355 "snps,u2ss_inp3_quirk");
1356 dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
1357 "snps,req_p1p2p3_quirk");
1358 dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
1359 "snps,del_p1p2p3_quirk");
1360 dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
1361 "snps,del_phy_power_chg_quirk");
1362 dwc->lfps_filter_quirk = device_property_read_bool(dev,
1363 "snps,lfps_filter_quirk");
1364 dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
1365 "snps,rx_detect_poll_quirk");
1366 dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
1367 "snps,dis_u3_susphy_quirk");
1368 dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
1369 "snps,dis_u2_susphy_quirk");
1370 dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
1371 "snps,dis_enblslpm_quirk");
1372 dwc->dis_u1_entry_quirk = device_property_read_bool(dev,
1373 "snps,dis-u1-entry-quirk");
1374 dwc->dis_u2_entry_quirk = device_property_read_bool(dev,
1375 "snps,dis-u2-entry-quirk");
1376 dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev,
1377 "snps,dis_rxdet_inp3_quirk");
1378 dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
1379 "snps,dis-u2-freeclk-exists-quirk");
1380 dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev,
1381 "snps,dis-del-phy-power-chg-quirk");
1382 dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev,
1383 "snps,dis-tx-ipgap-linecheck-quirk");
1384 dwc->parkmode_disable_ss_quirk = device_property_read_bool(dev,
1385 "snps,parkmode-disable-ss-quirk");
1386
1387 dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
1388 "snps,tx_de_emphasis_quirk");
1389 device_property_read_u8(dev, "snps,tx_de_emphasis",
1390 &tx_de_emphasis);
1391 device_property_read_string(dev, "snps,hsphy_interface",
1392 &dwc->hsphy_interface);
1393 device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
1394 &dwc->fladj);
1395
1396 dwc->dis_metastability_quirk = device_property_read_bool(dev,
1397 "snps,dis_metastability_quirk");
1398
1399 dwc->dis_split_quirk = device_property_read_bool(dev,
1400 "snps,dis-split-quirk");
1401
1402 dwc->lpm_nyet_threshold = lpm_nyet_threshold;
1403 dwc->tx_de_emphasis = tx_de_emphasis;
1404
1405 dwc->hird_threshold = hird_threshold;
1406
1407 dwc->rx_thr_num_pkt_prd = rx_thr_num_pkt_prd;
1408 dwc->rx_max_burst_prd = rx_max_burst_prd;
1409
1410 dwc->tx_thr_num_pkt_prd = tx_thr_num_pkt_prd;
1411 dwc->tx_max_burst_prd = tx_max_burst_prd;
1412
1413 dwc->imod_interval = 0;
1414
1415 dwc->tx_fifo_resize_max_num = tx_fifo_resize_max_num;
1416 }
1417
1418 /* check whether the core supports IMOD */
dwc3_has_imod(struct dwc3 * dwc)1419 bool dwc3_has_imod(struct dwc3 *dwc)
1420 {
1421 return DWC3_VER_IS_WITHIN(DWC3, 300A, ANY) ||
1422 DWC3_VER_IS_WITHIN(DWC31, 120A, ANY) ||
1423 DWC3_IP_IS(DWC32);
1424 }
1425
dwc3_check_params(struct dwc3 * dwc)1426 static void dwc3_check_params(struct dwc3 *dwc)
1427 {
1428 struct device *dev = dwc->dev;
1429 unsigned int hwparam_gen =
1430 DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3);
1431
1432 /* Check for proper value of imod_interval */
1433 if (dwc->imod_interval && !dwc3_has_imod(dwc)) {
1434 dev_warn(dwc->dev, "Interrupt moderation not supported\n");
1435 dwc->imod_interval = 0;
1436 }
1437
1438 /*
1439 * Workaround for STAR 9000961433 which affects only version
1440 * 3.00a of the DWC_usb3 core. This prevents the controller
1441 * interrupt from being masked while handling events. IMOD
1442 * allows us to work around this issue. Enable it for the
1443 * affected version.
1444 */
1445 if (!dwc->imod_interval &&
1446 DWC3_VER_IS(DWC3, 300A))
1447 dwc->imod_interval = 1;
1448
1449 /* Check the maximum_speed parameter */
1450 switch (dwc->maximum_speed) {
1451 case USB_SPEED_LOW:
1452 case USB_SPEED_FULL:
1453 case USB_SPEED_HIGH:
1454 break;
1455 case USB_SPEED_SUPER:
1456 if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS)
1457 dev_warn(dev, "UDC doesn't support Gen 1\n");
1458 break;
1459 case USB_SPEED_SUPER_PLUS:
1460 if ((DWC3_IP_IS(DWC32) &&
1461 hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS) ||
1462 (!DWC3_IP_IS(DWC32) &&
1463 hwparam_gen != DWC3_GHWPARAMS3_SSPHY_IFC_GEN2))
1464 dev_warn(dev, "UDC doesn't support SSP\n");
1465 break;
1466 default:
1467 dev_err(dev, "invalid maximum_speed parameter %d\n",
1468 dwc->maximum_speed);
1469 fallthrough;
1470 case USB_SPEED_UNKNOWN:
1471 switch (hwparam_gen) {
1472 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2:
1473 dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1474 break;
1475 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1:
1476 if (DWC3_IP_IS(DWC32))
1477 dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1478 else
1479 dwc->maximum_speed = USB_SPEED_SUPER;
1480 break;
1481 case DWC3_GHWPARAMS3_SSPHY_IFC_DIS:
1482 dwc->maximum_speed = USB_SPEED_HIGH;
1483 break;
1484 default:
1485 dwc->maximum_speed = USB_SPEED_SUPER;
1486 break;
1487 }
1488 break;
1489 }
1490
1491 /*
1492 * Currently the controller does not have visibility into the HW
1493 * parameter to determine the maximum number of lanes the HW supports.
1494 * If the number of lanes is not specified in the device property, then
1495 * set the default to support dual-lane for DWC_usb32 and single-lane
1496 * for DWC_usb31 for super-speed-plus.
1497 */
1498 if (dwc->maximum_speed == USB_SPEED_SUPER_PLUS) {
1499 switch (dwc->max_ssp_rate) {
1500 case USB_SSP_GEN_2x1:
1501 if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_GEN1)
1502 dev_warn(dev, "UDC only supports Gen 1\n");
1503 break;
1504 case USB_SSP_GEN_1x2:
1505 case USB_SSP_GEN_2x2:
1506 if (DWC3_IP_IS(DWC31))
1507 dev_warn(dev, "UDC only supports single lane\n");
1508 break;
1509 case USB_SSP_GEN_UNKNOWN:
1510 default:
1511 switch (hwparam_gen) {
1512 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2:
1513 if (DWC3_IP_IS(DWC32))
1514 dwc->max_ssp_rate = USB_SSP_GEN_2x2;
1515 else
1516 dwc->max_ssp_rate = USB_SSP_GEN_2x1;
1517 break;
1518 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1:
1519 if (DWC3_IP_IS(DWC32))
1520 dwc->max_ssp_rate = USB_SSP_GEN_1x2;
1521 break;
1522 }
1523 break;
1524 }
1525 }
1526 }
1527
dwc3_probe(struct platform_device * pdev)1528 static int dwc3_probe(struct platform_device *pdev)
1529 {
1530 struct device *dev = &pdev->dev;
1531 struct resource *res, dwc_res;
1532 struct dwc3_vendor *vdwc;
1533 struct dwc3 *dwc;
1534
1535 int ret;
1536
1537 void __iomem *regs;
1538
1539 vdwc = devm_kzalloc(dev, sizeof(*vdwc), GFP_KERNEL);
1540 if (!vdwc)
1541 return -ENOMEM;
1542 dwc = &vdwc->dwc;
1543
1544 dwc->dev = dev;
1545
1546 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1547 if (!res) {
1548 dev_err(dev, "missing memory resource\n");
1549 return -ENODEV;
1550 }
1551
1552 dwc->xhci_resources[0].start = res->start;
1553 dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
1554 DWC3_XHCI_REGS_END;
1555 dwc->xhci_resources[0].flags = res->flags;
1556 dwc->xhci_resources[0].name = res->name;
1557
1558 /*
1559 * Request memory region but exclude xHCI regs,
1560 * since it will be requested by the xhci-plat driver.
1561 */
1562 dwc_res = *res;
1563 dwc_res.start += DWC3_GLOBALS_REGS_START;
1564
1565 regs = devm_ioremap_resource(dev, &dwc_res);
1566 if (IS_ERR(regs))
1567 return PTR_ERR(regs);
1568
1569 dwc->regs = regs;
1570 dwc->regs_size = resource_size(&dwc_res);
1571
1572 dwc3_get_properties(dwc);
1573
1574 dwc->reset = devm_reset_control_array_get_optional_shared(dev);
1575 if (IS_ERR(dwc->reset)) {
1576 ret = PTR_ERR(dwc->reset);
1577 goto put_usb_psy;
1578 }
1579
1580 if (dev->of_node) {
1581 ret = devm_clk_bulk_get_all(dev, &dwc->clks);
1582 if (ret == -EPROBE_DEFER) {
1583 goto put_usb_psy;
1584 }
1585
1586 /*
1587 * Clocks are optional, but new DT platforms should support all
1588 * clocks as required by the DT-binding.
1589 */
1590 if (ret < 0)
1591 dwc->num_clks = 0;
1592 else
1593 dwc->num_clks = ret;
1594 }
1595
1596 ret = reset_control_deassert(dwc->reset);
1597 if (ret)
1598 goto put_usb_psy;
1599
1600 ret = clk_bulk_prepare_enable(dwc->num_clks, dwc->clks);
1601 if (ret)
1602 goto assert_reset;
1603
1604 if (!dwc3_core_is_valid(dwc)) {
1605 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
1606 ret = -ENODEV;
1607 goto disable_clks;
1608 }
1609
1610 platform_set_drvdata(pdev, dwc);
1611 dwc3_cache_hwparams(dwc);
1612 device_init_wakeup(&pdev->dev, of_property_read_bool(dev->of_node, "wakeup-source"));
1613
1614 if (!dwc->sysdev_is_parent &&
1615 DWC3_GHWPARAMS0_AWIDTH(dwc->hwparams.hwparams0) == 64) {
1616 ret = dma_set_mask_and_coherent(dwc->sysdev, DMA_BIT_MASK(64));
1617 if (ret)
1618 goto disable_clks;
1619 }
1620
1621 spin_lock_init(&dwc->lock);
1622 mutex_init(&dwc->mutex);
1623
1624 pm_runtime_get_noresume(dev);
1625 pm_runtime_set_active(dev);
1626 pm_runtime_use_autosuspend(dev);
1627 pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY);
1628 pm_runtime_enable(dev);
1629
1630 pm_runtime_forbid(dev);
1631
1632 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
1633 if (ret) {
1634 dev_err(dwc->dev, "failed to allocate event buffers\n");
1635 ret = -ENOMEM;
1636 goto err2;
1637 }
1638
1639 ret = dwc3_get_dr_mode(dwc);
1640 if (ret)
1641 goto err3;
1642
1643 ret = dwc3_alloc_scratch_buffers(dwc);
1644 if (ret)
1645 goto err3;
1646
1647 ret = dwc3_core_init(dwc);
1648 if (ret) {
1649 dev_err_probe(dev, ret, "failed to initialize core\n");
1650 goto err4;
1651 }
1652
1653 dwc3_check_params(dwc);
1654 dwc3_debugfs_init(dwc);
1655
1656 ret = dwc3_core_init_mode(dwc);
1657 if (ret)
1658 goto err5;
1659
1660 pm_runtime_put(dev);
1661
1662 dma_set_max_seg_size(dev, UINT_MAX);
1663
1664 return 0;
1665
1666 err5:
1667 dwc3_debugfs_exit(dwc);
1668 dwc3_event_buffers_cleanup(dwc);
1669
1670 usb_phy_set_suspend(dwc->usb2_phy, 1);
1671 usb_phy_set_suspend(dwc->usb3_phy, 1);
1672 phy_power_off(dwc->usb2_generic_phy);
1673 phy_power_off(dwc->usb3_generic_phy);
1674
1675 usb_phy_shutdown(dwc->usb2_phy);
1676 usb_phy_shutdown(dwc->usb3_phy);
1677 phy_exit(dwc->usb2_generic_phy);
1678 phy_exit(dwc->usb3_generic_phy);
1679
1680 dwc3_ulpi_exit(dwc);
1681
1682 err4:
1683 dwc3_free_scratch_buffers(dwc);
1684
1685 err3:
1686 dwc3_free_event_buffers(dwc);
1687
1688 err2:
1689 pm_runtime_allow(dev);
1690 pm_runtime_disable(dev);
1691 pm_runtime_set_suspended(dev);
1692 pm_runtime_put_noidle(dev);
1693 disable_clks:
1694 clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks);
1695 assert_reset:
1696 reset_control_assert(dwc->reset);
1697 put_usb_psy:
1698 if (dwc->usb_psy)
1699 power_supply_put(dwc->usb_psy);
1700
1701 return ret;
1702 }
1703
dwc3_remove(struct platform_device * pdev)1704 static int dwc3_remove(struct platform_device *pdev)
1705 {
1706 struct dwc3 *dwc = platform_get_drvdata(pdev);
1707
1708 pm_runtime_get_sync(&pdev->dev);
1709
1710 dwc3_core_exit_mode(dwc);
1711 dwc3_debugfs_exit(dwc);
1712
1713 dwc3_core_exit(dwc);
1714 dwc3_ulpi_exit(dwc);
1715
1716 pm_runtime_allow(&pdev->dev);
1717 pm_runtime_disable(&pdev->dev);
1718 pm_runtime_put_noidle(&pdev->dev);
1719 /*
1720 * HACK: Clear the driver data, which is currently accessed by parent
1721 * glue drivers, before allowing the parent to suspend.
1722 */
1723 platform_set_drvdata(pdev, NULL);
1724 pm_runtime_set_suspended(&pdev->dev);
1725
1726 dwc3_free_event_buffers(dwc);
1727 dwc3_free_scratch_buffers(dwc);
1728
1729 if (dwc->usb_psy)
1730 power_supply_put(dwc->usb_psy);
1731
1732 return 0;
1733 }
1734
1735 #ifdef CONFIG_PM
dwc3_core_init_for_resume(struct dwc3 * dwc)1736 static int dwc3_core_init_for_resume(struct dwc3 *dwc)
1737 {
1738 int ret;
1739
1740 ret = reset_control_deassert(dwc->reset);
1741 if (ret)
1742 return ret;
1743
1744 ret = clk_bulk_prepare_enable(dwc->num_clks, dwc->clks);
1745 if (ret)
1746 goto assert_reset;
1747
1748 ret = dwc3_core_init(dwc);
1749 if (ret)
1750 goto disable_clks;
1751
1752 return 0;
1753
1754 disable_clks:
1755 clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks);
1756 assert_reset:
1757 reset_control_assert(dwc->reset);
1758
1759 return ret;
1760 }
1761
dwc3_suspend_common(struct dwc3 * dwc,pm_message_t msg)1762 static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg)
1763 {
1764 unsigned long flags;
1765 u32 reg;
1766
1767 switch (dwc->current_dr_role) {
1768 case DWC3_GCTL_PRTCAP_DEVICE:
1769 if (pm_runtime_suspended(dwc->dev))
1770 break;
1771 spin_lock_irqsave(&dwc->lock, flags);
1772 dwc3_gadget_suspend(dwc);
1773 spin_unlock_irqrestore(&dwc->lock, flags);
1774 synchronize_irq(dwc->irq_gadget);
1775 dwc3_core_exit(dwc);
1776 break;
1777 case DWC3_GCTL_PRTCAP_HOST:
1778 if (!PMSG_IS_AUTO(msg) && !device_can_wakeup(dwc->dev)) {
1779 dwc3_core_exit(dwc);
1780 break;
1781 }
1782
1783 /* Let controller to suspend HSPHY before PHY driver suspends */
1784 if (dwc->dis_u2_susphy_quirk ||
1785 dwc->dis_enblslpm_quirk) {
1786 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1787 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM |
1788 DWC3_GUSB2PHYCFG_SUSPHY;
1789 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1790
1791 /* Give some time for USB2 PHY to suspend */
1792 usleep_range(5000, 6000);
1793 }
1794
1795 phy_pm_runtime_put_sync(dwc->usb2_generic_phy);
1796 phy_pm_runtime_put_sync(dwc->usb3_generic_phy);
1797 break;
1798 case DWC3_GCTL_PRTCAP_OTG:
1799 /* do nothing during runtime_suspend */
1800 if (PMSG_IS_AUTO(msg))
1801 break;
1802
1803 if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
1804 spin_lock_irqsave(&dwc->lock, flags);
1805 dwc3_gadget_suspend(dwc);
1806 spin_unlock_irqrestore(&dwc->lock, flags);
1807 synchronize_irq(dwc->irq_gadget);
1808 }
1809
1810 dwc3_otg_exit(dwc);
1811 dwc3_core_exit(dwc);
1812 break;
1813 default:
1814 /* do nothing */
1815 break;
1816 }
1817
1818 return 0;
1819 }
1820
dwc3_resume_common(struct dwc3 * dwc,pm_message_t msg)1821 static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg)
1822 {
1823 unsigned long flags;
1824 int ret;
1825 u32 reg;
1826
1827 switch (dwc->current_dr_role) {
1828 case DWC3_GCTL_PRTCAP_DEVICE:
1829 ret = dwc3_core_init_for_resume(dwc);
1830 if (ret)
1831 return ret;
1832
1833 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1834 spin_lock_irqsave(&dwc->lock, flags);
1835 dwc3_gadget_resume(dwc);
1836 spin_unlock_irqrestore(&dwc->lock, flags);
1837 break;
1838 case DWC3_GCTL_PRTCAP_HOST:
1839 if (!PMSG_IS_AUTO(msg) && !device_can_wakeup(dwc->dev)) {
1840 ret = dwc3_core_init_for_resume(dwc);
1841 if (ret)
1842 return ret;
1843 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
1844 break;
1845 }
1846 /* Restore GUSB2PHYCFG bits that were modified in suspend */
1847 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1848 if (dwc->dis_u2_susphy_quirk)
1849 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
1850
1851 if (dwc->dis_enblslpm_quirk)
1852 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
1853
1854 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1855
1856 phy_pm_runtime_get_sync(dwc->usb2_generic_phy);
1857 phy_pm_runtime_get_sync(dwc->usb3_generic_phy);
1858 break;
1859 case DWC3_GCTL_PRTCAP_OTG:
1860 /* nothing to do on runtime_resume */
1861 if (PMSG_IS_AUTO(msg))
1862 break;
1863
1864 ret = dwc3_core_init_for_resume(dwc);
1865 if (ret)
1866 return ret;
1867
1868 dwc3_set_prtcap(dwc, dwc->current_dr_role);
1869
1870 dwc3_otg_init(dwc);
1871 if (dwc->current_otg_role == DWC3_OTG_ROLE_HOST) {
1872 dwc3_otg_host_init(dwc);
1873 } else if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
1874 spin_lock_irqsave(&dwc->lock, flags);
1875 dwc3_gadget_resume(dwc);
1876 spin_unlock_irqrestore(&dwc->lock, flags);
1877 }
1878
1879 break;
1880 default:
1881 /* do nothing */
1882 break;
1883 }
1884
1885 return 0;
1886 }
1887
dwc3_runtime_checks(struct dwc3 * dwc)1888 static int dwc3_runtime_checks(struct dwc3 *dwc)
1889 {
1890 switch (dwc->current_dr_role) {
1891 case DWC3_GCTL_PRTCAP_DEVICE:
1892 if (dwc->connected)
1893 return -EBUSY;
1894 break;
1895 case DWC3_GCTL_PRTCAP_HOST:
1896 default:
1897 /* do nothing */
1898 break;
1899 }
1900
1901 return 0;
1902 }
1903
dwc3_runtime_suspend(struct device * dev)1904 static int dwc3_runtime_suspend(struct device *dev)
1905 {
1906 struct dwc3 *dwc = dev_get_drvdata(dev);
1907 int ret;
1908
1909 if (dwc3_runtime_checks(dwc))
1910 return -EBUSY;
1911
1912 ret = dwc3_suspend_common(dwc, PMSG_AUTO_SUSPEND);
1913 if (ret)
1914 return ret;
1915
1916 return 0;
1917 }
1918
dwc3_runtime_resume(struct device * dev)1919 static int dwc3_runtime_resume(struct device *dev)
1920 {
1921 struct dwc3 *dwc = dev_get_drvdata(dev);
1922 int ret;
1923
1924 ret = dwc3_resume_common(dwc, PMSG_AUTO_RESUME);
1925 if (ret)
1926 return ret;
1927
1928 switch (dwc->current_dr_role) {
1929 case DWC3_GCTL_PRTCAP_DEVICE:
1930 dwc3_gadget_process_pending_events(dwc);
1931 break;
1932 case DWC3_GCTL_PRTCAP_HOST:
1933 default:
1934 /* do nothing */
1935 break;
1936 }
1937
1938 pm_runtime_mark_last_busy(dev);
1939
1940 return 0;
1941 }
1942
dwc3_runtime_idle(struct device * dev)1943 static int dwc3_runtime_idle(struct device *dev)
1944 {
1945 struct dwc3 *dwc = dev_get_drvdata(dev);
1946
1947 switch (dwc->current_dr_role) {
1948 case DWC3_GCTL_PRTCAP_DEVICE:
1949 if (dwc3_runtime_checks(dwc))
1950 return -EBUSY;
1951 break;
1952 case DWC3_GCTL_PRTCAP_HOST:
1953 default:
1954 /* do nothing */
1955 break;
1956 }
1957
1958 pm_runtime_mark_last_busy(dev);
1959 pm_runtime_autosuspend(dev);
1960
1961 return 0;
1962 }
1963 #endif /* CONFIG_PM */
1964
1965 #ifdef CONFIG_PM_SLEEP
dwc3_suspend(struct device * dev)1966 static int dwc3_suspend(struct device *dev)
1967 {
1968 struct dwc3 *dwc = dev_get_drvdata(dev);
1969 int ret;
1970
1971 ret = dwc3_suspend_common(dwc, PMSG_SUSPEND);
1972 if (ret)
1973 return ret;
1974
1975 pinctrl_pm_select_sleep_state(dev);
1976
1977 return 0;
1978 }
1979
dwc3_resume(struct device * dev)1980 static int dwc3_resume(struct device *dev)
1981 {
1982 struct dwc3 *dwc = dev_get_drvdata(dev);
1983 int ret;
1984
1985 pinctrl_pm_select_default_state(dev);
1986
1987 ret = dwc3_resume_common(dwc, PMSG_RESUME);
1988 if (ret)
1989 return ret;
1990
1991 pm_runtime_disable(dev);
1992 pm_runtime_set_active(dev);
1993 pm_runtime_enable(dev);
1994
1995 return 0;
1996 }
1997
dwc3_complete(struct device * dev)1998 static void dwc3_complete(struct device *dev)
1999 {
2000 struct dwc3 *dwc = dev_get_drvdata(dev);
2001 u32 reg;
2002
2003 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST &&
2004 dwc->dis_split_quirk) {
2005 reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);
2006 reg |= DWC3_GUCTL3_SPLITDISABLE;
2007 dwc3_writel(dwc->regs, DWC3_GUCTL3, reg);
2008 }
2009 }
2010 #else
2011 #define dwc3_complete NULL
2012 #endif /* CONFIG_PM_SLEEP */
2013
2014 static const struct dev_pm_ops dwc3_dev_pm_ops = {
2015 SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
2016 .complete = dwc3_complete,
2017 SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume,
2018 dwc3_runtime_idle)
2019 };
2020
2021 #ifdef CONFIG_OF
2022 static const struct of_device_id of_dwc3_match[] = {
2023 {
2024 .compatible = "snps,dwc3"
2025 },
2026 {
2027 .compatible = "synopsys,dwc3"
2028 },
2029 { },
2030 };
2031 MODULE_DEVICE_TABLE(of, of_dwc3_match);
2032 #endif
2033
2034 #ifdef CONFIG_ACPI
2035
2036 #define ACPI_ID_INTEL_BSW "808622B7"
2037
2038 static const struct acpi_device_id dwc3_acpi_match[] = {
2039 { ACPI_ID_INTEL_BSW, 0 },
2040 { },
2041 };
2042 MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
2043 #endif
2044
2045 static struct platform_driver dwc3_driver = {
2046 .probe = dwc3_probe,
2047 .remove = dwc3_remove,
2048 .driver = {
2049 .name = "dwc3",
2050 .of_match_table = of_match_ptr(of_dwc3_match),
2051 .acpi_match_table = ACPI_PTR(dwc3_acpi_match),
2052 .pm = &dwc3_dev_pm_ops,
2053 },
2054 };
2055
2056 module_platform_driver(dwc3_driver);
2057
2058 MODULE_ALIAS("platform:dwc3");
2059 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
2060 MODULE_LICENSE("GPL v2");
2061 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");
2062