1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * driver for Microsemi PQI-based storage controllers
4 * Copyright (c) 2019-2020 Microchip Technology Inc. and its subsidiaries
5 * Copyright (c) 2016-2018 Microsemi Corporation
6 * Copyright (c) 2016 PMC-Sierra, Inc.
7 *
8 * Questions/Comments/Bugfixes to storagedev@microchip.com
9 *
10 */
11
12 #include <linux/io-64-nonatomic-lo-hi.h>
13
14 #if !defined(_SMARTPQI_H)
15 #define _SMARTPQI_H
16
17 #include <scsi/scsi_host.h>
18 #include <linux/bsg-lib.h>
19
20 #pragma pack(1)
21
22 #define PQI_DEVICE_SIGNATURE "PQI DREG"
23
24 /* This structure is defined by the PQI specification. */
25 struct pqi_device_registers {
26 __le64 signature;
27 u8 function_and_status_code;
28 u8 reserved[7];
29 u8 max_admin_iq_elements;
30 u8 max_admin_oq_elements;
31 u8 admin_iq_element_length; /* in 16-byte units */
32 u8 admin_oq_element_length; /* in 16-byte units */
33 __le16 max_reset_timeout; /* in 100-millisecond units */
34 u8 reserved1[2];
35 __le32 legacy_intx_status;
36 __le32 legacy_intx_mask_set;
37 __le32 legacy_intx_mask_clear;
38 u8 reserved2[28];
39 __le32 device_status;
40 u8 reserved3[4];
41 __le64 admin_iq_pi_offset;
42 __le64 admin_oq_ci_offset;
43 __le64 admin_iq_element_array_addr;
44 __le64 admin_oq_element_array_addr;
45 __le64 admin_iq_ci_addr;
46 __le64 admin_oq_pi_addr;
47 u8 admin_iq_num_elements;
48 u8 admin_oq_num_elements;
49 __le16 admin_queue_int_msg_num;
50 u8 reserved4[4];
51 __le32 device_error;
52 u8 reserved5[4];
53 __le64 error_details;
54 __le32 device_reset;
55 __le32 power_action;
56 u8 reserved6[104];
57 };
58
59 /*
60 * controller registers
61 *
62 * These are defined by the Microsemi implementation.
63 *
64 * Some registers (those named sis_*) are only used when in
65 * legacy SIS mode before we transition the controller into
66 * PQI mode. There are a number of other SIS mode registers,
67 * but we don't use them, so only the SIS registers that we
68 * care about are defined here. The offsets mentioned in the
69 * comments are the offsets from the PCIe BAR 0.
70 */
71 struct pqi_ctrl_registers {
72 u8 reserved[0x20];
73 __le32 sis_host_to_ctrl_doorbell; /* 20h */
74 u8 reserved1[0x34 - (0x20 + sizeof(__le32))];
75 __le32 sis_interrupt_mask; /* 34h */
76 u8 reserved2[0x9c - (0x34 + sizeof(__le32))];
77 __le32 sis_ctrl_to_host_doorbell; /* 9Ch */
78 u8 reserved3[0xa0 - (0x9c + sizeof(__le32))];
79 __le32 sis_ctrl_to_host_doorbell_clear; /* A0h */
80 u8 reserved4[0xb0 - (0xa0 + sizeof(__le32))];
81 __le32 sis_driver_scratch; /* B0h */
82 u8 reserved5[0xbc - (0xb0 + sizeof(__le32))];
83 __le32 sis_firmware_status; /* BCh */
84 u8 reserved6[0x1000 - (0xbc + sizeof(__le32))];
85 __le32 sis_mailbox[8]; /* 1000h */
86 u8 reserved7[0x4000 - (0x1000 + (sizeof(__le32) * 8))];
87 /*
88 * The PQI spec states that the PQI registers should be at
89 * offset 0 from the PCIe BAR 0. However, we can't map
90 * them at offset 0 because that would break compatibility
91 * with the SIS registers. So we map them at offset 4000h.
92 */
93 struct pqi_device_registers pqi_registers; /* 4000h */
94 };
95
96 #if ((HZ) < 1000)
97 #define PQI_HZ 1000
98 #else
99 #define PQI_HZ (HZ)
100 #endif
101
102 #define PQI_DEVICE_REGISTERS_OFFSET 0x4000
103
104 enum pqi_io_path {
105 RAID_PATH = 0,
106 AIO_PATH = 1
107 };
108
109 enum pqi_irq_mode {
110 IRQ_MODE_NONE,
111 IRQ_MODE_INTX,
112 IRQ_MODE_MSIX
113 };
114
115 struct pqi_sg_descriptor {
116 __le64 address;
117 __le32 length;
118 __le32 flags;
119 };
120
121 /* manifest constants for the flags field of pqi_sg_descriptor */
122 #define CISS_SG_LAST 0x40000000
123 #define CISS_SG_CHAIN 0x80000000
124
125 struct pqi_iu_header {
126 u8 iu_type;
127 u8 reserved;
128 __le16 iu_length; /* in bytes - does not include the length */
129 /* of this header */
130 __le16 response_queue_id; /* specifies the OQ where the */
131 /* response IU is to be delivered */
132 u8 work_area[2]; /* reserved for driver use */
133 };
134
135 /*
136 * According to the PQI spec, the IU header is only the first 4 bytes of our
137 * pqi_iu_header structure.
138 */
139 #define PQI_REQUEST_HEADER_LENGTH 4
140
141 struct pqi_general_admin_request {
142 struct pqi_iu_header header;
143 __le16 request_id;
144 u8 function_code;
145 union {
146 struct {
147 u8 reserved[33];
148 __le32 buffer_length;
149 struct pqi_sg_descriptor sg_descriptor;
150 } report_device_capability;
151
152 struct {
153 u8 reserved;
154 __le16 queue_id;
155 u8 reserved1[2];
156 __le64 element_array_addr;
157 __le64 ci_addr;
158 __le16 num_elements;
159 __le16 element_length;
160 u8 queue_protocol;
161 u8 reserved2[23];
162 __le32 vendor_specific;
163 } create_operational_iq;
164
165 struct {
166 u8 reserved;
167 __le16 queue_id;
168 u8 reserved1[2];
169 __le64 element_array_addr;
170 __le64 pi_addr;
171 __le16 num_elements;
172 __le16 element_length;
173 u8 queue_protocol;
174 u8 reserved2[3];
175 __le16 int_msg_num;
176 __le16 coalescing_count;
177 __le32 min_coalescing_time;
178 __le32 max_coalescing_time;
179 u8 reserved3[8];
180 __le32 vendor_specific;
181 } create_operational_oq;
182
183 struct {
184 u8 reserved;
185 __le16 queue_id;
186 u8 reserved1[50];
187 } delete_operational_queue;
188
189 struct {
190 u8 reserved;
191 __le16 queue_id;
192 u8 reserved1[46];
193 __le32 vendor_specific;
194 } change_operational_iq_properties;
195
196 } data;
197 };
198
199 struct pqi_general_admin_response {
200 struct pqi_iu_header header;
201 __le16 request_id;
202 u8 function_code;
203 u8 status;
204 union {
205 struct {
206 u8 status_descriptor[4];
207 __le64 iq_pi_offset;
208 u8 reserved[40];
209 } create_operational_iq;
210
211 struct {
212 u8 status_descriptor[4];
213 __le64 oq_ci_offset;
214 u8 reserved[40];
215 } create_operational_oq;
216 } data;
217 };
218
219 struct pqi_iu_layer_descriptor {
220 u8 inbound_spanning_supported : 1;
221 u8 reserved : 7;
222 u8 reserved1[5];
223 __le16 max_inbound_iu_length;
224 u8 outbound_spanning_supported : 1;
225 u8 reserved2 : 7;
226 u8 reserved3[5];
227 __le16 max_outbound_iu_length;
228 };
229
230 struct pqi_device_capability {
231 __le16 data_length;
232 u8 reserved[6];
233 u8 iq_arbitration_priority_support_bitmask;
234 u8 maximum_aw_a;
235 u8 maximum_aw_b;
236 u8 maximum_aw_c;
237 u8 max_arbitration_burst : 3;
238 u8 reserved1 : 4;
239 u8 iqa : 1;
240 u8 reserved2[2];
241 u8 iq_freeze : 1;
242 u8 reserved3 : 7;
243 __le16 max_inbound_queues;
244 __le16 max_elements_per_iq;
245 u8 reserved4[4];
246 __le16 max_iq_element_length;
247 __le16 min_iq_element_length;
248 u8 reserved5[2];
249 __le16 max_outbound_queues;
250 __le16 max_elements_per_oq;
251 __le16 intr_coalescing_time_granularity;
252 __le16 max_oq_element_length;
253 __le16 min_oq_element_length;
254 u8 reserved6[24];
255 struct pqi_iu_layer_descriptor iu_layer_descriptors[32];
256 };
257
258 #define PQI_MAX_EMBEDDED_SG_DESCRIPTORS 4
259
260 struct pqi_raid_path_request {
261 struct pqi_iu_header header;
262 __le16 request_id;
263 __le16 nexus_id;
264 __le32 buffer_length;
265 u8 lun_number[8];
266 __le16 protocol_specific;
267 u8 data_direction : 2;
268 u8 partial : 1;
269 u8 reserved1 : 4;
270 u8 fence : 1;
271 __le16 error_index;
272 u8 reserved2;
273 u8 task_attribute : 3;
274 u8 command_priority : 4;
275 u8 reserved3 : 1;
276 u8 reserved4 : 2;
277 u8 additional_cdb_bytes_usage : 3;
278 u8 reserved5 : 3;
279 u8 cdb[16];
280 u8 reserved6[12];
281 __le32 timeout;
282 struct pqi_sg_descriptor
283 sg_descriptors[PQI_MAX_EMBEDDED_SG_DESCRIPTORS];
284 };
285
286 struct pqi_aio_path_request {
287 struct pqi_iu_header header;
288 __le16 request_id;
289 u8 reserved1[2];
290 __le32 nexus_id;
291 __le32 buffer_length;
292 u8 data_direction : 2;
293 u8 partial : 1;
294 u8 memory_type : 1;
295 u8 fence : 1;
296 u8 encryption_enable : 1;
297 u8 reserved2 : 2;
298 u8 task_attribute : 3;
299 u8 command_priority : 4;
300 u8 reserved3 : 1;
301 __le16 data_encryption_key_index;
302 __le32 encrypt_tweak_lower;
303 __le32 encrypt_tweak_upper;
304 u8 cdb[16];
305 __le16 error_index;
306 u8 num_sg_descriptors;
307 u8 cdb_length;
308 u8 lun_number[8];
309 u8 reserved4[4];
310 struct pqi_sg_descriptor
311 sg_descriptors[PQI_MAX_EMBEDDED_SG_DESCRIPTORS];
312 };
313
314 struct pqi_io_response {
315 struct pqi_iu_header header;
316 __le16 request_id;
317 __le16 error_index;
318 u8 reserved2[4];
319 };
320
321 struct pqi_general_management_request {
322 struct pqi_iu_header header;
323 __le16 request_id;
324 union {
325 struct {
326 u8 reserved[2];
327 __le32 buffer_length;
328 struct pqi_sg_descriptor sg_descriptors[3];
329 } report_event_configuration;
330
331 struct {
332 __le16 global_event_oq_id;
333 __le32 buffer_length;
334 struct pqi_sg_descriptor sg_descriptors[3];
335 } set_event_configuration;
336 } data;
337 };
338
339 struct pqi_event_descriptor {
340 u8 event_type;
341 u8 reserved;
342 __le16 oq_id;
343 };
344
345 struct pqi_event_config {
346 u8 reserved[2];
347 u8 num_event_descriptors;
348 u8 reserved1;
349 struct pqi_event_descriptor descriptors[1];
350 };
351
352 #define PQI_MAX_EVENT_DESCRIPTORS 255
353
354 #define PQI_EVENT_OFA_MEMORY_ALLOCATION 0x0
355 #define PQI_EVENT_OFA_QUIESCE 0x1
356 #define PQI_EVENT_OFA_CANCELLED 0x2
357
358 struct pqi_event_response {
359 struct pqi_iu_header header;
360 u8 event_type;
361 u8 reserved2 : 7;
362 u8 request_acknowledge : 1;
363 __le16 event_id;
364 __le32 additional_event_id;
365 union {
366 struct {
367 __le32 bytes_requested;
368 u8 reserved[12];
369 } ofa_memory_allocation;
370
371 struct {
372 __le16 reason; /* reason for cancellation */
373 u8 reserved[14];
374 } ofa_cancelled;
375 } data;
376 };
377
378 struct pqi_event_acknowledge_request {
379 struct pqi_iu_header header;
380 u8 event_type;
381 u8 reserved2;
382 __le16 event_id;
383 __le32 additional_event_id;
384 };
385
386 struct pqi_task_management_request {
387 struct pqi_iu_header header;
388 __le16 request_id;
389 __le16 nexus_id;
390 u8 reserved[2];
391 __le16 timeout;
392 u8 lun_number[8];
393 __le16 protocol_specific;
394 __le16 outbound_queue_id_to_manage;
395 __le16 request_id_to_manage;
396 u8 task_management_function;
397 u8 reserved2 : 7;
398 u8 fence : 1;
399 };
400
401 #define SOP_TASK_MANAGEMENT_LUN_RESET 0x8
402
403 struct pqi_task_management_response {
404 struct pqi_iu_header header;
405 __le16 request_id;
406 __le16 nexus_id;
407 u8 additional_response_info[3];
408 u8 response_code;
409 };
410
411 struct pqi_vendor_general_request {
412 struct pqi_iu_header header;
413 __le16 request_id;
414 __le16 function_code;
415 union {
416 struct {
417 __le16 first_section;
418 __le16 last_section;
419 u8 reserved[48];
420 } config_table_update;
421
422 struct {
423 __le64 buffer_address;
424 __le32 buffer_length;
425 u8 reserved[40];
426 } ofa_memory_allocation;
427 } data;
428 };
429
430 struct pqi_vendor_general_response {
431 struct pqi_iu_header header;
432 __le16 request_id;
433 __le16 function_code;
434 __le16 status;
435 u8 reserved[2];
436 };
437
438 #define PQI_VENDOR_GENERAL_CONFIG_TABLE_UPDATE 0
439 #define PQI_VENDOR_GENERAL_HOST_MEMORY_UPDATE 1
440
441 #define PQI_OFA_VERSION 1
442 #define PQI_OFA_SIGNATURE "OFA_QRM"
443 #define PQI_OFA_MAX_SG_DESCRIPTORS 64
444
445 #define PQI_OFA_MEMORY_DESCRIPTOR_LENGTH \
446 (offsetof(struct pqi_ofa_memory, sg_descriptor) + \
447 (PQI_OFA_MAX_SG_DESCRIPTORS * sizeof(struct pqi_sg_descriptor)))
448
449 struct pqi_ofa_memory {
450 __le64 signature; /* "OFA_QRM" */
451 __le16 version; /* version of this struct (1 = 1st version) */
452 u8 reserved[62];
453 __le32 bytes_allocated; /* total allocated memory in bytes */
454 __le16 num_memory_descriptors;
455 u8 reserved1[2];
456 struct pqi_sg_descriptor sg_descriptor[1];
457 };
458
459 struct pqi_aio_error_info {
460 u8 status;
461 u8 service_response;
462 u8 data_present;
463 u8 reserved;
464 __le32 residual_count;
465 __le16 data_length;
466 __le16 reserved1;
467 u8 data[256];
468 };
469
470 struct pqi_raid_error_info {
471 u8 data_in_result;
472 u8 data_out_result;
473 u8 reserved[3];
474 u8 status;
475 __le16 status_qualifier;
476 __le16 sense_data_length;
477 __le16 response_data_length;
478 __le32 data_in_transferred;
479 __le32 data_out_transferred;
480 u8 data[256];
481 };
482
483 #define PQI_REQUEST_IU_TASK_MANAGEMENT 0x13
484 #define PQI_REQUEST_IU_RAID_PATH_IO 0x14
485 #define PQI_REQUEST_IU_AIO_PATH_IO 0x15
486 #define PQI_REQUEST_IU_GENERAL_ADMIN 0x60
487 #define PQI_REQUEST_IU_REPORT_VENDOR_EVENT_CONFIG 0x72
488 #define PQI_REQUEST_IU_SET_VENDOR_EVENT_CONFIG 0x73
489 #define PQI_REQUEST_IU_VENDOR_GENERAL 0x75
490 #define PQI_REQUEST_IU_ACKNOWLEDGE_VENDOR_EVENT 0xf6
491
492 #define PQI_RESPONSE_IU_GENERAL_MANAGEMENT 0x81
493 #define PQI_RESPONSE_IU_TASK_MANAGEMENT 0x93
494 #define PQI_RESPONSE_IU_GENERAL_ADMIN 0xe0
495 #define PQI_RESPONSE_IU_RAID_PATH_IO_SUCCESS 0xf0
496 #define PQI_RESPONSE_IU_AIO_PATH_IO_SUCCESS 0xf1
497 #define PQI_RESPONSE_IU_RAID_PATH_IO_ERROR 0xf2
498 #define PQI_RESPONSE_IU_AIO_PATH_IO_ERROR 0xf3
499 #define PQI_RESPONSE_IU_AIO_PATH_DISABLED 0xf4
500 #define PQI_RESPONSE_IU_VENDOR_EVENT 0xf5
501 #define PQI_RESPONSE_IU_VENDOR_GENERAL 0xf7
502
503 #define PQI_GENERAL_ADMIN_FUNCTION_REPORT_DEVICE_CAPABILITY 0x0
504 #define PQI_GENERAL_ADMIN_FUNCTION_CREATE_IQ 0x10
505 #define PQI_GENERAL_ADMIN_FUNCTION_CREATE_OQ 0x11
506 #define PQI_GENERAL_ADMIN_FUNCTION_DELETE_IQ 0x12
507 #define PQI_GENERAL_ADMIN_FUNCTION_DELETE_OQ 0x13
508 #define PQI_GENERAL_ADMIN_FUNCTION_CHANGE_IQ_PROPERTY 0x14
509
510 #define PQI_GENERAL_ADMIN_STATUS_SUCCESS 0x0
511
512 #define PQI_IQ_PROPERTY_IS_AIO_QUEUE 0x1
513
514 #define PQI_GENERAL_ADMIN_IU_LENGTH 0x3c
515 #define PQI_PROTOCOL_SOP 0x0
516
517 #define PQI_DATA_IN_OUT_GOOD 0x0
518 #define PQI_DATA_IN_OUT_UNDERFLOW 0x1
519 #define PQI_DATA_IN_OUT_BUFFER_ERROR 0x40
520 #define PQI_DATA_IN_OUT_BUFFER_OVERFLOW 0x41
521 #define PQI_DATA_IN_OUT_BUFFER_OVERFLOW_DESCRIPTOR_AREA 0x42
522 #define PQI_DATA_IN_OUT_BUFFER_OVERFLOW_BRIDGE 0x43
523 #define PQI_DATA_IN_OUT_PCIE_FABRIC_ERROR 0x60
524 #define PQI_DATA_IN_OUT_PCIE_COMPLETION_TIMEOUT 0x61
525 #define PQI_DATA_IN_OUT_PCIE_COMPLETER_ABORT_RECEIVED 0x62
526 #define PQI_DATA_IN_OUT_PCIE_UNSUPPORTED_REQUEST_RECEIVED 0x63
527 #define PQI_DATA_IN_OUT_PCIE_ECRC_CHECK_FAILED 0x64
528 #define PQI_DATA_IN_OUT_PCIE_UNSUPPORTED_REQUEST 0x65
529 #define PQI_DATA_IN_OUT_PCIE_ACS_VIOLATION 0x66
530 #define PQI_DATA_IN_OUT_PCIE_TLP_PREFIX_BLOCKED 0x67
531 #define PQI_DATA_IN_OUT_PCIE_POISONED_MEMORY_READ 0x6F
532 #define PQI_DATA_IN_OUT_ERROR 0xf0
533 #define PQI_DATA_IN_OUT_PROTOCOL_ERROR 0xf1
534 #define PQI_DATA_IN_OUT_HARDWARE_ERROR 0xf2
535 #define PQI_DATA_IN_OUT_UNSOLICITED_ABORT 0xf3
536 #define PQI_DATA_IN_OUT_ABORTED 0xf4
537 #define PQI_DATA_IN_OUT_TIMEOUT 0xf5
538
539 #define CISS_CMD_STATUS_SUCCESS 0x0
540 #define CISS_CMD_STATUS_TARGET_STATUS 0x1
541 #define CISS_CMD_STATUS_DATA_UNDERRUN 0x2
542 #define CISS_CMD_STATUS_DATA_OVERRUN 0x3
543 #define CISS_CMD_STATUS_INVALID 0x4
544 #define CISS_CMD_STATUS_PROTOCOL_ERROR 0x5
545 #define CISS_CMD_STATUS_HARDWARE_ERROR 0x6
546 #define CISS_CMD_STATUS_CONNECTION_LOST 0x7
547 #define CISS_CMD_STATUS_ABORTED 0x8
548 #define CISS_CMD_STATUS_ABORT_FAILED 0x9
549 #define CISS_CMD_STATUS_UNSOLICITED_ABORT 0xa
550 #define CISS_CMD_STATUS_TIMEOUT 0xb
551 #define CISS_CMD_STATUS_UNABORTABLE 0xc
552 #define CISS_CMD_STATUS_TMF 0xd
553 #define CISS_CMD_STATUS_AIO_DISABLED 0xe
554
555 #define PQI_CMD_STATUS_ABORTED CISS_CMD_STATUS_ABORTED
556
557 #define PQI_NUM_EVENT_QUEUE_ELEMENTS 32
558 #define PQI_EVENT_OQ_ELEMENT_LENGTH sizeof(struct pqi_event_response)
559
560 #define PQI_EVENT_TYPE_HOTPLUG 0x1
561 #define PQI_EVENT_TYPE_HARDWARE 0x2
562 #define PQI_EVENT_TYPE_PHYSICAL_DEVICE 0x4
563 #define PQI_EVENT_TYPE_LOGICAL_DEVICE 0x5
564 #define PQI_EVENT_TYPE_OFA 0xfb
565 #define PQI_EVENT_TYPE_AIO_STATE_CHANGE 0xfd
566 #define PQI_EVENT_TYPE_AIO_CONFIG_CHANGE 0xfe
567
568 #pragma pack()
569
570 #define PQI_ERROR_BUFFER_ELEMENT_LENGTH \
571 sizeof(struct pqi_raid_error_info)
572
573 /* these values are based on our implementation */
574 #define PQI_ADMIN_IQ_NUM_ELEMENTS 8
575 #define PQI_ADMIN_OQ_NUM_ELEMENTS 20
576 #define PQI_ADMIN_IQ_ELEMENT_LENGTH 64
577 #define PQI_ADMIN_OQ_ELEMENT_LENGTH 64
578
579 #define PQI_OPERATIONAL_IQ_ELEMENT_LENGTH 128
580 #define PQI_OPERATIONAL_OQ_ELEMENT_LENGTH 16
581
582 #define PQI_MIN_MSIX_VECTORS 1
583 #define PQI_MAX_MSIX_VECTORS 64
584
585 /* these values are defined by the PQI spec */
586 #define PQI_MAX_NUM_ELEMENTS_ADMIN_QUEUE 255
587 #define PQI_MAX_NUM_ELEMENTS_OPERATIONAL_QUEUE 65535
588 #define PQI_QUEUE_ELEMENT_ARRAY_ALIGNMENT 64
589 #define PQI_QUEUE_ELEMENT_LENGTH_ALIGNMENT 16
590 #define PQI_ADMIN_INDEX_ALIGNMENT 64
591 #define PQI_OPERATIONAL_INDEX_ALIGNMENT 4
592
593 #define PQI_MIN_OPERATIONAL_QUEUE_ID 1
594 #define PQI_MAX_OPERATIONAL_QUEUE_ID 65535
595
596 #define PQI_AIO_SERV_RESPONSE_COMPLETE 0
597 #define PQI_AIO_SERV_RESPONSE_FAILURE 1
598 #define PQI_AIO_SERV_RESPONSE_TMF_COMPLETE 2
599 #define PQI_AIO_SERV_RESPONSE_TMF_SUCCEEDED 3
600 #define PQI_AIO_SERV_RESPONSE_TMF_REJECTED 4
601 #define PQI_AIO_SERV_RESPONSE_TMF_INCORRECT_LUN 5
602
603 #define PQI_AIO_STATUS_IO_ERROR 0x1
604 #define PQI_AIO_STATUS_IO_ABORTED 0x2
605 #define PQI_AIO_STATUS_NO_PATH_TO_DEVICE 0x3
606 #define PQI_AIO_STATUS_INVALID_DEVICE 0x4
607 #define PQI_AIO_STATUS_AIO_PATH_DISABLED 0xe
608 #define PQI_AIO_STATUS_UNDERRUN 0x51
609 #define PQI_AIO_STATUS_OVERRUN 0x75
610
611 typedef u32 pqi_index_t;
612
613 /* SOP data direction flags */
614 #define SOP_NO_DIRECTION_FLAG 0
615 #define SOP_WRITE_FLAG 1 /* host writes data to Data-Out */
616 /* buffer */
617 #define SOP_READ_FLAG 2 /* host receives data from Data-In */
618 /* buffer */
619 #define SOP_BIDIRECTIONAL 3 /* data is transferred from the */
620 /* Data-Out buffer and data is */
621 /* transferred to the Data-In buffer */
622
623 #define SOP_TASK_ATTRIBUTE_SIMPLE 0
624 #define SOP_TASK_ATTRIBUTE_HEAD_OF_QUEUE 1
625 #define SOP_TASK_ATTRIBUTE_ORDERED 2
626 #define SOP_TASK_ATTRIBUTE_ACA 4
627
628 #define SOP_TMF_COMPLETE 0x0
629 #define SOP_TMF_REJECTED 0x4
630 #define SOP_TMF_FUNCTION_SUCCEEDED 0x8
631
632 /* additional CDB bytes usage field codes */
633 #define SOP_ADDITIONAL_CDB_BYTES_0 0 /* 16-byte CDB */
634 #define SOP_ADDITIONAL_CDB_BYTES_4 1 /* 20-byte CDB */
635 #define SOP_ADDITIONAL_CDB_BYTES_8 2 /* 24-byte CDB */
636 #define SOP_ADDITIONAL_CDB_BYTES_12 3 /* 28-byte CDB */
637 #define SOP_ADDITIONAL_CDB_BYTES_16 4 /* 32-byte CDB */
638
639 /*
640 * The purpose of this structure is to obtain proper alignment of objects in
641 * an admin queue pair.
642 */
643 struct pqi_admin_queues_aligned {
644 __aligned(PQI_QUEUE_ELEMENT_ARRAY_ALIGNMENT)
645 u8 iq_element_array[PQI_ADMIN_IQ_ELEMENT_LENGTH]
646 [PQI_ADMIN_IQ_NUM_ELEMENTS];
647 __aligned(PQI_QUEUE_ELEMENT_ARRAY_ALIGNMENT)
648 u8 oq_element_array[PQI_ADMIN_OQ_ELEMENT_LENGTH]
649 [PQI_ADMIN_OQ_NUM_ELEMENTS];
650 __aligned(PQI_ADMIN_INDEX_ALIGNMENT) pqi_index_t iq_ci;
651 __aligned(PQI_ADMIN_INDEX_ALIGNMENT) pqi_index_t oq_pi;
652 };
653
654 struct pqi_admin_queues {
655 void *iq_element_array;
656 void *oq_element_array;
657 pqi_index_t *iq_ci;
658 pqi_index_t __iomem *oq_pi;
659 dma_addr_t iq_element_array_bus_addr;
660 dma_addr_t oq_element_array_bus_addr;
661 dma_addr_t iq_ci_bus_addr;
662 dma_addr_t oq_pi_bus_addr;
663 __le32 __iomem *iq_pi;
664 pqi_index_t iq_pi_copy;
665 __le32 __iomem *oq_ci;
666 pqi_index_t oq_ci_copy;
667 struct task_struct *task;
668 u16 int_msg_num;
669 };
670
671 struct pqi_queue_group {
672 struct pqi_ctrl_info *ctrl_info; /* backpointer */
673 u16 iq_id[2];
674 u16 oq_id;
675 u16 int_msg_num;
676 void *iq_element_array[2];
677 void *oq_element_array;
678 dma_addr_t iq_element_array_bus_addr[2];
679 dma_addr_t oq_element_array_bus_addr;
680 __le32 __iomem *iq_pi[2];
681 pqi_index_t iq_pi_copy[2];
682 pqi_index_t __iomem *iq_ci[2];
683 pqi_index_t __iomem *oq_pi;
684 dma_addr_t iq_ci_bus_addr[2];
685 dma_addr_t oq_pi_bus_addr;
686 __le32 __iomem *oq_ci;
687 pqi_index_t oq_ci_copy;
688 spinlock_t submit_lock[2]; /* protect submission queue */
689 struct list_head request_list[2];
690 };
691
692 struct pqi_event_queue {
693 u16 oq_id;
694 u16 int_msg_num;
695 void *oq_element_array;
696 pqi_index_t __iomem *oq_pi;
697 dma_addr_t oq_element_array_bus_addr;
698 dma_addr_t oq_pi_bus_addr;
699 __le32 __iomem *oq_ci;
700 pqi_index_t oq_ci_copy;
701 };
702
703 #define PQI_DEFAULT_QUEUE_GROUP 0
704 #define PQI_MAX_QUEUE_GROUPS PQI_MAX_MSIX_VECTORS
705
706 struct pqi_encryption_info {
707 u16 data_encryption_key_index;
708 u32 encrypt_tweak_lower;
709 u32 encrypt_tweak_upper;
710 };
711
712 #pragma pack(1)
713
714 #define PQI_CONFIG_TABLE_SIGNATURE "CFGTABLE"
715 #define PQI_CONFIG_TABLE_MAX_LENGTH ((u16)~0)
716
717 /* configuration table section IDs */
718 #define PQI_CONFIG_TABLE_ALL_SECTIONS (-1)
719 #define PQI_CONFIG_TABLE_SECTION_GENERAL_INFO 0
720 #define PQI_CONFIG_TABLE_SECTION_FIRMWARE_FEATURES 1
721 #define PQI_CONFIG_TABLE_SECTION_FIRMWARE_ERRATA 2
722 #define PQI_CONFIG_TABLE_SECTION_DEBUG 3
723 #define PQI_CONFIG_TABLE_SECTION_HEARTBEAT 4
724 #define PQI_CONFIG_TABLE_SECTION_SOFT_RESET 5
725
726 struct pqi_config_table {
727 u8 signature[8]; /* "CFGTABLE" */
728 __le32 first_section_offset; /* offset in bytes from the base */
729 /* address of this table to the */
730 /* first section */
731 };
732
733 struct pqi_config_table_section_header {
734 __le16 section_id; /* as defined by the */
735 /* PQI_CONFIG_TABLE_SECTION_* */
736 /* manifest constants above */
737 __le16 next_section_offset; /* offset in bytes from base */
738 /* address of the table of the */
739 /* next section or 0 if last entry */
740 };
741
742 struct pqi_config_table_general_info {
743 struct pqi_config_table_section_header header;
744 __le32 section_length; /* size of this section in bytes */
745 /* including the section header */
746 __le32 max_outstanding_requests; /* max. outstanding */
747 /* commands supported by */
748 /* the controller */
749 __le32 max_sg_size; /* max. transfer size of a single */
750 /* command */
751 __le32 max_sg_per_request; /* max. number of scatter-gather */
752 /* entries supported in a single */
753 /* command */
754 };
755
756 struct pqi_config_table_firmware_features {
757 struct pqi_config_table_section_header header;
758 __le16 num_elements;
759 u8 features_supported[];
760 /* u8 features_requested_by_host[]; */
761 /* u8 features_enabled[]; */
762 };
763
764 #define PQI_FIRMWARE_FEATURE_OFA 0
765 #define PQI_FIRMWARE_FEATURE_SMP 1
766 #define PQI_FIRMWARE_FEATURE_SOFT_RESET_HANDSHAKE 11
767 #define PQI_FIRMWARE_FEATURE_RAID_IU_TIMEOUT 13
768 #define PQI_FIRMWARE_FEATURE_TMF_IU_TIMEOUT 14
769
770 struct pqi_config_table_debug {
771 struct pqi_config_table_section_header header;
772 __le32 scratchpad;
773 };
774
775 struct pqi_config_table_heartbeat {
776 struct pqi_config_table_section_header header;
777 __le32 heartbeat_counter;
778 };
779
780 struct pqi_config_table_soft_reset {
781 struct pqi_config_table_section_header header;
782 u8 soft_reset_status;
783 };
784
785 #define PQI_SOFT_RESET_INITIATE 0x1
786 #define PQI_SOFT_RESET_ABORT 0x2
787
788 enum pqi_soft_reset_status {
789 RESET_INITIATE_FIRMWARE,
790 RESET_INITIATE_DRIVER,
791 RESET_ABORT,
792 RESET_NORESPONSE,
793 RESET_TIMEDOUT
794 };
795
796 union pqi_reset_register {
797 struct {
798 u32 reset_type : 3;
799 u32 reserved : 2;
800 u32 reset_action : 3;
801 u32 hold_in_pd1 : 1;
802 u32 reserved2 : 23;
803 } bits;
804 u32 all_bits;
805 };
806
807 #define PQI_RESET_ACTION_RESET 0x1
808
809 #define PQI_RESET_TYPE_NO_RESET 0x0
810 #define PQI_RESET_TYPE_SOFT_RESET 0x1
811 #define PQI_RESET_TYPE_FIRM_RESET 0x2
812 #define PQI_RESET_TYPE_HARD_RESET 0x3
813
814 #define PQI_RESET_ACTION_COMPLETED 0x2
815
816 #define PQI_RESET_POLL_INTERVAL_MSECS 100
817
818 #define PQI_MAX_OUTSTANDING_REQUESTS ((u32)~0)
819 #define PQI_MAX_OUTSTANDING_REQUESTS_KDUMP 32
820 #define PQI_MAX_TRANSFER_SIZE (1024U * 1024U)
821 #define PQI_MAX_TRANSFER_SIZE_KDUMP (512 * 1024U)
822
823 #define RAID_MAP_MAX_ENTRIES 1024
824
825 #define PQI_PHYSICAL_DEVICE_BUS 0
826 #define PQI_RAID_VOLUME_BUS 1
827 #define PQI_HBA_BUS 2
828 #define PQI_EXTERNAL_RAID_VOLUME_BUS 3
829 #define PQI_MAX_BUS PQI_EXTERNAL_RAID_VOLUME_BUS
830 #define PQI_VSEP_CISS_BTL 379
831
832 struct report_lun_header {
833 __be32 list_length;
834 u8 flags;
835 u8 reserved[3];
836 };
837
838 /* for flags field of struct report_lun_header */
839 #define CISS_REPORT_LOG_FLAG_UNIQUE_LUN_ID (1 << 0)
840 #define CISS_REPORT_LOG_FLAG_QUEUE_DEPTH (1 << 5)
841 #define CISS_REPORT_LOG_FLAG_DRIVE_TYPE_MIX (1 << 6)
842
843 #define CISS_REPORT_PHYS_FLAG_OTHER (1 << 1)
844
845 struct report_log_lun_extended_entry {
846 u8 lunid[8];
847 u8 volume_id[16];
848 };
849
850 struct report_log_lun_extended {
851 struct report_lun_header header;
852 struct report_log_lun_extended_entry lun_entries[1];
853 };
854
855 struct report_phys_lun_extended_entry {
856 u8 lunid[8];
857 __be64 wwid;
858 u8 device_type;
859 u8 device_flags;
860 u8 lun_count; /* number of LUNs in a multi-LUN device */
861 u8 redundant_paths;
862 u32 aio_handle;
863 };
864
865 /* for device_flags field of struct report_phys_lun_extended_entry */
866 #define CISS_REPORT_PHYS_DEV_FLAG_AIO_ENABLED 0x8
867
868 struct report_phys_lun_extended {
869 struct report_lun_header header;
870 struct report_phys_lun_extended_entry lun_entries[1];
871 };
872
873 struct raid_map_disk_data {
874 u32 aio_handle;
875 u8 xor_mult[2];
876 u8 reserved[2];
877 };
878
879 /* for flags field of RAID map */
880 #define RAID_MAP_ENCRYPTION_ENABLED 0x1
881
882 struct raid_map {
883 __le32 structure_size; /* size of entire structure in bytes */
884 __le32 volume_blk_size; /* bytes / block in the volume */
885 __le64 volume_blk_cnt; /* logical blocks on the volume */
886 u8 phys_blk_shift; /* shift factor to convert between */
887 /* units of logical blocks and */
888 /* physical disk blocks */
889 u8 parity_rotation_shift; /* shift factor to convert between */
890 /* units of logical stripes and */
891 /* physical stripes */
892 __le16 strip_size; /* blocks used on each disk / stripe */
893 __le64 disk_starting_blk; /* first disk block used in volume */
894 __le64 disk_blk_cnt; /* disk blocks used by volume / disk */
895 __le16 data_disks_per_row; /* data disk entries / row in the map */
896 __le16 metadata_disks_per_row; /* mirror/parity disk entries / row */
897 /* in the map */
898 __le16 row_cnt; /* rows in each layout map */
899 __le16 layout_map_count; /* layout maps (1 map per */
900 /* mirror parity group) */
901 __le16 flags;
902 __le16 data_encryption_key_index;
903 u8 reserved[16];
904 struct raid_map_disk_data disk_data[RAID_MAP_MAX_ENTRIES];
905 };
906
907 #pragma pack()
908
909 #define RAID_CTLR_LUNID "\0\0\0\0\0\0\0\0"
910
911 struct pqi_scsi_dev {
912 int devtype; /* as reported by INQUIRY commmand */
913 u8 device_type; /* as reported by */
914 /* BMIC_IDENTIFY_PHYSICAL_DEVICE */
915 /* only valid for devtype = TYPE_DISK */
916 int bus;
917 int target;
918 int lun;
919 u8 scsi3addr[8];
920 __be64 wwid;
921 u8 volume_id[16];
922 u8 is_physical_device : 1;
923 u8 is_external_raid_device : 1;
924 u8 is_expander_smp_device : 1;
925 u8 target_lun_valid : 1;
926 u8 device_gone : 1;
927 u8 new_device : 1;
928 u8 keep_device : 1;
929 u8 volume_offline : 1;
930 u8 rescan : 1;
931 bool aio_enabled; /* only valid for physical disks */
932 bool in_reset;
933 bool in_remove;
934 bool device_offline;
935 u8 vendor[8]; /* bytes 8-15 of inquiry data */
936 u8 model[16]; /* bytes 16-31 of inquiry data */
937 u64 sas_address;
938 u8 raid_level;
939 u16 queue_depth; /* max. queue_depth for this device */
940 u16 advertised_queue_depth;
941 u32 aio_handle;
942 u8 volume_status;
943 u8 active_path_index;
944 u8 path_map;
945 u8 bay;
946 u8 box_index;
947 u8 phys_box_on_bus;
948 u8 phy_connected_dev_type;
949 u8 box[8];
950 u16 phys_connector[8];
951 bool raid_bypass_configured; /* RAID bypass configured */
952 bool raid_bypass_enabled; /* RAID bypass enabled */
953 int offload_to_mirror; /* Send next RAID bypass request */
954 /* to mirror drive. */
955 struct raid_map *raid_map; /* RAID bypass map */
956
957 struct pqi_sas_port *sas_port;
958 struct scsi_device *sdev;
959
960 struct list_head scsi_device_list_entry;
961 struct list_head new_device_list_entry;
962 struct list_head add_list_entry;
963 struct list_head delete_list_entry;
964
965 atomic_t scsi_cmds_outstanding;
966 atomic_t raid_bypass_cnt;
967 };
968
969 /* VPD inquiry pages */
970 #define CISS_VPD_LV_DEVICE_GEOMETRY 0xc1 /* vendor-specific page */
971 #define CISS_VPD_LV_BYPASS_STATUS 0xc2 /* vendor-specific page */
972 #define CISS_VPD_LV_STATUS 0xc3 /* vendor-specific page */
973
974 #define VPD_PAGE (1 << 8)
975
976 #pragma pack(1)
977
978 /* structure for CISS_VPD_LV_STATUS */
979 struct ciss_vpd_logical_volume_status {
980 u8 peripheral_info;
981 u8 page_code;
982 u8 reserved;
983 u8 page_length;
984 u8 volume_status;
985 u8 reserved2[3];
986 __be32 flags;
987 };
988
989 #pragma pack()
990
991 /* constants for volume_status field of ciss_vpd_logical_volume_status */
992 #define CISS_LV_OK 0
993 #define CISS_LV_FAILED 1
994 #define CISS_LV_NOT_CONFIGURED 2
995 #define CISS_LV_DEGRADED 3
996 #define CISS_LV_READY_FOR_RECOVERY 4
997 #define CISS_LV_UNDERGOING_RECOVERY 5
998 #define CISS_LV_WRONG_PHYSICAL_DRIVE_REPLACED 6
999 #define CISS_LV_PHYSICAL_DRIVE_CONNECTION_PROBLEM 7
1000 #define CISS_LV_HARDWARE_OVERHEATING 8
1001 #define CISS_LV_HARDWARE_HAS_OVERHEATED 9
1002 #define CISS_LV_UNDERGOING_EXPANSION 10
1003 #define CISS_LV_NOT_AVAILABLE 11
1004 #define CISS_LV_QUEUED_FOR_EXPANSION 12
1005 #define CISS_LV_DISABLED_SCSI_ID_CONFLICT 13
1006 #define CISS_LV_EJECTED 14
1007 #define CISS_LV_UNDERGOING_ERASE 15
1008 /* state 16 not used */
1009 #define CISS_LV_READY_FOR_PREDICTIVE_SPARE_REBUILD 17
1010 #define CISS_LV_UNDERGOING_RPI 18
1011 #define CISS_LV_PENDING_RPI 19
1012 #define CISS_LV_ENCRYPTED_NO_KEY 20
1013 /* state 21 not used */
1014 #define CISS_LV_UNDERGOING_ENCRYPTION 22
1015 #define CISS_LV_UNDERGOING_ENCRYPTION_REKEYING 23
1016 #define CISS_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER 24
1017 #define CISS_LV_PENDING_ENCRYPTION 25
1018 #define CISS_LV_PENDING_ENCRYPTION_REKEYING 26
1019 #define CISS_LV_NOT_SUPPORTED 27
1020 #define CISS_LV_STATUS_UNAVAILABLE 255
1021
1022 /* constants for flags field of ciss_vpd_logical_volume_status */
1023 #define CISS_LV_FLAGS_NO_HOST_IO 0x1 /* volume not available for */
1024 /* host I/O */
1025
1026 /* for SAS hosts and SAS expanders */
1027 struct pqi_sas_node {
1028 struct device *parent_dev;
1029 struct list_head port_list_head;
1030 };
1031
1032 struct pqi_sas_port {
1033 struct list_head port_list_entry;
1034 u64 sas_address;
1035 struct pqi_scsi_dev *device;
1036 struct sas_port *port;
1037 int next_phy_index;
1038 struct list_head phy_list_head;
1039 struct pqi_sas_node *parent_node;
1040 struct sas_rphy *rphy;
1041 };
1042
1043 struct pqi_sas_phy {
1044 struct list_head phy_list_entry;
1045 struct sas_phy *phy;
1046 struct pqi_sas_port *parent_port;
1047 bool added_to_port;
1048 };
1049
1050 struct pqi_io_request {
1051 atomic_t refcount;
1052 u16 index;
1053 void (*io_complete_callback)(struct pqi_io_request *io_request,
1054 void *context);
1055 void *context;
1056 u8 raid_bypass : 1;
1057 int status;
1058 struct pqi_queue_group *queue_group;
1059 struct scsi_cmnd *scmd;
1060 void *error_info;
1061 struct pqi_sg_descriptor *sg_chain_buffer;
1062 dma_addr_t sg_chain_buffer_dma_handle;
1063 void *iu;
1064 struct list_head request_list_entry;
1065 };
1066
1067 #define PQI_NUM_SUPPORTED_EVENTS 7
1068
1069 struct pqi_event {
1070 bool pending;
1071 u8 event_type;
1072 __le16 event_id;
1073 __le32 additional_event_id;
1074 __le32 ofa_bytes_requested;
1075 __le16 ofa_cancel_reason;
1076 };
1077
1078 #define PQI_RESERVED_IO_SLOTS_LUN_RESET 1
1079 #define PQI_RESERVED_IO_SLOTS_EVENT_ACK PQI_NUM_SUPPORTED_EVENTS
1080 #define PQI_RESERVED_IO_SLOTS_SYNCHRONOUS_REQUESTS 3
1081 #define PQI_RESERVED_IO_SLOTS \
1082 (PQI_RESERVED_IO_SLOTS_LUN_RESET + PQI_RESERVED_IO_SLOTS_EVENT_ACK + \
1083 PQI_RESERVED_IO_SLOTS_SYNCHRONOUS_REQUESTS)
1084
1085 struct pqi_ctrl_info {
1086 unsigned int ctrl_id;
1087 struct pci_dev *pci_dev;
1088 char firmware_version[11];
1089 char serial_number[17];
1090 char model[17];
1091 char vendor[9];
1092 void __iomem *iomem_base;
1093 struct pqi_ctrl_registers __iomem *registers;
1094 struct pqi_device_registers __iomem *pqi_registers;
1095 u32 max_sg_entries;
1096 u32 config_table_offset;
1097 u32 config_table_length;
1098 u16 max_inbound_queues;
1099 u16 max_elements_per_iq;
1100 u16 max_iq_element_length;
1101 u16 max_outbound_queues;
1102 u16 max_elements_per_oq;
1103 u16 max_oq_element_length;
1104 u32 max_transfer_size;
1105 u32 max_outstanding_requests;
1106 u32 max_io_slots;
1107 unsigned int scsi_ml_can_queue;
1108 unsigned short sg_tablesize;
1109 unsigned int max_sectors;
1110 u32 error_buffer_length;
1111 void *error_buffer;
1112 dma_addr_t error_buffer_dma_handle;
1113 size_t sg_chain_buffer_length;
1114 unsigned int num_queue_groups;
1115 u16 max_hw_queue_index;
1116 u16 num_elements_per_iq;
1117 u16 num_elements_per_oq;
1118 u16 max_inbound_iu_length_per_firmware;
1119 u16 max_inbound_iu_length;
1120 unsigned int max_sg_per_iu;
1121 void *admin_queue_memory_base;
1122 u32 admin_queue_memory_length;
1123 dma_addr_t admin_queue_memory_base_dma_handle;
1124 void *queue_memory_base;
1125 u32 queue_memory_length;
1126 dma_addr_t queue_memory_base_dma_handle;
1127 struct pqi_admin_queues admin_queues;
1128 struct pqi_queue_group queue_groups[PQI_MAX_QUEUE_GROUPS];
1129 struct pqi_event_queue event_queue;
1130 enum pqi_irq_mode irq_mode;
1131 int max_msix_vectors;
1132 int num_msix_vectors_enabled;
1133 int num_msix_vectors_initialized;
1134 int event_irq;
1135 struct Scsi_Host *scsi_host;
1136
1137 struct mutex scan_mutex;
1138 struct mutex lun_reset_mutex;
1139 struct mutex ofa_mutex; /* serialize ofa */
1140 bool controller_online;
1141 bool block_requests;
1142 bool block_device_reset;
1143 bool in_ofa;
1144 bool in_shutdown;
1145 u8 inbound_spanning_supported : 1;
1146 u8 outbound_spanning_supported : 1;
1147 u8 pqi_mode_enabled : 1;
1148 u8 pqi_reset_quiesce_supported : 1;
1149 u8 soft_reset_handshake_supported : 1;
1150 u8 raid_iu_timeout_supported: 1;
1151 u8 tmf_iu_timeout_supported: 1;
1152
1153 struct list_head scsi_device_list;
1154 spinlock_t scsi_device_list_lock;
1155
1156 struct delayed_work rescan_work;
1157 struct delayed_work update_time_work;
1158
1159 struct pqi_sas_node *sas_host;
1160 u64 sas_address;
1161
1162 struct pqi_io_request *io_request_pool;
1163 u16 next_io_request_slot;
1164
1165 struct pqi_event events[PQI_NUM_SUPPORTED_EVENTS];
1166 struct work_struct event_work;
1167
1168 atomic_t num_interrupts;
1169 int previous_num_interrupts;
1170 u32 previous_heartbeat_count;
1171 __le32 __iomem *heartbeat_counter;
1172 u8 __iomem *soft_reset_status;
1173 struct timer_list heartbeat_timer;
1174 struct work_struct ctrl_offline_work;
1175
1176 struct semaphore sync_request_sem;
1177 atomic_t num_busy_threads;
1178 atomic_t num_blocked_threads;
1179 wait_queue_head_t block_requests_wait;
1180
1181 struct list_head raid_bypass_retry_list;
1182 spinlock_t raid_bypass_retry_list_lock;
1183 struct work_struct raid_bypass_retry_work;
1184
1185 struct pqi_ofa_memory *pqi_ofa_mem_virt_addr;
1186 dma_addr_t pqi_ofa_mem_dma_handle;
1187 void **pqi_ofa_chunk_virt_addr;
1188 atomic_t sync_cmds_outstanding;
1189 };
1190
1191 enum pqi_ctrl_mode {
1192 SIS_MODE = 0,
1193 PQI_MODE
1194 };
1195
1196 /*
1197 * assume worst case: SATA queue depth of 31 minus 4 internal firmware commands
1198 */
1199 #define PQI_PHYSICAL_DISK_DEFAULT_MAX_QUEUE_DEPTH 27
1200
1201 /* CISS commands */
1202 #define CISS_READ 0xc0
1203 #define CISS_REPORT_LOG 0xc2 /* Report Logical LUNs */
1204 #define CISS_REPORT_PHYS 0xc3 /* Report Physical LUNs */
1205 #define CISS_GET_RAID_MAP 0xc8
1206
1207 /* BMIC commands */
1208 #define BMIC_IDENTIFY_CONTROLLER 0x11
1209 #define BMIC_IDENTIFY_PHYSICAL_DEVICE 0x15
1210 #define BMIC_READ 0x26
1211 #define BMIC_WRITE 0x27
1212 #define BMIC_SENSE_CONTROLLER_PARAMETERS 0x64
1213 #define BMIC_SENSE_SUBSYSTEM_INFORMATION 0x66
1214 #define BMIC_CSMI_PASSTHRU 0x68
1215 #define BMIC_WRITE_HOST_WELLNESS 0xa5
1216 #define BMIC_FLUSH_CACHE 0xc2
1217 #define BMIC_SET_DIAG_OPTIONS 0xf4
1218 #define BMIC_SENSE_DIAG_OPTIONS 0xf5
1219
1220 #define CSMI_CC_SAS_SMP_PASSTHRU 0x17
1221
1222 #define SA_FLUSH_CACHE 0x1
1223
1224 #define MASKED_DEVICE(lunid) ((lunid)[3] & 0xc0)
1225 #define CISS_GET_LEVEL_2_BUS(lunid) ((lunid)[7] & 0x3f)
1226 #define CISS_GET_LEVEL_2_TARGET(lunid) ((lunid)[6])
1227 #define CISS_GET_DRIVE_NUMBER(lunid) \
1228 (((CISS_GET_LEVEL_2_BUS((lunid)) - 1) << 8) + \
1229 CISS_GET_LEVEL_2_TARGET((lunid)))
1230
1231 #define NO_TIMEOUT ((unsigned long) -1)
1232
1233 #pragma pack(1)
1234
1235 struct bmic_identify_controller {
1236 u8 configured_logical_drive_count;
1237 __le32 configuration_signature;
1238 u8 firmware_version[4];
1239 u8 reserved[145];
1240 __le16 extended_logical_unit_count;
1241 u8 reserved1[34];
1242 __le16 firmware_build_number;
1243 u8 reserved2[8];
1244 u8 vendor_id[8];
1245 u8 product_id[16];
1246 u8 reserved3[68];
1247 u8 controller_mode;
1248 u8 reserved4[32];
1249 };
1250
1251 struct bmic_sense_subsystem_info {
1252 u8 reserved[44];
1253 u8 ctrl_serial_number[16];
1254 };
1255
1256 /* constants for device_type field */
1257 #define SA_DEVICE_TYPE_SATA 0x1
1258 #define SA_DEVICE_TYPE_SAS 0x2
1259 #define SA_DEVICE_TYPE_EXPANDER_SMP 0x5
1260 #define SA_DEVICE_TYPE_SES 0x6
1261 #define SA_DEVICE_TYPE_CONTROLLER 0x7
1262 #define SA_DEVICE_TYPE_NVME 0x9
1263
1264 struct bmic_identify_physical_device {
1265 u8 scsi_bus; /* SCSI Bus number on controller */
1266 u8 scsi_id; /* SCSI ID on this bus */
1267 __le16 block_size; /* sector size in bytes */
1268 __le32 total_blocks; /* number for sectors on drive */
1269 __le32 reserved_blocks; /* controller reserved (RIS) */
1270 u8 model[40]; /* Physical Drive Model */
1271 u8 serial_number[40]; /* Drive Serial Number */
1272 u8 firmware_revision[8]; /* drive firmware revision */
1273 u8 scsi_inquiry_bits; /* inquiry byte 7 bits */
1274 u8 compaq_drive_stamp; /* 0 means drive not stamped */
1275 u8 last_failure_reason;
1276 u8 flags;
1277 u8 more_flags;
1278 u8 scsi_lun; /* SCSI LUN for phys drive */
1279 u8 yet_more_flags;
1280 u8 even_more_flags;
1281 __le32 spi_speed_rules;
1282 u8 phys_connector[2]; /* connector number on controller */
1283 u8 phys_box_on_bus; /* phys enclosure this drive resides */
1284 u8 phys_bay_in_box; /* phys drv bay this drive resides */
1285 __le32 rpm; /* drive rotational speed in RPM */
1286 u8 device_type; /* type of drive */
1287 u8 sata_version; /* only valid when device_type = */
1288 /* SA_DEVICE_TYPE_SATA */
1289 __le64 big_total_block_count;
1290 __le64 ris_starting_lba;
1291 __le32 ris_size;
1292 u8 wwid[20];
1293 u8 controller_phy_map[32];
1294 __le16 phy_count;
1295 u8 phy_connected_dev_type[256];
1296 u8 phy_to_drive_bay_num[256];
1297 __le16 phy_to_attached_dev_index[256];
1298 u8 box_index;
1299 u8 reserved;
1300 __le16 extra_physical_drive_flags;
1301 u8 negotiated_link_rate[256];
1302 u8 phy_to_phy_map[256];
1303 u8 redundant_path_present_map;
1304 u8 redundant_path_failure_map;
1305 u8 active_path_number;
1306 __le16 alternate_paths_phys_connector[8];
1307 u8 alternate_paths_phys_box_on_port[8];
1308 u8 multi_lun_device_lun_count;
1309 u8 minimum_good_fw_revision[8];
1310 u8 unique_inquiry_bytes[20];
1311 u8 current_temperature_degrees;
1312 u8 temperature_threshold_degrees;
1313 u8 max_temperature_degrees;
1314 u8 logical_blocks_per_phys_block_exp;
1315 __le16 current_queue_depth_limit;
1316 u8 switch_name[10];
1317 __le16 switch_port;
1318 u8 alternate_paths_switch_name[40];
1319 u8 alternate_paths_switch_port[8];
1320 __le16 power_on_hours;
1321 __le16 percent_endurance_used;
1322 u8 drive_authentication;
1323 u8 smart_carrier_authentication;
1324 u8 smart_carrier_app_fw_version;
1325 u8 smart_carrier_bootloader_fw_version;
1326 u8 sanitize_flags;
1327 u8 encryption_key_flags;
1328 u8 encryption_key_name[64];
1329 __le32 misc_drive_flags;
1330 __le16 dek_index;
1331 __le16 hba_drive_encryption_flags;
1332 __le16 max_overwrite_time;
1333 __le16 max_block_erase_time;
1334 __le16 max_crypto_erase_time;
1335 u8 connector_info[5];
1336 u8 connector_name[8][8];
1337 u8 page_83_identifier[16];
1338 u8 maximum_link_rate[256];
1339 u8 negotiated_physical_link_rate[256];
1340 u8 box_connector_name[8];
1341 u8 padding_to_multiple_of_512[9];
1342 };
1343
1344 struct bmic_smp_request {
1345 u8 frame_type;
1346 u8 function;
1347 u8 allocated_response_length;
1348 u8 request_length;
1349 u8 additional_request_bytes[1016];
1350 };
1351
1352 struct bmic_smp_response {
1353 u8 frame_type;
1354 u8 function;
1355 u8 function_result;
1356 u8 response_length;
1357 u8 additional_response_bytes[1016];
1358 };
1359
1360 struct bmic_csmi_ioctl_header {
1361 __le32 header_length;
1362 u8 signature[8];
1363 __le32 timeout;
1364 __le32 control_code;
1365 __le32 return_code;
1366 __le32 length;
1367 };
1368
1369 struct bmic_csmi_smp_passthru {
1370 u8 phy_identifier;
1371 u8 port_identifier;
1372 u8 connection_rate;
1373 u8 reserved;
1374 __be64 destination_sas_address;
1375 __le32 request_length;
1376 struct bmic_smp_request request;
1377 u8 connection_status;
1378 u8 reserved1[3];
1379 __le32 response_length;
1380 struct bmic_smp_response response;
1381 };
1382
1383 struct bmic_csmi_smp_passthru_buffer {
1384 struct bmic_csmi_ioctl_header ioctl_header;
1385 struct bmic_csmi_smp_passthru parameters;
1386 };
1387
1388 struct bmic_flush_cache {
1389 u8 disable_flag;
1390 u8 system_power_action;
1391 u8 ndu_flush;
1392 u8 shutdown_event;
1393 u8 reserved[28];
1394 };
1395
1396 /* for shutdown_event member of struct bmic_flush_cache */
1397 enum bmic_flush_cache_shutdown_event {
1398 NONE_CACHE_FLUSH_ONLY = 0,
1399 SHUTDOWN = 1,
1400 HIBERNATE = 2,
1401 SUSPEND = 3,
1402 RESTART = 4
1403 };
1404
1405 struct bmic_diag_options {
1406 __le32 options;
1407 };
1408
1409 #pragma pack()
1410
pqi_ctrl_busy(struct pqi_ctrl_info * ctrl_info)1411 static inline void pqi_ctrl_busy(struct pqi_ctrl_info *ctrl_info)
1412 {
1413 atomic_inc(&ctrl_info->num_busy_threads);
1414 }
1415
pqi_ctrl_unbusy(struct pqi_ctrl_info * ctrl_info)1416 static inline void pqi_ctrl_unbusy(struct pqi_ctrl_info *ctrl_info)
1417 {
1418 atomic_dec(&ctrl_info->num_busy_threads);
1419 }
1420
shost_to_hba(struct Scsi_Host * shost)1421 static inline struct pqi_ctrl_info *shost_to_hba(struct Scsi_Host *shost)
1422 {
1423 void *hostdata = shost_priv(shost);
1424
1425 return *((struct pqi_ctrl_info **)hostdata);
1426 }
1427
1428 void pqi_sas_smp_handler(struct bsg_job *job, struct Scsi_Host *shost,
1429 struct sas_rphy *rphy);
1430
1431 int pqi_add_sas_host(struct Scsi_Host *shost, struct pqi_ctrl_info *ctrl_info);
1432 void pqi_delete_sas_host(struct pqi_ctrl_info *ctrl_info);
1433 int pqi_add_sas_device(struct pqi_sas_node *pqi_sas_node,
1434 struct pqi_scsi_dev *device);
1435 void pqi_remove_sas_device(struct pqi_scsi_dev *device);
1436 struct pqi_scsi_dev *pqi_find_device_by_sas_rphy(
1437 struct pqi_ctrl_info *ctrl_info, struct sas_rphy *rphy);
1438 void pqi_prep_for_scsi_done(struct scsi_cmnd *scmd);
1439 int pqi_csmi_smp_passthru(struct pqi_ctrl_info *ctrl_info,
1440 struct bmic_csmi_smp_passthru_buffer *buffer, size_t buffer_length,
1441 struct pqi_raid_error_info *error_info);
1442
1443 extern struct sas_function_template pqi_sas_transport_functions;
1444
1445 #endif /* _SMARTPQI_H */
1446