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1 /*
2  * Copyright 2012 Red Hat Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: Ben Skeggs
23  */
24 #include "priv.h"
25 
26 static const struct nvkm_mc_map
27 gf100_mc_reset[] = {
28 	{ 0x00020000, NVKM_ENGINE_MSPDEC },
29 	{ 0x00008000, NVKM_ENGINE_MSVLD },
30 	{ 0x00002000, NVKM_SUBDEV_PMU, true },
31 	{ 0x00001000, NVKM_ENGINE_GR },
32 	{ 0x00000100, NVKM_ENGINE_FIFO },
33 	{ 0x00000080, NVKM_ENGINE_CE1 },
34 	{ 0x00000040, NVKM_ENGINE_CE0 },
35 	{ 0x00000002, NVKM_ENGINE_MSPPP },
36 	{}
37 };
38 
39 static const struct nvkm_mc_map
40 gf100_mc_intr[] = {
41 	{ 0x04000000, NVKM_ENGINE_DISP },
42 	{ 0x00020000, NVKM_ENGINE_MSPDEC },
43 	{ 0x00008000, NVKM_ENGINE_MSVLD },
44 	{ 0x00001000, NVKM_ENGINE_GR },
45 	{ 0x00000100, NVKM_ENGINE_FIFO },
46 	{ 0x00000040, NVKM_ENGINE_CE1 },
47 	{ 0x00000020, NVKM_ENGINE_CE0 },
48 	{ 0x00000001, NVKM_ENGINE_MSPPP },
49 	{ 0x40000000, NVKM_SUBDEV_IBUS },
50 	{ 0x10000000, NVKM_SUBDEV_BUS },
51 	{ 0x08000000, NVKM_SUBDEV_FB },
52 	{ 0x02000000, NVKM_SUBDEV_LTC },
53 	{ 0x01000000, NVKM_SUBDEV_PMU },
54 	{ 0x00200000, NVKM_SUBDEV_GPIO },
55 	{ 0x00200000, NVKM_SUBDEV_I2C },
56 	{ 0x00100000, NVKM_SUBDEV_TIMER },
57 	{ 0x00040000, NVKM_SUBDEV_THERM },
58 	{ 0x00002000, NVKM_SUBDEV_FB },
59 	{},
60 };
61 
62 void
gf100_mc_intr_unarm(struct nvkm_mc * mc)63 gf100_mc_intr_unarm(struct nvkm_mc *mc)
64 {
65 	struct nvkm_device *device = mc->subdev.device;
66 	nvkm_wr32(device, 0x000140, 0x00000000);
67 	nvkm_wr32(device, 0x000144, 0x00000000);
68 	nvkm_rd32(device, 0x000140);
69 }
70 
71 void
gf100_mc_intr_rearm(struct nvkm_mc * mc)72 gf100_mc_intr_rearm(struct nvkm_mc *mc)
73 {
74 	struct nvkm_device *device = mc->subdev.device;
75 	nvkm_wr32(device, 0x000140, 0x00000001);
76 	nvkm_wr32(device, 0x000144, 0x00000001);
77 }
78 
79 u32
gf100_mc_intr_stat(struct nvkm_mc * mc)80 gf100_mc_intr_stat(struct nvkm_mc *mc)
81 {
82 	struct nvkm_device *device = mc->subdev.device;
83 	u32 intr0 = nvkm_rd32(device, 0x000100);
84 	u32 intr1 = nvkm_rd32(device, 0x000104);
85 	return intr0 | intr1;
86 }
87 
88 void
gf100_mc_intr_mask(struct nvkm_mc * mc,u32 mask,u32 stat)89 gf100_mc_intr_mask(struct nvkm_mc *mc, u32 mask, u32 stat)
90 {
91 	struct nvkm_device *device = mc->subdev.device;
92 	nvkm_mask(device, 0x000640, mask, stat);
93 	nvkm_mask(device, 0x000644, mask, stat);
94 }
95 
96 void
gf100_mc_unk260(struct nvkm_mc * mc,u32 data)97 gf100_mc_unk260(struct nvkm_mc *mc, u32 data)
98 {
99 	nvkm_wr32(mc->subdev.device, 0x000260, data);
100 }
101 
102 static const struct nvkm_mc_func
103 gf100_mc = {
104 	.init = nv50_mc_init,
105 	.intr = gf100_mc_intr,
106 	.intr_unarm = gf100_mc_intr_unarm,
107 	.intr_rearm = gf100_mc_intr_rearm,
108 	.intr_mask = gf100_mc_intr_mask,
109 	.intr_stat = gf100_mc_intr_stat,
110 	.reset = gf100_mc_reset,
111 	.unk260 = gf100_mc_unk260,
112 };
113 
114 int
gf100_mc_new(struct nvkm_device * device,int index,struct nvkm_mc ** pmc)115 gf100_mc_new(struct nvkm_device *device, int index, struct nvkm_mc **pmc)
116 {
117 	return nvkm_mc_new_(&gf100_mc, device, index, pmc);
118 }
119