1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * intel TCO Watchdog Driver
4 *
5 * (c) Copyright 2006-2011 Wim Van Sebroeck <wim@iguana.be>.
6 *
7 * Neither Wim Van Sebroeck nor Iguana vzw. admit liability nor
8 * provide warranty for any of this software. This material is
9 * provided "AS-IS" and at no charge.
10 *
11 * The TCO watchdog is implemented in the following I/O controller hubs:
12 * (See the intel documentation on http://developer.intel.com.)
13 * document number 290655-003, 290677-014: 82801AA (ICH), 82801AB (ICHO)
14 * document number 290687-002, 298242-027: 82801BA (ICH2)
15 * document number 290733-003, 290739-013: 82801CA (ICH3-S)
16 * document number 290716-001, 290718-007: 82801CAM (ICH3-M)
17 * document number 290744-001, 290745-025: 82801DB (ICH4)
18 * document number 252337-001, 252663-008: 82801DBM (ICH4-M)
19 * document number 273599-001, 273645-002: 82801E (C-ICH)
20 * document number 252516-001, 252517-028: 82801EB (ICH5), 82801ER (ICH5R)
21 * document number 300641-004, 300884-013: 6300ESB
22 * document number 301473-002, 301474-026: 82801F (ICH6)
23 * document number 313082-001, 313075-006: 631xESB, 632xESB
24 * document number 307013-003, 307014-024: 82801G (ICH7)
25 * document number 322896-001, 322897-001: NM10
26 * document number 313056-003, 313057-017: 82801H (ICH8)
27 * document number 316972-004, 316973-012: 82801I (ICH9)
28 * document number 319973-002, 319974-002: 82801J (ICH10)
29 * document number 322169-001, 322170-003: 5 Series, 3400 Series (PCH)
30 * document number 320066-003, 320257-008: EP80597 (IICH)
31 * document number 324645-001, 324646-001: Cougar Point (CPT)
32 * document number TBD : Patsburg (PBG)
33 * document number TBD : DH89xxCC
34 * document number TBD : Panther Point
35 * document number TBD : Lynx Point
36 * document number TBD : Lynx Point-LP
37 */
38
39 /*
40 * Includes, defines, variables, module parameters, ...
41 */
42
43 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
44
45 /* Module and version information */
46 #define DRV_NAME "iTCO_wdt"
47 #define DRV_VERSION "1.11"
48
49 /* Includes */
50 #include <linux/acpi.h> /* For ACPI support */
51 #include <linux/bits.h> /* For BIT() */
52 #include <linux/module.h> /* For module specific items */
53 #include <linux/moduleparam.h> /* For new moduleparam's */
54 #include <linux/types.h> /* For standard types (like size_t) */
55 #include <linux/errno.h> /* For the -ENODEV/... values */
56 #include <linux/kernel.h> /* For printk/panic/... */
57 #include <linux/watchdog.h> /* For the watchdog specific items */
58 #include <linux/init.h> /* For __init/__exit/... */
59 #include <linux/fs.h> /* For file operations */
60 #include <linux/platform_device.h> /* For platform_driver framework */
61 #include <linux/pci.h> /* For pci functions */
62 #include <linux/ioport.h> /* For io-port access */
63 #include <linux/spinlock.h> /* For spin_lock/spin_unlock/... */
64 #include <linux/uaccess.h> /* For copy_to_user/put_user/... */
65 #include <linux/io.h> /* For inb/outb/... */
66 #include <linux/platform_data/itco_wdt.h>
67 #include <linux/mfd/intel_pmc_bxt.h>
68
69 #include "iTCO_vendor.h"
70
71 /* Address definitions for the TCO */
72 /* TCO base address */
73 #define TCOBASE(p) ((p)->tco_res->start)
74 /* SMI Control and Enable Register */
75 #define SMI_EN(p) ((p)->smi_res->start)
76
77 #define TCO_RLD(p) (TCOBASE(p) + 0x00) /* TCO Timer Reload/Curr. Value */
78 #define TCOv1_TMR(p) (TCOBASE(p) + 0x01) /* TCOv1 Timer Initial Value*/
79 #define TCO_DAT_IN(p) (TCOBASE(p) + 0x02) /* TCO Data In Register */
80 #define TCO_DAT_OUT(p) (TCOBASE(p) + 0x03) /* TCO Data Out Register */
81 #define TCO1_STS(p) (TCOBASE(p) + 0x04) /* TCO1 Status Register */
82 #define TCO2_STS(p) (TCOBASE(p) + 0x06) /* TCO2 Status Register */
83 #define TCO1_CNT(p) (TCOBASE(p) + 0x08) /* TCO1 Control Register */
84 #define TCO2_CNT(p) (TCOBASE(p) + 0x0a) /* TCO2 Control Register */
85 #define TCOv2_TMR(p) (TCOBASE(p) + 0x12) /* TCOv2 Timer Initial Value*/
86
87 /* internal variables */
88 struct iTCO_wdt_private {
89 struct watchdog_device wddev;
90
91 /* TCO version/generation */
92 unsigned int iTCO_version;
93 struct resource *tco_res;
94 struct resource *smi_res;
95 /*
96 * NO_REBOOT flag is Memory-Mapped GCS register bit 5 (TCO version 2),
97 * or memory-mapped PMC register bit 4 (TCO version 3).
98 */
99 struct resource *gcs_pmc_res;
100 unsigned long __iomem *gcs_pmc;
101 /* the lock for io operations */
102 spinlock_t io_lock;
103 /* the PCI-device */
104 struct pci_dev *pci_dev;
105 /* whether or not the watchdog has been suspended */
106 bool suspended;
107 /* no reboot API private data */
108 void *no_reboot_priv;
109 /* no reboot update function pointer */
110 int (*update_no_reboot_bit)(void *p, bool set);
111 };
112
113 /* module parameters */
114 #define WATCHDOG_TIMEOUT 30 /* 30 sec default heartbeat */
115 static int heartbeat = WATCHDOG_TIMEOUT; /* in seconds */
116 module_param(heartbeat, int, 0);
117 MODULE_PARM_DESC(heartbeat, "Watchdog timeout in seconds. "
118 "5..76 (TCO v1) or 3..614 (TCO v2), default="
119 __MODULE_STRING(WATCHDOG_TIMEOUT) ")");
120
121 static bool nowayout = WATCHDOG_NOWAYOUT;
122 module_param(nowayout, bool, 0);
123 MODULE_PARM_DESC(nowayout,
124 "Watchdog cannot be stopped once started (default="
125 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
126
127 static int turn_SMI_watchdog_clear_off = 1;
128 module_param(turn_SMI_watchdog_clear_off, int, 0);
129 MODULE_PARM_DESC(turn_SMI_watchdog_clear_off,
130 "Turn off SMI clearing watchdog (depends on TCO-version)(default=1)");
131
132 /*
133 * Some TCO specific functions
134 */
135
136 /*
137 * The iTCO v1 and v2's internal timer is stored as ticks which decrement
138 * every 0.6 seconds. v3's internal timer is stored as seconds (some
139 * datasheets incorrectly state 0.6 seconds).
140 */
seconds_to_ticks(struct iTCO_wdt_private * p,int secs)141 static inline unsigned int seconds_to_ticks(struct iTCO_wdt_private *p,
142 int secs)
143 {
144 return p->iTCO_version == 3 ? secs : (secs * 10) / 6;
145 }
146
ticks_to_seconds(struct iTCO_wdt_private * p,int ticks)147 static inline unsigned int ticks_to_seconds(struct iTCO_wdt_private *p,
148 int ticks)
149 {
150 return p->iTCO_version == 3 ? ticks : (ticks * 6) / 10;
151 }
152
no_reboot_bit(struct iTCO_wdt_private * p)153 static inline u32 no_reboot_bit(struct iTCO_wdt_private *p)
154 {
155 u32 enable_bit;
156
157 switch (p->iTCO_version) {
158 case 5:
159 case 3:
160 enable_bit = 0x00000010;
161 break;
162 case 2:
163 enable_bit = 0x00000020;
164 break;
165 case 4:
166 case 1:
167 default:
168 enable_bit = 0x00000002;
169 break;
170 }
171
172 return enable_bit;
173 }
174
update_no_reboot_bit_def(void * priv,bool set)175 static int update_no_reboot_bit_def(void *priv, bool set)
176 {
177 return 0;
178 }
179
update_no_reboot_bit_pci(void * priv,bool set)180 static int update_no_reboot_bit_pci(void *priv, bool set)
181 {
182 struct iTCO_wdt_private *p = priv;
183 u32 val32 = 0, newval32 = 0;
184
185 pci_read_config_dword(p->pci_dev, 0xd4, &val32);
186 if (set)
187 val32 |= no_reboot_bit(p);
188 else
189 val32 &= ~no_reboot_bit(p);
190 pci_write_config_dword(p->pci_dev, 0xd4, val32);
191 pci_read_config_dword(p->pci_dev, 0xd4, &newval32);
192
193 /* make sure the update is successful */
194 if (val32 != newval32)
195 return -EIO;
196
197 return 0;
198 }
199
update_no_reboot_bit_mem(void * priv,bool set)200 static int update_no_reboot_bit_mem(void *priv, bool set)
201 {
202 struct iTCO_wdt_private *p = priv;
203 u32 val32 = 0, newval32 = 0;
204
205 val32 = readl(p->gcs_pmc);
206 if (set)
207 val32 |= no_reboot_bit(p);
208 else
209 val32 &= ~no_reboot_bit(p);
210 writel(val32, p->gcs_pmc);
211 newval32 = readl(p->gcs_pmc);
212
213 /* make sure the update is successful */
214 if (val32 != newval32)
215 return -EIO;
216
217 return 0;
218 }
219
update_no_reboot_bit_cnt(void * priv,bool set)220 static int update_no_reboot_bit_cnt(void *priv, bool set)
221 {
222 struct iTCO_wdt_private *p = priv;
223 u16 val, newval;
224
225 val = inw(TCO1_CNT(p));
226 if (set)
227 val |= BIT(0);
228 else
229 val &= ~BIT(0);
230 outw(val, TCO1_CNT(p));
231 newval = inw(TCO1_CNT(p));
232
233 /* make sure the update is successful */
234 return val != newval ? -EIO : 0;
235 }
236
update_no_reboot_bit_pmc(void * priv,bool set)237 static int update_no_reboot_bit_pmc(void *priv, bool set)
238 {
239 struct intel_pmc_dev *pmc = priv;
240 u32 bits = PMC_CFG_NO_REBOOT_EN;
241 u32 value = set ? bits : 0;
242
243 return intel_pmc_gcr_update(pmc, PMC_GCR_PMC_CFG_REG, bits, value);
244 }
245
iTCO_wdt_no_reboot_bit_setup(struct iTCO_wdt_private * p,struct platform_device * pdev,struct itco_wdt_platform_data * pdata)246 static void iTCO_wdt_no_reboot_bit_setup(struct iTCO_wdt_private *p,
247 struct platform_device *pdev,
248 struct itco_wdt_platform_data *pdata)
249 {
250 if (pdata->no_reboot_use_pmc) {
251 struct intel_pmc_dev *pmc = dev_get_drvdata(pdev->dev.parent);
252
253 p->update_no_reboot_bit = update_no_reboot_bit_pmc;
254 p->no_reboot_priv = pmc;
255 return;
256 }
257
258 if (p->iTCO_version >= 6)
259 p->update_no_reboot_bit = update_no_reboot_bit_cnt;
260 else if (p->iTCO_version >= 2)
261 p->update_no_reboot_bit = update_no_reboot_bit_mem;
262 else if (p->iTCO_version == 1)
263 p->update_no_reboot_bit = update_no_reboot_bit_pci;
264 else
265 p->update_no_reboot_bit = update_no_reboot_bit_def;
266
267 p->no_reboot_priv = p;
268 }
269
iTCO_wdt_start(struct watchdog_device * wd_dev)270 static int iTCO_wdt_start(struct watchdog_device *wd_dev)
271 {
272 struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev);
273 unsigned int val;
274
275 spin_lock(&p->io_lock);
276
277 iTCO_vendor_pre_start(p->smi_res, wd_dev->timeout);
278
279 /* disable chipset's NO_REBOOT bit */
280 if (p->update_no_reboot_bit(p->no_reboot_priv, false)) {
281 spin_unlock(&p->io_lock);
282 pr_err("failed to reset NO_REBOOT flag, reboot disabled by hardware/BIOS\n");
283 return -EIO;
284 }
285
286 /* Force the timer to its reload value by writing to the TCO_RLD
287 register */
288 if (p->iTCO_version >= 2)
289 outw(0x01, TCO_RLD(p));
290 else if (p->iTCO_version == 1)
291 outb(0x01, TCO_RLD(p));
292
293 /* Bit 11: TCO Timer Halt -> 0 = The TCO timer is enabled to count */
294 val = inw(TCO1_CNT(p));
295 val &= 0xf7ff;
296 outw(val, TCO1_CNT(p));
297 val = inw(TCO1_CNT(p));
298 spin_unlock(&p->io_lock);
299
300 if (val & 0x0800)
301 return -1;
302 return 0;
303 }
304
iTCO_wdt_stop(struct watchdog_device * wd_dev)305 static int iTCO_wdt_stop(struct watchdog_device *wd_dev)
306 {
307 struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev);
308 unsigned int val;
309
310 spin_lock(&p->io_lock);
311
312 iTCO_vendor_pre_stop(p->smi_res);
313
314 /* Bit 11: TCO Timer Halt -> 1 = The TCO timer is disabled */
315 val = inw(TCO1_CNT(p));
316 val |= 0x0800;
317 outw(val, TCO1_CNT(p));
318 val = inw(TCO1_CNT(p));
319
320 /* Set the NO_REBOOT bit to prevent later reboots, just for sure */
321 p->update_no_reboot_bit(p->no_reboot_priv, true);
322
323 spin_unlock(&p->io_lock);
324
325 if ((val & 0x0800) == 0)
326 return -1;
327 return 0;
328 }
329
iTCO_wdt_ping(struct watchdog_device * wd_dev)330 static int iTCO_wdt_ping(struct watchdog_device *wd_dev)
331 {
332 struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev);
333
334 spin_lock(&p->io_lock);
335
336 /* Reload the timer by writing to the TCO Timer Counter register */
337 if (p->iTCO_version >= 2) {
338 outw(0x01, TCO_RLD(p));
339 } else if (p->iTCO_version == 1) {
340 /* Reset the timeout status bit so that the timer
341 * needs to count down twice again before rebooting */
342 outw(0x0008, TCO1_STS(p)); /* write 1 to clear bit */
343
344 outb(0x01, TCO_RLD(p));
345 }
346
347 spin_unlock(&p->io_lock);
348 return 0;
349 }
350
iTCO_wdt_set_timeout(struct watchdog_device * wd_dev,unsigned int t)351 static int iTCO_wdt_set_timeout(struct watchdog_device *wd_dev, unsigned int t)
352 {
353 struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev);
354 unsigned int val16;
355 unsigned char val8;
356 unsigned int tmrval;
357
358 tmrval = seconds_to_ticks(p, t);
359
360 /* For TCO v1 the timer counts down twice before rebooting */
361 if (p->iTCO_version == 1)
362 tmrval /= 2;
363
364 /* from the specs: */
365 /* "Values of 0h-3h are ignored and should not be attempted" */
366 if (tmrval < 0x04)
367 return -EINVAL;
368 if ((p->iTCO_version >= 2 && tmrval > 0x3ff) ||
369 (p->iTCO_version == 1 && tmrval > 0x03f))
370 return -EINVAL;
371
372 /* Write new heartbeat to watchdog */
373 if (p->iTCO_version >= 2) {
374 spin_lock(&p->io_lock);
375 val16 = inw(TCOv2_TMR(p));
376 val16 &= 0xfc00;
377 val16 |= tmrval;
378 outw(val16, TCOv2_TMR(p));
379 val16 = inw(TCOv2_TMR(p));
380 spin_unlock(&p->io_lock);
381
382 if ((val16 & 0x3ff) != tmrval)
383 return -EINVAL;
384 } else if (p->iTCO_version == 1) {
385 spin_lock(&p->io_lock);
386 val8 = inb(TCOv1_TMR(p));
387 val8 &= 0xc0;
388 val8 |= (tmrval & 0xff);
389 outb(val8, TCOv1_TMR(p));
390 val8 = inb(TCOv1_TMR(p));
391 spin_unlock(&p->io_lock);
392
393 if ((val8 & 0x3f) != tmrval)
394 return -EINVAL;
395 }
396
397 wd_dev->timeout = t;
398 return 0;
399 }
400
iTCO_wdt_get_timeleft(struct watchdog_device * wd_dev)401 static unsigned int iTCO_wdt_get_timeleft(struct watchdog_device *wd_dev)
402 {
403 struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev);
404 unsigned int val16;
405 unsigned char val8;
406 unsigned int time_left = 0;
407
408 /* read the TCO Timer */
409 if (p->iTCO_version >= 2) {
410 spin_lock(&p->io_lock);
411 val16 = inw(TCO_RLD(p));
412 val16 &= 0x3ff;
413 spin_unlock(&p->io_lock);
414
415 time_left = ticks_to_seconds(p, val16);
416 } else if (p->iTCO_version == 1) {
417 spin_lock(&p->io_lock);
418 val8 = inb(TCO_RLD(p));
419 val8 &= 0x3f;
420 if (!(inw(TCO1_STS(p)) & 0x0008))
421 val8 += (inb(TCOv1_TMR(p)) & 0x3f);
422 spin_unlock(&p->io_lock);
423
424 time_left = ticks_to_seconds(p, val8);
425 }
426 return time_left;
427 }
428
429 /* Returns true if the watchdog was running */
iTCO_wdt_set_running(struct iTCO_wdt_private * p)430 static bool iTCO_wdt_set_running(struct iTCO_wdt_private *p)
431 {
432 u16 val;
433
434 /* Bit 11: TCO Timer Halt -> 0 = The TCO timer is enabled */
435 val = inw(TCO1_CNT(p));
436 if (!(val & BIT(11))) {
437 set_bit(WDOG_HW_RUNNING, &p->wddev.status);
438 return true;
439 }
440 return false;
441 }
442
443 /*
444 * Kernel Interfaces
445 */
446
447 static const struct watchdog_info ident = {
448 .options = WDIOF_SETTIMEOUT |
449 WDIOF_KEEPALIVEPING |
450 WDIOF_MAGICCLOSE,
451 .firmware_version = 0,
452 .identity = DRV_NAME,
453 };
454
455 static const struct watchdog_ops iTCO_wdt_ops = {
456 .owner = THIS_MODULE,
457 .start = iTCO_wdt_start,
458 .stop = iTCO_wdt_stop,
459 .ping = iTCO_wdt_ping,
460 .set_timeout = iTCO_wdt_set_timeout,
461 .get_timeleft = iTCO_wdt_get_timeleft,
462 };
463
464 /*
465 * Init & exit routines
466 */
467
iTCO_wdt_probe(struct platform_device * pdev)468 static int iTCO_wdt_probe(struct platform_device *pdev)
469 {
470 struct device *dev = &pdev->dev;
471 struct itco_wdt_platform_data *pdata = dev_get_platdata(dev);
472 struct iTCO_wdt_private *p;
473 unsigned long val32;
474 int ret;
475
476 if (!pdata)
477 return -ENODEV;
478
479 p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL);
480 if (!p)
481 return -ENOMEM;
482
483 spin_lock_init(&p->io_lock);
484
485 p->tco_res = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_IO_TCO);
486 if (!p->tco_res)
487 return -ENODEV;
488
489 p->iTCO_version = pdata->version;
490 p->pci_dev = to_pci_dev(dev->parent);
491
492 p->smi_res = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_IO_SMI);
493 if (p->smi_res) {
494 /* The TCO logic uses the TCO_EN bit in the SMI_EN register */
495 if (!devm_request_region(dev, p->smi_res->start,
496 resource_size(p->smi_res),
497 pdev->name)) {
498 pr_err("I/O address 0x%04llx already in use, device disabled\n",
499 (u64)SMI_EN(p));
500 return -EBUSY;
501 }
502 } else if (iTCO_vendorsupport ||
503 turn_SMI_watchdog_clear_off >= p->iTCO_version) {
504 pr_err("SMI I/O resource is missing\n");
505 return -ENODEV;
506 }
507
508 iTCO_wdt_no_reboot_bit_setup(p, pdev, pdata);
509
510 /*
511 * Get the Memory-Mapped GCS or PMC register, we need it for the
512 * NO_REBOOT flag (TCO v2 and v3).
513 */
514 if (p->iTCO_version >= 2 && p->iTCO_version < 6 &&
515 !pdata->no_reboot_use_pmc) {
516 p->gcs_pmc_res = platform_get_resource(pdev,
517 IORESOURCE_MEM,
518 ICH_RES_MEM_GCS_PMC);
519 p->gcs_pmc = devm_ioremap_resource(dev, p->gcs_pmc_res);
520 if (IS_ERR(p->gcs_pmc))
521 return PTR_ERR(p->gcs_pmc);
522 }
523
524 /* Check chipset's NO_REBOOT bit */
525 if (p->update_no_reboot_bit(p->no_reboot_priv, false) &&
526 iTCO_vendor_check_noreboot_on()) {
527 pr_info("unable to reset NO_REBOOT flag, device disabled by hardware/BIOS\n");
528 return -ENODEV; /* Cannot reset NO_REBOOT bit */
529 }
530
531 if (turn_SMI_watchdog_clear_off >= p->iTCO_version) {
532 /*
533 * Bit 13: TCO_EN -> 0
534 * Disables TCO logic generating an SMI#
535 */
536 val32 = inl(SMI_EN(p));
537 val32 &= 0xffffdfff; /* Turn off SMI clearing watchdog */
538 outl(val32, SMI_EN(p));
539 }
540
541 if (!devm_request_region(dev, p->tco_res->start,
542 resource_size(p->tco_res),
543 pdev->name)) {
544 pr_err("I/O address 0x%04llx already in use, device disabled\n",
545 (u64)TCOBASE(p));
546 return -EBUSY;
547 }
548
549 pr_info("Found a %s TCO device (Version=%d, TCOBASE=0x%04llx)\n",
550 pdata->name, pdata->version, (u64)TCOBASE(p));
551
552 /* Clear out the (probably old) status */
553 switch (p->iTCO_version) {
554 case 6:
555 case 5:
556 case 4:
557 outw(0x0008, TCO1_STS(p)); /* Clear the Time Out Status bit */
558 outw(0x0002, TCO2_STS(p)); /* Clear SECOND_TO_STS bit */
559 break;
560 case 3:
561 outl(0x20008, TCO1_STS(p));
562 break;
563 case 2:
564 case 1:
565 default:
566 outw(0x0008, TCO1_STS(p)); /* Clear the Time Out Status bit */
567 outw(0x0002, TCO2_STS(p)); /* Clear SECOND_TO_STS bit */
568 outw(0x0004, TCO2_STS(p)); /* Clear BOOT_STS bit */
569 break;
570 }
571
572 p->wddev.info = &ident,
573 p->wddev.ops = &iTCO_wdt_ops,
574 p->wddev.bootstatus = 0;
575 p->wddev.timeout = WATCHDOG_TIMEOUT;
576 watchdog_set_nowayout(&p->wddev, nowayout);
577 p->wddev.parent = dev;
578
579 watchdog_set_drvdata(&p->wddev, p);
580 platform_set_drvdata(pdev, p);
581
582 if (!iTCO_wdt_set_running(p)) {
583 /*
584 * If the watchdog was not running set NO_REBOOT now to
585 * prevent later reboots.
586 */
587 p->update_no_reboot_bit(p->no_reboot_priv, true);
588 }
589
590 /* Check that the heartbeat value is within it's range;
591 if not reset to the default */
592 if (iTCO_wdt_set_timeout(&p->wddev, heartbeat)) {
593 iTCO_wdt_set_timeout(&p->wddev, WATCHDOG_TIMEOUT);
594 pr_info("timeout value out of range, using %d\n",
595 WATCHDOG_TIMEOUT);
596 }
597
598 watchdog_stop_on_reboot(&p->wddev);
599 watchdog_stop_on_unregister(&p->wddev);
600 ret = devm_watchdog_register_device(dev, &p->wddev);
601 if (ret != 0) {
602 pr_err("cannot register watchdog device (err=%d)\n", ret);
603 return ret;
604 }
605
606 pr_info("initialized. heartbeat=%d sec (nowayout=%d)\n",
607 heartbeat, nowayout);
608
609 return 0;
610 }
611
612 #ifdef CONFIG_PM_SLEEP
613 /*
614 * Suspend-to-idle requires this, because it stops the ticks and timekeeping, so
615 * the watchdog cannot be pinged while in that state. In ACPI sleep states the
616 * watchdog is stopped by the platform firmware.
617 */
618
619 #ifdef CONFIG_ACPI
need_suspend(void)620 static inline bool need_suspend(void)
621 {
622 return acpi_target_system_state() == ACPI_STATE_S0;
623 }
624 #else
need_suspend(void)625 static inline bool need_suspend(void) { return true; }
626 #endif
627
iTCO_wdt_suspend_noirq(struct device * dev)628 static int iTCO_wdt_suspend_noirq(struct device *dev)
629 {
630 struct iTCO_wdt_private *p = dev_get_drvdata(dev);
631 int ret = 0;
632
633 p->suspended = false;
634 if (watchdog_active(&p->wddev) && need_suspend()) {
635 ret = iTCO_wdt_stop(&p->wddev);
636 if (!ret)
637 p->suspended = true;
638 }
639 return ret;
640 }
641
iTCO_wdt_resume_noirq(struct device * dev)642 static int iTCO_wdt_resume_noirq(struct device *dev)
643 {
644 struct iTCO_wdt_private *p = dev_get_drvdata(dev);
645
646 if (p->suspended)
647 iTCO_wdt_start(&p->wddev);
648
649 return 0;
650 }
651
652 static const struct dev_pm_ops iTCO_wdt_pm = {
653 .suspend_noirq = iTCO_wdt_suspend_noirq,
654 .resume_noirq = iTCO_wdt_resume_noirq,
655 };
656
657 #define ITCO_WDT_PM_OPS (&iTCO_wdt_pm)
658 #else
659 #define ITCO_WDT_PM_OPS NULL
660 #endif /* CONFIG_PM_SLEEP */
661
662 static struct platform_driver iTCO_wdt_driver = {
663 .probe = iTCO_wdt_probe,
664 .driver = {
665 .name = DRV_NAME,
666 .pm = ITCO_WDT_PM_OPS,
667 },
668 };
669
iTCO_wdt_init_module(void)670 static int __init iTCO_wdt_init_module(void)
671 {
672 pr_info("Intel TCO WatchDog Timer Driver v%s\n", DRV_VERSION);
673
674 return platform_driver_register(&iTCO_wdt_driver);
675 }
676
iTCO_wdt_cleanup_module(void)677 static void __exit iTCO_wdt_cleanup_module(void)
678 {
679 platform_driver_unregister(&iTCO_wdt_driver);
680 pr_info("Watchdog Module Unloaded\n");
681 }
682
683 module_init(iTCO_wdt_init_module);
684 module_exit(iTCO_wdt_cleanup_module);
685
686 MODULE_AUTHOR("Wim Van Sebroeck <wim@iguana.be>");
687 MODULE_DESCRIPTION("Intel TCO WatchDog Timer Driver");
688 MODULE_VERSION(DRV_VERSION);
689 MODULE_LICENSE("GPL");
690 MODULE_ALIAS("platform:" DRV_NAME);
691