1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2019 Intel Corporation. All rights rsvd. */
3 #include <linux/init.h>
4 #include <linux/kernel.h>
5 #include <linux/module.h>
6 #include <linux/pci.h>
7 #include <linux/io-64-nonatomic-lo-hi.h>
8 #include <linux/dmaengine.h>
9 #include <linux/irq.h>
10 #include <linux/msi.h>
11 #include <uapi/linux/idxd.h>
12 #include "../dmaengine.h"
13 #include "idxd.h"
14 #include "registers.h"
15
16 static void idxd_cmd_exec(struct idxd_device *idxd, int cmd_code, u32 operand,
17 u32 *status);
18
19 /* Interrupt control bits */
idxd_mask_msix_vector(struct idxd_device * idxd,int vec_id)20 void idxd_mask_msix_vector(struct idxd_device *idxd, int vec_id)
21 {
22 struct irq_data *data = irq_get_irq_data(idxd->msix_entries[vec_id].vector);
23
24 pci_msi_mask_irq(data);
25 }
26
idxd_mask_msix_vectors(struct idxd_device * idxd)27 void idxd_mask_msix_vectors(struct idxd_device *idxd)
28 {
29 struct pci_dev *pdev = idxd->pdev;
30 int msixcnt = pci_msix_vec_count(pdev);
31 int i;
32
33 for (i = 0; i < msixcnt; i++)
34 idxd_mask_msix_vector(idxd, i);
35 }
36
idxd_unmask_msix_vector(struct idxd_device * idxd,int vec_id)37 void idxd_unmask_msix_vector(struct idxd_device *idxd, int vec_id)
38 {
39 struct irq_data *data = irq_get_irq_data(idxd->msix_entries[vec_id].vector);
40
41 pci_msi_unmask_irq(data);
42 }
43
idxd_unmask_error_interrupts(struct idxd_device * idxd)44 void idxd_unmask_error_interrupts(struct idxd_device *idxd)
45 {
46 union genctrl_reg genctrl;
47
48 genctrl.bits = ioread32(idxd->reg_base + IDXD_GENCTRL_OFFSET);
49 genctrl.softerr_int_en = 1;
50 iowrite32(genctrl.bits, idxd->reg_base + IDXD_GENCTRL_OFFSET);
51 }
52
idxd_mask_error_interrupts(struct idxd_device * idxd)53 void idxd_mask_error_interrupts(struct idxd_device *idxd)
54 {
55 union genctrl_reg genctrl;
56
57 genctrl.bits = ioread32(idxd->reg_base + IDXD_GENCTRL_OFFSET);
58 genctrl.softerr_int_en = 0;
59 iowrite32(genctrl.bits, idxd->reg_base + IDXD_GENCTRL_OFFSET);
60 }
61
free_hw_descs(struct idxd_wq * wq)62 static void free_hw_descs(struct idxd_wq *wq)
63 {
64 int i;
65
66 for (i = 0; i < wq->num_descs; i++)
67 kfree(wq->hw_descs[i]);
68
69 kfree(wq->hw_descs);
70 }
71
alloc_hw_descs(struct idxd_wq * wq,int num)72 static int alloc_hw_descs(struct idxd_wq *wq, int num)
73 {
74 struct device *dev = &wq->idxd->pdev->dev;
75 int i;
76 int node = dev_to_node(dev);
77
78 wq->hw_descs = kcalloc_node(num, sizeof(struct dsa_hw_desc *),
79 GFP_KERNEL, node);
80 if (!wq->hw_descs)
81 return -ENOMEM;
82
83 for (i = 0; i < num; i++) {
84 wq->hw_descs[i] = kzalloc_node(sizeof(*wq->hw_descs[i]),
85 GFP_KERNEL, node);
86 if (!wq->hw_descs[i]) {
87 free_hw_descs(wq);
88 return -ENOMEM;
89 }
90 }
91
92 return 0;
93 }
94
free_descs(struct idxd_wq * wq)95 static void free_descs(struct idxd_wq *wq)
96 {
97 int i;
98
99 for (i = 0; i < wq->num_descs; i++)
100 kfree(wq->descs[i]);
101
102 kfree(wq->descs);
103 }
104
alloc_descs(struct idxd_wq * wq,int num)105 static int alloc_descs(struct idxd_wq *wq, int num)
106 {
107 struct device *dev = &wq->idxd->pdev->dev;
108 int i;
109 int node = dev_to_node(dev);
110
111 wq->descs = kcalloc_node(num, sizeof(struct idxd_desc *),
112 GFP_KERNEL, node);
113 if (!wq->descs)
114 return -ENOMEM;
115
116 for (i = 0; i < num; i++) {
117 wq->descs[i] = kzalloc_node(sizeof(*wq->descs[i]),
118 GFP_KERNEL, node);
119 if (!wq->descs[i]) {
120 free_descs(wq);
121 return -ENOMEM;
122 }
123 }
124
125 return 0;
126 }
127
128 /* WQ control bits */
idxd_wq_alloc_resources(struct idxd_wq * wq)129 int idxd_wq_alloc_resources(struct idxd_wq *wq)
130 {
131 struct idxd_device *idxd = wq->idxd;
132 struct device *dev = &idxd->pdev->dev;
133 int rc, num_descs, i;
134
135 if (wq->type != IDXD_WQT_KERNEL)
136 return 0;
137
138 wq->num_descs = wq->size;
139 num_descs = wq->size;
140
141 rc = alloc_hw_descs(wq, num_descs);
142 if (rc < 0)
143 return rc;
144
145 wq->compls_size = num_descs * sizeof(struct dsa_completion_record);
146 wq->compls = dma_alloc_coherent(dev, wq->compls_size,
147 &wq->compls_addr, GFP_KERNEL);
148 if (!wq->compls) {
149 rc = -ENOMEM;
150 goto fail_alloc_compls;
151 }
152
153 rc = alloc_descs(wq, num_descs);
154 if (rc < 0)
155 goto fail_alloc_descs;
156
157 rc = sbitmap_queue_init_node(&wq->sbq, num_descs, -1, false, GFP_KERNEL,
158 dev_to_node(dev));
159 if (rc < 0)
160 goto fail_sbitmap_init;
161
162 for (i = 0; i < num_descs; i++) {
163 struct idxd_desc *desc = wq->descs[i];
164
165 desc->hw = wq->hw_descs[i];
166 desc->completion = &wq->compls[i];
167 desc->compl_dma = wq->compls_addr +
168 sizeof(struct dsa_completion_record) * i;
169 desc->id = i;
170 desc->wq = wq;
171 desc->cpu = -1;
172 }
173
174 return 0;
175
176 fail_sbitmap_init:
177 free_descs(wq);
178 fail_alloc_descs:
179 dma_free_coherent(dev, wq->compls_size, wq->compls, wq->compls_addr);
180 fail_alloc_compls:
181 free_hw_descs(wq);
182 return rc;
183 }
184
idxd_wq_free_resources(struct idxd_wq * wq)185 void idxd_wq_free_resources(struct idxd_wq *wq)
186 {
187 struct device *dev = &wq->idxd->pdev->dev;
188
189 if (wq->type != IDXD_WQT_KERNEL)
190 return;
191
192 free_hw_descs(wq);
193 free_descs(wq);
194 dma_free_coherent(dev, wq->compls_size, wq->compls, wq->compls_addr);
195 sbitmap_queue_free(&wq->sbq);
196 }
197
idxd_wq_enable(struct idxd_wq * wq)198 int idxd_wq_enable(struct idxd_wq *wq)
199 {
200 struct idxd_device *idxd = wq->idxd;
201 struct device *dev = &idxd->pdev->dev;
202 u32 status;
203
204 if (wq->state == IDXD_WQ_ENABLED) {
205 dev_dbg(dev, "WQ %d already enabled\n", wq->id);
206 return -ENXIO;
207 }
208
209 idxd_cmd_exec(idxd, IDXD_CMD_ENABLE_WQ, wq->id, &status);
210
211 if (status != IDXD_CMDSTS_SUCCESS &&
212 status != IDXD_CMDSTS_ERR_WQ_ENABLED) {
213 dev_dbg(dev, "WQ enable failed: %#x\n", status);
214 return -ENXIO;
215 }
216
217 wq->state = IDXD_WQ_ENABLED;
218 dev_dbg(dev, "WQ %d enabled\n", wq->id);
219 return 0;
220 }
221
idxd_wq_disable(struct idxd_wq * wq)222 int idxd_wq_disable(struct idxd_wq *wq)
223 {
224 struct idxd_device *idxd = wq->idxd;
225 struct device *dev = &idxd->pdev->dev;
226 u32 status, operand;
227
228 dev_dbg(dev, "Disabling WQ %d\n", wq->id);
229
230 if (wq->state != IDXD_WQ_ENABLED) {
231 dev_dbg(dev, "WQ %d in wrong state: %d\n", wq->id, wq->state);
232 return 0;
233 }
234
235 operand = BIT(wq->id % 16) | ((wq->id / 16) << 16);
236 idxd_cmd_exec(idxd, IDXD_CMD_DISABLE_WQ, operand, &status);
237
238 if (status != IDXD_CMDSTS_SUCCESS) {
239 dev_dbg(dev, "WQ disable failed: %#x\n", status);
240 return -ENXIO;
241 }
242
243 wq->state = IDXD_WQ_DISABLED;
244 dev_dbg(dev, "WQ %d disabled\n", wq->id);
245 return 0;
246 }
247
idxd_wq_drain(struct idxd_wq * wq)248 void idxd_wq_drain(struct idxd_wq *wq)
249 {
250 struct idxd_device *idxd = wq->idxd;
251 struct device *dev = &idxd->pdev->dev;
252 u32 operand;
253
254 if (wq->state != IDXD_WQ_ENABLED) {
255 dev_dbg(dev, "WQ %d in wrong state: %d\n", wq->id, wq->state);
256 return;
257 }
258
259 dev_dbg(dev, "Draining WQ %d\n", wq->id);
260 operand = BIT(wq->id % 16) | ((wq->id / 16) << 16);
261 idxd_cmd_exec(idxd, IDXD_CMD_DRAIN_WQ, operand, NULL);
262 }
263
idxd_wq_reset(struct idxd_wq * wq)264 void idxd_wq_reset(struct idxd_wq *wq)
265 {
266 struct idxd_device *idxd = wq->idxd;
267 struct device *dev = &idxd->pdev->dev;
268 u32 operand;
269
270 if (wq->state != IDXD_WQ_ENABLED) {
271 dev_dbg(dev, "WQ %d in wrong state: %d\n", wq->id, wq->state);
272 return;
273 }
274
275 operand = BIT(wq->id % 16) | ((wq->id / 16) << 16);
276 idxd_cmd_exec(idxd, IDXD_CMD_RESET_WQ, operand, NULL);
277 wq->state = IDXD_WQ_DISABLED;
278 }
279
idxd_wq_map_portal(struct idxd_wq * wq)280 int idxd_wq_map_portal(struct idxd_wq *wq)
281 {
282 struct idxd_device *idxd = wq->idxd;
283 struct pci_dev *pdev = idxd->pdev;
284 struct device *dev = &pdev->dev;
285 resource_size_t start;
286
287 start = pci_resource_start(pdev, IDXD_WQ_BAR);
288 start += idxd_get_wq_portal_full_offset(wq->id, IDXD_PORTAL_LIMITED);
289
290 wq->dportal = devm_ioremap(dev, start, IDXD_PORTAL_SIZE);
291 if (!wq->dportal)
292 return -ENOMEM;
293 dev_dbg(dev, "wq %d portal mapped at %p\n", wq->id, wq->dportal);
294
295 return 0;
296 }
297
idxd_wq_unmap_portal(struct idxd_wq * wq)298 void idxd_wq_unmap_portal(struct idxd_wq *wq)
299 {
300 struct device *dev = &wq->idxd->pdev->dev;
301
302 devm_iounmap(dev, wq->dportal);
303 }
304
idxd_wq_disable_cleanup(struct idxd_wq * wq)305 void idxd_wq_disable_cleanup(struct idxd_wq *wq)
306 {
307 struct idxd_device *idxd = wq->idxd;
308
309 lockdep_assert_held(&idxd->dev_lock);
310 memset(wq->wqcfg, 0, idxd->wqcfg_size);
311 wq->type = IDXD_WQT_NONE;
312 wq->size = 0;
313 wq->group = NULL;
314 wq->threshold = 0;
315 wq->priority = 0;
316 clear_bit(WQ_FLAG_DEDICATED, &wq->flags);
317 memset(wq->name, 0, WQ_NAME_SIZE);
318 }
319
320 /* Device control bits */
idxd_is_enabled(struct idxd_device * idxd)321 static inline bool idxd_is_enabled(struct idxd_device *idxd)
322 {
323 union gensts_reg gensts;
324
325 gensts.bits = ioread32(idxd->reg_base + IDXD_GENSTATS_OFFSET);
326
327 if (gensts.state == IDXD_DEVICE_STATE_ENABLED)
328 return true;
329 return false;
330 }
331
idxd_device_is_halted(struct idxd_device * idxd)332 static inline bool idxd_device_is_halted(struct idxd_device *idxd)
333 {
334 union gensts_reg gensts;
335
336 gensts.bits = ioread32(idxd->reg_base + IDXD_GENSTATS_OFFSET);
337
338 return (gensts.state == IDXD_DEVICE_STATE_HALT);
339 }
340
341 /*
342 * This is function is only used for reset during probe and will
343 * poll for completion. Once the device is setup with interrupts,
344 * all commands will be done via interrupt completion.
345 */
idxd_device_init_reset(struct idxd_device * idxd)346 int idxd_device_init_reset(struct idxd_device *idxd)
347 {
348 struct device *dev = &idxd->pdev->dev;
349 union idxd_command_reg cmd;
350 unsigned long flags;
351
352 if (idxd_device_is_halted(idxd)) {
353 dev_warn(&idxd->pdev->dev, "Device is HALTED!\n");
354 return -ENXIO;
355 }
356
357 memset(&cmd, 0, sizeof(cmd));
358 cmd.cmd = IDXD_CMD_RESET_DEVICE;
359 dev_dbg(dev, "%s: sending reset for init.\n", __func__);
360 spin_lock_irqsave(&idxd->dev_lock, flags);
361 iowrite32(cmd.bits, idxd->reg_base + IDXD_CMD_OFFSET);
362
363 while (ioread32(idxd->reg_base + IDXD_CMDSTS_OFFSET) &
364 IDXD_CMDSTS_ACTIVE)
365 cpu_relax();
366 spin_unlock_irqrestore(&idxd->dev_lock, flags);
367 return 0;
368 }
369
idxd_cmd_exec(struct idxd_device * idxd,int cmd_code,u32 operand,u32 * status)370 static void idxd_cmd_exec(struct idxd_device *idxd, int cmd_code, u32 operand,
371 u32 *status)
372 {
373 union idxd_command_reg cmd;
374 DECLARE_COMPLETION_ONSTACK(done);
375 unsigned long flags;
376
377 if (idxd_device_is_halted(idxd)) {
378 dev_warn(&idxd->pdev->dev, "Device is HALTED!\n");
379 if (status)
380 *status = IDXD_CMDSTS_HW_ERR;
381 return;
382 }
383
384 memset(&cmd, 0, sizeof(cmd));
385 cmd.cmd = cmd_code;
386 cmd.operand = operand;
387 cmd.int_req = 1;
388
389 spin_lock_irqsave(&idxd->dev_lock, flags);
390 wait_event_lock_irq(idxd->cmd_waitq,
391 !test_bit(IDXD_FLAG_CMD_RUNNING, &idxd->flags),
392 idxd->dev_lock);
393
394 dev_dbg(&idxd->pdev->dev, "%s: sending cmd: %#x op: %#x\n",
395 __func__, cmd_code, operand);
396
397 idxd->cmd_status = 0;
398 __set_bit(IDXD_FLAG_CMD_RUNNING, &idxd->flags);
399 idxd->cmd_done = &done;
400 iowrite32(cmd.bits, idxd->reg_base + IDXD_CMD_OFFSET);
401
402 /*
403 * After command submitted, release lock and go to sleep until
404 * the command completes via interrupt.
405 */
406 spin_unlock_irqrestore(&idxd->dev_lock, flags);
407 wait_for_completion(&done);
408 spin_lock_irqsave(&idxd->dev_lock, flags);
409 if (status) {
410 *status = ioread32(idxd->reg_base + IDXD_CMDSTS_OFFSET);
411 idxd->cmd_status = *status & GENMASK(7, 0);
412 }
413
414 __clear_bit(IDXD_FLAG_CMD_RUNNING, &idxd->flags);
415 /* Wake up other pending commands */
416 wake_up(&idxd->cmd_waitq);
417 spin_unlock_irqrestore(&idxd->dev_lock, flags);
418 }
419
idxd_device_enable(struct idxd_device * idxd)420 int idxd_device_enable(struct idxd_device *idxd)
421 {
422 struct device *dev = &idxd->pdev->dev;
423 u32 status;
424
425 if (idxd_is_enabled(idxd)) {
426 dev_dbg(dev, "Device already enabled\n");
427 return -ENXIO;
428 }
429
430 idxd_cmd_exec(idxd, IDXD_CMD_ENABLE_DEVICE, 0, &status);
431
432 /* If the command is successful or if the device was enabled */
433 if (status != IDXD_CMDSTS_SUCCESS &&
434 status != IDXD_CMDSTS_ERR_DEV_ENABLED) {
435 dev_dbg(dev, "%s: err_code: %#x\n", __func__, status);
436 return -ENXIO;
437 }
438
439 idxd->state = IDXD_DEV_ENABLED;
440 return 0;
441 }
442
idxd_device_wqs_clear_state(struct idxd_device * idxd)443 void idxd_device_wqs_clear_state(struct idxd_device *idxd)
444 {
445 int i;
446
447 lockdep_assert_held(&idxd->dev_lock);
448
449 for (i = 0; i < idxd->max_wqs; i++) {
450 struct idxd_wq *wq = &idxd->wqs[i];
451
452 if (wq->state == IDXD_WQ_ENABLED) {
453 idxd_wq_disable_cleanup(wq);
454 wq->state = IDXD_WQ_DISABLED;
455 }
456 }
457 }
458
idxd_device_disable(struct idxd_device * idxd)459 int idxd_device_disable(struct idxd_device *idxd)
460 {
461 struct device *dev = &idxd->pdev->dev;
462 u32 status;
463 unsigned long flags;
464
465 if (!idxd_is_enabled(idxd)) {
466 dev_dbg(dev, "Device is not enabled\n");
467 return 0;
468 }
469
470 idxd_cmd_exec(idxd, IDXD_CMD_DISABLE_DEVICE, 0, &status);
471
472 /* If the command is successful or if the device was disabled */
473 if (status != IDXD_CMDSTS_SUCCESS &&
474 !(status & IDXD_CMDSTS_ERR_DIS_DEV_EN)) {
475 dev_dbg(dev, "%s: err_code: %#x\n", __func__, status);
476 return -ENXIO;
477 }
478
479 spin_lock_irqsave(&idxd->dev_lock, flags);
480 idxd_device_wqs_clear_state(idxd);
481 idxd->state = IDXD_DEV_CONF_READY;
482 spin_unlock_irqrestore(&idxd->dev_lock, flags);
483 return 0;
484 }
485
idxd_device_reset(struct idxd_device * idxd)486 void idxd_device_reset(struct idxd_device *idxd)
487 {
488 unsigned long flags;
489
490 idxd_cmd_exec(idxd, IDXD_CMD_RESET_DEVICE, 0, NULL);
491 spin_lock_irqsave(&idxd->dev_lock, flags);
492 idxd_device_wqs_clear_state(idxd);
493 idxd->state = IDXD_DEV_CONF_READY;
494 spin_unlock_irqrestore(&idxd->dev_lock, flags);
495 }
496
497 /* Device configuration bits */
idxd_group_config_write(struct idxd_group * group)498 static void idxd_group_config_write(struct idxd_group *group)
499 {
500 struct idxd_device *idxd = group->idxd;
501 struct device *dev = &idxd->pdev->dev;
502 int i;
503 u32 grpcfg_offset;
504
505 dev_dbg(dev, "Writing group %d cfg registers\n", group->id);
506
507 /* setup GRPWQCFG */
508 for (i = 0; i < 4; i++) {
509 grpcfg_offset = idxd->grpcfg_offset +
510 group->id * 64 + i * sizeof(u64);
511 iowrite64(group->grpcfg.wqs[i],
512 idxd->reg_base + grpcfg_offset);
513 dev_dbg(dev, "GRPCFG wq[%d:%d: %#x]: %#llx\n",
514 group->id, i, grpcfg_offset,
515 ioread64(idxd->reg_base + grpcfg_offset));
516 }
517
518 /* setup GRPENGCFG */
519 grpcfg_offset = idxd->grpcfg_offset + group->id * 64 + 32;
520 iowrite64(group->grpcfg.engines, idxd->reg_base + grpcfg_offset);
521 dev_dbg(dev, "GRPCFG engs[%d: %#x]: %#llx\n", group->id,
522 grpcfg_offset, ioread64(idxd->reg_base + grpcfg_offset));
523
524 /* setup GRPFLAGS */
525 grpcfg_offset = idxd->grpcfg_offset + group->id * 64 + 40;
526 iowrite32(group->grpcfg.flags.bits, idxd->reg_base + grpcfg_offset);
527 dev_dbg(dev, "GRPFLAGS flags[%d: %#x]: %#x\n",
528 group->id, grpcfg_offset,
529 ioread32(idxd->reg_base + grpcfg_offset));
530 }
531
idxd_groups_config_write(struct idxd_device * idxd)532 static int idxd_groups_config_write(struct idxd_device *idxd)
533
534 {
535 union gencfg_reg reg;
536 int i;
537 struct device *dev = &idxd->pdev->dev;
538
539 /* Setup bandwidth token limit */
540 if (idxd->token_limit) {
541 reg.bits = ioread32(idxd->reg_base + IDXD_GENCFG_OFFSET);
542 reg.token_limit = idxd->token_limit;
543 iowrite32(reg.bits, idxd->reg_base + IDXD_GENCFG_OFFSET);
544 }
545
546 dev_dbg(dev, "GENCFG(%#x): %#x\n", IDXD_GENCFG_OFFSET,
547 ioread32(idxd->reg_base + IDXD_GENCFG_OFFSET));
548
549 for (i = 0; i < idxd->max_groups; i++) {
550 struct idxd_group *group = &idxd->groups[i];
551
552 idxd_group_config_write(group);
553 }
554
555 return 0;
556 }
557
idxd_wq_config_write(struct idxd_wq * wq)558 static int idxd_wq_config_write(struct idxd_wq *wq)
559 {
560 struct idxd_device *idxd = wq->idxd;
561 struct device *dev = &idxd->pdev->dev;
562 u32 wq_offset;
563 int i;
564
565 if (!wq->group)
566 return 0;
567
568 /*
569 * Instead of memset the entire shadow copy of WQCFG, copy from the hardware after
570 * wq reset. This will copy back the sticky values that are present on some devices.
571 */
572 for (i = 0; i < WQCFG_STRIDES(idxd); i++) {
573 wq_offset = WQCFG_OFFSET(idxd, wq->id, i);
574 wq->wqcfg->bits[i] = ioread32(idxd->reg_base + wq_offset);
575 }
576
577 /* byte 0-3 */
578 wq->wqcfg->wq_size = wq->size;
579
580 if (wq->size == 0) {
581 dev_warn(dev, "Incorrect work queue size: 0\n");
582 return -EINVAL;
583 }
584
585 /* bytes 4-7 */
586 wq->wqcfg->wq_thresh = wq->threshold;
587
588 /* byte 8-11 */
589 wq->wqcfg->priv = !!(wq->type == IDXD_WQT_KERNEL);
590 wq->wqcfg->mode = 1;
591 wq->wqcfg->priority = wq->priority;
592
593 /* bytes 12-15 */
594 wq->wqcfg->max_xfer_shift = ilog2(wq->max_xfer_bytes);
595 wq->wqcfg->max_batch_shift = ilog2(wq->max_batch_size);
596
597 dev_dbg(dev, "WQ %d CFGs\n", wq->id);
598 for (i = 0; i < WQCFG_STRIDES(idxd); i++) {
599 wq_offset = WQCFG_OFFSET(idxd, wq->id, i);
600 iowrite32(wq->wqcfg->bits[i], idxd->reg_base + wq_offset);
601 dev_dbg(dev, "WQ[%d][%d][%#x]: %#x\n",
602 wq->id, i, wq_offset,
603 ioread32(idxd->reg_base + wq_offset));
604 }
605
606 return 0;
607 }
608
idxd_wqs_config_write(struct idxd_device * idxd)609 static int idxd_wqs_config_write(struct idxd_device *idxd)
610 {
611 int i, rc;
612
613 for (i = 0; i < idxd->max_wqs; i++) {
614 struct idxd_wq *wq = &idxd->wqs[i];
615
616 rc = idxd_wq_config_write(wq);
617 if (rc < 0)
618 return rc;
619 }
620
621 return 0;
622 }
623
idxd_group_flags_setup(struct idxd_device * idxd)624 static void idxd_group_flags_setup(struct idxd_device *idxd)
625 {
626 int i;
627
628 /* TC-A 0 and TC-B 1 should be defaults */
629 for (i = 0; i < idxd->max_groups; i++) {
630 struct idxd_group *group = &idxd->groups[i];
631
632 if (group->tc_a == -1)
633 group->tc_a = group->grpcfg.flags.tc_a = 0;
634 else
635 group->grpcfg.flags.tc_a = group->tc_a;
636 if (group->tc_b == -1)
637 group->tc_b = group->grpcfg.flags.tc_b = 1;
638 else
639 group->grpcfg.flags.tc_b = group->tc_b;
640 group->grpcfg.flags.use_token_limit = group->use_token_limit;
641 group->grpcfg.flags.tokens_reserved = group->tokens_reserved;
642 if (group->tokens_allowed)
643 group->grpcfg.flags.tokens_allowed =
644 group->tokens_allowed;
645 else
646 group->grpcfg.flags.tokens_allowed = idxd->max_tokens;
647 }
648 }
649
idxd_engines_setup(struct idxd_device * idxd)650 static int idxd_engines_setup(struct idxd_device *idxd)
651 {
652 int i, engines = 0;
653 struct idxd_engine *eng;
654 struct idxd_group *group;
655
656 for (i = 0; i < idxd->max_groups; i++) {
657 group = &idxd->groups[i];
658 group->grpcfg.engines = 0;
659 }
660
661 for (i = 0; i < idxd->max_engines; i++) {
662 eng = &idxd->engines[i];
663 group = eng->group;
664
665 if (!group)
666 continue;
667
668 group->grpcfg.engines |= BIT(eng->id);
669 engines++;
670 }
671
672 if (!engines)
673 return -EINVAL;
674
675 return 0;
676 }
677
idxd_wqs_setup(struct idxd_device * idxd)678 static int idxd_wqs_setup(struct idxd_device *idxd)
679 {
680 struct idxd_wq *wq;
681 struct idxd_group *group;
682 int i, j, configured = 0;
683 struct device *dev = &idxd->pdev->dev;
684
685 for (i = 0; i < idxd->max_groups; i++) {
686 group = &idxd->groups[i];
687 for (j = 0; j < 4; j++)
688 group->grpcfg.wqs[j] = 0;
689 }
690
691 for (i = 0; i < idxd->max_wqs; i++) {
692 wq = &idxd->wqs[i];
693 group = wq->group;
694
695 if (!wq->group)
696 continue;
697 if (!wq->size)
698 continue;
699
700 if (!wq_dedicated(wq)) {
701 dev_warn(dev, "No shared workqueue support.\n");
702 return -EINVAL;
703 }
704
705 group->grpcfg.wqs[wq->id / 64] |= BIT(wq->id % 64);
706 configured++;
707 }
708
709 if (configured == 0)
710 return -EINVAL;
711
712 return 0;
713 }
714
idxd_device_config(struct idxd_device * idxd)715 int idxd_device_config(struct idxd_device *idxd)
716 {
717 int rc;
718
719 lockdep_assert_held(&idxd->dev_lock);
720 rc = idxd_wqs_setup(idxd);
721 if (rc < 0)
722 return rc;
723
724 rc = idxd_engines_setup(idxd);
725 if (rc < 0)
726 return rc;
727
728 idxd_group_flags_setup(idxd);
729
730 rc = idxd_wqs_config_write(idxd);
731 if (rc < 0)
732 return rc;
733
734 rc = idxd_groups_config_write(idxd);
735 if (rc < 0)
736 return rc;
737
738 return 0;
739 }
740