1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
3
4 #include <linux/if_ether.h>
5 #include <linux/delay.h>
6 #include <linux/pci.h>
7 #include <linux/netdevice.h>
8 #include <linux/etherdevice.h>
9
10 #include "e1000_mac.h"
11
12 #include "igb.h"
13
14 static s32 igb_set_default_fc(struct e1000_hw *hw);
15 static void igb_set_fc_watermarks(struct e1000_hw *hw);
16
17 /**
18 * igb_get_bus_info_pcie - Get PCIe bus information
19 * @hw: pointer to the HW structure
20 *
21 * Determines and stores the system bus information for a particular
22 * network interface. The following bus information is determined and stored:
23 * bus speed, bus width, type (PCIe), and PCIe function.
24 **/
igb_get_bus_info_pcie(struct e1000_hw * hw)25 s32 igb_get_bus_info_pcie(struct e1000_hw *hw)
26 {
27 struct e1000_bus_info *bus = &hw->bus;
28 s32 ret_val;
29 u32 reg;
30 u16 pcie_link_status;
31
32 bus->type = e1000_bus_type_pci_express;
33
34 ret_val = igb_read_pcie_cap_reg(hw,
35 PCI_EXP_LNKSTA,
36 &pcie_link_status);
37 if (ret_val) {
38 bus->width = e1000_bus_width_unknown;
39 bus->speed = e1000_bus_speed_unknown;
40 } else {
41 switch (pcie_link_status & PCI_EXP_LNKSTA_CLS) {
42 case PCI_EXP_LNKSTA_CLS_2_5GB:
43 bus->speed = e1000_bus_speed_2500;
44 break;
45 case PCI_EXP_LNKSTA_CLS_5_0GB:
46 bus->speed = e1000_bus_speed_5000;
47 break;
48 default:
49 bus->speed = e1000_bus_speed_unknown;
50 break;
51 }
52
53 bus->width = (enum e1000_bus_width)((pcie_link_status &
54 PCI_EXP_LNKSTA_NLW) >>
55 PCI_EXP_LNKSTA_NLW_SHIFT);
56 }
57
58 reg = rd32(E1000_STATUS);
59 bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT;
60
61 return 0;
62 }
63
64 /**
65 * igb_clear_vfta - Clear VLAN filter table
66 * @hw: pointer to the HW structure
67 *
68 * Clears the register array which contains the VLAN filter table by
69 * setting all the values to 0.
70 **/
igb_clear_vfta(struct e1000_hw * hw)71 void igb_clear_vfta(struct e1000_hw *hw)
72 {
73 u32 offset;
74
75 for (offset = E1000_VLAN_FILTER_TBL_SIZE; offset--;)
76 hw->mac.ops.write_vfta(hw, offset, 0);
77 }
78
79 /**
80 * igb_write_vfta - Write value to VLAN filter table
81 * @hw: pointer to the HW structure
82 * @offset: register offset in VLAN filter table
83 * @value: register value written to VLAN filter table
84 *
85 * Writes value at the given offset in the register array which stores
86 * the VLAN filter table.
87 **/
igb_write_vfta(struct e1000_hw * hw,u32 offset,u32 value)88 void igb_write_vfta(struct e1000_hw *hw, u32 offset, u32 value)
89 {
90 struct igb_adapter *adapter = hw->back;
91
92 array_wr32(E1000_VFTA, offset, value);
93 wrfl();
94
95 adapter->shadow_vfta[offset] = value;
96 }
97
98 /**
99 * igb_init_rx_addrs - Initialize receive address's
100 * @hw: pointer to the HW structure
101 * @rar_count: receive address registers
102 *
103 * Setups the receive address registers by setting the base receive address
104 * register to the devices MAC address and clearing all the other receive
105 * address registers to 0.
106 **/
igb_init_rx_addrs(struct e1000_hw * hw,u16 rar_count)107 void igb_init_rx_addrs(struct e1000_hw *hw, u16 rar_count)
108 {
109 u32 i;
110 u8 mac_addr[ETH_ALEN] = {0};
111
112 /* Setup the receive address */
113 hw_dbg("Programming MAC Address into RAR[0]\n");
114
115 hw->mac.ops.rar_set(hw, hw->mac.addr, 0);
116
117 /* Zero out the other (rar_entry_count - 1) receive addresses */
118 hw_dbg("Clearing RAR[1-%u]\n", rar_count-1);
119 for (i = 1; i < rar_count; i++)
120 hw->mac.ops.rar_set(hw, mac_addr, i);
121 }
122
123 /**
124 * igb_find_vlvf_slot - find the VLAN id or the first empty slot
125 * @hw: pointer to hardware structure
126 * @vlan: VLAN id to write to VLAN filter
127 * @vlvf_bypass: skip VLVF if no match is found
128 *
129 * return the VLVF index where this VLAN id should be placed
130 *
131 **/
igb_find_vlvf_slot(struct e1000_hw * hw,u32 vlan,bool vlvf_bypass)132 static s32 igb_find_vlvf_slot(struct e1000_hw *hw, u32 vlan, bool vlvf_bypass)
133 {
134 s32 regindex, first_empty_slot;
135 u32 bits;
136
137 /* short cut the special case */
138 if (vlan == 0)
139 return 0;
140
141 /* if vlvf_bypass is set we don't want to use an empty slot, we
142 * will simply bypass the VLVF if there are no entries present in the
143 * VLVF that contain our VLAN
144 */
145 first_empty_slot = vlvf_bypass ? -E1000_ERR_NO_SPACE : 0;
146
147 /* Search for the VLAN id in the VLVF entries. Save off the first empty
148 * slot found along the way.
149 *
150 * pre-decrement loop covering (IXGBE_VLVF_ENTRIES - 1) .. 1
151 */
152 for (regindex = E1000_VLVF_ARRAY_SIZE; --regindex > 0;) {
153 bits = rd32(E1000_VLVF(regindex)) & E1000_VLVF_VLANID_MASK;
154 if (bits == vlan)
155 return regindex;
156 if (!first_empty_slot && !bits)
157 first_empty_slot = regindex;
158 }
159
160 return first_empty_slot ? : -E1000_ERR_NO_SPACE;
161 }
162
163 /**
164 * igb_vfta_set - enable or disable vlan in VLAN filter table
165 * @hw: pointer to the HW structure
166 * @vlan: VLAN id to add or remove
167 * @vind: VMDq output index that maps queue to VLAN id
168 * @vlan_on: if true add filter, if false remove
169 * @vlvf_bypass: skip VLVF if no match is found
170 *
171 * Sets or clears a bit in the VLAN filter table array based on VLAN id
172 * and if we are adding or removing the filter
173 **/
igb_vfta_set(struct e1000_hw * hw,u32 vlan,u32 vind,bool vlan_on,bool vlvf_bypass)174 s32 igb_vfta_set(struct e1000_hw *hw, u32 vlan, u32 vind,
175 bool vlan_on, bool vlvf_bypass)
176 {
177 struct igb_adapter *adapter = hw->back;
178 u32 regidx, vfta_delta, vfta, bits;
179 s32 vlvf_index;
180
181 if ((vlan > 4095) || (vind > 7))
182 return -E1000_ERR_PARAM;
183
184 /* this is a 2 part operation - first the VFTA, then the
185 * VLVF and VLVFB if VT Mode is set
186 * We don't write the VFTA until we know the VLVF part succeeded.
187 */
188
189 /* Part 1
190 * The VFTA is a bitstring made up of 128 32-bit registers
191 * that enable the particular VLAN id, much like the MTA:
192 * bits[11-5]: which register
193 * bits[4-0]: which bit in the register
194 */
195 regidx = vlan / 32;
196 vfta_delta = BIT(vlan % 32);
197 vfta = adapter->shadow_vfta[regidx];
198
199 /* vfta_delta represents the difference between the current value
200 * of vfta and the value we want in the register. Since the diff
201 * is an XOR mask we can just update vfta using an XOR.
202 */
203 vfta_delta &= vlan_on ? ~vfta : vfta;
204 vfta ^= vfta_delta;
205
206 /* Part 2
207 * If VT Mode is set
208 * Either vlan_on
209 * make sure the VLAN is in VLVF
210 * set the vind bit in the matching VLVFB
211 * Or !vlan_on
212 * clear the pool bit and possibly the vind
213 */
214 if (!adapter->vfs_allocated_count)
215 goto vfta_update;
216
217 vlvf_index = igb_find_vlvf_slot(hw, vlan, vlvf_bypass);
218 if (vlvf_index < 0) {
219 if (vlvf_bypass)
220 goto vfta_update;
221 return vlvf_index;
222 }
223
224 bits = rd32(E1000_VLVF(vlvf_index));
225
226 /* set the pool bit */
227 bits |= BIT(E1000_VLVF_POOLSEL_SHIFT + vind);
228 if (vlan_on)
229 goto vlvf_update;
230
231 /* clear the pool bit */
232 bits ^= BIT(E1000_VLVF_POOLSEL_SHIFT + vind);
233
234 if (!(bits & E1000_VLVF_POOLSEL_MASK)) {
235 /* Clear VFTA first, then disable VLVF. Otherwise
236 * we run the risk of stray packets leaking into
237 * the PF via the default pool
238 */
239 if (vfta_delta)
240 hw->mac.ops.write_vfta(hw, regidx, vfta);
241
242 /* disable VLVF and clear remaining bit from pool */
243 wr32(E1000_VLVF(vlvf_index), 0);
244
245 return 0;
246 }
247
248 /* If there are still bits set in the VLVFB registers
249 * for the VLAN ID indicated we need to see if the
250 * caller is requesting that we clear the VFTA entry bit.
251 * If the caller has requested that we clear the VFTA
252 * entry bit but there are still pools/VFs using this VLAN
253 * ID entry then ignore the request. We're not worried
254 * about the case where we're turning the VFTA VLAN ID
255 * entry bit on, only when requested to turn it off as
256 * there may be multiple pools and/or VFs using the
257 * VLAN ID entry. In that case we cannot clear the
258 * VFTA bit until all pools/VFs using that VLAN ID have also
259 * been cleared. This will be indicated by "bits" being
260 * zero.
261 */
262 vfta_delta = 0;
263
264 vlvf_update:
265 /* record pool change and enable VLAN ID if not already enabled */
266 wr32(E1000_VLVF(vlvf_index), bits | vlan | E1000_VLVF_VLANID_ENABLE);
267
268 vfta_update:
269 /* bit was set/cleared before we started */
270 if (vfta_delta)
271 hw->mac.ops.write_vfta(hw, regidx, vfta);
272
273 return 0;
274 }
275
276 /**
277 * igb_check_alt_mac_addr - Check for alternate MAC addr
278 * @hw: pointer to the HW structure
279 *
280 * Checks the nvm for an alternate MAC address. An alternate MAC address
281 * can be setup by pre-boot software and must be treated like a permanent
282 * address and must override the actual permanent MAC address. If an
283 * alternate MAC address is found it is saved in the hw struct and
284 * programmed into RAR0 and the function returns success, otherwise the
285 * function returns an error.
286 **/
igb_check_alt_mac_addr(struct e1000_hw * hw)287 s32 igb_check_alt_mac_addr(struct e1000_hw *hw)
288 {
289 u32 i;
290 s32 ret_val = 0;
291 u16 offset, nvm_alt_mac_addr_offset, nvm_data;
292 u8 alt_mac_addr[ETH_ALEN];
293
294 /* Alternate MAC address is handled by the option ROM for 82580
295 * and newer. SW support not required.
296 */
297 if (hw->mac.type >= e1000_82580)
298 goto out;
299
300 ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1,
301 &nvm_alt_mac_addr_offset);
302 if (ret_val) {
303 hw_dbg("NVM Read Error\n");
304 goto out;
305 }
306
307 if ((nvm_alt_mac_addr_offset == 0xFFFF) ||
308 (nvm_alt_mac_addr_offset == 0x0000))
309 /* There is no Alternate MAC Address */
310 goto out;
311
312 if (hw->bus.func == E1000_FUNC_1)
313 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1;
314 if (hw->bus.func == E1000_FUNC_2)
315 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN2;
316
317 if (hw->bus.func == E1000_FUNC_3)
318 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN3;
319 for (i = 0; i < ETH_ALEN; i += 2) {
320 offset = nvm_alt_mac_addr_offset + (i >> 1);
321 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);
322 if (ret_val) {
323 hw_dbg("NVM Read Error\n");
324 goto out;
325 }
326
327 alt_mac_addr[i] = (u8)(nvm_data & 0xFF);
328 alt_mac_addr[i + 1] = (u8)(nvm_data >> 8);
329 }
330
331 /* if multicast bit is set, the alternate address will not be used */
332 if (is_multicast_ether_addr(alt_mac_addr)) {
333 hw_dbg("Ignoring Alternate Mac Address with MC bit set\n");
334 goto out;
335 }
336
337 /* We have a valid alternate MAC address, and we want to treat it the
338 * same as the normal permanent MAC address stored by the HW into the
339 * RAR. Do this by mapping this address into RAR0.
340 */
341 hw->mac.ops.rar_set(hw, alt_mac_addr, 0);
342
343 out:
344 return ret_val;
345 }
346
347 /**
348 * igb_rar_set - Set receive address register
349 * @hw: pointer to the HW structure
350 * @addr: pointer to the receive address
351 * @index: receive address array register
352 *
353 * Sets the receive address array register at index to the address passed
354 * in by addr.
355 **/
igb_rar_set(struct e1000_hw * hw,u8 * addr,u32 index)356 void igb_rar_set(struct e1000_hw *hw, u8 *addr, u32 index)
357 {
358 u32 rar_low, rar_high;
359
360 /* HW expects these in little endian so we reverse the byte order
361 * from network order (big endian) to little endian
362 */
363 rar_low = ((u32) addr[0] |
364 ((u32) addr[1] << 8) |
365 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
366
367 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
368
369 /* If MAC address zero, no need to set the AV bit */
370 if (rar_low || rar_high)
371 rar_high |= E1000_RAH_AV;
372
373 /* Some bridges will combine consecutive 32-bit writes into
374 * a single burst write, which will malfunction on some parts.
375 * The flushes avoid this.
376 */
377 wr32(E1000_RAL(index), rar_low);
378 wrfl();
379 wr32(E1000_RAH(index), rar_high);
380 wrfl();
381 }
382
383 /**
384 * igb_mta_set - Set multicast filter table address
385 * @hw: pointer to the HW structure
386 * @hash_value: determines the MTA register and bit to set
387 *
388 * The multicast table address is a register array of 32-bit registers.
389 * The hash_value is used to determine what register the bit is in, the
390 * current value is read, the new bit is OR'd in and the new value is
391 * written back into the register.
392 **/
igb_mta_set(struct e1000_hw * hw,u32 hash_value)393 void igb_mta_set(struct e1000_hw *hw, u32 hash_value)
394 {
395 u32 hash_bit, hash_reg, mta;
396
397 /* The MTA is a register array of 32-bit registers. It is
398 * treated like an array of (32*mta_reg_count) bits. We want to
399 * set bit BitArray[hash_value]. So we figure out what register
400 * the bit is in, read it, OR in the new bit, then write
401 * back the new value. The (hw->mac.mta_reg_count - 1) serves as a
402 * mask to bits 31:5 of the hash value which gives us the
403 * register we're modifying. The hash bit within that register
404 * is determined by the lower 5 bits of the hash value.
405 */
406 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);
407 hash_bit = hash_value & 0x1F;
408
409 mta = array_rd32(E1000_MTA, hash_reg);
410
411 mta |= BIT(hash_bit);
412
413 array_wr32(E1000_MTA, hash_reg, mta);
414 wrfl();
415 }
416
417 /**
418 * igb_hash_mc_addr - Generate a multicast hash value
419 * @hw: pointer to the HW structure
420 * @mc_addr: pointer to a multicast address
421 *
422 * Generates a multicast address hash value which is used to determine
423 * the multicast filter table array address and new table value. See
424 * igb_mta_set()
425 **/
igb_hash_mc_addr(struct e1000_hw * hw,u8 * mc_addr)426 static u32 igb_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr)
427 {
428 u32 hash_value, hash_mask;
429 u8 bit_shift = 1;
430
431 /* Register count multiplied by bits per register */
432 hash_mask = (hw->mac.mta_reg_count * 32) - 1;
433
434 /* For a mc_filter_type of 0, bit_shift is the number of left-shifts
435 * where 0xFF would still fall within the hash mask.
436 */
437 while (hash_mask >> bit_shift != 0xFF && bit_shift < 4)
438 bit_shift++;
439
440 /* The portion of the address that is used for the hash table
441 * is determined by the mc_filter_type setting.
442 * The algorithm is such that there is a total of 8 bits of shifting.
443 * The bit_shift for a mc_filter_type of 0 represents the number of
444 * left-shifts where the MSB of mc_addr[5] would still fall within
445 * the hash_mask. Case 0 does this exactly. Since there are a total
446 * of 8 bits of shifting, then mc_addr[4] will shift right the
447 * remaining number of bits. Thus 8 - bit_shift. The rest of the
448 * cases are a variation of this algorithm...essentially raising the
449 * number of bits to shift mc_addr[5] left, while still keeping the
450 * 8-bit shifting total.
451 *
452 * For example, given the following Destination MAC Address and an
453 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask),
454 * we can see that the bit_shift for case 0 is 4. These are the hash
455 * values resulting from each mc_filter_type...
456 * [0] [1] [2] [3] [4] [5]
457 * 01 AA 00 12 34 56
458 * LSB MSB
459 *
460 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563
461 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6
462 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163
463 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634
464 */
465 switch (hw->mac.mc_filter_type) {
466 default:
467 case 0:
468 break;
469 case 1:
470 bit_shift += 1;
471 break;
472 case 2:
473 bit_shift += 2;
474 break;
475 case 3:
476 bit_shift += 4;
477 break;
478 }
479
480 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) |
481 (((u16) mc_addr[5]) << bit_shift)));
482
483 return hash_value;
484 }
485
486 /**
487 * igb_update_mc_addr_list - Update Multicast addresses
488 * @hw: pointer to the HW structure
489 * @mc_addr_list: array of multicast addresses to program
490 * @mc_addr_count: number of multicast addresses to program
491 *
492 * Updates entire Multicast Table Array.
493 * The caller must have a packed mc_addr_list of multicast addresses.
494 **/
igb_update_mc_addr_list(struct e1000_hw * hw,u8 * mc_addr_list,u32 mc_addr_count)495 void igb_update_mc_addr_list(struct e1000_hw *hw,
496 u8 *mc_addr_list, u32 mc_addr_count)
497 {
498 u32 hash_value, hash_bit, hash_reg;
499 int i;
500
501 /* clear mta_shadow */
502 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
503
504 /* update mta_shadow from mc_addr_list */
505 for (i = 0; (u32) i < mc_addr_count; i++) {
506 hash_value = igb_hash_mc_addr(hw, mc_addr_list);
507
508 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);
509 hash_bit = hash_value & 0x1F;
510
511 hw->mac.mta_shadow[hash_reg] |= BIT(hash_bit);
512 mc_addr_list += (ETH_ALEN);
513 }
514
515 /* replace the entire MTA table */
516 for (i = hw->mac.mta_reg_count - 1; i >= 0; i--)
517 array_wr32(E1000_MTA, i, hw->mac.mta_shadow[i]);
518 wrfl();
519 }
520
521 /**
522 * igb_clear_hw_cntrs_base - Clear base hardware counters
523 * @hw: pointer to the HW structure
524 *
525 * Clears the base hardware counters by reading the counter registers.
526 **/
igb_clear_hw_cntrs_base(struct e1000_hw * hw)527 void igb_clear_hw_cntrs_base(struct e1000_hw *hw)
528 {
529 rd32(E1000_CRCERRS);
530 rd32(E1000_SYMERRS);
531 rd32(E1000_MPC);
532 rd32(E1000_SCC);
533 rd32(E1000_ECOL);
534 rd32(E1000_MCC);
535 rd32(E1000_LATECOL);
536 rd32(E1000_COLC);
537 rd32(E1000_DC);
538 rd32(E1000_SEC);
539 rd32(E1000_RLEC);
540 rd32(E1000_XONRXC);
541 rd32(E1000_XONTXC);
542 rd32(E1000_XOFFRXC);
543 rd32(E1000_XOFFTXC);
544 rd32(E1000_FCRUC);
545 rd32(E1000_GPRC);
546 rd32(E1000_BPRC);
547 rd32(E1000_MPRC);
548 rd32(E1000_GPTC);
549 rd32(E1000_GORCL);
550 rd32(E1000_GORCH);
551 rd32(E1000_GOTCL);
552 rd32(E1000_GOTCH);
553 rd32(E1000_RNBC);
554 rd32(E1000_RUC);
555 rd32(E1000_RFC);
556 rd32(E1000_ROC);
557 rd32(E1000_RJC);
558 rd32(E1000_TORL);
559 rd32(E1000_TORH);
560 rd32(E1000_TOTL);
561 rd32(E1000_TOTH);
562 rd32(E1000_TPR);
563 rd32(E1000_TPT);
564 rd32(E1000_MPTC);
565 rd32(E1000_BPTC);
566 }
567
568 /**
569 * igb_check_for_copper_link - Check for link (Copper)
570 * @hw: pointer to the HW structure
571 *
572 * Checks to see of the link status of the hardware has changed. If a
573 * change in link status has been detected, then we read the PHY registers
574 * to get the current speed/duplex if link exists.
575 **/
igb_check_for_copper_link(struct e1000_hw * hw)576 s32 igb_check_for_copper_link(struct e1000_hw *hw)
577 {
578 struct e1000_mac_info *mac = &hw->mac;
579 s32 ret_val;
580 bool link;
581
582 /* We only want to go out to the PHY registers to see if Auto-Neg
583 * has completed and/or if our link status has changed. The
584 * get_link_status flag is set upon receiving a Link Status
585 * Change or Rx Sequence Error interrupt.
586 */
587 if (!mac->get_link_status) {
588 ret_val = 0;
589 goto out;
590 }
591
592 /* First we want to see if the MII Status Register reports
593 * link. If so, then we want to get the current speed/duplex
594 * of the PHY.
595 */
596 ret_val = igb_phy_has_link(hw, 1, 0, &link);
597 if (ret_val)
598 goto out;
599
600 if (!link)
601 goto out; /* No link detected */
602
603 mac->get_link_status = false;
604
605 /* Check if there was DownShift, must be checked
606 * immediately after link-up
607 */
608 igb_check_downshift(hw);
609
610 /* If we are forcing speed/duplex, then we simply return since
611 * we have already determined whether we have link or not.
612 */
613 if (!mac->autoneg) {
614 ret_val = -E1000_ERR_CONFIG;
615 goto out;
616 }
617
618 /* Auto-Neg is enabled. Auto Speed Detection takes care
619 * of MAC speed/duplex configuration. So we only need to
620 * configure Collision Distance in the MAC.
621 */
622 igb_config_collision_dist(hw);
623
624 /* Configure Flow Control now that Auto-Neg has completed.
625 * First, we need to restore the desired flow control
626 * settings because we may have had to re-autoneg with a
627 * different link partner.
628 */
629 ret_val = igb_config_fc_after_link_up(hw);
630 if (ret_val)
631 hw_dbg("Error configuring flow control\n");
632
633 out:
634 return ret_val;
635 }
636
637 /**
638 * igb_setup_link - Setup flow control and link settings
639 * @hw: pointer to the HW structure
640 *
641 * Determines which flow control settings to use, then configures flow
642 * control. Calls the appropriate media-specific link configuration
643 * function. Assuming the adapter has a valid link partner, a valid link
644 * should be established. Assumes the hardware has previously been reset
645 * and the transmitter and receiver are not enabled.
646 **/
igb_setup_link(struct e1000_hw * hw)647 s32 igb_setup_link(struct e1000_hw *hw)
648 {
649 s32 ret_val = 0;
650
651 /* In the case of the phy reset being blocked, we already have a link.
652 * We do not need to set it up again.
653 */
654 if (igb_check_reset_block(hw))
655 goto out;
656
657 /* If requested flow control is set to default, set flow control
658 * based on the EEPROM flow control settings.
659 */
660 if (hw->fc.requested_mode == e1000_fc_default) {
661 ret_val = igb_set_default_fc(hw);
662 if (ret_val)
663 goto out;
664 }
665
666 /* We want to save off the original Flow Control configuration just
667 * in case we get disconnected and then reconnected into a different
668 * hub or switch with different Flow Control capabilities.
669 */
670 hw->fc.current_mode = hw->fc.requested_mode;
671
672 hw_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.current_mode);
673
674 /* Call the necessary media_type subroutine to configure the link. */
675 ret_val = hw->mac.ops.setup_physical_interface(hw);
676 if (ret_val)
677 goto out;
678
679 /* Initialize the flow control address, type, and PAUSE timer
680 * registers to their default values. This is done even if flow
681 * control is disabled, because it does not hurt anything to
682 * initialize these registers.
683 */
684 hw_dbg("Initializing the Flow Control address, type and timer regs\n");
685 wr32(E1000_FCT, FLOW_CONTROL_TYPE);
686 wr32(E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH);
687 wr32(E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW);
688
689 wr32(E1000_FCTTV, hw->fc.pause_time);
690
691 igb_set_fc_watermarks(hw);
692
693 out:
694
695 return ret_val;
696 }
697
698 /**
699 * igb_config_collision_dist - Configure collision distance
700 * @hw: pointer to the HW structure
701 *
702 * Configures the collision distance to the default value and is used
703 * during link setup. Currently no func pointer exists and all
704 * implementations are handled in the generic version of this function.
705 **/
igb_config_collision_dist(struct e1000_hw * hw)706 void igb_config_collision_dist(struct e1000_hw *hw)
707 {
708 u32 tctl;
709
710 tctl = rd32(E1000_TCTL);
711
712 tctl &= ~E1000_TCTL_COLD;
713 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT;
714
715 wr32(E1000_TCTL, tctl);
716 wrfl();
717 }
718
719 /**
720 * igb_set_fc_watermarks - Set flow control high/low watermarks
721 * @hw: pointer to the HW structure
722 *
723 * Sets the flow control high/low threshold (watermark) registers. If
724 * flow control XON frame transmission is enabled, then set XON frame
725 * tansmission as well.
726 **/
igb_set_fc_watermarks(struct e1000_hw * hw)727 static void igb_set_fc_watermarks(struct e1000_hw *hw)
728 {
729 u32 fcrtl = 0, fcrth = 0;
730
731 /* Set the flow control receive threshold registers. Normally,
732 * these registers will be set to a default threshold that may be
733 * adjusted later by the driver's runtime code. However, if the
734 * ability to transmit pause frames is not enabled, then these
735 * registers will be set to 0.
736 */
737 if (hw->fc.current_mode & e1000_fc_tx_pause) {
738 /* We need to set up the Receive Threshold high and low water
739 * marks as well as (optionally) enabling the transmission of
740 * XON frames.
741 */
742 fcrtl = hw->fc.low_water;
743 if (hw->fc.send_xon)
744 fcrtl |= E1000_FCRTL_XONE;
745
746 fcrth = hw->fc.high_water;
747 }
748 wr32(E1000_FCRTL, fcrtl);
749 wr32(E1000_FCRTH, fcrth);
750 }
751
752 /**
753 * igb_set_default_fc - Set flow control default values
754 * @hw: pointer to the HW structure
755 *
756 * Read the EEPROM for the default values for flow control and store the
757 * values.
758 **/
igb_set_default_fc(struct e1000_hw * hw)759 static s32 igb_set_default_fc(struct e1000_hw *hw)
760 {
761 s32 ret_val = 0;
762 u16 lan_offset;
763 u16 nvm_data;
764
765 /* Read and store word 0x0F of the EEPROM. This word contains bits
766 * that determine the hardware's default PAUSE (flow control) mode,
767 * a bit that determines whether the HW defaults to enabling or
768 * disabling auto-negotiation, and the direction of the
769 * SW defined pins. If there is no SW over-ride of the flow
770 * control setting, then the variable hw->fc will
771 * be initialized based on a value in the EEPROM.
772 */
773 if (hw->mac.type == e1000_i350)
774 lan_offset = NVM_82580_LAN_FUNC_OFFSET(hw->bus.func);
775 else
776 lan_offset = 0;
777
778 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG + lan_offset,
779 1, &nvm_data);
780 if (ret_val) {
781 hw_dbg("NVM Read Error\n");
782 goto out;
783 }
784
785 if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 0)
786 hw->fc.requested_mode = e1000_fc_none;
787 else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == NVM_WORD0F_ASM_DIR)
788 hw->fc.requested_mode = e1000_fc_tx_pause;
789 else
790 hw->fc.requested_mode = e1000_fc_full;
791
792 out:
793 return ret_val;
794 }
795
796 /**
797 * igb_force_mac_fc - Force the MAC's flow control settings
798 * @hw: pointer to the HW structure
799 *
800 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the
801 * device control register to reflect the adapter settings. TFCE and RFCE
802 * need to be explicitly set by software when a copper PHY is used because
803 * autonegotiation is managed by the PHY rather than the MAC. Software must
804 * also configure these bits when link is forced on a fiber connection.
805 **/
igb_force_mac_fc(struct e1000_hw * hw)806 s32 igb_force_mac_fc(struct e1000_hw *hw)
807 {
808 u32 ctrl;
809 s32 ret_val = 0;
810
811 ctrl = rd32(E1000_CTRL);
812
813 /* Because we didn't get link via the internal auto-negotiation
814 * mechanism (we either forced link or we got link via PHY
815 * auto-neg), we have to manually enable/disable transmit an
816 * receive flow control.
817 *
818 * The "Case" statement below enables/disable flow control
819 * according to the "hw->fc.current_mode" parameter.
820 *
821 * The possible values of the "fc" parameter are:
822 * 0: Flow control is completely disabled
823 * 1: Rx flow control is enabled (we can receive pause
824 * frames but not send pause frames).
825 * 2: Tx flow control is enabled (we can send pause frames
826 * frames but we do not receive pause frames).
827 * 3: Both Rx and TX flow control (symmetric) is enabled.
828 * other: No other values should be possible at this point.
829 */
830 hw_dbg("hw->fc.current_mode = %u\n", hw->fc.current_mode);
831
832 switch (hw->fc.current_mode) {
833 case e1000_fc_none:
834 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
835 break;
836 case e1000_fc_rx_pause:
837 ctrl &= (~E1000_CTRL_TFCE);
838 ctrl |= E1000_CTRL_RFCE;
839 break;
840 case e1000_fc_tx_pause:
841 ctrl &= (~E1000_CTRL_RFCE);
842 ctrl |= E1000_CTRL_TFCE;
843 break;
844 case e1000_fc_full:
845 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
846 break;
847 default:
848 hw_dbg("Flow control param set incorrectly\n");
849 ret_val = -E1000_ERR_CONFIG;
850 goto out;
851 }
852
853 wr32(E1000_CTRL, ctrl);
854
855 out:
856 return ret_val;
857 }
858
859 /**
860 * igb_config_fc_after_link_up - Configures flow control after link
861 * @hw: pointer to the HW structure
862 *
863 * Checks the status of auto-negotiation after link up to ensure that the
864 * speed and duplex were not forced. If the link needed to be forced, then
865 * flow control needs to be forced also. If auto-negotiation is enabled
866 * and did not fail, then we configure flow control based on our link
867 * partner.
868 **/
igb_config_fc_after_link_up(struct e1000_hw * hw)869 s32 igb_config_fc_after_link_up(struct e1000_hw *hw)
870 {
871 struct e1000_mac_info *mac = &hw->mac;
872 s32 ret_val = 0;
873 u32 pcs_status_reg, pcs_adv_reg, pcs_lp_ability_reg, pcs_ctrl_reg;
874 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg;
875 u16 speed, duplex;
876
877 /* Check for the case where we have fiber media and auto-neg failed
878 * so we had to force link. In this case, we need to force the
879 * configuration of the MAC to match the "fc" parameter.
880 */
881 if (mac->autoneg_failed) {
882 if (hw->phy.media_type == e1000_media_type_internal_serdes)
883 ret_val = igb_force_mac_fc(hw);
884 } else {
885 if (hw->phy.media_type == e1000_media_type_copper)
886 ret_val = igb_force_mac_fc(hw);
887 }
888
889 if (ret_val) {
890 hw_dbg("Error forcing flow control settings\n");
891 goto out;
892 }
893
894 /* Check for the case where we have copper media and auto-neg is
895 * enabled. In this case, we need to check and see if Auto-Neg
896 * has completed, and if so, how the PHY and link partner has
897 * flow control configured.
898 */
899 if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) {
900 /* Read the MII Status Register and check to see if AutoNeg
901 * has completed. We read this twice because this reg has
902 * some "sticky" (latched) bits.
903 */
904 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS,
905 &mii_status_reg);
906 if (ret_val)
907 goto out;
908 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS,
909 &mii_status_reg);
910 if (ret_val)
911 goto out;
912
913 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) {
914 hw_dbg("Copper PHY and Auto Neg has not completed.\n");
915 goto out;
916 }
917
918 /* The AutoNeg process has completed, so we now need to
919 * read both the Auto Negotiation Advertisement
920 * Register (Address 4) and the Auto_Negotiation Base
921 * Page Ability Register (Address 5) to determine how
922 * flow control was negotiated.
923 */
924 ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV,
925 &mii_nway_adv_reg);
926 if (ret_val)
927 goto out;
928 ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY,
929 &mii_nway_lp_ability_reg);
930 if (ret_val)
931 goto out;
932
933 /* Two bits in the Auto Negotiation Advertisement Register
934 * (Address 4) and two bits in the Auto Negotiation Base
935 * Page Ability Register (Address 5) determine flow control
936 * for both the PHY and the link partner. The following
937 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
938 * 1999, describes these PAUSE resolution bits and how flow
939 * control is determined based upon these settings.
940 * NOTE: DC = Don't Care
941 *
942 * LOCAL DEVICE | LINK PARTNER
943 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
944 *-------|---------|-------|---------|--------------------
945 * 0 | 0 | DC | DC | e1000_fc_none
946 * 0 | 1 | 0 | DC | e1000_fc_none
947 * 0 | 1 | 1 | 0 | e1000_fc_none
948 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
949 * 1 | 0 | 0 | DC | e1000_fc_none
950 * 1 | DC | 1 | DC | e1000_fc_full
951 * 1 | 1 | 0 | 0 | e1000_fc_none
952 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
953 *
954 * Are both PAUSE bits set to 1? If so, this implies
955 * Symmetric Flow Control is enabled at both ends. The
956 * ASM_DIR bits are irrelevant per the spec.
957 *
958 * For Symmetric Flow Control:
959 *
960 * LOCAL DEVICE | LINK PARTNER
961 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
962 *-------|---------|-------|---------|--------------------
963 * 1 | DC | 1 | DC | E1000_fc_full
964 *
965 */
966 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
967 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
968 /* Now we need to check if the user selected RX ONLY
969 * of pause frames. In this case, we had to advertise
970 * FULL flow control because we could not advertise RX
971 * ONLY. Hence, we must now check to see if we need to
972 * turn OFF the TRANSMISSION of PAUSE frames.
973 */
974 if (hw->fc.requested_mode == e1000_fc_full) {
975 hw->fc.current_mode = e1000_fc_full;
976 hw_dbg("Flow Control = FULL.\n");
977 } else {
978 hw->fc.current_mode = e1000_fc_rx_pause;
979 hw_dbg("Flow Control = RX PAUSE frames only.\n");
980 }
981 }
982 /* For receiving PAUSE frames ONLY.
983 *
984 * LOCAL DEVICE | LINK PARTNER
985 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
986 *-------|---------|-------|---------|--------------------
987 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
988 */
989 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
990 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
991 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
992 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
993 hw->fc.current_mode = e1000_fc_tx_pause;
994 hw_dbg("Flow Control = TX PAUSE frames only.\n");
995 }
996 /* For transmitting PAUSE frames ONLY.
997 *
998 * LOCAL DEVICE | LINK PARTNER
999 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1000 *-------|---------|-------|---------|--------------------
1001 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1002 */
1003 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1004 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1005 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1006 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1007 hw->fc.current_mode = e1000_fc_rx_pause;
1008 hw_dbg("Flow Control = RX PAUSE frames only.\n");
1009 }
1010 /* Per the IEEE spec, at this point flow control should be
1011 * disabled. However, we want to consider that we could
1012 * be connected to a legacy switch that doesn't advertise
1013 * desired flow control, but can be forced on the link
1014 * partner. So if we advertised no flow control, that is
1015 * what we will resolve to. If we advertised some kind of
1016 * receive capability (Rx Pause Only or Full Flow Control)
1017 * and the link partner advertised none, we will configure
1018 * ourselves to enable Rx Flow Control only. We can do
1019 * this safely for two reasons: If the link partner really
1020 * didn't want flow control enabled, and we enable Rx, no
1021 * harm done since we won't be receiving any PAUSE frames
1022 * anyway. If the intent on the link partner was to have
1023 * flow control enabled, then by us enabling RX only, we
1024 * can at least receive pause frames and process them.
1025 * This is a good idea because in most cases, since we are
1026 * predominantly a server NIC, more times than not we will
1027 * be asked to delay transmission of packets than asking
1028 * our link partner to pause transmission of frames.
1029 */
1030 else if ((hw->fc.requested_mode == e1000_fc_none) ||
1031 (hw->fc.requested_mode == e1000_fc_tx_pause) ||
1032 (hw->fc.strict_ieee)) {
1033 hw->fc.current_mode = e1000_fc_none;
1034 hw_dbg("Flow Control = NONE.\n");
1035 } else {
1036 hw->fc.current_mode = e1000_fc_rx_pause;
1037 hw_dbg("Flow Control = RX PAUSE frames only.\n");
1038 }
1039
1040 /* Now we need to do one last check... If we auto-
1041 * negotiated to HALF DUPLEX, flow control should not be
1042 * enabled per IEEE 802.3 spec.
1043 */
1044 ret_val = hw->mac.ops.get_speed_and_duplex(hw, &speed, &duplex);
1045 if (ret_val) {
1046 hw_dbg("Error getting link speed and duplex\n");
1047 goto out;
1048 }
1049
1050 if (duplex == HALF_DUPLEX)
1051 hw->fc.current_mode = e1000_fc_none;
1052
1053 /* Now we call a subroutine to actually force the MAC
1054 * controller to use the correct flow control settings.
1055 */
1056 ret_val = igb_force_mac_fc(hw);
1057 if (ret_val) {
1058 hw_dbg("Error forcing flow control settings\n");
1059 goto out;
1060 }
1061 }
1062 /* Check for the case where we have SerDes media and auto-neg is
1063 * enabled. In this case, we need to check and see if Auto-Neg
1064 * has completed, and if so, how the PHY and link partner has
1065 * flow control configured.
1066 */
1067 if ((hw->phy.media_type == e1000_media_type_internal_serdes)
1068 && mac->autoneg) {
1069 /* Read the PCS_LSTS and check to see if AutoNeg
1070 * has completed.
1071 */
1072 pcs_status_reg = rd32(E1000_PCS_LSTAT);
1073
1074 if (!(pcs_status_reg & E1000_PCS_LSTS_AN_COMPLETE)) {
1075 hw_dbg("PCS Auto Neg has not completed.\n");
1076 return ret_val;
1077 }
1078
1079 /* The AutoNeg process has completed, so we now need to
1080 * read both the Auto Negotiation Advertisement
1081 * Register (PCS_ANADV) and the Auto_Negotiation Base
1082 * Page Ability Register (PCS_LPAB) to determine how
1083 * flow control was negotiated.
1084 */
1085 pcs_adv_reg = rd32(E1000_PCS_ANADV);
1086 pcs_lp_ability_reg = rd32(E1000_PCS_LPAB);
1087
1088 /* Two bits in the Auto Negotiation Advertisement Register
1089 * (PCS_ANADV) and two bits in the Auto Negotiation Base
1090 * Page Ability Register (PCS_LPAB) determine flow control
1091 * for both the PHY and the link partner. The following
1092 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
1093 * 1999, describes these PAUSE resolution bits and how flow
1094 * control is determined based upon these settings.
1095 * NOTE: DC = Don't Care
1096 *
1097 * LOCAL DEVICE | LINK PARTNER
1098 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
1099 *-------|---------|-------|---------|--------------------
1100 * 0 | 0 | DC | DC | e1000_fc_none
1101 * 0 | 1 | 0 | DC | e1000_fc_none
1102 * 0 | 1 | 1 | 0 | e1000_fc_none
1103 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1104 * 1 | 0 | 0 | DC | e1000_fc_none
1105 * 1 | DC | 1 | DC | e1000_fc_full
1106 * 1 | 1 | 0 | 0 | e1000_fc_none
1107 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1108 *
1109 * Are both PAUSE bits set to 1? If so, this implies
1110 * Symmetric Flow Control is enabled at both ends. The
1111 * ASM_DIR bits are irrelevant per the spec.
1112 *
1113 * For Symmetric Flow Control:
1114 *
1115 * LOCAL DEVICE | LINK PARTNER
1116 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1117 *-------|---------|-------|---------|--------------------
1118 * 1 | DC | 1 | DC | e1000_fc_full
1119 *
1120 */
1121 if ((pcs_adv_reg & E1000_TXCW_PAUSE) &&
1122 (pcs_lp_ability_reg & E1000_TXCW_PAUSE)) {
1123 /* Now we need to check if the user selected Rx ONLY
1124 * of pause frames. In this case, we had to advertise
1125 * FULL flow control because we could not advertise Rx
1126 * ONLY. Hence, we must now check to see if we need to
1127 * turn OFF the TRANSMISSION of PAUSE frames.
1128 */
1129 if (hw->fc.requested_mode == e1000_fc_full) {
1130 hw->fc.current_mode = e1000_fc_full;
1131 hw_dbg("Flow Control = FULL.\n");
1132 } else {
1133 hw->fc.current_mode = e1000_fc_rx_pause;
1134 hw_dbg("Flow Control = Rx PAUSE frames only.\n");
1135 }
1136 }
1137 /* For receiving PAUSE frames ONLY.
1138 *
1139 * LOCAL DEVICE | LINK PARTNER
1140 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1141 *-------|---------|-------|---------|--------------------
1142 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1143 */
1144 else if (!(pcs_adv_reg & E1000_TXCW_PAUSE) &&
1145 (pcs_adv_reg & E1000_TXCW_ASM_DIR) &&
1146 (pcs_lp_ability_reg & E1000_TXCW_PAUSE) &&
1147 (pcs_lp_ability_reg & E1000_TXCW_ASM_DIR)) {
1148 hw->fc.current_mode = e1000_fc_tx_pause;
1149 hw_dbg("Flow Control = Tx PAUSE frames only.\n");
1150 }
1151 /* For transmitting PAUSE frames ONLY.
1152 *
1153 * LOCAL DEVICE | LINK PARTNER
1154 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1155 *-------|---------|-------|---------|--------------------
1156 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1157 */
1158 else if ((pcs_adv_reg & E1000_TXCW_PAUSE) &&
1159 (pcs_adv_reg & E1000_TXCW_ASM_DIR) &&
1160 !(pcs_lp_ability_reg & E1000_TXCW_PAUSE) &&
1161 (pcs_lp_ability_reg & E1000_TXCW_ASM_DIR)) {
1162 hw->fc.current_mode = e1000_fc_rx_pause;
1163 hw_dbg("Flow Control = Rx PAUSE frames only.\n");
1164 } else {
1165 /* Per the IEEE spec, at this point flow control
1166 * should be disabled.
1167 */
1168 hw->fc.current_mode = e1000_fc_none;
1169 hw_dbg("Flow Control = NONE.\n");
1170 }
1171
1172 /* Now we call a subroutine to actually force the MAC
1173 * controller to use the correct flow control settings.
1174 */
1175 pcs_ctrl_reg = rd32(E1000_PCS_LCTL);
1176 pcs_ctrl_reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1177 wr32(E1000_PCS_LCTL, pcs_ctrl_reg);
1178
1179 ret_val = igb_force_mac_fc(hw);
1180 if (ret_val) {
1181 hw_dbg("Error forcing flow control settings\n");
1182 return ret_val;
1183 }
1184 }
1185
1186 out:
1187 return ret_val;
1188 }
1189
1190 /**
1191 * igb_get_speed_and_duplex_copper - Retrieve current speed/duplex
1192 * @hw: pointer to the HW structure
1193 * @speed: stores the current speed
1194 * @duplex: stores the current duplex
1195 *
1196 * Read the status register for the current speed/duplex and store the current
1197 * speed and duplex for copper connections.
1198 **/
igb_get_speed_and_duplex_copper(struct e1000_hw * hw,u16 * speed,u16 * duplex)1199 s32 igb_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed,
1200 u16 *duplex)
1201 {
1202 u32 status;
1203
1204 status = rd32(E1000_STATUS);
1205 if (status & E1000_STATUS_SPEED_1000) {
1206 *speed = SPEED_1000;
1207 hw_dbg("1000 Mbs, ");
1208 } else if (status & E1000_STATUS_SPEED_100) {
1209 *speed = SPEED_100;
1210 hw_dbg("100 Mbs, ");
1211 } else {
1212 *speed = SPEED_10;
1213 hw_dbg("10 Mbs, ");
1214 }
1215
1216 if (status & E1000_STATUS_FD) {
1217 *duplex = FULL_DUPLEX;
1218 hw_dbg("Full Duplex\n");
1219 } else {
1220 *duplex = HALF_DUPLEX;
1221 hw_dbg("Half Duplex\n");
1222 }
1223
1224 return 0;
1225 }
1226
1227 /**
1228 * igb_get_hw_semaphore - Acquire hardware semaphore
1229 * @hw: pointer to the HW structure
1230 *
1231 * Acquire the HW semaphore to access the PHY or NVM
1232 **/
igb_get_hw_semaphore(struct e1000_hw * hw)1233 s32 igb_get_hw_semaphore(struct e1000_hw *hw)
1234 {
1235 u32 swsm;
1236 s32 ret_val = 0;
1237 s32 timeout = hw->nvm.word_size + 1;
1238 s32 i = 0;
1239
1240 /* Get the SW semaphore */
1241 while (i < timeout) {
1242 swsm = rd32(E1000_SWSM);
1243 if (!(swsm & E1000_SWSM_SMBI))
1244 break;
1245
1246 udelay(50);
1247 i++;
1248 }
1249
1250 if (i == timeout) {
1251 hw_dbg("Driver can't access device - SMBI bit is set.\n");
1252 ret_val = -E1000_ERR_NVM;
1253 goto out;
1254 }
1255
1256 /* Get the FW semaphore. */
1257 for (i = 0; i < timeout; i++) {
1258 swsm = rd32(E1000_SWSM);
1259 wr32(E1000_SWSM, swsm | E1000_SWSM_SWESMBI);
1260
1261 /* Semaphore acquired if bit latched */
1262 if (rd32(E1000_SWSM) & E1000_SWSM_SWESMBI)
1263 break;
1264
1265 udelay(50);
1266 }
1267
1268 if (i == timeout) {
1269 /* Release semaphores */
1270 igb_put_hw_semaphore(hw);
1271 hw_dbg("Driver can't access the NVM\n");
1272 ret_val = -E1000_ERR_NVM;
1273 goto out;
1274 }
1275
1276 out:
1277 return ret_val;
1278 }
1279
1280 /**
1281 * igb_put_hw_semaphore - Release hardware semaphore
1282 * @hw: pointer to the HW structure
1283 *
1284 * Release hardware semaphore used to access the PHY or NVM
1285 **/
igb_put_hw_semaphore(struct e1000_hw * hw)1286 void igb_put_hw_semaphore(struct e1000_hw *hw)
1287 {
1288 u32 swsm;
1289
1290 swsm = rd32(E1000_SWSM);
1291
1292 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
1293
1294 wr32(E1000_SWSM, swsm);
1295 }
1296
1297 /**
1298 * igb_get_auto_rd_done - Check for auto read completion
1299 * @hw: pointer to the HW structure
1300 *
1301 * Check EEPROM for Auto Read done bit.
1302 **/
igb_get_auto_rd_done(struct e1000_hw * hw)1303 s32 igb_get_auto_rd_done(struct e1000_hw *hw)
1304 {
1305 s32 i = 0;
1306 s32 ret_val = 0;
1307
1308
1309 while (i < AUTO_READ_DONE_TIMEOUT) {
1310 if (rd32(E1000_EECD) & E1000_EECD_AUTO_RD)
1311 break;
1312 usleep_range(1000, 2000);
1313 i++;
1314 }
1315
1316 if (i == AUTO_READ_DONE_TIMEOUT) {
1317 hw_dbg("Auto read by HW from NVM has not completed.\n");
1318 ret_val = -E1000_ERR_RESET;
1319 goto out;
1320 }
1321
1322 out:
1323 return ret_val;
1324 }
1325
1326 /**
1327 * igb_valid_led_default - Verify a valid default LED config
1328 * @hw: pointer to the HW structure
1329 * @data: pointer to the NVM (EEPROM)
1330 *
1331 * Read the EEPROM for the current default LED configuration. If the
1332 * LED configuration is not valid, set to a valid LED configuration.
1333 **/
igb_valid_led_default(struct e1000_hw * hw,u16 * data)1334 static s32 igb_valid_led_default(struct e1000_hw *hw, u16 *data)
1335 {
1336 s32 ret_val;
1337
1338 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1339 if (ret_val) {
1340 hw_dbg("NVM Read Error\n");
1341 goto out;
1342 }
1343
1344 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) {
1345 switch (hw->phy.media_type) {
1346 case e1000_media_type_internal_serdes:
1347 *data = ID_LED_DEFAULT_82575_SERDES;
1348 break;
1349 case e1000_media_type_copper:
1350 default:
1351 *data = ID_LED_DEFAULT;
1352 break;
1353 }
1354 }
1355 out:
1356 return ret_val;
1357 }
1358
1359 /**
1360 * igb_id_led_init -
1361 * @hw: pointer to the HW structure
1362 *
1363 **/
igb_id_led_init(struct e1000_hw * hw)1364 s32 igb_id_led_init(struct e1000_hw *hw)
1365 {
1366 struct e1000_mac_info *mac = &hw->mac;
1367 s32 ret_val;
1368 const u32 ledctl_mask = 0x000000FF;
1369 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON;
1370 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
1371 u16 data, i, temp;
1372 const u16 led_mask = 0x0F;
1373
1374 /* i210 and i211 devices have different LED mechanism */
1375 if ((hw->mac.type == e1000_i210) ||
1376 (hw->mac.type == e1000_i211))
1377 ret_val = igb_valid_led_default_i210(hw, &data);
1378 else
1379 ret_val = igb_valid_led_default(hw, &data);
1380
1381 if (ret_val)
1382 goto out;
1383
1384 mac->ledctl_default = rd32(E1000_LEDCTL);
1385 mac->ledctl_mode1 = mac->ledctl_default;
1386 mac->ledctl_mode2 = mac->ledctl_default;
1387
1388 for (i = 0; i < 4; i++) {
1389 temp = (data >> (i << 2)) & led_mask;
1390 switch (temp) {
1391 case ID_LED_ON1_DEF2:
1392 case ID_LED_ON1_ON2:
1393 case ID_LED_ON1_OFF2:
1394 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1395 mac->ledctl_mode1 |= ledctl_on << (i << 3);
1396 break;
1397 case ID_LED_OFF1_DEF2:
1398 case ID_LED_OFF1_ON2:
1399 case ID_LED_OFF1_OFF2:
1400 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1401 mac->ledctl_mode1 |= ledctl_off << (i << 3);
1402 break;
1403 default:
1404 /* Do nothing */
1405 break;
1406 }
1407 switch (temp) {
1408 case ID_LED_DEF1_ON2:
1409 case ID_LED_ON1_ON2:
1410 case ID_LED_OFF1_ON2:
1411 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1412 mac->ledctl_mode2 |= ledctl_on << (i << 3);
1413 break;
1414 case ID_LED_DEF1_OFF2:
1415 case ID_LED_ON1_OFF2:
1416 case ID_LED_OFF1_OFF2:
1417 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1418 mac->ledctl_mode2 |= ledctl_off << (i << 3);
1419 break;
1420 default:
1421 /* Do nothing */
1422 break;
1423 }
1424 }
1425
1426 out:
1427 return ret_val;
1428 }
1429
1430 /**
1431 * igb_cleanup_led - Set LED config to default operation
1432 * @hw: pointer to the HW structure
1433 *
1434 * Remove the current LED configuration and set the LED configuration
1435 * to the default value, saved from the EEPROM.
1436 **/
igb_cleanup_led(struct e1000_hw * hw)1437 s32 igb_cleanup_led(struct e1000_hw *hw)
1438 {
1439 wr32(E1000_LEDCTL, hw->mac.ledctl_default);
1440 return 0;
1441 }
1442
1443 /**
1444 * igb_blink_led - Blink LED
1445 * @hw: pointer to the HW structure
1446 *
1447 * Blink the led's which are set to be on.
1448 **/
igb_blink_led(struct e1000_hw * hw)1449 s32 igb_blink_led(struct e1000_hw *hw)
1450 {
1451 u32 ledctl_blink = 0;
1452 u32 i;
1453
1454 if (hw->phy.media_type == e1000_media_type_fiber) {
1455 /* always blink LED0 for PCI-E fiber */
1456 ledctl_blink = E1000_LEDCTL_LED0_BLINK |
1457 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT);
1458 } else {
1459 /* Set the blink bit for each LED that's "on" (0x0E)
1460 * (or "off" if inverted) in ledctl_mode2. The blink
1461 * logic in hardware only works when mode is set to "on"
1462 * so it must be changed accordingly when the mode is
1463 * "off" and inverted.
1464 */
1465 ledctl_blink = hw->mac.ledctl_mode2;
1466 for (i = 0; i < 32; i += 8) {
1467 u32 mode = (hw->mac.ledctl_mode2 >> i) &
1468 E1000_LEDCTL_LED0_MODE_MASK;
1469 u32 led_default = hw->mac.ledctl_default >> i;
1470
1471 if ((!(led_default & E1000_LEDCTL_LED0_IVRT) &&
1472 (mode == E1000_LEDCTL_MODE_LED_ON)) ||
1473 ((led_default & E1000_LEDCTL_LED0_IVRT) &&
1474 (mode == E1000_LEDCTL_MODE_LED_OFF))) {
1475 ledctl_blink &=
1476 ~(E1000_LEDCTL_LED0_MODE_MASK << i);
1477 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK |
1478 E1000_LEDCTL_MODE_LED_ON) << i;
1479 }
1480 }
1481 }
1482
1483 wr32(E1000_LEDCTL, ledctl_blink);
1484
1485 return 0;
1486 }
1487
1488 /**
1489 * igb_led_off - Turn LED off
1490 * @hw: pointer to the HW structure
1491 *
1492 * Turn LED off.
1493 **/
igb_led_off(struct e1000_hw * hw)1494 s32 igb_led_off(struct e1000_hw *hw)
1495 {
1496 switch (hw->phy.media_type) {
1497 case e1000_media_type_copper:
1498 wr32(E1000_LEDCTL, hw->mac.ledctl_mode1);
1499 break;
1500 default:
1501 break;
1502 }
1503
1504 return 0;
1505 }
1506
1507 /**
1508 * igb_disable_pcie_master - Disables PCI-express master access
1509 * @hw: pointer to the HW structure
1510 *
1511 * Returns 0 (0) if successful, else returns -10
1512 * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused
1513 * the master requests to be disabled.
1514 *
1515 * Disables PCI-Express master access and verifies there are no pending
1516 * requests.
1517 **/
igb_disable_pcie_master(struct e1000_hw * hw)1518 s32 igb_disable_pcie_master(struct e1000_hw *hw)
1519 {
1520 u32 ctrl;
1521 s32 timeout = MASTER_DISABLE_TIMEOUT;
1522 s32 ret_val = 0;
1523
1524 if (hw->bus.type != e1000_bus_type_pci_express)
1525 goto out;
1526
1527 ctrl = rd32(E1000_CTRL);
1528 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE;
1529 wr32(E1000_CTRL, ctrl);
1530
1531 while (timeout) {
1532 if (!(rd32(E1000_STATUS) &
1533 E1000_STATUS_GIO_MASTER_ENABLE))
1534 break;
1535 udelay(100);
1536 timeout--;
1537 }
1538
1539 if (!timeout) {
1540 hw_dbg("Master requests are pending.\n");
1541 ret_val = -E1000_ERR_MASTER_REQUESTS_PENDING;
1542 goto out;
1543 }
1544
1545 out:
1546 return ret_val;
1547 }
1548
1549 /**
1550 * igb_validate_mdi_setting - Verify MDI/MDIx settings
1551 * @hw: pointer to the HW structure
1552 *
1553 * Verify that when not using auto-negotitation that MDI/MDIx is correctly
1554 * set, which is forced to MDI mode only.
1555 **/
igb_validate_mdi_setting(struct e1000_hw * hw)1556 s32 igb_validate_mdi_setting(struct e1000_hw *hw)
1557 {
1558 s32 ret_val = 0;
1559
1560 /* All MDI settings are supported on 82580 and newer. */
1561 if (hw->mac.type >= e1000_82580)
1562 goto out;
1563
1564 if (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) {
1565 hw_dbg("Invalid MDI setting detected\n");
1566 hw->phy.mdix = 1;
1567 ret_val = -E1000_ERR_CONFIG;
1568 goto out;
1569 }
1570
1571 out:
1572 return ret_val;
1573 }
1574
1575 /**
1576 * igb_write_8bit_ctrl_reg - Write a 8bit CTRL register
1577 * @hw: pointer to the HW structure
1578 * @reg: 32bit register offset such as E1000_SCTL
1579 * @offset: register offset to write to
1580 * @data: data to write at register offset
1581 *
1582 * Writes an address/data control type register. There are several of these
1583 * and they all have the format address << 8 | data and bit 31 is polled for
1584 * completion.
1585 **/
igb_write_8bit_ctrl_reg(struct e1000_hw * hw,u32 reg,u32 offset,u8 data)1586 s32 igb_write_8bit_ctrl_reg(struct e1000_hw *hw, u32 reg,
1587 u32 offset, u8 data)
1588 {
1589 u32 i, regvalue = 0;
1590 s32 ret_val = 0;
1591
1592 /* Set up the address and data */
1593 regvalue = ((u32)data) | (offset << E1000_GEN_CTL_ADDRESS_SHIFT);
1594 wr32(reg, regvalue);
1595
1596 /* Poll the ready bit to see if the MDI read completed */
1597 for (i = 0; i < E1000_GEN_POLL_TIMEOUT; i++) {
1598 udelay(5);
1599 regvalue = rd32(reg);
1600 if (regvalue & E1000_GEN_CTL_READY)
1601 break;
1602 }
1603 if (!(regvalue & E1000_GEN_CTL_READY)) {
1604 hw_dbg("Reg %08x did not indicate ready\n", reg);
1605 ret_val = -E1000_ERR_PHY;
1606 goto out;
1607 }
1608
1609 out:
1610 return ret_val;
1611 }
1612
1613 /**
1614 * igb_enable_mng_pass_thru - Enable processing of ARP's
1615 * @hw: pointer to the HW structure
1616 *
1617 * Verifies the hardware needs to leave interface enabled so that frames can
1618 * be directed to and from the management interface.
1619 **/
igb_enable_mng_pass_thru(struct e1000_hw * hw)1620 bool igb_enable_mng_pass_thru(struct e1000_hw *hw)
1621 {
1622 u32 manc;
1623 u32 fwsm, factps;
1624 bool ret_val = false;
1625
1626 if (!hw->mac.asf_firmware_present)
1627 goto out;
1628
1629 manc = rd32(E1000_MANC);
1630
1631 if (!(manc & E1000_MANC_RCV_TCO_EN))
1632 goto out;
1633
1634 if (hw->mac.arc_subsystem_valid) {
1635 fwsm = rd32(E1000_FWSM);
1636 factps = rd32(E1000_FACTPS);
1637
1638 if (!(factps & E1000_FACTPS_MNGCG) &&
1639 ((fwsm & E1000_FWSM_MODE_MASK) ==
1640 (e1000_mng_mode_pt << E1000_FWSM_MODE_SHIFT))) {
1641 ret_val = true;
1642 goto out;
1643 }
1644 } else {
1645 if ((manc & E1000_MANC_SMBUS_EN) &&
1646 !(manc & E1000_MANC_ASF_EN)) {
1647 ret_val = true;
1648 goto out;
1649 }
1650 }
1651
1652 out:
1653 return ret_val;
1654 }
1655