1 /* SPDX-License-Identifier: MIT */
2 /*
3 * Copyright © 2019 Intel Corporation
4 */
5
6 #ifndef __INTEL_DP_H__
7 #define __INTEL_DP_H__
8
9 #include <linux/types.h>
10
11 #include "i915_reg.h"
12
13 enum pipe;
14 enum port;
15 struct drm_connector_state;
16 struct drm_encoder;
17 struct drm_i915_private;
18 struct drm_modeset_acquire_ctx;
19 struct drm_dp_vsc_sdp;
20 struct intel_atomic_state;
21 struct intel_connector;
22 struct intel_crtc_state;
23 struct intel_digital_port;
24 struct intel_dp;
25 struct intel_encoder;
26
27 struct link_config_limits {
28 int min_clock, max_clock;
29 int min_lane_count, max_lane_count;
30 int min_bpp, max_bpp;
31 };
32
33 void intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
34 struct intel_crtc_state *pipe_config,
35 struct link_config_limits *limits);
36 bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
37 const struct drm_connector_state *conn_state);
38 int intel_dp_min_bpp(const struct intel_crtc_state *crtc_state);
39 bool intel_dp_port_enabled(struct drm_i915_private *dev_priv,
40 i915_reg_t dp_reg, enum port port,
41 enum pipe *pipe);
42 bool intel_dp_init(struct drm_i915_private *dev_priv, i915_reg_t output_reg,
43 enum port port);
44 bool intel_dp_init_connector(struct intel_digital_port *dig_port,
45 struct intel_connector *intel_connector);
46 void intel_dp_set_link_params(struct intel_dp *intel_dp,
47 int link_rate, u8 lane_count,
48 bool link_mst);
49 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
50 int link_rate, u8 lane_count);
51 int intel_dp_retrain_link(struct intel_encoder *encoder,
52 struct drm_modeset_acquire_ctx *ctx);
53 void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode);
54 void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp,
55 const struct intel_crtc_state *crtc_state);
56 void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
57 const struct intel_crtc_state *crtc_state,
58 bool enable);
59 void intel_dp_encoder_reset(struct drm_encoder *encoder);
60 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
61 void intel_dp_encoder_flush_work(struct drm_encoder *encoder);
62 int intel_dp_compute_config(struct intel_encoder *encoder,
63 struct intel_crtc_state *pipe_config,
64 struct drm_connector_state *conn_state);
65 bool intel_dp_is_edp(struct intel_dp *intel_dp);
66 bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
67 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *dig_port,
68 bool long_hpd);
69 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
70 const struct drm_connector_state *conn_state);
71 void intel_edp_backlight_off(const struct drm_connector_state *conn_state);
72 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
73 void intel_edp_panel_on(struct intel_dp *intel_dp);
74 void intel_edp_panel_off(struct intel_dp *intel_dp);
75 void intel_dp_mst_suspend(struct drm_i915_private *dev_priv);
76 void intel_dp_mst_resume(struct drm_i915_private *dev_priv);
77 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
78 int intel_dp_max_lane_count(struct intel_dp *intel_dp);
79 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
80 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv);
81 u32 intel_dp_pack_aux(const u8 *src, int src_bytes);
82
83 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
84 const struct intel_crtc_state *crtc_state);
85 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
86 const struct intel_crtc_state *crtc_state);
87 void intel_edp_drrs_update(struct intel_dp *intel_dp,
88 const struct intel_crtc_state *crtc_state);
89 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
90 unsigned int frontbuffer_bits);
91 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
92 unsigned int frontbuffer_bits);
93
94 void
95 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
96 u8 dp_train_pat);
97 void
98 intel_dp_set_signal_levels(struct intel_dp *intel_dp);
99 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
100 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
101 u8 *link_bw, u8 *rate_select);
102 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
103 bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp);
104 bool
105 intel_dp_get_link_status(struct intel_dp *intel_dp, u8 *link_status);
106
107 bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp);
108 int intel_dp_link_required(int pixel_clock, int bpp);
109 int intel_dp_max_data_rate(int max_link_clock, int max_lanes);
110 bool intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
111 const struct drm_connector_state *conn_state);
112 void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp,
113 const struct intel_crtc_state *crtc_state,
114 const struct drm_connector_state *conn_state,
115 struct drm_dp_vsc_sdp *vsc);
116 void intel_write_dp_vsc_sdp(struct intel_encoder *encoder,
117 const struct intel_crtc_state *crtc_state,
118 struct drm_dp_vsc_sdp *vsc);
119 void intel_dp_set_infoframes(struct intel_encoder *encoder, bool enable,
120 const struct intel_crtc_state *crtc_state,
121 const struct drm_connector_state *conn_state);
122 void intel_read_dp_sdp(struct intel_encoder *encoder,
123 struct intel_crtc_state *crtc_state,
124 unsigned int type);
125 bool intel_digital_port_connected(struct intel_encoder *encoder);
126 void intel_dp_process_phy_request(struct intel_dp *intel_dp);
127
intel_dp_unused_lane_mask(int lane_count)128 static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
129 {
130 return ~((1 << lane_count) - 1) & 0xf;
131 }
132
133 u32 intel_dp_mode_to_fec_clock(u32 mode_clock);
134
135 void intel_ddi_update_pipe(struct intel_atomic_state *state,
136 struct intel_encoder *encoder,
137 const struct intel_crtc_state *crtc_state,
138 const struct drm_connector_state *conn_state);
139
140 int intel_dp_init_hdcp(struct intel_digital_port *dig_port,
141 struct intel_connector *intel_connector);
142
143 #endif /* __INTEL_DP_H__ */
144