1 /*
2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33
34 #include <linux/module.h>
35 #include <linux/init.h>
36 #include <linux/slab.h>
37 #include <linux/errno.h>
38 #include <linux/netdevice.h>
39 #include <linux/inetdevice.h>
40 #include <linux/rtnetlink.h>
41 #include <linux/if_vlan.h>
42 #include <linux/sched/mm.h>
43 #include <linux/sched/task.h>
44
45 #include <net/ipv6.h>
46 #include <net/addrconf.h>
47 #include <net/devlink.h>
48
49 #include <rdma/ib_smi.h>
50 #include <rdma/ib_user_verbs.h>
51 #include <rdma/ib_addr.h>
52 #include <rdma/ib_cache.h>
53
54 #include <net/bonding.h>
55
56 #include <linux/mlx4/driver.h>
57 #include <linux/mlx4/cmd.h>
58 #include <linux/mlx4/qp.h>
59
60 #include "mlx4_ib.h"
61 #include <rdma/mlx4-abi.h>
62
63 #define DRV_NAME MLX4_IB_DRV_NAME
64 #define DRV_VERSION "4.0-0"
65
66 #define MLX4_IB_FLOW_MAX_PRIO 0xFFF
67 #define MLX4_IB_FLOW_QPN_MASK 0xFFFFFF
68 #define MLX4_IB_CARD_REV_A0 0xA0
69
70 MODULE_AUTHOR("Roland Dreier");
71 MODULE_DESCRIPTION("Mellanox ConnectX HCA InfiniBand driver");
72 MODULE_LICENSE("Dual BSD/GPL");
73
74 int mlx4_ib_sm_guid_assign = 0;
75 module_param_named(sm_guid_assign, mlx4_ib_sm_guid_assign, int, 0444);
76 MODULE_PARM_DESC(sm_guid_assign, "Enable SM alias_GUID assignment if sm_guid_assign > 0 (Default: 0)");
77
78 static const char mlx4_ib_version[] =
79 DRV_NAME ": Mellanox ConnectX InfiniBand driver v"
80 DRV_VERSION "\n";
81
82 static void do_slave_init(struct mlx4_ib_dev *ibdev, int slave, int do_init);
83 static enum rdma_link_layer mlx4_ib_port_link_layer(struct ib_device *device,
84 u8 port_num);
85
86 static struct workqueue_struct *wq;
87
init_query_mad(struct ib_smp * mad)88 static void init_query_mad(struct ib_smp *mad)
89 {
90 mad->base_version = 1;
91 mad->mgmt_class = IB_MGMT_CLASS_SUBN_LID_ROUTED;
92 mad->class_version = 1;
93 mad->method = IB_MGMT_METHOD_GET;
94 }
95
check_flow_steering_support(struct mlx4_dev * dev)96 static int check_flow_steering_support(struct mlx4_dev *dev)
97 {
98 int eth_num_ports = 0;
99 int ib_num_ports = 0;
100
101 int dmfs = dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED;
102
103 if (dmfs) {
104 int i;
105 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_ETH)
106 eth_num_ports++;
107 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
108 ib_num_ports++;
109 dmfs &= (!ib_num_ports ||
110 (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DMFS_IPOIB)) &&
111 (!eth_num_ports ||
112 (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN));
113 if (ib_num_ports && mlx4_is_mfunc(dev)) {
114 pr_warn("Device managed flow steering is unavailable for IB port in multifunction env.\n");
115 dmfs = 0;
116 }
117 }
118 return dmfs;
119 }
120
num_ib_ports(struct mlx4_dev * dev)121 static int num_ib_ports(struct mlx4_dev *dev)
122 {
123 int ib_ports = 0;
124 int i;
125
126 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
127 ib_ports++;
128
129 return ib_ports;
130 }
131
mlx4_ib_get_netdev(struct ib_device * device,u8 port_num)132 static struct net_device *mlx4_ib_get_netdev(struct ib_device *device, u8 port_num)
133 {
134 struct mlx4_ib_dev *ibdev = to_mdev(device);
135 struct net_device *dev;
136
137 rcu_read_lock();
138 dev = mlx4_get_protocol_dev(ibdev->dev, MLX4_PROT_ETH, port_num);
139
140 if (dev) {
141 if (mlx4_is_bonded(ibdev->dev)) {
142 struct net_device *upper = NULL;
143
144 upper = netdev_master_upper_dev_get_rcu(dev);
145 if (upper) {
146 struct net_device *active;
147
148 active = bond_option_active_slave_get_rcu(netdev_priv(upper));
149 if (active)
150 dev = active;
151 }
152 }
153 }
154 if (dev)
155 dev_hold(dev);
156
157 rcu_read_unlock();
158 return dev;
159 }
160
mlx4_ib_update_gids_v1(struct gid_entry * gids,struct mlx4_ib_dev * ibdev,u8 port_num)161 static int mlx4_ib_update_gids_v1(struct gid_entry *gids,
162 struct mlx4_ib_dev *ibdev,
163 u8 port_num)
164 {
165 struct mlx4_cmd_mailbox *mailbox;
166 int err;
167 struct mlx4_dev *dev = ibdev->dev;
168 int i;
169 union ib_gid *gid_tbl;
170
171 mailbox = mlx4_alloc_cmd_mailbox(dev);
172 if (IS_ERR(mailbox))
173 return -ENOMEM;
174
175 gid_tbl = mailbox->buf;
176
177 for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i)
178 memcpy(&gid_tbl[i], &gids[i].gid, sizeof(union ib_gid));
179
180 err = mlx4_cmd(dev, mailbox->dma,
181 MLX4_SET_PORT_GID_TABLE << 8 | port_num,
182 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
183 MLX4_CMD_WRAPPED);
184 if (mlx4_is_bonded(dev))
185 err += mlx4_cmd(dev, mailbox->dma,
186 MLX4_SET_PORT_GID_TABLE << 8 | 2,
187 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
188 MLX4_CMD_WRAPPED);
189
190 mlx4_free_cmd_mailbox(dev, mailbox);
191 return err;
192 }
193
mlx4_ib_update_gids_v1_v2(struct gid_entry * gids,struct mlx4_ib_dev * ibdev,u8 port_num)194 static int mlx4_ib_update_gids_v1_v2(struct gid_entry *gids,
195 struct mlx4_ib_dev *ibdev,
196 u8 port_num)
197 {
198 struct mlx4_cmd_mailbox *mailbox;
199 int err;
200 struct mlx4_dev *dev = ibdev->dev;
201 int i;
202 struct {
203 union ib_gid gid;
204 __be32 rsrvd1[2];
205 __be16 rsrvd2;
206 u8 type;
207 u8 version;
208 __be32 rsrvd3;
209 } *gid_tbl;
210
211 mailbox = mlx4_alloc_cmd_mailbox(dev);
212 if (IS_ERR(mailbox))
213 return -ENOMEM;
214
215 gid_tbl = mailbox->buf;
216 for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i) {
217 memcpy(&gid_tbl[i].gid, &gids[i].gid, sizeof(union ib_gid));
218 if (gids[i].gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) {
219 gid_tbl[i].version = 2;
220 if (!ipv6_addr_v4mapped((struct in6_addr *)&gids[i].gid))
221 gid_tbl[i].type = 1;
222 }
223 }
224
225 err = mlx4_cmd(dev, mailbox->dma,
226 MLX4_SET_PORT_ROCE_ADDR << 8 | port_num,
227 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
228 MLX4_CMD_WRAPPED);
229 if (mlx4_is_bonded(dev))
230 err += mlx4_cmd(dev, mailbox->dma,
231 MLX4_SET_PORT_ROCE_ADDR << 8 | 2,
232 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
233 MLX4_CMD_WRAPPED);
234
235 mlx4_free_cmd_mailbox(dev, mailbox);
236 return err;
237 }
238
mlx4_ib_update_gids(struct gid_entry * gids,struct mlx4_ib_dev * ibdev,u8 port_num)239 static int mlx4_ib_update_gids(struct gid_entry *gids,
240 struct mlx4_ib_dev *ibdev,
241 u8 port_num)
242 {
243 if (ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2)
244 return mlx4_ib_update_gids_v1_v2(gids, ibdev, port_num);
245
246 return mlx4_ib_update_gids_v1(gids, ibdev, port_num);
247 }
248
free_gid_entry(struct gid_entry * entry)249 static void free_gid_entry(struct gid_entry *entry)
250 {
251 memset(&entry->gid, 0, sizeof(entry->gid));
252 kfree(entry->ctx);
253 entry->ctx = NULL;
254 }
255
mlx4_ib_add_gid(const struct ib_gid_attr * attr,void ** context)256 static int mlx4_ib_add_gid(const struct ib_gid_attr *attr, void **context)
257 {
258 struct mlx4_ib_dev *ibdev = to_mdev(attr->device);
259 struct mlx4_ib_iboe *iboe = &ibdev->iboe;
260 struct mlx4_port_gid_table *port_gid_table;
261 int free = -1, found = -1;
262 int ret = 0;
263 int hw_update = 0;
264 int i;
265 struct gid_entry *gids = NULL;
266 u16 vlan_id = 0xffff;
267 u8 mac[ETH_ALEN];
268
269 if (!rdma_cap_roce_gid_table(attr->device, attr->port_num))
270 return -EINVAL;
271
272 if (attr->port_num > MLX4_MAX_PORTS)
273 return -EINVAL;
274
275 if (!context)
276 return -EINVAL;
277
278 ret = rdma_read_gid_l2_fields(attr, &vlan_id, &mac[0]);
279 if (ret)
280 return ret;
281 port_gid_table = &iboe->gids[attr->port_num - 1];
282 spin_lock_bh(&iboe->lock);
283 for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i) {
284 if (!memcmp(&port_gid_table->gids[i].gid,
285 &attr->gid, sizeof(attr->gid)) &&
286 port_gid_table->gids[i].gid_type == attr->gid_type &&
287 port_gid_table->gids[i].vlan_id == vlan_id) {
288 found = i;
289 break;
290 }
291 if (free < 0 && rdma_is_zero_gid(&port_gid_table->gids[i].gid))
292 free = i; /* HW has space */
293 }
294
295 if (found < 0) {
296 if (free < 0) {
297 ret = -ENOSPC;
298 } else {
299 port_gid_table->gids[free].ctx = kmalloc(sizeof(*port_gid_table->gids[free].ctx), GFP_ATOMIC);
300 if (!port_gid_table->gids[free].ctx) {
301 ret = -ENOMEM;
302 } else {
303 *context = port_gid_table->gids[free].ctx;
304 memcpy(&port_gid_table->gids[free].gid,
305 &attr->gid, sizeof(attr->gid));
306 port_gid_table->gids[free].gid_type = attr->gid_type;
307 port_gid_table->gids[free].vlan_id = vlan_id;
308 port_gid_table->gids[free].ctx->real_index = free;
309 port_gid_table->gids[free].ctx->refcount = 1;
310 hw_update = 1;
311 }
312 }
313 } else {
314 struct gid_cache_context *ctx = port_gid_table->gids[found].ctx;
315 *context = ctx;
316 ctx->refcount++;
317 }
318 if (!ret && hw_update) {
319 gids = kmalloc_array(MLX4_MAX_PORT_GIDS, sizeof(*gids),
320 GFP_ATOMIC);
321 if (!gids) {
322 ret = -ENOMEM;
323 *context = NULL;
324 free_gid_entry(&port_gid_table->gids[free]);
325 } else {
326 for (i = 0; i < MLX4_MAX_PORT_GIDS; i++) {
327 memcpy(&gids[i].gid, &port_gid_table->gids[i].gid, sizeof(union ib_gid));
328 gids[i].gid_type = port_gid_table->gids[i].gid_type;
329 }
330 }
331 }
332 spin_unlock_bh(&iboe->lock);
333
334 if (!ret && hw_update) {
335 ret = mlx4_ib_update_gids(gids, ibdev, attr->port_num);
336 if (ret) {
337 spin_lock_bh(&iboe->lock);
338 *context = NULL;
339 free_gid_entry(&port_gid_table->gids[free]);
340 spin_unlock_bh(&iboe->lock);
341 }
342 kfree(gids);
343 }
344
345 return ret;
346 }
347
mlx4_ib_del_gid(const struct ib_gid_attr * attr,void ** context)348 static int mlx4_ib_del_gid(const struct ib_gid_attr *attr, void **context)
349 {
350 struct gid_cache_context *ctx = *context;
351 struct mlx4_ib_dev *ibdev = to_mdev(attr->device);
352 struct mlx4_ib_iboe *iboe = &ibdev->iboe;
353 struct mlx4_port_gid_table *port_gid_table;
354 int ret = 0;
355 int hw_update = 0;
356 struct gid_entry *gids = NULL;
357
358 if (!rdma_cap_roce_gid_table(attr->device, attr->port_num))
359 return -EINVAL;
360
361 if (attr->port_num > MLX4_MAX_PORTS)
362 return -EINVAL;
363
364 port_gid_table = &iboe->gids[attr->port_num - 1];
365 spin_lock_bh(&iboe->lock);
366 if (ctx) {
367 ctx->refcount--;
368 if (!ctx->refcount) {
369 unsigned int real_index = ctx->real_index;
370
371 free_gid_entry(&port_gid_table->gids[real_index]);
372 hw_update = 1;
373 }
374 }
375 if (!ret && hw_update) {
376 int i;
377
378 gids = kmalloc_array(MLX4_MAX_PORT_GIDS, sizeof(*gids),
379 GFP_ATOMIC);
380 if (!gids) {
381 ret = -ENOMEM;
382 } else {
383 for (i = 0; i < MLX4_MAX_PORT_GIDS; i++) {
384 memcpy(&gids[i].gid,
385 &port_gid_table->gids[i].gid,
386 sizeof(union ib_gid));
387 gids[i].gid_type =
388 port_gid_table->gids[i].gid_type;
389 }
390 }
391 }
392 spin_unlock_bh(&iboe->lock);
393
394 if (!ret && hw_update) {
395 ret = mlx4_ib_update_gids(gids, ibdev, attr->port_num);
396 kfree(gids);
397 }
398 return ret;
399 }
400
mlx4_ib_gid_index_to_real_index(struct mlx4_ib_dev * ibdev,const struct ib_gid_attr * attr)401 int mlx4_ib_gid_index_to_real_index(struct mlx4_ib_dev *ibdev,
402 const struct ib_gid_attr *attr)
403 {
404 struct mlx4_ib_iboe *iboe = &ibdev->iboe;
405 struct gid_cache_context *ctx = NULL;
406 struct mlx4_port_gid_table *port_gid_table;
407 int real_index = -EINVAL;
408 int i;
409 unsigned long flags;
410 u8 port_num = attr->port_num;
411
412 if (port_num > MLX4_MAX_PORTS)
413 return -EINVAL;
414
415 if (mlx4_is_bonded(ibdev->dev))
416 port_num = 1;
417
418 if (!rdma_cap_roce_gid_table(&ibdev->ib_dev, port_num))
419 return attr->index;
420
421 spin_lock_irqsave(&iboe->lock, flags);
422 port_gid_table = &iboe->gids[port_num - 1];
423
424 for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i)
425 if (!memcmp(&port_gid_table->gids[i].gid,
426 &attr->gid, sizeof(attr->gid)) &&
427 attr->gid_type == port_gid_table->gids[i].gid_type) {
428 ctx = port_gid_table->gids[i].ctx;
429 break;
430 }
431 if (ctx)
432 real_index = ctx->real_index;
433 spin_unlock_irqrestore(&iboe->lock, flags);
434 return real_index;
435 }
436
mlx4_ib_query_device(struct ib_device * ibdev,struct ib_device_attr * props,struct ib_udata * uhw)437 static int mlx4_ib_query_device(struct ib_device *ibdev,
438 struct ib_device_attr *props,
439 struct ib_udata *uhw)
440 {
441 struct mlx4_ib_dev *dev = to_mdev(ibdev);
442 struct ib_smp *in_mad = NULL;
443 struct ib_smp *out_mad = NULL;
444 int err;
445 int have_ib_ports;
446 struct mlx4_uverbs_ex_query_device cmd;
447 struct mlx4_uverbs_ex_query_device_resp resp = {};
448 struct mlx4_clock_params clock_params;
449
450 if (uhw->inlen) {
451 if (uhw->inlen < sizeof(cmd))
452 return -EINVAL;
453
454 err = ib_copy_from_udata(&cmd, uhw, sizeof(cmd));
455 if (err)
456 return err;
457
458 if (cmd.comp_mask)
459 return -EINVAL;
460
461 if (cmd.reserved)
462 return -EINVAL;
463 }
464
465 resp.response_length = offsetof(typeof(resp), response_length) +
466 sizeof(resp.response_length);
467 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
468 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
469 err = -ENOMEM;
470 if (!in_mad || !out_mad)
471 goto out;
472
473 init_query_mad(in_mad);
474 in_mad->attr_id = IB_SMP_ATTR_NODE_INFO;
475
476 err = mlx4_MAD_IFC(to_mdev(ibdev), MLX4_MAD_IFC_IGNORE_KEYS,
477 1, NULL, NULL, in_mad, out_mad);
478 if (err)
479 goto out;
480
481 memset(props, 0, sizeof *props);
482
483 have_ib_ports = num_ib_ports(dev->dev);
484
485 props->fw_ver = dev->dev->caps.fw_ver;
486 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
487 IB_DEVICE_PORT_ACTIVE_EVENT |
488 IB_DEVICE_SYS_IMAGE_GUID |
489 IB_DEVICE_RC_RNR_NAK_GEN |
490 IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
491 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR)
492 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
493 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR)
494 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
495 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_APM && have_ib_ports)
496 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
497 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_UD_AV_PORT)
498 props->device_cap_flags |= IB_DEVICE_UD_AV_PORT_ENFORCE;
499 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM)
500 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
501 if (dev->dev->caps.max_gso_sz &&
502 (dev->dev->rev_id != MLX4_IB_CARD_REV_A0) &&
503 (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BLH))
504 props->device_cap_flags |= IB_DEVICE_UD_TSO;
505 if (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_RESERVED_LKEY)
506 props->device_cap_flags |= IB_DEVICE_LOCAL_DMA_LKEY;
507 if ((dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_LOCAL_INV) &&
508 (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_REMOTE_INV) &&
509 (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_FAST_REG_WR))
510 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
511 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC)
512 props->device_cap_flags |= IB_DEVICE_XRC;
513 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW)
514 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW;
515 if (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN) {
516 if (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_WIN_TYPE_2B)
517 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW_TYPE_2B;
518 else
519 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW_TYPE_2A;
520 }
521 if (dev->steering_support == MLX4_STEERING_MODE_DEVICE_MANAGED)
522 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
523
524 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
525
526 props->vendor_id = be32_to_cpup((__be32 *) (out_mad->data + 36)) &
527 0xffffff;
528 props->vendor_part_id = dev->dev->persist->pdev->device;
529 props->hw_ver = be32_to_cpup((__be32 *) (out_mad->data + 32));
530 memcpy(&props->sys_image_guid, out_mad->data + 4, 8);
531
532 props->max_mr_size = ~0ull;
533 props->page_size_cap = dev->dev->caps.page_size_cap;
534 props->max_qp = dev->dev->quotas.qp;
535 props->max_qp_wr = dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE;
536 props->max_send_sge =
537 min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg);
538 props->max_recv_sge =
539 min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg);
540 props->max_sge_rd = MLX4_MAX_SGE_RD;
541 props->max_cq = dev->dev->quotas.cq;
542 props->max_cqe = dev->dev->caps.max_cqes;
543 props->max_mr = dev->dev->quotas.mpt;
544 props->max_pd = dev->dev->caps.num_pds - dev->dev->caps.reserved_pds;
545 props->max_qp_rd_atom = dev->dev->caps.max_qp_dest_rdma;
546 props->max_qp_init_rd_atom = dev->dev->caps.max_qp_init_rdma;
547 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
548 props->max_srq = dev->dev->quotas.srq;
549 props->max_srq_wr = dev->dev->caps.max_srq_wqes - 1;
550 props->max_srq_sge = dev->dev->caps.max_srq_sge;
551 props->max_fast_reg_page_list_len = MLX4_MAX_FAST_REG_PAGES;
552 props->local_ca_ack_delay = dev->dev->caps.local_ca_ack_delay;
553 props->atomic_cap = dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_ATOMIC ?
554 IB_ATOMIC_HCA : IB_ATOMIC_NONE;
555 props->masked_atomic_cap = props->atomic_cap;
556 props->max_pkeys = dev->dev->caps.pkey_table_len[1];
557 props->max_mcast_grp = dev->dev->caps.num_mgms + dev->dev->caps.num_amgms;
558 props->max_mcast_qp_attach = dev->dev->caps.num_qp_per_mgm;
559 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
560 props->max_mcast_grp;
561 props->hca_core_clock = dev->dev->caps.hca_core_clock * 1000UL;
562 props->timestamp_mask = 0xFFFFFFFFFFFFULL;
563 props->max_ah = INT_MAX;
564
565 if (mlx4_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET ||
566 mlx4_ib_port_link_layer(ibdev, 2) == IB_LINK_LAYER_ETHERNET) {
567 if (dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS) {
568 props->rss_caps.max_rwq_indirection_tables =
569 props->max_qp;
570 props->rss_caps.max_rwq_indirection_table_size =
571 dev->dev->caps.max_rss_tbl_sz;
572 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
573 props->max_wq_type_rq = props->max_qp;
574 }
575
576 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP)
577 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS;
578 }
579
580 props->cq_caps.max_cq_moderation_count = MLX4_MAX_CQ_COUNT;
581 props->cq_caps.max_cq_moderation_period = MLX4_MAX_CQ_PERIOD;
582
583 if (uhw->outlen >= resp.response_length + sizeof(resp.hca_core_clock_offset)) {
584 resp.response_length += sizeof(resp.hca_core_clock_offset);
585 if (!mlx4_get_internal_clock_params(dev->dev, &clock_params)) {
586 resp.comp_mask |= MLX4_IB_QUERY_DEV_RESP_MASK_CORE_CLOCK_OFFSET;
587 resp.hca_core_clock_offset = clock_params.offset % PAGE_SIZE;
588 }
589 }
590
591 if (uhw->outlen >= resp.response_length +
592 sizeof(resp.max_inl_recv_sz)) {
593 resp.response_length += sizeof(resp.max_inl_recv_sz);
594 resp.max_inl_recv_sz = dev->dev->caps.max_rq_sg *
595 sizeof(struct mlx4_wqe_data_seg);
596 }
597
598 if (offsetofend(typeof(resp), rss_caps) <= uhw->outlen) {
599 if (props->rss_caps.supported_qpts) {
600 resp.rss_caps.rx_hash_function =
601 MLX4_IB_RX_HASH_FUNC_TOEPLITZ;
602
603 resp.rss_caps.rx_hash_fields_mask =
604 MLX4_IB_RX_HASH_SRC_IPV4 |
605 MLX4_IB_RX_HASH_DST_IPV4 |
606 MLX4_IB_RX_HASH_SRC_IPV6 |
607 MLX4_IB_RX_HASH_DST_IPV6 |
608 MLX4_IB_RX_HASH_SRC_PORT_TCP |
609 MLX4_IB_RX_HASH_DST_PORT_TCP |
610 MLX4_IB_RX_HASH_SRC_PORT_UDP |
611 MLX4_IB_RX_HASH_DST_PORT_UDP;
612
613 if (dev->dev->caps.tunnel_offload_mode ==
614 MLX4_TUNNEL_OFFLOAD_MODE_VXLAN)
615 resp.rss_caps.rx_hash_fields_mask |=
616 MLX4_IB_RX_HASH_INNER;
617 }
618 resp.response_length = offsetof(typeof(resp), rss_caps) +
619 sizeof(resp.rss_caps);
620 }
621
622 if (offsetofend(typeof(resp), tso_caps) <= uhw->outlen) {
623 if (dev->dev->caps.max_gso_sz &&
624 ((mlx4_ib_port_link_layer(ibdev, 1) ==
625 IB_LINK_LAYER_ETHERNET) ||
626 (mlx4_ib_port_link_layer(ibdev, 2) ==
627 IB_LINK_LAYER_ETHERNET))) {
628 resp.tso_caps.max_tso = dev->dev->caps.max_gso_sz;
629 resp.tso_caps.supported_qpts |=
630 1 << IB_QPT_RAW_PACKET;
631 }
632 resp.response_length = offsetof(typeof(resp), tso_caps) +
633 sizeof(resp.tso_caps);
634 }
635
636 if (uhw->outlen) {
637 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
638 if (err)
639 goto out;
640 }
641 out:
642 kfree(in_mad);
643 kfree(out_mad);
644
645 return err;
646 }
647
648 static enum rdma_link_layer
mlx4_ib_port_link_layer(struct ib_device * device,u8 port_num)649 mlx4_ib_port_link_layer(struct ib_device *device, u8 port_num)
650 {
651 struct mlx4_dev *dev = to_mdev(device)->dev;
652
653 return dev->caps.port_mask[port_num] == MLX4_PORT_TYPE_IB ?
654 IB_LINK_LAYER_INFINIBAND : IB_LINK_LAYER_ETHERNET;
655 }
656
ib_link_query_port(struct ib_device * ibdev,u8 port,struct ib_port_attr * props,int netw_view)657 static int ib_link_query_port(struct ib_device *ibdev, u8 port,
658 struct ib_port_attr *props, int netw_view)
659 {
660 struct ib_smp *in_mad = NULL;
661 struct ib_smp *out_mad = NULL;
662 int ext_active_speed;
663 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS;
664 int err = -ENOMEM;
665
666 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
667 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
668 if (!in_mad || !out_mad)
669 goto out;
670
671 init_query_mad(in_mad);
672 in_mad->attr_id = IB_SMP_ATTR_PORT_INFO;
673 in_mad->attr_mod = cpu_to_be32(port);
674
675 if (mlx4_is_mfunc(to_mdev(ibdev)->dev) && netw_view)
676 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW;
677
678 err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, NULL, NULL,
679 in_mad, out_mad);
680 if (err)
681 goto out;
682
683
684 props->lid = be16_to_cpup((__be16 *) (out_mad->data + 16));
685 props->lmc = out_mad->data[34] & 0x7;
686 props->sm_lid = be16_to_cpup((__be16 *) (out_mad->data + 18));
687 props->sm_sl = out_mad->data[36] & 0xf;
688 props->state = out_mad->data[32] & 0xf;
689 props->phys_state = out_mad->data[33] >> 4;
690 props->port_cap_flags = be32_to_cpup((__be32 *) (out_mad->data + 20));
691 if (netw_view)
692 props->gid_tbl_len = out_mad->data[50];
693 else
694 props->gid_tbl_len = to_mdev(ibdev)->dev->caps.gid_table_len[port];
695 props->max_msg_sz = to_mdev(ibdev)->dev->caps.max_msg_sz;
696 props->pkey_tbl_len = to_mdev(ibdev)->dev->caps.pkey_table_len[port];
697 props->bad_pkey_cntr = be16_to_cpup((__be16 *) (out_mad->data + 46));
698 props->qkey_viol_cntr = be16_to_cpup((__be16 *) (out_mad->data + 48));
699 props->active_width = out_mad->data[31] & 0xf;
700 props->active_speed = out_mad->data[35] >> 4;
701 props->max_mtu = out_mad->data[41] & 0xf;
702 props->active_mtu = out_mad->data[36] >> 4;
703 props->subnet_timeout = out_mad->data[51] & 0x1f;
704 props->max_vl_num = out_mad->data[37] >> 4;
705 props->init_type_reply = out_mad->data[41] >> 4;
706
707 /* Check if extended speeds (EDR/FDR/...) are supported */
708 if (props->port_cap_flags & IB_PORT_EXTENDED_SPEEDS_SUP) {
709 ext_active_speed = out_mad->data[62] >> 4;
710
711 switch (ext_active_speed) {
712 case 1:
713 props->active_speed = IB_SPEED_FDR;
714 break;
715 case 2:
716 props->active_speed = IB_SPEED_EDR;
717 break;
718 }
719 }
720
721 /* If reported active speed is QDR, check if is FDR-10 */
722 if (props->active_speed == IB_SPEED_QDR) {
723 init_query_mad(in_mad);
724 in_mad->attr_id = MLX4_ATTR_EXTENDED_PORT_INFO;
725 in_mad->attr_mod = cpu_to_be32(port);
726
727 err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port,
728 NULL, NULL, in_mad, out_mad);
729 if (err)
730 goto out;
731
732 /* Checking LinkSpeedActive for FDR-10 */
733 if (out_mad->data[15] & 0x1)
734 props->active_speed = IB_SPEED_FDR10;
735 }
736
737 /* Avoid wrong speed value returned by FW if the IB link is down. */
738 if (props->state == IB_PORT_DOWN)
739 props->active_speed = IB_SPEED_SDR;
740
741 out:
742 kfree(in_mad);
743 kfree(out_mad);
744 return err;
745 }
746
state_to_phys_state(enum ib_port_state state)747 static u8 state_to_phys_state(enum ib_port_state state)
748 {
749 return state == IB_PORT_ACTIVE ?
750 IB_PORT_PHYS_STATE_LINK_UP : IB_PORT_PHYS_STATE_DISABLED;
751 }
752
eth_link_query_port(struct ib_device * ibdev,u8 port,struct ib_port_attr * props)753 static int eth_link_query_port(struct ib_device *ibdev, u8 port,
754 struct ib_port_attr *props)
755 {
756
757 struct mlx4_ib_dev *mdev = to_mdev(ibdev);
758 struct mlx4_ib_iboe *iboe = &mdev->iboe;
759 struct net_device *ndev;
760 enum ib_mtu tmp;
761 struct mlx4_cmd_mailbox *mailbox;
762 int err = 0;
763 int is_bonded = mlx4_is_bonded(mdev->dev);
764
765 mailbox = mlx4_alloc_cmd_mailbox(mdev->dev);
766 if (IS_ERR(mailbox))
767 return PTR_ERR(mailbox);
768
769 err = mlx4_cmd_box(mdev->dev, 0, mailbox->dma, port, 0,
770 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B,
771 MLX4_CMD_WRAPPED);
772 if (err)
773 goto out;
774
775 props->active_width = (((u8 *)mailbox->buf)[5] == 0x40) ||
776 (((u8 *)mailbox->buf)[5] == 0x20 /*56Gb*/) ?
777 IB_WIDTH_4X : IB_WIDTH_1X;
778 props->active_speed = (((u8 *)mailbox->buf)[5] == 0x20 /*56Gb*/) ?
779 IB_SPEED_FDR : IB_SPEED_QDR;
780 props->port_cap_flags = IB_PORT_CM_SUP;
781 props->ip_gids = true;
782 props->gid_tbl_len = mdev->dev->caps.gid_table_len[port];
783 props->max_msg_sz = mdev->dev->caps.max_msg_sz;
784 if (mdev->dev->caps.pkey_table_len[port])
785 props->pkey_tbl_len = 1;
786 props->max_mtu = IB_MTU_4096;
787 props->max_vl_num = 2;
788 props->state = IB_PORT_DOWN;
789 props->phys_state = state_to_phys_state(props->state);
790 props->active_mtu = IB_MTU_256;
791 spin_lock_bh(&iboe->lock);
792 ndev = iboe->netdevs[port - 1];
793 if (ndev && is_bonded) {
794 rcu_read_lock(); /* required to get upper dev */
795 ndev = netdev_master_upper_dev_get_rcu(ndev);
796 rcu_read_unlock();
797 }
798 if (!ndev)
799 goto out_unlock;
800
801 tmp = iboe_get_mtu(ndev->mtu);
802 props->active_mtu = tmp ? min(props->max_mtu, tmp) : IB_MTU_256;
803
804 props->state = (netif_running(ndev) && netif_carrier_ok(ndev)) ?
805 IB_PORT_ACTIVE : IB_PORT_DOWN;
806 props->phys_state = state_to_phys_state(props->state);
807 out_unlock:
808 spin_unlock_bh(&iboe->lock);
809 out:
810 mlx4_free_cmd_mailbox(mdev->dev, mailbox);
811 return err;
812 }
813
__mlx4_ib_query_port(struct ib_device * ibdev,u8 port,struct ib_port_attr * props,int netw_view)814 int __mlx4_ib_query_port(struct ib_device *ibdev, u8 port,
815 struct ib_port_attr *props, int netw_view)
816 {
817 int err;
818
819 /* props being zeroed by the caller, avoid zeroing it here */
820
821 err = mlx4_ib_port_link_layer(ibdev, port) == IB_LINK_LAYER_INFINIBAND ?
822 ib_link_query_port(ibdev, port, props, netw_view) :
823 eth_link_query_port(ibdev, port, props);
824
825 return err;
826 }
827
mlx4_ib_query_port(struct ib_device * ibdev,u8 port,struct ib_port_attr * props)828 static int mlx4_ib_query_port(struct ib_device *ibdev, u8 port,
829 struct ib_port_attr *props)
830 {
831 /* returns host view */
832 return __mlx4_ib_query_port(ibdev, port, props, 0);
833 }
834
__mlx4_ib_query_gid(struct ib_device * ibdev,u8 port,int index,union ib_gid * gid,int netw_view)835 int __mlx4_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
836 union ib_gid *gid, int netw_view)
837 {
838 struct ib_smp *in_mad = NULL;
839 struct ib_smp *out_mad = NULL;
840 int err = -ENOMEM;
841 struct mlx4_ib_dev *dev = to_mdev(ibdev);
842 int clear = 0;
843 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS;
844
845 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
846 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
847 if (!in_mad || !out_mad)
848 goto out;
849
850 init_query_mad(in_mad);
851 in_mad->attr_id = IB_SMP_ATTR_PORT_INFO;
852 in_mad->attr_mod = cpu_to_be32(port);
853
854 if (mlx4_is_mfunc(dev->dev) && netw_view)
855 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW;
856
857 err = mlx4_MAD_IFC(dev, mad_ifc_flags, port, NULL, NULL, in_mad, out_mad);
858 if (err)
859 goto out;
860
861 memcpy(gid->raw, out_mad->data + 8, 8);
862
863 if (mlx4_is_mfunc(dev->dev) && !netw_view) {
864 if (index) {
865 /* For any index > 0, return the null guid */
866 err = 0;
867 clear = 1;
868 goto out;
869 }
870 }
871
872 init_query_mad(in_mad);
873 in_mad->attr_id = IB_SMP_ATTR_GUID_INFO;
874 in_mad->attr_mod = cpu_to_be32(index / 8);
875
876 err = mlx4_MAD_IFC(dev, mad_ifc_flags, port,
877 NULL, NULL, in_mad, out_mad);
878 if (err)
879 goto out;
880
881 memcpy(gid->raw + 8, out_mad->data + (index % 8) * 8, 8);
882
883 out:
884 if (clear)
885 memset(gid->raw + 8, 0, 8);
886 kfree(in_mad);
887 kfree(out_mad);
888 return err;
889 }
890
mlx4_ib_query_gid(struct ib_device * ibdev,u8 port,int index,union ib_gid * gid)891 static int mlx4_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
892 union ib_gid *gid)
893 {
894 if (rdma_protocol_ib(ibdev, port))
895 return __mlx4_ib_query_gid(ibdev, port, index, gid, 0);
896 return 0;
897 }
898
mlx4_ib_query_sl2vl(struct ib_device * ibdev,u8 port,u64 * sl2vl_tbl)899 static int mlx4_ib_query_sl2vl(struct ib_device *ibdev, u8 port, u64 *sl2vl_tbl)
900 {
901 union sl2vl_tbl_to_u64 sl2vl64;
902 struct ib_smp *in_mad = NULL;
903 struct ib_smp *out_mad = NULL;
904 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS;
905 int err = -ENOMEM;
906 int jj;
907
908 if (mlx4_is_slave(to_mdev(ibdev)->dev)) {
909 *sl2vl_tbl = 0;
910 return 0;
911 }
912
913 in_mad = kzalloc(sizeof(*in_mad), GFP_KERNEL);
914 out_mad = kmalloc(sizeof(*out_mad), GFP_KERNEL);
915 if (!in_mad || !out_mad)
916 goto out;
917
918 init_query_mad(in_mad);
919 in_mad->attr_id = IB_SMP_ATTR_SL_TO_VL_TABLE;
920 in_mad->attr_mod = 0;
921
922 if (mlx4_is_mfunc(to_mdev(ibdev)->dev))
923 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW;
924
925 err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, NULL, NULL,
926 in_mad, out_mad);
927 if (err)
928 goto out;
929
930 for (jj = 0; jj < 8; jj++)
931 sl2vl64.sl8[jj] = ((struct ib_smp *)out_mad)->data[jj];
932 *sl2vl_tbl = sl2vl64.sl64;
933
934 out:
935 kfree(in_mad);
936 kfree(out_mad);
937 return err;
938 }
939
mlx4_init_sl2vl_tbl(struct mlx4_ib_dev * mdev)940 static void mlx4_init_sl2vl_tbl(struct mlx4_ib_dev *mdev)
941 {
942 u64 sl2vl;
943 int i;
944 int err;
945
946 for (i = 1; i <= mdev->dev->caps.num_ports; i++) {
947 if (mdev->dev->caps.port_type[i] == MLX4_PORT_TYPE_ETH)
948 continue;
949 err = mlx4_ib_query_sl2vl(&mdev->ib_dev, i, &sl2vl);
950 if (err) {
951 pr_err("Unable to get default sl to vl mapping for port %d. Using all zeroes (%d)\n",
952 i, err);
953 sl2vl = 0;
954 }
955 atomic64_set(&mdev->sl2vl[i - 1], sl2vl);
956 }
957 }
958
__mlx4_ib_query_pkey(struct ib_device * ibdev,u8 port,u16 index,u16 * pkey,int netw_view)959 int __mlx4_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
960 u16 *pkey, int netw_view)
961 {
962 struct ib_smp *in_mad = NULL;
963 struct ib_smp *out_mad = NULL;
964 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS;
965 int err = -ENOMEM;
966
967 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
968 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
969 if (!in_mad || !out_mad)
970 goto out;
971
972 init_query_mad(in_mad);
973 in_mad->attr_id = IB_SMP_ATTR_PKEY_TABLE;
974 in_mad->attr_mod = cpu_to_be32(index / 32);
975
976 if (mlx4_is_mfunc(to_mdev(ibdev)->dev) && netw_view)
977 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW;
978
979 err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, NULL, NULL,
980 in_mad, out_mad);
981 if (err)
982 goto out;
983
984 *pkey = be16_to_cpu(((__be16 *) out_mad->data)[index % 32]);
985
986 out:
987 kfree(in_mad);
988 kfree(out_mad);
989 return err;
990 }
991
mlx4_ib_query_pkey(struct ib_device * ibdev,u8 port,u16 index,u16 * pkey)992 static int mlx4_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index, u16 *pkey)
993 {
994 return __mlx4_ib_query_pkey(ibdev, port, index, pkey, 0);
995 }
996
mlx4_ib_modify_device(struct ib_device * ibdev,int mask,struct ib_device_modify * props)997 static int mlx4_ib_modify_device(struct ib_device *ibdev, int mask,
998 struct ib_device_modify *props)
999 {
1000 struct mlx4_cmd_mailbox *mailbox;
1001 unsigned long flags;
1002
1003 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
1004 return -EOPNOTSUPP;
1005
1006 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
1007 return 0;
1008
1009 if (mlx4_is_slave(to_mdev(ibdev)->dev))
1010 return -EOPNOTSUPP;
1011
1012 spin_lock_irqsave(&to_mdev(ibdev)->sm_lock, flags);
1013 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
1014 spin_unlock_irqrestore(&to_mdev(ibdev)->sm_lock, flags);
1015
1016 /*
1017 * If possible, pass node desc to FW, so it can generate
1018 * a 144 trap. If cmd fails, just ignore.
1019 */
1020 mailbox = mlx4_alloc_cmd_mailbox(to_mdev(ibdev)->dev);
1021 if (IS_ERR(mailbox))
1022 return 0;
1023
1024 memcpy(mailbox->buf, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
1025 mlx4_cmd(to_mdev(ibdev)->dev, mailbox->dma, 1, 0,
1026 MLX4_CMD_SET_NODE, MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1027
1028 mlx4_free_cmd_mailbox(to_mdev(ibdev)->dev, mailbox);
1029
1030 return 0;
1031 }
1032
mlx4_ib_SET_PORT(struct mlx4_ib_dev * dev,u8 port,int reset_qkey_viols,u32 cap_mask)1033 static int mlx4_ib_SET_PORT(struct mlx4_ib_dev *dev, u8 port, int reset_qkey_viols,
1034 u32 cap_mask)
1035 {
1036 struct mlx4_cmd_mailbox *mailbox;
1037 int err;
1038
1039 mailbox = mlx4_alloc_cmd_mailbox(dev->dev);
1040 if (IS_ERR(mailbox))
1041 return PTR_ERR(mailbox);
1042
1043 if (dev->dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
1044 *(u8 *) mailbox->buf = !!reset_qkey_viols << 6;
1045 ((__be32 *) mailbox->buf)[2] = cpu_to_be32(cap_mask);
1046 } else {
1047 ((u8 *) mailbox->buf)[3] = !!reset_qkey_viols;
1048 ((__be32 *) mailbox->buf)[1] = cpu_to_be32(cap_mask);
1049 }
1050
1051 err = mlx4_cmd(dev->dev, mailbox->dma, port, MLX4_SET_PORT_IB_OPCODE,
1052 MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
1053 MLX4_CMD_WRAPPED);
1054
1055 mlx4_free_cmd_mailbox(dev->dev, mailbox);
1056 return err;
1057 }
1058
mlx4_ib_modify_port(struct ib_device * ibdev,u8 port,int mask,struct ib_port_modify * props)1059 static int mlx4_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
1060 struct ib_port_modify *props)
1061 {
1062 struct mlx4_ib_dev *mdev = to_mdev(ibdev);
1063 u8 is_eth = mdev->dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH;
1064 struct ib_port_attr attr;
1065 u32 cap_mask;
1066 int err;
1067
1068 /* return OK if this is RoCE. CM calls ib_modify_port() regardless
1069 * of whether port link layer is ETH or IB. For ETH ports, qkey
1070 * violations and port capabilities are not meaningful.
1071 */
1072 if (is_eth)
1073 return 0;
1074
1075 mutex_lock(&mdev->cap_mask_mutex);
1076
1077 err = ib_query_port(ibdev, port, &attr);
1078 if (err)
1079 goto out;
1080
1081 cap_mask = (attr.port_cap_flags | props->set_port_cap_mask) &
1082 ~props->clr_port_cap_mask;
1083
1084 err = mlx4_ib_SET_PORT(mdev, port,
1085 !!(mask & IB_PORT_RESET_QKEY_CNTR),
1086 cap_mask);
1087
1088 out:
1089 mutex_unlock(&to_mdev(ibdev)->cap_mask_mutex);
1090 return err;
1091 }
1092
mlx4_ib_alloc_ucontext(struct ib_ucontext * uctx,struct ib_udata * udata)1093 static int mlx4_ib_alloc_ucontext(struct ib_ucontext *uctx,
1094 struct ib_udata *udata)
1095 {
1096 struct ib_device *ibdev = uctx->device;
1097 struct mlx4_ib_dev *dev = to_mdev(ibdev);
1098 struct mlx4_ib_ucontext *context = to_mucontext(uctx);
1099 struct mlx4_ib_alloc_ucontext_resp_v3 resp_v3;
1100 struct mlx4_ib_alloc_ucontext_resp resp;
1101 int err;
1102
1103 if (!dev->ib_active)
1104 return -EAGAIN;
1105
1106 if (ibdev->ops.uverbs_abi_ver ==
1107 MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION) {
1108 resp_v3.qp_tab_size = dev->dev->caps.num_qps;
1109 resp_v3.bf_reg_size = dev->dev->caps.bf_reg_size;
1110 resp_v3.bf_regs_per_page = dev->dev->caps.bf_regs_per_page;
1111 } else {
1112 resp.dev_caps = dev->dev->caps.userspace_caps;
1113 resp.qp_tab_size = dev->dev->caps.num_qps;
1114 resp.bf_reg_size = dev->dev->caps.bf_reg_size;
1115 resp.bf_regs_per_page = dev->dev->caps.bf_regs_per_page;
1116 resp.cqe_size = dev->dev->caps.cqe_size;
1117 }
1118
1119 err = mlx4_uar_alloc(to_mdev(ibdev)->dev, &context->uar);
1120 if (err)
1121 return err;
1122
1123 INIT_LIST_HEAD(&context->db_page_list);
1124 mutex_init(&context->db_page_mutex);
1125
1126 INIT_LIST_HEAD(&context->wqn_ranges_list);
1127 mutex_init(&context->wqn_ranges_mutex);
1128
1129 if (ibdev->ops.uverbs_abi_ver == MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION)
1130 err = ib_copy_to_udata(udata, &resp_v3, sizeof(resp_v3));
1131 else
1132 err = ib_copy_to_udata(udata, &resp, sizeof(resp));
1133
1134 if (err) {
1135 mlx4_uar_free(to_mdev(ibdev)->dev, &context->uar);
1136 return -EFAULT;
1137 }
1138
1139 return err;
1140 }
1141
mlx4_ib_dealloc_ucontext(struct ib_ucontext * ibcontext)1142 static void mlx4_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1143 {
1144 struct mlx4_ib_ucontext *context = to_mucontext(ibcontext);
1145
1146 mlx4_uar_free(to_mdev(ibcontext->device)->dev, &context->uar);
1147 }
1148
mlx4_ib_disassociate_ucontext(struct ib_ucontext * ibcontext)1149 static void mlx4_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
1150 {
1151 }
1152
mlx4_ib_mmap(struct ib_ucontext * context,struct vm_area_struct * vma)1153 static int mlx4_ib_mmap(struct ib_ucontext *context, struct vm_area_struct *vma)
1154 {
1155 struct mlx4_ib_dev *dev = to_mdev(context->device);
1156
1157 switch (vma->vm_pgoff) {
1158 case 0:
1159 return rdma_user_mmap_io(context, vma,
1160 to_mucontext(context)->uar.pfn,
1161 PAGE_SIZE,
1162 pgprot_noncached(vma->vm_page_prot),
1163 NULL);
1164
1165 case 1:
1166 if (dev->dev->caps.bf_reg_size == 0)
1167 return -EINVAL;
1168 return rdma_user_mmap_io(
1169 context, vma,
1170 to_mucontext(context)->uar.pfn +
1171 dev->dev->caps.num_uars,
1172 PAGE_SIZE, pgprot_writecombine(vma->vm_page_prot),
1173 NULL);
1174
1175 case 3: {
1176 struct mlx4_clock_params params;
1177 int ret;
1178
1179 ret = mlx4_get_internal_clock_params(dev->dev, ¶ms);
1180 if (ret)
1181 return ret;
1182
1183 return rdma_user_mmap_io(
1184 context, vma,
1185 (pci_resource_start(dev->dev->persist->pdev,
1186 params.bar) +
1187 params.offset) >>
1188 PAGE_SHIFT,
1189 PAGE_SIZE, pgprot_noncached(vma->vm_page_prot),
1190 NULL);
1191 }
1192
1193 default:
1194 return -EINVAL;
1195 }
1196 }
1197
mlx4_ib_alloc_pd(struct ib_pd * ibpd,struct ib_udata * udata)1198 static int mlx4_ib_alloc_pd(struct ib_pd *ibpd, struct ib_udata *udata)
1199 {
1200 struct mlx4_ib_pd *pd = to_mpd(ibpd);
1201 struct ib_device *ibdev = ibpd->device;
1202 int err;
1203
1204 err = mlx4_pd_alloc(to_mdev(ibdev)->dev, &pd->pdn);
1205 if (err)
1206 return err;
1207
1208 if (udata && ib_copy_to_udata(udata, &pd->pdn, sizeof(__u32))) {
1209 mlx4_pd_free(to_mdev(ibdev)->dev, pd->pdn);
1210 return -EFAULT;
1211 }
1212 return 0;
1213 }
1214
mlx4_ib_dealloc_pd(struct ib_pd * pd,struct ib_udata * udata)1215 static int mlx4_ib_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata)
1216 {
1217 mlx4_pd_free(to_mdev(pd->device)->dev, to_mpd(pd)->pdn);
1218 return 0;
1219 }
1220
mlx4_ib_alloc_xrcd(struct ib_xrcd * ibxrcd,struct ib_udata * udata)1221 static int mlx4_ib_alloc_xrcd(struct ib_xrcd *ibxrcd, struct ib_udata *udata)
1222 {
1223 struct mlx4_ib_dev *dev = to_mdev(ibxrcd->device);
1224 struct mlx4_ib_xrcd *xrcd = to_mxrcd(ibxrcd);
1225 struct ib_cq_init_attr cq_attr = {};
1226 int err;
1227
1228 if (!(dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC))
1229 return -EOPNOTSUPP;
1230
1231 err = mlx4_xrcd_alloc(dev->dev, &xrcd->xrcdn);
1232 if (err)
1233 return err;
1234
1235 xrcd->pd = ib_alloc_pd(ibxrcd->device, 0);
1236 if (IS_ERR(xrcd->pd)) {
1237 err = PTR_ERR(xrcd->pd);
1238 goto err2;
1239 }
1240
1241 cq_attr.cqe = 1;
1242 xrcd->cq = ib_create_cq(ibxrcd->device, NULL, NULL, xrcd, &cq_attr);
1243 if (IS_ERR(xrcd->cq)) {
1244 err = PTR_ERR(xrcd->cq);
1245 goto err3;
1246 }
1247
1248 return 0;
1249
1250 err3:
1251 ib_dealloc_pd(xrcd->pd);
1252 err2:
1253 mlx4_xrcd_free(dev->dev, xrcd->xrcdn);
1254 return err;
1255 }
1256
mlx4_ib_dealloc_xrcd(struct ib_xrcd * xrcd,struct ib_udata * udata)1257 static int mlx4_ib_dealloc_xrcd(struct ib_xrcd *xrcd, struct ib_udata *udata)
1258 {
1259 ib_destroy_cq(to_mxrcd(xrcd)->cq);
1260 ib_dealloc_pd(to_mxrcd(xrcd)->pd);
1261 mlx4_xrcd_free(to_mdev(xrcd->device)->dev, to_mxrcd(xrcd)->xrcdn);
1262 return 0;
1263 }
1264
add_gid_entry(struct ib_qp * ibqp,union ib_gid * gid)1265 static int add_gid_entry(struct ib_qp *ibqp, union ib_gid *gid)
1266 {
1267 struct mlx4_ib_qp *mqp = to_mqp(ibqp);
1268 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
1269 struct mlx4_ib_gid_entry *ge;
1270
1271 ge = kzalloc(sizeof *ge, GFP_KERNEL);
1272 if (!ge)
1273 return -ENOMEM;
1274
1275 ge->gid = *gid;
1276 if (mlx4_ib_add_mc(mdev, mqp, gid)) {
1277 ge->port = mqp->port;
1278 ge->added = 1;
1279 }
1280
1281 mutex_lock(&mqp->mutex);
1282 list_add_tail(&ge->list, &mqp->gid_list);
1283 mutex_unlock(&mqp->mutex);
1284
1285 return 0;
1286 }
1287
mlx4_ib_delete_counters_table(struct mlx4_ib_dev * ibdev,struct mlx4_ib_counters * ctr_table)1288 static void mlx4_ib_delete_counters_table(struct mlx4_ib_dev *ibdev,
1289 struct mlx4_ib_counters *ctr_table)
1290 {
1291 struct counter_index *counter, *tmp_count;
1292
1293 mutex_lock(&ctr_table->mutex);
1294 list_for_each_entry_safe(counter, tmp_count, &ctr_table->counters_list,
1295 list) {
1296 if (counter->allocated)
1297 mlx4_counter_free(ibdev->dev, counter->index);
1298 list_del(&counter->list);
1299 kfree(counter);
1300 }
1301 mutex_unlock(&ctr_table->mutex);
1302 }
1303
mlx4_ib_add_mc(struct mlx4_ib_dev * mdev,struct mlx4_ib_qp * mqp,union ib_gid * gid)1304 int mlx4_ib_add_mc(struct mlx4_ib_dev *mdev, struct mlx4_ib_qp *mqp,
1305 union ib_gid *gid)
1306 {
1307 struct net_device *ndev;
1308 int ret = 0;
1309
1310 if (!mqp->port)
1311 return 0;
1312
1313 spin_lock_bh(&mdev->iboe.lock);
1314 ndev = mdev->iboe.netdevs[mqp->port - 1];
1315 if (ndev)
1316 dev_hold(ndev);
1317 spin_unlock_bh(&mdev->iboe.lock);
1318
1319 if (ndev) {
1320 ret = 1;
1321 dev_put(ndev);
1322 }
1323
1324 return ret;
1325 }
1326
1327 struct mlx4_ib_steering {
1328 struct list_head list;
1329 struct mlx4_flow_reg_id reg_id;
1330 union ib_gid gid;
1331 };
1332
1333 #define LAST_ETH_FIELD vlan_tag
1334 #define LAST_IB_FIELD sl
1335 #define LAST_IPV4_FIELD dst_ip
1336 #define LAST_TCP_UDP_FIELD src_port
1337
1338 /* Field is the last supported field */
1339 #define FIELDS_NOT_SUPPORTED(filter, field)\
1340 memchr_inv((void *)&filter.field +\
1341 sizeof(filter.field), 0,\
1342 sizeof(filter) -\
1343 offsetof(typeof(filter), field) -\
1344 sizeof(filter.field))
1345
parse_flow_attr(struct mlx4_dev * dev,u32 qp_num,union ib_flow_spec * ib_spec,struct _rule_hw * mlx4_spec)1346 static int parse_flow_attr(struct mlx4_dev *dev,
1347 u32 qp_num,
1348 union ib_flow_spec *ib_spec,
1349 struct _rule_hw *mlx4_spec)
1350 {
1351 enum mlx4_net_trans_rule_id type;
1352
1353 switch (ib_spec->type) {
1354 case IB_FLOW_SPEC_ETH:
1355 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
1356 return -ENOTSUPP;
1357
1358 type = MLX4_NET_TRANS_RULE_ID_ETH;
1359 memcpy(mlx4_spec->eth.dst_mac, ib_spec->eth.val.dst_mac,
1360 ETH_ALEN);
1361 memcpy(mlx4_spec->eth.dst_mac_msk, ib_spec->eth.mask.dst_mac,
1362 ETH_ALEN);
1363 mlx4_spec->eth.vlan_tag = ib_spec->eth.val.vlan_tag;
1364 mlx4_spec->eth.vlan_tag_msk = ib_spec->eth.mask.vlan_tag;
1365 break;
1366 case IB_FLOW_SPEC_IB:
1367 if (FIELDS_NOT_SUPPORTED(ib_spec->ib.mask, LAST_IB_FIELD))
1368 return -ENOTSUPP;
1369
1370 type = MLX4_NET_TRANS_RULE_ID_IB;
1371 mlx4_spec->ib.l3_qpn =
1372 cpu_to_be32(qp_num);
1373 mlx4_spec->ib.qpn_mask =
1374 cpu_to_be32(MLX4_IB_FLOW_QPN_MASK);
1375 break;
1376
1377
1378 case IB_FLOW_SPEC_IPV4:
1379 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
1380 return -ENOTSUPP;
1381
1382 type = MLX4_NET_TRANS_RULE_ID_IPV4;
1383 mlx4_spec->ipv4.src_ip = ib_spec->ipv4.val.src_ip;
1384 mlx4_spec->ipv4.src_ip_msk = ib_spec->ipv4.mask.src_ip;
1385 mlx4_spec->ipv4.dst_ip = ib_spec->ipv4.val.dst_ip;
1386 mlx4_spec->ipv4.dst_ip_msk = ib_spec->ipv4.mask.dst_ip;
1387 break;
1388
1389 case IB_FLOW_SPEC_TCP:
1390 case IB_FLOW_SPEC_UDP:
1391 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask, LAST_TCP_UDP_FIELD))
1392 return -ENOTSUPP;
1393
1394 type = ib_spec->type == IB_FLOW_SPEC_TCP ?
1395 MLX4_NET_TRANS_RULE_ID_TCP :
1396 MLX4_NET_TRANS_RULE_ID_UDP;
1397 mlx4_spec->tcp_udp.dst_port = ib_spec->tcp_udp.val.dst_port;
1398 mlx4_spec->tcp_udp.dst_port_msk = ib_spec->tcp_udp.mask.dst_port;
1399 mlx4_spec->tcp_udp.src_port = ib_spec->tcp_udp.val.src_port;
1400 mlx4_spec->tcp_udp.src_port_msk = ib_spec->tcp_udp.mask.src_port;
1401 break;
1402
1403 default:
1404 return -EINVAL;
1405 }
1406 if (mlx4_map_sw_to_hw_steering_id(dev, type) < 0 ||
1407 mlx4_hw_rule_sz(dev, type) < 0)
1408 return -EINVAL;
1409 mlx4_spec->id = cpu_to_be16(mlx4_map_sw_to_hw_steering_id(dev, type));
1410 mlx4_spec->size = mlx4_hw_rule_sz(dev, type) >> 2;
1411 return mlx4_hw_rule_sz(dev, type);
1412 }
1413
1414 struct default_rules {
1415 __u32 mandatory_fields[IB_FLOW_SPEC_SUPPORT_LAYERS];
1416 __u32 mandatory_not_fields[IB_FLOW_SPEC_SUPPORT_LAYERS];
1417 __u32 rules_create_list[IB_FLOW_SPEC_SUPPORT_LAYERS];
1418 __u8 link_layer;
1419 };
1420 static const struct default_rules default_table[] = {
1421 {
1422 .mandatory_fields = {IB_FLOW_SPEC_IPV4},
1423 .mandatory_not_fields = {IB_FLOW_SPEC_ETH},
1424 .rules_create_list = {IB_FLOW_SPEC_IB},
1425 .link_layer = IB_LINK_LAYER_INFINIBAND
1426 }
1427 };
1428
__mlx4_ib_default_rules_match(struct ib_qp * qp,struct ib_flow_attr * flow_attr)1429 static int __mlx4_ib_default_rules_match(struct ib_qp *qp,
1430 struct ib_flow_attr *flow_attr)
1431 {
1432 int i, j, k;
1433 void *ib_flow;
1434 const struct default_rules *pdefault_rules = default_table;
1435 u8 link_layer = rdma_port_get_link_layer(qp->device, flow_attr->port);
1436
1437 for (i = 0; i < ARRAY_SIZE(default_table); i++, pdefault_rules++) {
1438 __u32 field_types[IB_FLOW_SPEC_SUPPORT_LAYERS];
1439 memset(&field_types, 0, sizeof(field_types));
1440
1441 if (link_layer != pdefault_rules->link_layer)
1442 continue;
1443
1444 ib_flow = flow_attr + 1;
1445 /* we assume the specs are sorted */
1446 for (j = 0, k = 0; k < IB_FLOW_SPEC_SUPPORT_LAYERS &&
1447 j < flow_attr->num_of_specs; k++) {
1448 union ib_flow_spec *current_flow =
1449 (union ib_flow_spec *)ib_flow;
1450
1451 /* same layer but different type */
1452 if (((current_flow->type & IB_FLOW_SPEC_LAYER_MASK) ==
1453 (pdefault_rules->mandatory_fields[k] &
1454 IB_FLOW_SPEC_LAYER_MASK)) &&
1455 (current_flow->type !=
1456 pdefault_rules->mandatory_fields[k]))
1457 goto out;
1458
1459 /* same layer, try match next one */
1460 if (current_flow->type ==
1461 pdefault_rules->mandatory_fields[k]) {
1462 j++;
1463 ib_flow +=
1464 ((union ib_flow_spec *)ib_flow)->size;
1465 }
1466 }
1467
1468 ib_flow = flow_attr + 1;
1469 for (j = 0; j < flow_attr->num_of_specs;
1470 j++, ib_flow += ((union ib_flow_spec *)ib_flow)->size)
1471 for (k = 0; k < IB_FLOW_SPEC_SUPPORT_LAYERS; k++)
1472 /* same layer and same type */
1473 if (((union ib_flow_spec *)ib_flow)->type ==
1474 pdefault_rules->mandatory_not_fields[k])
1475 goto out;
1476
1477 return i;
1478 }
1479 out:
1480 return -1;
1481 }
1482
__mlx4_ib_create_default_rules(struct mlx4_ib_dev * mdev,struct ib_qp * qp,const struct default_rules * pdefault_rules,struct _rule_hw * mlx4_spec)1483 static int __mlx4_ib_create_default_rules(
1484 struct mlx4_ib_dev *mdev,
1485 struct ib_qp *qp,
1486 const struct default_rules *pdefault_rules,
1487 struct _rule_hw *mlx4_spec) {
1488 int size = 0;
1489 int i;
1490
1491 for (i = 0; i < ARRAY_SIZE(pdefault_rules->rules_create_list); i++) {
1492 union ib_flow_spec ib_spec = {};
1493 int ret;
1494
1495 switch (pdefault_rules->rules_create_list[i]) {
1496 case 0:
1497 /* no rule */
1498 continue;
1499 case IB_FLOW_SPEC_IB:
1500 ib_spec.type = IB_FLOW_SPEC_IB;
1501 ib_spec.size = sizeof(struct ib_flow_spec_ib);
1502
1503 break;
1504 default:
1505 /* invalid rule */
1506 return -EINVAL;
1507 }
1508 /* We must put empty rule, qpn is being ignored */
1509 ret = parse_flow_attr(mdev->dev, 0, &ib_spec,
1510 mlx4_spec);
1511 if (ret < 0) {
1512 pr_info("invalid parsing\n");
1513 return -EINVAL;
1514 }
1515
1516 mlx4_spec = (void *)mlx4_spec + ret;
1517 size += ret;
1518 }
1519 return size;
1520 }
1521
__mlx4_ib_create_flow(struct ib_qp * qp,struct ib_flow_attr * flow_attr,int domain,enum mlx4_net_trans_promisc_mode flow_type,u64 * reg_id)1522 static int __mlx4_ib_create_flow(struct ib_qp *qp, struct ib_flow_attr *flow_attr,
1523 int domain,
1524 enum mlx4_net_trans_promisc_mode flow_type,
1525 u64 *reg_id)
1526 {
1527 int ret, i;
1528 int size = 0;
1529 void *ib_flow;
1530 struct mlx4_ib_dev *mdev = to_mdev(qp->device);
1531 struct mlx4_cmd_mailbox *mailbox;
1532 struct mlx4_net_trans_rule_hw_ctrl *ctrl;
1533 int default_flow;
1534
1535 if (flow_attr->priority > MLX4_IB_FLOW_MAX_PRIO) {
1536 pr_err("Invalid priority value %d\n", flow_attr->priority);
1537 return -EINVAL;
1538 }
1539
1540 if (mlx4_map_sw_to_hw_steering_mode(mdev->dev, flow_type) < 0)
1541 return -EINVAL;
1542
1543 mailbox = mlx4_alloc_cmd_mailbox(mdev->dev);
1544 if (IS_ERR(mailbox))
1545 return PTR_ERR(mailbox);
1546 ctrl = mailbox->buf;
1547
1548 ctrl->prio = cpu_to_be16(domain | flow_attr->priority);
1549 ctrl->type = mlx4_map_sw_to_hw_steering_mode(mdev->dev, flow_type);
1550 ctrl->port = flow_attr->port;
1551 ctrl->qpn = cpu_to_be32(qp->qp_num);
1552
1553 ib_flow = flow_attr + 1;
1554 size += sizeof(struct mlx4_net_trans_rule_hw_ctrl);
1555 /* Add default flows */
1556 default_flow = __mlx4_ib_default_rules_match(qp, flow_attr);
1557 if (default_flow >= 0) {
1558 ret = __mlx4_ib_create_default_rules(
1559 mdev, qp, default_table + default_flow,
1560 mailbox->buf + size);
1561 if (ret < 0) {
1562 mlx4_free_cmd_mailbox(mdev->dev, mailbox);
1563 return -EINVAL;
1564 }
1565 size += ret;
1566 }
1567 for (i = 0; i < flow_attr->num_of_specs; i++) {
1568 ret = parse_flow_attr(mdev->dev, qp->qp_num, ib_flow,
1569 mailbox->buf + size);
1570 if (ret < 0) {
1571 mlx4_free_cmd_mailbox(mdev->dev, mailbox);
1572 return -EINVAL;
1573 }
1574 ib_flow += ((union ib_flow_spec *) ib_flow)->size;
1575 size += ret;
1576 }
1577
1578 if (mlx4_is_master(mdev->dev) && flow_type == MLX4_FS_REGULAR &&
1579 flow_attr->num_of_specs == 1) {
1580 struct _rule_hw *rule_header = (struct _rule_hw *)(ctrl + 1);
1581 enum ib_flow_spec_type header_spec =
1582 ((union ib_flow_spec *)(flow_attr + 1))->type;
1583
1584 if (header_spec == IB_FLOW_SPEC_ETH)
1585 mlx4_handle_eth_header_mcast_prio(ctrl, rule_header);
1586 }
1587
1588 ret = mlx4_cmd_imm(mdev->dev, mailbox->dma, reg_id, size >> 2, 0,
1589 MLX4_QP_FLOW_STEERING_ATTACH, MLX4_CMD_TIME_CLASS_A,
1590 MLX4_CMD_NATIVE);
1591 if (ret == -ENOMEM)
1592 pr_err("mcg table is full. Fail to register network rule.\n");
1593 else if (ret == -ENXIO)
1594 pr_err("Device managed flow steering is disabled. Fail to register network rule.\n");
1595 else if (ret)
1596 pr_err("Invalid argument. Fail to register network rule.\n");
1597
1598 mlx4_free_cmd_mailbox(mdev->dev, mailbox);
1599 return ret;
1600 }
1601
__mlx4_ib_destroy_flow(struct mlx4_dev * dev,u64 reg_id)1602 static int __mlx4_ib_destroy_flow(struct mlx4_dev *dev, u64 reg_id)
1603 {
1604 int err;
1605 err = mlx4_cmd(dev, reg_id, 0, 0,
1606 MLX4_QP_FLOW_STEERING_DETACH, MLX4_CMD_TIME_CLASS_A,
1607 MLX4_CMD_NATIVE);
1608 if (err)
1609 pr_err("Fail to detach network rule. registration id = 0x%llx\n",
1610 reg_id);
1611 return err;
1612 }
1613
mlx4_ib_tunnel_steer_add(struct ib_qp * qp,struct ib_flow_attr * flow_attr,u64 * reg_id)1614 static int mlx4_ib_tunnel_steer_add(struct ib_qp *qp, struct ib_flow_attr *flow_attr,
1615 u64 *reg_id)
1616 {
1617 void *ib_flow;
1618 union ib_flow_spec *ib_spec;
1619 struct mlx4_dev *dev = to_mdev(qp->device)->dev;
1620 int err = 0;
1621
1622 if (dev->caps.tunnel_offload_mode != MLX4_TUNNEL_OFFLOAD_MODE_VXLAN ||
1623 dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC)
1624 return 0; /* do nothing */
1625
1626 ib_flow = flow_attr + 1;
1627 ib_spec = (union ib_flow_spec *)ib_flow;
1628
1629 if (ib_spec->type != IB_FLOW_SPEC_ETH || flow_attr->num_of_specs != 1)
1630 return 0; /* do nothing */
1631
1632 err = mlx4_tunnel_steer_add(to_mdev(qp->device)->dev, ib_spec->eth.val.dst_mac,
1633 flow_attr->port, qp->qp_num,
1634 MLX4_DOMAIN_UVERBS | (flow_attr->priority & 0xff),
1635 reg_id);
1636 return err;
1637 }
1638
mlx4_ib_add_dont_trap_rule(struct mlx4_dev * dev,struct ib_flow_attr * flow_attr,enum mlx4_net_trans_promisc_mode * type)1639 static int mlx4_ib_add_dont_trap_rule(struct mlx4_dev *dev,
1640 struct ib_flow_attr *flow_attr,
1641 enum mlx4_net_trans_promisc_mode *type)
1642 {
1643 int err = 0;
1644
1645 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DMFS_UC_MC_SNIFFER) ||
1646 (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC) ||
1647 (flow_attr->num_of_specs > 1) || (flow_attr->priority != 0)) {
1648 return -EOPNOTSUPP;
1649 }
1650
1651 if (flow_attr->num_of_specs == 0) {
1652 type[0] = MLX4_FS_MC_SNIFFER;
1653 type[1] = MLX4_FS_UC_SNIFFER;
1654 } else {
1655 union ib_flow_spec *ib_spec;
1656
1657 ib_spec = (union ib_flow_spec *)(flow_attr + 1);
1658 if (ib_spec->type != IB_FLOW_SPEC_ETH)
1659 return -EINVAL;
1660
1661 /* if all is zero than MC and UC */
1662 if (is_zero_ether_addr(ib_spec->eth.mask.dst_mac)) {
1663 type[0] = MLX4_FS_MC_SNIFFER;
1664 type[1] = MLX4_FS_UC_SNIFFER;
1665 } else {
1666 u8 mac[ETH_ALEN] = {ib_spec->eth.mask.dst_mac[0] ^ 0x01,
1667 ib_spec->eth.mask.dst_mac[1],
1668 ib_spec->eth.mask.dst_mac[2],
1669 ib_spec->eth.mask.dst_mac[3],
1670 ib_spec->eth.mask.dst_mac[4],
1671 ib_spec->eth.mask.dst_mac[5]};
1672
1673 /* Above xor was only on MC bit, non empty mask is valid
1674 * only if this bit is set and rest are zero.
1675 */
1676 if (!is_zero_ether_addr(&mac[0]))
1677 return -EINVAL;
1678
1679 if (is_multicast_ether_addr(ib_spec->eth.val.dst_mac))
1680 type[0] = MLX4_FS_MC_SNIFFER;
1681 else
1682 type[0] = MLX4_FS_UC_SNIFFER;
1683 }
1684 }
1685
1686 return err;
1687 }
1688
mlx4_ib_create_flow(struct ib_qp * qp,struct ib_flow_attr * flow_attr,struct ib_udata * udata)1689 static struct ib_flow *mlx4_ib_create_flow(struct ib_qp *qp,
1690 struct ib_flow_attr *flow_attr,
1691 struct ib_udata *udata)
1692 {
1693 int err = 0, i = 0, j = 0;
1694 struct mlx4_ib_flow *mflow;
1695 enum mlx4_net_trans_promisc_mode type[2];
1696 struct mlx4_dev *dev = (to_mdev(qp->device))->dev;
1697 int is_bonded = mlx4_is_bonded(dev);
1698
1699 if (flow_attr->port < 1 || flow_attr->port > qp->device->phys_port_cnt)
1700 return ERR_PTR(-EINVAL);
1701
1702 if (flow_attr->flags & ~IB_FLOW_ATTR_FLAGS_DONT_TRAP)
1703 return ERR_PTR(-EOPNOTSUPP);
1704
1705 if ((flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) &&
1706 (flow_attr->type != IB_FLOW_ATTR_NORMAL))
1707 return ERR_PTR(-EOPNOTSUPP);
1708
1709 if (udata &&
1710 udata->inlen && !ib_is_udata_cleared(udata, 0, udata->inlen))
1711 return ERR_PTR(-EOPNOTSUPP);
1712
1713 memset(type, 0, sizeof(type));
1714
1715 mflow = kzalloc(sizeof(*mflow), GFP_KERNEL);
1716 if (!mflow) {
1717 err = -ENOMEM;
1718 goto err_free;
1719 }
1720
1721 switch (flow_attr->type) {
1722 case IB_FLOW_ATTR_NORMAL:
1723 /* If dont trap flag (continue match) is set, under specific
1724 * condition traffic be replicated to given qp,
1725 * without stealing it
1726 */
1727 if (unlikely(flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP)) {
1728 err = mlx4_ib_add_dont_trap_rule(dev,
1729 flow_attr,
1730 type);
1731 if (err)
1732 goto err_free;
1733 } else {
1734 type[0] = MLX4_FS_REGULAR;
1735 }
1736 break;
1737
1738 case IB_FLOW_ATTR_ALL_DEFAULT:
1739 type[0] = MLX4_FS_ALL_DEFAULT;
1740 break;
1741
1742 case IB_FLOW_ATTR_MC_DEFAULT:
1743 type[0] = MLX4_FS_MC_DEFAULT;
1744 break;
1745
1746 case IB_FLOW_ATTR_SNIFFER:
1747 type[0] = MLX4_FS_MIRROR_RX_PORT;
1748 type[1] = MLX4_FS_MIRROR_SX_PORT;
1749 break;
1750
1751 default:
1752 err = -EINVAL;
1753 goto err_free;
1754 }
1755
1756 while (i < ARRAY_SIZE(type) && type[i]) {
1757 err = __mlx4_ib_create_flow(qp, flow_attr, MLX4_DOMAIN_UVERBS,
1758 type[i], &mflow->reg_id[i].id);
1759 if (err)
1760 goto err_create_flow;
1761 if (is_bonded) {
1762 /* Application always sees one port so the mirror rule
1763 * must be on port #2
1764 */
1765 flow_attr->port = 2;
1766 err = __mlx4_ib_create_flow(qp, flow_attr,
1767 MLX4_DOMAIN_UVERBS, type[j],
1768 &mflow->reg_id[j].mirror);
1769 flow_attr->port = 1;
1770 if (err)
1771 goto err_create_flow;
1772 j++;
1773 }
1774
1775 i++;
1776 }
1777
1778 if (i < ARRAY_SIZE(type) && flow_attr->type == IB_FLOW_ATTR_NORMAL) {
1779 err = mlx4_ib_tunnel_steer_add(qp, flow_attr,
1780 &mflow->reg_id[i].id);
1781 if (err)
1782 goto err_create_flow;
1783
1784 if (is_bonded) {
1785 flow_attr->port = 2;
1786 err = mlx4_ib_tunnel_steer_add(qp, flow_attr,
1787 &mflow->reg_id[j].mirror);
1788 flow_attr->port = 1;
1789 if (err)
1790 goto err_create_flow;
1791 j++;
1792 }
1793 /* function to create mirror rule */
1794 i++;
1795 }
1796
1797 return &mflow->ibflow;
1798
1799 err_create_flow:
1800 while (i) {
1801 (void)__mlx4_ib_destroy_flow(to_mdev(qp->device)->dev,
1802 mflow->reg_id[i].id);
1803 i--;
1804 }
1805
1806 while (j) {
1807 (void)__mlx4_ib_destroy_flow(to_mdev(qp->device)->dev,
1808 mflow->reg_id[j].mirror);
1809 j--;
1810 }
1811 err_free:
1812 kfree(mflow);
1813 return ERR_PTR(err);
1814 }
1815
mlx4_ib_destroy_flow(struct ib_flow * flow_id)1816 static int mlx4_ib_destroy_flow(struct ib_flow *flow_id)
1817 {
1818 int err, ret = 0;
1819 int i = 0;
1820 struct mlx4_ib_dev *mdev = to_mdev(flow_id->qp->device);
1821 struct mlx4_ib_flow *mflow = to_mflow(flow_id);
1822
1823 while (i < ARRAY_SIZE(mflow->reg_id) && mflow->reg_id[i].id) {
1824 err = __mlx4_ib_destroy_flow(mdev->dev, mflow->reg_id[i].id);
1825 if (err)
1826 ret = err;
1827 if (mflow->reg_id[i].mirror) {
1828 err = __mlx4_ib_destroy_flow(mdev->dev,
1829 mflow->reg_id[i].mirror);
1830 if (err)
1831 ret = err;
1832 }
1833 i++;
1834 }
1835
1836 kfree(mflow);
1837 return ret;
1838 }
1839
mlx4_ib_mcg_attach(struct ib_qp * ibqp,union ib_gid * gid,u16 lid)1840 static int mlx4_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
1841 {
1842 int err;
1843 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
1844 struct mlx4_dev *dev = mdev->dev;
1845 struct mlx4_ib_qp *mqp = to_mqp(ibqp);
1846 struct mlx4_ib_steering *ib_steering = NULL;
1847 enum mlx4_protocol prot = MLX4_PROT_IB_IPV6;
1848 struct mlx4_flow_reg_id reg_id;
1849
1850 if (mdev->dev->caps.steering_mode ==
1851 MLX4_STEERING_MODE_DEVICE_MANAGED) {
1852 ib_steering = kmalloc(sizeof(*ib_steering), GFP_KERNEL);
1853 if (!ib_steering)
1854 return -ENOMEM;
1855 }
1856
1857 err = mlx4_multicast_attach(mdev->dev, &mqp->mqp, gid->raw, mqp->port,
1858 !!(mqp->flags &
1859 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK),
1860 prot, ®_id.id);
1861 if (err) {
1862 pr_err("multicast attach op failed, err %d\n", err);
1863 goto err_malloc;
1864 }
1865
1866 reg_id.mirror = 0;
1867 if (mlx4_is_bonded(dev)) {
1868 err = mlx4_multicast_attach(mdev->dev, &mqp->mqp, gid->raw,
1869 (mqp->port == 1) ? 2 : 1,
1870 !!(mqp->flags &
1871 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK),
1872 prot, ®_id.mirror);
1873 if (err)
1874 goto err_add;
1875 }
1876
1877 err = add_gid_entry(ibqp, gid);
1878 if (err)
1879 goto err_add;
1880
1881 if (ib_steering) {
1882 memcpy(ib_steering->gid.raw, gid->raw, 16);
1883 ib_steering->reg_id = reg_id;
1884 mutex_lock(&mqp->mutex);
1885 list_add(&ib_steering->list, &mqp->steering_rules);
1886 mutex_unlock(&mqp->mutex);
1887 }
1888 return 0;
1889
1890 err_add:
1891 mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw,
1892 prot, reg_id.id);
1893 if (reg_id.mirror)
1894 mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw,
1895 prot, reg_id.mirror);
1896 err_malloc:
1897 kfree(ib_steering);
1898
1899 return err;
1900 }
1901
find_gid_entry(struct mlx4_ib_qp * qp,u8 * raw)1902 static struct mlx4_ib_gid_entry *find_gid_entry(struct mlx4_ib_qp *qp, u8 *raw)
1903 {
1904 struct mlx4_ib_gid_entry *ge;
1905 struct mlx4_ib_gid_entry *tmp;
1906 struct mlx4_ib_gid_entry *ret = NULL;
1907
1908 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
1909 if (!memcmp(raw, ge->gid.raw, 16)) {
1910 ret = ge;
1911 break;
1912 }
1913 }
1914
1915 return ret;
1916 }
1917
mlx4_ib_mcg_detach(struct ib_qp * ibqp,union ib_gid * gid,u16 lid)1918 static int mlx4_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
1919 {
1920 int err;
1921 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
1922 struct mlx4_dev *dev = mdev->dev;
1923 struct mlx4_ib_qp *mqp = to_mqp(ibqp);
1924 struct net_device *ndev;
1925 struct mlx4_ib_gid_entry *ge;
1926 struct mlx4_flow_reg_id reg_id = {0, 0};
1927 enum mlx4_protocol prot = MLX4_PROT_IB_IPV6;
1928
1929 if (mdev->dev->caps.steering_mode ==
1930 MLX4_STEERING_MODE_DEVICE_MANAGED) {
1931 struct mlx4_ib_steering *ib_steering;
1932
1933 mutex_lock(&mqp->mutex);
1934 list_for_each_entry(ib_steering, &mqp->steering_rules, list) {
1935 if (!memcmp(ib_steering->gid.raw, gid->raw, 16)) {
1936 list_del(&ib_steering->list);
1937 break;
1938 }
1939 }
1940 mutex_unlock(&mqp->mutex);
1941 if (&ib_steering->list == &mqp->steering_rules) {
1942 pr_err("Couldn't find reg_id for mgid. Steering rule is left attached\n");
1943 return -EINVAL;
1944 }
1945 reg_id = ib_steering->reg_id;
1946 kfree(ib_steering);
1947 }
1948
1949 err = mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw,
1950 prot, reg_id.id);
1951 if (err)
1952 return err;
1953
1954 if (mlx4_is_bonded(dev)) {
1955 err = mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw,
1956 prot, reg_id.mirror);
1957 if (err)
1958 return err;
1959 }
1960
1961 mutex_lock(&mqp->mutex);
1962 ge = find_gid_entry(mqp, gid->raw);
1963 if (ge) {
1964 spin_lock_bh(&mdev->iboe.lock);
1965 ndev = ge->added ? mdev->iboe.netdevs[ge->port - 1] : NULL;
1966 if (ndev)
1967 dev_hold(ndev);
1968 spin_unlock_bh(&mdev->iboe.lock);
1969 if (ndev)
1970 dev_put(ndev);
1971 list_del(&ge->list);
1972 kfree(ge);
1973 } else
1974 pr_warn("could not find mgid entry\n");
1975
1976 mutex_unlock(&mqp->mutex);
1977
1978 return 0;
1979 }
1980
init_node_data(struct mlx4_ib_dev * dev)1981 static int init_node_data(struct mlx4_ib_dev *dev)
1982 {
1983 struct ib_smp *in_mad = NULL;
1984 struct ib_smp *out_mad = NULL;
1985 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS;
1986 int err = -ENOMEM;
1987
1988 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
1989 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
1990 if (!in_mad || !out_mad)
1991 goto out;
1992
1993 init_query_mad(in_mad);
1994 in_mad->attr_id = IB_SMP_ATTR_NODE_DESC;
1995 if (mlx4_is_master(dev->dev))
1996 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW;
1997
1998 err = mlx4_MAD_IFC(dev, mad_ifc_flags, 1, NULL, NULL, in_mad, out_mad);
1999 if (err)
2000 goto out;
2001
2002 memcpy(dev->ib_dev.node_desc, out_mad->data, IB_DEVICE_NODE_DESC_MAX);
2003
2004 in_mad->attr_id = IB_SMP_ATTR_NODE_INFO;
2005
2006 err = mlx4_MAD_IFC(dev, mad_ifc_flags, 1, NULL, NULL, in_mad, out_mad);
2007 if (err)
2008 goto out;
2009
2010 dev->dev->rev_id = be32_to_cpup((__be32 *) (out_mad->data + 32));
2011 memcpy(&dev->ib_dev.node_guid, out_mad->data + 12, 8);
2012
2013 out:
2014 kfree(in_mad);
2015 kfree(out_mad);
2016 return err;
2017 }
2018
hca_type_show(struct device * device,struct device_attribute * attr,char * buf)2019 static ssize_t hca_type_show(struct device *device,
2020 struct device_attribute *attr, char *buf)
2021 {
2022 struct mlx4_ib_dev *dev =
2023 rdma_device_to_drv_device(device, struct mlx4_ib_dev, ib_dev);
2024 return sprintf(buf, "MT%d\n", dev->dev->persist->pdev->device);
2025 }
2026 static DEVICE_ATTR_RO(hca_type);
2027
hw_rev_show(struct device * device,struct device_attribute * attr,char * buf)2028 static ssize_t hw_rev_show(struct device *device,
2029 struct device_attribute *attr, char *buf)
2030 {
2031 struct mlx4_ib_dev *dev =
2032 rdma_device_to_drv_device(device, struct mlx4_ib_dev, ib_dev);
2033 return sprintf(buf, "%x\n", dev->dev->rev_id);
2034 }
2035 static DEVICE_ATTR_RO(hw_rev);
2036
board_id_show(struct device * device,struct device_attribute * attr,char * buf)2037 static ssize_t board_id_show(struct device *device,
2038 struct device_attribute *attr, char *buf)
2039 {
2040 struct mlx4_ib_dev *dev =
2041 rdma_device_to_drv_device(device, struct mlx4_ib_dev, ib_dev);
2042
2043 return sprintf(buf, "%.*s\n", MLX4_BOARD_ID_LEN,
2044 dev->dev->board_id);
2045 }
2046 static DEVICE_ATTR_RO(board_id);
2047
2048 static struct attribute *mlx4_class_attributes[] = {
2049 &dev_attr_hw_rev.attr,
2050 &dev_attr_hca_type.attr,
2051 &dev_attr_board_id.attr,
2052 NULL
2053 };
2054
2055 static const struct attribute_group mlx4_attr_group = {
2056 .attrs = mlx4_class_attributes,
2057 };
2058
2059 struct diag_counter {
2060 const char *name;
2061 u32 offset;
2062 };
2063
2064 #define DIAG_COUNTER(_name, _offset) \
2065 { .name = #_name, .offset = _offset }
2066
2067 static const struct diag_counter diag_basic[] = {
2068 DIAG_COUNTER(rq_num_lle, 0x00),
2069 DIAG_COUNTER(sq_num_lle, 0x04),
2070 DIAG_COUNTER(rq_num_lqpoe, 0x08),
2071 DIAG_COUNTER(sq_num_lqpoe, 0x0C),
2072 DIAG_COUNTER(rq_num_lpe, 0x18),
2073 DIAG_COUNTER(sq_num_lpe, 0x1C),
2074 DIAG_COUNTER(rq_num_wrfe, 0x20),
2075 DIAG_COUNTER(sq_num_wrfe, 0x24),
2076 DIAG_COUNTER(sq_num_mwbe, 0x2C),
2077 DIAG_COUNTER(sq_num_bre, 0x34),
2078 DIAG_COUNTER(sq_num_rire, 0x44),
2079 DIAG_COUNTER(rq_num_rire, 0x48),
2080 DIAG_COUNTER(sq_num_rae, 0x4C),
2081 DIAG_COUNTER(rq_num_rae, 0x50),
2082 DIAG_COUNTER(sq_num_roe, 0x54),
2083 DIAG_COUNTER(sq_num_tree, 0x5C),
2084 DIAG_COUNTER(sq_num_rree, 0x64),
2085 DIAG_COUNTER(rq_num_rnr, 0x68),
2086 DIAG_COUNTER(sq_num_rnr, 0x6C),
2087 DIAG_COUNTER(rq_num_oos, 0x100),
2088 DIAG_COUNTER(sq_num_oos, 0x104),
2089 };
2090
2091 static const struct diag_counter diag_ext[] = {
2092 DIAG_COUNTER(rq_num_dup, 0x130),
2093 DIAG_COUNTER(sq_num_to, 0x134),
2094 };
2095
2096 static const struct diag_counter diag_device_only[] = {
2097 DIAG_COUNTER(num_cqovf, 0x1A0),
2098 DIAG_COUNTER(rq_num_udsdprd, 0x118),
2099 };
2100
mlx4_ib_alloc_hw_stats(struct ib_device * ibdev,u8 port_num)2101 static struct rdma_hw_stats *mlx4_ib_alloc_hw_stats(struct ib_device *ibdev,
2102 u8 port_num)
2103 {
2104 struct mlx4_ib_dev *dev = to_mdev(ibdev);
2105 struct mlx4_ib_diag_counters *diag = dev->diag_counters;
2106
2107 if (!diag[!!port_num].name)
2108 return NULL;
2109
2110 return rdma_alloc_hw_stats_struct(diag[!!port_num].name,
2111 diag[!!port_num].num_counters,
2112 RDMA_HW_STATS_DEFAULT_LIFESPAN);
2113 }
2114
mlx4_ib_get_hw_stats(struct ib_device * ibdev,struct rdma_hw_stats * stats,u8 port,int index)2115 static int mlx4_ib_get_hw_stats(struct ib_device *ibdev,
2116 struct rdma_hw_stats *stats,
2117 u8 port, int index)
2118 {
2119 struct mlx4_ib_dev *dev = to_mdev(ibdev);
2120 struct mlx4_ib_diag_counters *diag = dev->diag_counters;
2121 u32 hw_value[ARRAY_SIZE(diag_device_only) +
2122 ARRAY_SIZE(diag_ext) + ARRAY_SIZE(diag_basic)] = {};
2123 int ret;
2124 int i;
2125
2126 ret = mlx4_query_diag_counters(dev->dev,
2127 MLX4_OP_MOD_QUERY_TRANSPORT_CI_ERRORS,
2128 diag[!!port].offset, hw_value,
2129 diag[!!port].num_counters, port);
2130
2131 if (ret)
2132 return ret;
2133
2134 for (i = 0; i < diag[!!port].num_counters; i++)
2135 stats->value[i] = hw_value[i];
2136
2137 return diag[!!port].num_counters;
2138 }
2139
__mlx4_ib_alloc_diag_counters(struct mlx4_ib_dev * ibdev,const char *** name,u32 ** offset,u32 * num,bool port)2140 static int __mlx4_ib_alloc_diag_counters(struct mlx4_ib_dev *ibdev,
2141 const char ***name,
2142 u32 **offset,
2143 u32 *num,
2144 bool port)
2145 {
2146 u32 num_counters;
2147
2148 num_counters = ARRAY_SIZE(diag_basic);
2149
2150 if (ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT)
2151 num_counters += ARRAY_SIZE(diag_ext);
2152
2153 if (!port)
2154 num_counters += ARRAY_SIZE(diag_device_only);
2155
2156 *name = kcalloc(num_counters, sizeof(**name), GFP_KERNEL);
2157 if (!*name)
2158 return -ENOMEM;
2159
2160 *offset = kcalloc(num_counters, sizeof(**offset), GFP_KERNEL);
2161 if (!*offset)
2162 goto err_name;
2163
2164 *num = num_counters;
2165
2166 return 0;
2167
2168 err_name:
2169 kfree(*name);
2170 return -ENOMEM;
2171 }
2172
mlx4_ib_fill_diag_counters(struct mlx4_ib_dev * ibdev,const char ** name,u32 * offset,bool port)2173 static void mlx4_ib_fill_diag_counters(struct mlx4_ib_dev *ibdev,
2174 const char **name,
2175 u32 *offset,
2176 bool port)
2177 {
2178 int i;
2179 int j;
2180
2181 for (i = 0, j = 0; i < ARRAY_SIZE(diag_basic); i++, j++) {
2182 name[i] = diag_basic[i].name;
2183 offset[i] = diag_basic[i].offset;
2184 }
2185
2186 if (ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT) {
2187 for (i = 0; i < ARRAY_SIZE(diag_ext); i++, j++) {
2188 name[j] = diag_ext[i].name;
2189 offset[j] = diag_ext[i].offset;
2190 }
2191 }
2192
2193 if (!port) {
2194 for (i = 0; i < ARRAY_SIZE(diag_device_only); i++, j++) {
2195 name[j] = diag_device_only[i].name;
2196 offset[j] = diag_device_only[i].offset;
2197 }
2198 }
2199 }
2200
2201 static const struct ib_device_ops mlx4_ib_hw_stats_ops = {
2202 .alloc_hw_stats = mlx4_ib_alloc_hw_stats,
2203 .get_hw_stats = mlx4_ib_get_hw_stats,
2204 };
2205
mlx4_ib_alloc_diag_counters(struct mlx4_ib_dev * ibdev)2206 static int mlx4_ib_alloc_diag_counters(struct mlx4_ib_dev *ibdev)
2207 {
2208 struct mlx4_ib_diag_counters *diag = ibdev->diag_counters;
2209 int i;
2210 int ret;
2211 bool per_port = !!(ibdev->dev->caps.flags2 &
2212 MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT);
2213
2214 if (mlx4_is_slave(ibdev->dev))
2215 return 0;
2216
2217 for (i = 0; i < MLX4_DIAG_COUNTERS_TYPES; i++) {
2218 /* i == 1 means we are building port counters */
2219 if (i && !per_port)
2220 continue;
2221
2222 ret = __mlx4_ib_alloc_diag_counters(ibdev, &diag[i].name,
2223 &diag[i].offset,
2224 &diag[i].num_counters, i);
2225 if (ret)
2226 goto err_alloc;
2227
2228 mlx4_ib_fill_diag_counters(ibdev, diag[i].name,
2229 diag[i].offset, i);
2230 }
2231
2232 ib_set_device_ops(&ibdev->ib_dev, &mlx4_ib_hw_stats_ops);
2233
2234 return 0;
2235
2236 err_alloc:
2237 if (i) {
2238 kfree(diag[i - 1].name);
2239 kfree(diag[i - 1].offset);
2240 }
2241
2242 return ret;
2243 }
2244
mlx4_ib_diag_cleanup(struct mlx4_ib_dev * ibdev)2245 static void mlx4_ib_diag_cleanup(struct mlx4_ib_dev *ibdev)
2246 {
2247 int i;
2248
2249 for (i = 0; i < MLX4_DIAG_COUNTERS_TYPES; i++) {
2250 kfree(ibdev->diag_counters[i].offset);
2251 kfree(ibdev->diag_counters[i].name);
2252 }
2253 }
2254
2255 #define MLX4_IB_INVALID_MAC ((u64)-1)
mlx4_ib_update_qps(struct mlx4_ib_dev * ibdev,struct net_device * dev,int port)2256 static void mlx4_ib_update_qps(struct mlx4_ib_dev *ibdev,
2257 struct net_device *dev,
2258 int port)
2259 {
2260 u64 new_smac = 0;
2261 u64 release_mac = MLX4_IB_INVALID_MAC;
2262 struct mlx4_ib_qp *qp;
2263
2264 read_lock(&dev_base_lock);
2265 new_smac = mlx4_mac_to_u64(dev->dev_addr);
2266 read_unlock(&dev_base_lock);
2267
2268 atomic64_set(&ibdev->iboe.mac[port - 1], new_smac);
2269
2270 /* no need for update QP1 and mac registration in non-SRIOV */
2271 if (!mlx4_is_mfunc(ibdev->dev))
2272 return;
2273
2274 mutex_lock(&ibdev->qp1_proxy_lock[port - 1]);
2275 qp = ibdev->qp1_proxy[port - 1];
2276 if (qp) {
2277 int new_smac_index;
2278 u64 old_smac;
2279 struct mlx4_update_qp_params update_params;
2280
2281 mutex_lock(&qp->mutex);
2282 old_smac = qp->pri.smac;
2283 if (new_smac == old_smac)
2284 goto unlock;
2285
2286 new_smac_index = mlx4_register_mac(ibdev->dev, port, new_smac);
2287
2288 if (new_smac_index < 0)
2289 goto unlock;
2290
2291 update_params.smac_index = new_smac_index;
2292 if (mlx4_update_qp(ibdev->dev, qp->mqp.qpn, MLX4_UPDATE_QP_SMAC,
2293 &update_params)) {
2294 release_mac = new_smac;
2295 goto unlock;
2296 }
2297 /* if old port was zero, no mac was yet registered for this QP */
2298 if (qp->pri.smac_port)
2299 release_mac = old_smac;
2300 qp->pri.smac = new_smac;
2301 qp->pri.smac_port = port;
2302 qp->pri.smac_index = new_smac_index;
2303 }
2304
2305 unlock:
2306 if (release_mac != MLX4_IB_INVALID_MAC)
2307 mlx4_unregister_mac(ibdev->dev, port, release_mac);
2308 if (qp)
2309 mutex_unlock(&qp->mutex);
2310 mutex_unlock(&ibdev->qp1_proxy_lock[port - 1]);
2311 }
2312
mlx4_ib_scan_netdevs(struct mlx4_ib_dev * ibdev,struct net_device * dev,unsigned long event)2313 static void mlx4_ib_scan_netdevs(struct mlx4_ib_dev *ibdev,
2314 struct net_device *dev,
2315 unsigned long event)
2316
2317 {
2318 struct mlx4_ib_iboe *iboe;
2319 int update_qps_port = -1;
2320 int port;
2321
2322 ASSERT_RTNL();
2323
2324 iboe = &ibdev->iboe;
2325
2326 spin_lock_bh(&iboe->lock);
2327 mlx4_foreach_ib_transport_port(port, ibdev->dev) {
2328
2329 iboe->netdevs[port - 1] =
2330 mlx4_get_protocol_dev(ibdev->dev, MLX4_PROT_ETH, port);
2331
2332 if (dev == iboe->netdevs[port - 1] &&
2333 (event == NETDEV_CHANGEADDR || event == NETDEV_REGISTER ||
2334 event == NETDEV_UP || event == NETDEV_CHANGE))
2335 update_qps_port = port;
2336
2337 if (dev == iboe->netdevs[port - 1] &&
2338 (event == NETDEV_UP || event == NETDEV_DOWN)) {
2339 enum ib_port_state port_state;
2340 struct ib_event ibev = { };
2341
2342 if (ib_get_cached_port_state(&ibdev->ib_dev, port,
2343 &port_state))
2344 continue;
2345
2346 if (event == NETDEV_UP &&
2347 (port_state != IB_PORT_ACTIVE ||
2348 iboe->last_port_state[port - 1] != IB_PORT_DOWN))
2349 continue;
2350 if (event == NETDEV_DOWN &&
2351 (port_state != IB_PORT_DOWN ||
2352 iboe->last_port_state[port - 1] != IB_PORT_ACTIVE))
2353 continue;
2354 iboe->last_port_state[port - 1] = port_state;
2355
2356 ibev.device = &ibdev->ib_dev;
2357 ibev.element.port_num = port;
2358 ibev.event = event == NETDEV_UP ? IB_EVENT_PORT_ACTIVE :
2359 IB_EVENT_PORT_ERR;
2360 ib_dispatch_event(&ibev);
2361 }
2362
2363 }
2364 spin_unlock_bh(&iboe->lock);
2365
2366 if (update_qps_port > 0)
2367 mlx4_ib_update_qps(ibdev, dev, update_qps_port);
2368 }
2369
mlx4_ib_netdev_event(struct notifier_block * this,unsigned long event,void * ptr)2370 static int mlx4_ib_netdev_event(struct notifier_block *this,
2371 unsigned long event, void *ptr)
2372 {
2373 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
2374 struct mlx4_ib_dev *ibdev;
2375
2376 if (!net_eq(dev_net(dev), &init_net))
2377 return NOTIFY_DONE;
2378
2379 ibdev = container_of(this, struct mlx4_ib_dev, iboe.nb);
2380 mlx4_ib_scan_netdevs(ibdev, dev, event);
2381
2382 return NOTIFY_DONE;
2383 }
2384
init_pkeys(struct mlx4_ib_dev * ibdev)2385 static void init_pkeys(struct mlx4_ib_dev *ibdev)
2386 {
2387 int port;
2388 int slave;
2389 int i;
2390
2391 if (mlx4_is_master(ibdev->dev)) {
2392 for (slave = 0; slave <= ibdev->dev->persist->num_vfs;
2393 ++slave) {
2394 for (port = 1; port <= ibdev->dev->caps.num_ports; ++port) {
2395 for (i = 0;
2396 i < ibdev->dev->phys_caps.pkey_phys_table_len[port];
2397 ++i) {
2398 ibdev->pkeys.virt2phys_pkey[slave][port - 1][i] =
2399 /* master has the identity virt2phys pkey mapping */
2400 (slave == mlx4_master_func_num(ibdev->dev) || !i) ? i :
2401 ibdev->dev->phys_caps.pkey_phys_table_len[port] - 1;
2402 mlx4_sync_pkey_table(ibdev->dev, slave, port, i,
2403 ibdev->pkeys.virt2phys_pkey[slave][port - 1][i]);
2404 }
2405 }
2406 }
2407 /* initialize pkey cache */
2408 for (port = 1; port <= ibdev->dev->caps.num_ports; ++port) {
2409 for (i = 0;
2410 i < ibdev->dev->phys_caps.pkey_phys_table_len[port];
2411 ++i)
2412 ibdev->pkeys.phys_pkey_cache[port-1][i] =
2413 (i) ? 0 : 0xFFFF;
2414 }
2415 }
2416 }
2417
mlx4_ib_alloc_eqs(struct mlx4_dev * dev,struct mlx4_ib_dev * ibdev)2418 static void mlx4_ib_alloc_eqs(struct mlx4_dev *dev, struct mlx4_ib_dev *ibdev)
2419 {
2420 int i, j, eq = 0, total_eqs = 0;
2421
2422 ibdev->eq_table = kcalloc(dev->caps.num_comp_vectors,
2423 sizeof(ibdev->eq_table[0]), GFP_KERNEL);
2424 if (!ibdev->eq_table)
2425 return;
2426
2427 for (i = 1; i <= dev->caps.num_ports; i++) {
2428 for (j = 0; j < mlx4_get_eqs_per_port(dev, i);
2429 j++, total_eqs++) {
2430 if (i > 1 && mlx4_is_eq_shared(dev, total_eqs))
2431 continue;
2432 ibdev->eq_table[eq] = total_eqs;
2433 if (!mlx4_assign_eq(dev, i,
2434 &ibdev->eq_table[eq]))
2435 eq++;
2436 else
2437 ibdev->eq_table[eq] = -1;
2438 }
2439 }
2440
2441 for (i = eq; i < dev->caps.num_comp_vectors;
2442 ibdev->eq_table[i++] = -1)
2443 ;
2444
2445 /* Advertise the new number of EQs to clients */
2446 ibdev->ib_dev.num_comp_vectors = eq;
2447 }
2448
mlx4_ib_free_eqs(struct mlx4_dev * dev,struct mlx4_ib_dev * ibdev)2449 static void mlx4_ib_free_eqs(struct mlx4_dev *dev, struct mlx4_ib_dev *ibdev)
2450 {
2451 int i;
2452 int total_eqs = ibdev->ib_dev.num_comp_vectors;
2453
2454 /* no eqs were allocated */
2455 if (!ibdev->eq_table)
2456 return;
2457
2458 /* Reset the advertised EQ number */
2459 ibdev->ib_dev.num_comp_vectors = 0;
2460
2461 for (i = 0; i < total_eqs; i++)
2462 mlx4_release_eq(dev, ibdev->eq_table[i]);
2463
2464 kfree(ibdev->eq_table);
2465 ibdev->eq_table = NULL;
2466 }
2467
mlx4_port_immutable(struct ib_device * ibdev,u8 port_num,struct ib_port_immutable * immutable)2468 static int mlx4_port_immutable(struct ib_device *ibdev, u8 port_num,
2469 struct ib_port_immutable *immutable)
2470 {
2471 struct ib_port_attr attr;
2472 struct mlx4_ib_dev *mdev = to_mdev(ibdev);
2473 int err;
2474
2475 if (mlx4_ib_port_link_layer(ibdev, port_num) == IB_LINK_LAYER_INFINIBAND) {
2476 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_IB;
2477 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
2478 } else {
2479 if (mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_IBOE)
2480 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE;
2481 if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2)
2482 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE |
2483 RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
2484 immutable->core_cap_flags |= RDMA_CORE_PORT_RAW_PACKET;
2485 if (immutable->core_cap_flags & (RDMA_CORE_PORT_IBA_ROCE |
2486 RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP))
2487 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
2488 }
2489
2490 err = ib_query_port(ibdev, port_num, &attr);
2491 if (err)
2492 return err;
2493
2494 immutable->pkey_tbl_len = attr.pkey_tbl_len;
2495 immutable->gid_tbl_len = attr.gid_tbl_len;
2496
2497 return 0;
2498 }
2499
get_fw_ver_str(struct ib_device * device,char * str)2500 static void get_fw_ver_str(struct ib_device *device, char *str)
2501 {
2502 struct mlx4_ib_dev *dev =
2503 container_of(device, struct mlx4_ib_dev, ib_dev);
2504 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%d",
2505 (int) (dev->dev->caps.fw_ver >> 32),
2506 (int) (dev->dev->caps.fw_ver >> 16) & 0xffff,
2507 (int) dev->dev->caps.fw_ver & 0xffff);
2508 }
2509
2510 static const struct ib_device_ops mlx4_ib_dev_ops = {
2511 .owner = THIS_MODULE,
2512 .driver_id = RDMA_DRIVER_MLX4,
2513 .uverbs_abi_ver = MLX4_IB_UVERBS_ABI_VERSION,
2514
2515 .add_gid = mlx4_ib_add_gid,
2516 .alloc_mr = mlx4_ib_alloc_mr,
2517 .alloc_pd = mlx4_ib_alloc_pd,
2518 .alloc_ucontext = mlx4_ib_alloc_ucontext,
2519 .attach_mcast = mlx4_ib_mcg_attach,
2520 .create_ah = mlx4_ib_create_ah,
2521 .create_cq = mlx4_ib_create_cq,
2522 .create_qp = mlx4_ib_create_qp,
2523 .create_srq = mlx4_ib_create_srq,
2524 .dealloc_pd = mlx4_ib_dealloc_pd,
2525 .dealloc_ucontext = mlx4_ib_dealloc_ucontext,
2526 .del_gid = mlx4_ib_del_gid,
2527 .dereg_mr = mlx4_ib_dereg_mr,
2528 .destroy_ah = mlx4_ib_destroy_ah,
2529 .destroy_cq = mlx4_ib_destroy_cq,
2530 .destroy_qp = mlx4_ib_destroy_qp,
2531 .destroy_srq = mlx4_ib_destroy_srq,
2532 .detach_mcast = mlx4_ib_mcg_detach,
2533 .disassociate_ucontext = mlx4_ib_disassociate_ucontext,
2534 .drain_rq = mlx4_ib_drain_rq,
2535 .drain_sq = mlx4_ib_drain_sq,
2536 .get_dev_fw_str = get_fw_ver_str,
2537 .get_dma_mr = mlx4_ib_get_dma_mr,
2538 .get_link_layer = mlx4_ib_port_link_layer,
2539 .get_netdev = mlx4_ib_get_netdev,
2540 .get_port_immutable = mlx4_port_immutable,
2541 .map_mr_sg = mlx4_ib_map_mr_sg,
2542 .mmap = mlx4_ib_mmap,
2543 .modify_cq = mlx4_ib_modify_cq,
2544 .modify_device = mlx4_ib_modify_device,
2545 .modify_port = mlx4_ib_modify_port,
2546 .modify_qp = mlx4_ib_modify_qp,
2547 .modify_srq = mlx4_ib_modify_srq,
2548 .poll_cq = mlx4_ib_poll_cq,
2549 .post_recv = mlx4_ib_post_recv,
2550 .post_send = mlx4_ib_post_send,
2551 .post_srq_recv = mlx4_ib_post_srq_recv,
2552 .process_mad = mlx4_ib_process_mad,
2553 .query_ah = mlx4_ib_query_ah,
2554 .query_device = mlx4_ib_query_device,
2555 .query_gid = mlx4_ib_query_gid,
2556 .query_pkey = mlx4_ib_query_pkey,
2557 .query_port = mlx4_ib_query_port,
2558 .query_qp = mlx4_ib_query_qp,
2559 .query_srq = mlx4_ib_query_srq,
2560 .reg_user_mr = mlx4_ib_reg_user_mr,
2561 .req_notify_cq = mlx4_ib_arm_cq,
2562 .rereg_user_mr = mlx4_ib_rereg_user_mr,
2563 .resize_cq = mlx4_ib_resize_cq,
2564
2565 INIT_RDMA_OBJ_SIZE(ib_ah, mlx4_ib_ah, ibah),
2566 INIT_RDMA_OBJ_SIZE(ib_cq, mlx4_ib_cq, ibcq),
2567 INIT_RDMA_OBJ_SIZE(ib_pd, mlx4_ib_pd, ibpd),
2568 INIT_RDMA_OBJ_SIZE(ib_srq, mlx4_ib_srq, ibsrq),
2569 INIT_RDMA_OBJ_SIZE(ib_ucontext, mlx4_ib_ucontext, ibucontext),
2570 };
2571
2572 static const struct ib_device_ops mlx4_ib_dev_wq_ops = {
2573 .create_rwq_ind_table = mlx4_ib_create_rwq_ind_table,
2574 .create_wq = mlx4_ib_create_wq,
2575 .destroy_rwq_ind_table = mlx4_ib_destroy_rwq_ind_table,
2576 .destroy_wq = mlx4_ib_destroy_wq,
2577 .modify_wq = mlx4_ib_modify_wq,
2578
2579 INIT_RDMA_OBJ_SIZE(ib_rwq_ind_table, mlx4_ib_rwq_ind_table,
2580 ib_rwq_ind_tbl),
2581 };
2582
2583 static const struct ib_device_ops mlx4_ib_dev_mw_ops = {
2584 .alloc_mw = mlx4_ib_alloc_mw,
2585 .dealloc_mw = mlx4_ib_dealloc_mw,
2586
2587 INIT_RDMA_OBJ_SIZE(ib_mw, mlx4_ib_mw, ibmw),
2588 };
2589
2590 static const struct ib_device_ops mlx4_ib_dev_xrc_ops = {
2591 .alloc_xrcd = mlx4_ib_alloc_xrcd,
2592 .dealloc_xrcd = mlx4_ib_dealloc_xrcd,
2593
2594 INIT_RDMA_OBJ_SIZE(ib_xrcd, mlx4_ib_xrcd, ibxrcd),
2595 };
2596
2597 static const struct ib_device_ops mlx4_ib_dev_fs_ops = {
2598 .create_flow = mlx4_ib_create_flow,
2599 .destroy_flow = mlx4_ib_destroy_flow,
2600 };
2601
mlx4_ib_add(struct mlx4_dev * dev)2602 static void *mlx4_ib_add(struct mlx4_dev *dev)
2603 {
2604 struct mlx4_ib_dev *ibdev;
2605 int num_ports = 0;
2606 int i, j;
2607 int err;
2608 struct mlx4_ib_iboe *iboe;
2609 int ib_num_ports = 0;
2610 int num_req_counters;
2611 int allocated;
2612 u32 counter_index;
2613 struct counter_index *new_counter_index = NULL;
2614
2615 pr_info_once("%s", mlx4_ib_version);
2616
2617 num_ports = 0;
2618 mlx4_foreach_ib_transport_port(i, dev)
2619 num_ports++;
2620
2621 /* No point in registering a device with no ports... */
2622 if (num_ports == 0)
2623 return NULL;
2624
2625 ibdev = ib_alloc_device(mlx4_ib_dev, ib_dev);
2626 if (!ibdev) {
2627 dev_err(&dev->persist->pdev->dev,
2628 "Device struct alloc failed\n");
2629 return NULL;
2630 }
2631
2632 iboe = &ibdev->iboe;
2633
2634 if (mlx4_pd_alloc(dev, &ibdev->priv_pdn))
2635 goto err_dealloc;
2636
2637 if (mlx4_uar_alloc(dev, &ibdev->priv_uar))
2638 goto err_pd;
2639
2640 ibdev->uar_map = ioremap((phys_addr_t) ibdev->priv_uar.pfn << PAGE_SHIFT,
2641 PAGE_SIZE);
2642 if (!ibdev->uar_map)
2643 goto err_uar;
2644 MLX4_INIT_DOORBELL_LOCK(&ibdev->uar_lock);
2645
2646 ibdev->dev = dev;
2647 ibdev->bond_next_port = 0;
2648
2649 ibdev->ib_dev.node_type = RDMA_NODE_IB_CA;
2650 ibdev->ib_dev.local_dma_lkey = dev->caps.reserved_lkey;
2651 ibdev->num_ports = num_ports;
2652 ibdev->ib_dev.phys_port_cnt = mlx4_is_bonded(dev) ?
2653 1 : ibdev->num_ports;
2654 ibdev->ib_dev.num_comp_vectors = dev->caps.num_comp_vectors;
2655 ibdev->ib_dev.dev.parent = &dev->persist->pdev->dev;
2656
2657 ibdev->ib_dev.uverbs_cmd_mask =
2658 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
2659 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
2660 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
2661 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
2662 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
2663 (1ull << IB_USER_VERBS_CMD_REG_MR) |
2664 (1ull << IB_USER_VERBS_CMD_REREG_MR) |
2665 (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
2666 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
2667 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
2668 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
2669 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
2670 (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
2671 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
2672 (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
2673 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
2674 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
2675 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
2676 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
2677 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
2678 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
2679 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
2680 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) |
2681 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
2682
2683 ib_set_device_ops(&ibdev->ib_dev, &mlx4_ib_dev_ops);
2684 ibdev->ib_dev.uverbs_ex_cmd_mask |=
2685 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) |
2686 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP);
2687
2688 if ((dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS) &&
2689 ((mlx4_ib_port_link_layer(&ibdev->ib_dev, 1) ==
2690 IB_LINK_LAYER_ETHERNET) ||
2691 (mlx4_ib_port_link_layer(&ibdev->ib_dev, 2) ==
2692 IB_LINK_LAYER_ETHERNET)))
2693 ib_set_device_ops(&ibdev->ib_dev, &mlx4_ib_dev_wq_ops);
2694
2695 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW ||
2696 dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN) {
2697 ibdev->ib_dev.uverbs_cmd_mask |=
2698 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) |
2699 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
2700 ib_set_device_ops(&ibdev->ib_dev, &mlx4_ib_dev_mw_ops);
2701 }
2702
2703 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) {
2704 ibdev->ib_dev.uverbs_cmd_mask |=
2705 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
2706 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
2707 ib_set_device_ops(&ibdev->ib_dev, &mlx4_ib_dev_xrc_ops);
2708 }
2709
2710 if (check_flow_steering_support(dev)) {
2711 ibdev->steering_support = MLX4_STEERING_MODE_DEVICE_MANAGED;
2712 ib_set_device_ops(&ibdev->ib_dev, &mlx4_ib_dev_fs_ops);
2713 }
2714
2715 if (!dev->caps.userspace_caps)
2716 ibdev->ib_dev.ops.uverbs_abi_ver =
2717 MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION;
2718
2719 mlx4_ib_alloc_eqs(dev, ibdev);
2720
2721 spin_lock_init(&iboe->lock);
2722
2723 if (init_node_data(ibdev))
2724 goto err_map;
2725 mlx4_init_sl2vl_tbl(ibdev);
2726
2727 for (i = 0; i < ibdev->num_ports; ++i) {
2728 mutex_init(&ibdev->counters_table[i].mutex);
2729 INIT_LIST_HEAD(&ibdev->counters_table[i].counters_list);
2730 iboe->last_port_state[i] = IB_PORT_DOWN;
2731 }
2732
2733 num_req_counters = mlx4_is_bonded(dev) ? 1 : ibdev->num_ports;
2734 for (i = 0; i < num_req_counters; ++i) {
2735 mutex_init(&ibdev->qp1_proxy_lock[i]);
2736 allocated = 0;
2737 if (mlx4_ib_port_link_layer(&ibdev->ib_dev, i + 1) ==
2738 IB_LINK_LAYER_ETHERNET) {
2739 err = mlx4_counter_alloc(ibdev->dev, &counter_index,
2740 MLX4_RES_USAGE_DRIVER);
2741 /* if failed to allocate a new counter, use default */
2742 if (err)
2743 counter_index =
2744 mlx4_get_default_counter_index(dev,
2745 i + 1);
2746 else
2747 allocated = 1;
2748 } else { /* IB_LINK_LAYER_INFINIBAND use the default counter */
2749 counter_index = mlx4_get_default_counter_index(dev,
2750 i + 1);
2751 }
2752 new_counter_index = kmalloc(sizeof(*new_counter_index),
2753 GFP_KERNEL);
2754 if (!new_counter_index) {
2755 if (allocated)
2756 mlx4_counter_free(ibdev->dev, counter_index);
2757 goto err_counter;
2758 }
2759 new_counter_index->index = counter_index;
2760 new_counter_index->allocated = allocated;
2761 list_add_tail(&new_counter_index->list,
2762 &ibdev->counters_table[i].counters_list);
2763 ibdev->counters_table[i].default_counter = counter_index;
2764 pr_info("counter index %d for port %d allocated %d\n",
2765 counter_index, i + 1, allocated);
2766 }
2767 if (mlx4_is_bonded(dev))
2768 for (i = 1; i < ibdev->num_ports ; ++i) {
2769 new_counter_index =
2770 kmalloc(sizeof(struct counter_index),
2771 GFP_KERNEL);
2772 if (!new_counter_index)
2773 goto err_counter;
2774 new_counter_index->index = counter_index;
2775 new_counter_index->allocated = 0;
2776 list_add_tail(&new_counter_index->list,
2777 &ibdev->counters_table[i].counters_list);
2778 ibdev->counters_table[i].default_counter =
2779 counter_index;
2780 }
2781
2782 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
2783 ib_num_ports++;
2784
2785 spin_lock_init(&ibdev->sm_lock);
2786 mutex_init(&ibdev->cap_mask_mutex);
2787 INIT_LIST_HEAD(&ibdev->qp_list);
2788 spin_lock_init(&ibdev->reset_flow_resource_lock);
2789
2790 if (ibdev->steering_support == MLX4_STEERING_MODE_DEVICE_MANAGED &&
2791 ib_num_ports) {
2792 ibdev->steer_qpn_count = MLX4_IB_UC_MAX_NUM_QPS;
2793 err = mlx4_qp_reserve_range(dev, ibdev->steer_qpn_count,
2794 MLX4_IB_UC_STEER_QPN_ALIGN,
2795 &ibdev->steer_qpn_base, 0,
2796 MLX4_RES_USAGE_DRIVER);
2797 if (err)
2798 goto err_counter;
2799
2800 ibdev->ib_uc_qpns_bitmap =
2801 kmalloc_array(BITS_TO_LONGS(ibdev->steer_qpn_count),
2802 sizeof(long),
2803 GFP_KERNEL);
2804 if (!ibdev->ib_uc_qpns_bitmap)
2805 goto err_steer_qp_release;
2806
2807 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DMFS_IPOIB) {
2808 bitmap_zero(ibdev->ib_uc_qpns_bitmap,
2809 ibdev->steer_qpn_count);
2810 err = mlx4_FLOW_STEERING_IB_UC_QP_RANGE(
2811 dev, ibdev->steer_qpn_base,
2812 ibdev->steer_qpn_base +
2813 ibdev->steer_qpn_count - 1);
2814 if (err)
2815 goto err_steer_free_bitmap;
2816 } else {
2817 bitmap_fill(ibdev->ib_uc_qpns_bitmap,
2818 ibdev->steer_qpn_count);
2819 }
2820 }
2821
2822 for (j = 1; j <= ibdev->dev->caps.num_ports; j++)
2823 atomic64_set(&iboe->mac[j - 1], ibdev->dev->caps.def_mac[j]);
2824
2825 if (mlx4_ib_alloc_diag_counters(ibdev))
2826 goto err_steer_free_bitmap;
2827
2828 rdma_set_device_sysfs_group(&ibdev->ib_dev, &mlx4_attr_group);
2829 if (ib_register_device(&ibdev->ib_dev, "mlx4_%d",
2830 &dev->persist->pdev->dev))
2831 goto err_diag_counters;
2832
2833 if (mlx4_ib_mad_init(ibdev))
2834 goto err_reg;
2835
2836 if (mlx4_ib_init_sriov(ibdev))
2837 goto err_mad;
2838
2839 if (!iboe->nb.notifier_call) {
2840 iboe->nb.notifier_call = mlx4_ib_netdev_event;
2841 err = register_netdevice_notifier(&iboe->nb);
2842 if (err) {
2843 iboe->nb.notifier_call = NULL;
2844 goto err_notif;
2845 }
2846 }
2847 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2) {
2848 err = mlx4_config_roce_v2_port(dev, ROCE_V2_UDP_DPORT);
2849 if (err)
2850 goto err_notif;
2851 }
2852
2853 ibdev->ib_active = true;
2854 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
2855 devlink_port_type_ib_set(mlx4_get_devlink_port(dev, i),
2856 &ibdev->ib_dev);
2857
2858 if (mlx4_is_mfunc(ibdev->dev))
2859 init_pkeys(ibdev);
2860
2861 /* create paravirt contexts for any VFs which are active */
2862 if (mlx4_is_master(ibdev->dev)) {
2863 for (j = 0; j < MLX4_MFUNC_MAX; j++) {
2864 if (j == mlx4_master_func_num(ibdev->dev))
2865 continue;
2866 if (mlx4_is_slave_active(ibdev->dev, j))
2867 do_slave_init(ibdev, j, 1);
2868 }
2869 }
2870 return ibdev;
2871
2872 err_notif:
2873 if (ibdev->iboe.nb.notifier_call) {
2874 if (unregister_netdevice_notifier(&ibdev->iboe.nb))
2875 pr_warn("failure unregistering notifier\n");
2876 ibdev->iboe.nb.notifier_call = NULL;
2877 }
2878 flush_workqueue(wq);
2879
2880 mlx4_ib_close_sriov(ibdev);
2881
2882 err_mad:
2883 mlx4_ib_mad_cleanup(ibdev);
2884
2885 err_reg:
2886 ib_unregister_device(&ibdev->ib_dev);
2887
2888 err_diag_counters:
2889 mlx4_ib_diag_cleanup(ibdev);
2890
2891 err_steer_free_bitmap:
2892 kfree(ibdev->ib_uc_qpns_bitmap);
2893
2894 err_steer_qp_release:
2895 mlx4_qp_release_range(dev, ibdev->steer_qpn_base,
2896 ibdev->steer_qpn_count);
2897 err_counter:
2898 for (i = 0; i < ibdev->num_ports; ++i)
2899 mlx4_ib_delete_counters_table(ibdev, &ibdev->counters_table[i]);
2900
2901 err_map:
2902 mlx4_ib_free_eqs(dev, ibdev);
2903 iounmap(ibdev->uar_map);
2904
2905 err_uar:
2906 mlx4_uar_free(dev, &ibdev->priv_uar);
2907
2908 err_pd:
2909 mlx4_pd_free(dev, ibdev->priv_pdn);
2910
2911 err_dealloc:
2912 ib_dealloc_device(&ibdev->ib_dev);
2913
2914 return NULL;
2915 }
2916
mlx4_ib_steer_qp_alloc(struct mlx4_ib_dev * dev,int count,int * qpn)2917 int mlx4_ib_steer_qp_alloc(struct mlx4_ib_dev *dev, int count, int *qpn)
2918 {
2919 int offset;
2920
2921 WARN_ON(!dev->ib_uc_qpns_bitmap);
2922
2923 offset = bitmap_find_free_region(dev->ib_uc_qpns_bitmap,
2924 dev->steer_qpn_count,
2925 get_count_order(count));
2926 if (offset < 0)
2927 return offset;
2928
2929 *qpn = dev->steer_qpn_base + offset;
2930 return 0;
2931 }
2932
mlx4_ib_steer_qp_free(struct mlx4_ib_dev * dev,u32 qpn,int count)2933 void mlx4_ib_steer_qp_free(struct mlx4_ib_dev *dev, u32 qpn, int count)
2934 {
2935 if (!qpn ||
2936 dev->steering_support != MLX4_STEERING_MODE_DEVICE_MANAGED)
2937 return;
2938
2939 if (WARN(qpn < dev->steer_qpn_base, "qpn = %u, steer_qpn_base = %u\n",
2940 qpn, dev->steer_qpn_base))
2941 /* not supposed to be here */
2942 return;
2943
2944 bitmap_release_region(dev->ib_uc_qpns_bitmap,
2945 qpn - dev->steer_qpn_base,
2946 get_count_order(count));
2947 }
2948
mlx4_ib_steer_qp_reg(struct mlx4_ib_dev * mdev,struct mlx4_ib_qp * mqp,int is_attach)2949 int mlx4_ib_steer_qp_reg(struct mlx4_ib_dev *mdev, struct mlx4_ib_qp *mqp,
2950 int is_attach)
2951 {
2952 int err;
2953 size_t flow_size;
2954 struct ib_flow_attr *flow = NULL;
2955 struct ib_flow_spec_ib *ib_spec;
2956
2957 if (is_attach) {
2958 flow_size = sizeof(struct ib_flow_attr) +
2959 sizeof(struct ib_flow_spec_ib);
2960 flow = kzalloc(flow_size, GFP_KERNEL);
2961 if (!flow)
2962 return -ENOMEM;
2963 flow->port = mqp->port;
2964 flow->num_of_specs = 1;
2965 flow->size = flow_size;
2966 ib_spec = (struct ib_flow_spec_ib *)(flow + 1);
2967 ib_spec->type = IB_FLOW_SPEC_IB;
2968 ib_spec->size = sizeof(struct ib_flow_spec_ib);
2969 /* Add an empty rule for IB L2 */
2970 memset(&ib_spec->mask, 0, sizeof(ib_spec->mask));
2971
2972 err = __mlx4_ib_create_flow(&mqp->ibqp, flow, MLX4_DOMAIN_NIC,
2973 MLX4_FS_REGULAR, &mqp->reg_id);
2974 } else {
2975 err = __mlx4_ib_destroy_flow(mdev->dev, mqp->reg_id);
2976 }
2977 kfree(flow);
2978 return err;
2979 }
2980
mlx4_ib_remove(struct mlx4_dev * dev,void * ibdev_ptr)2981 static void mlx4_ib_remove(struct mlx4_dev *dev, void *ibdev_ptr)
2982 {
2983 struct mlx4_ib_dev *ibdev = ibdev_ptr;
2984 int p;
2985 int i;
2986
2987 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
2988 devlink_port_type_clear(mlx4_get_devlink_port(dev, i));
2989 ibdev->ib_active = false;
2990 flush_workqueue(wq);
2991
2992 if (ibdev->iboe.nb.notifier_call) {
2993 if (unregister_netdevice_notifier(&ibdev->iboe.nb))
2994 pr_warn("failure unregistering notifier\n");
2995 ibdev->iboe.nb.notifier_call = NULL;
2996 }
2997
2998 mlx4_ib_close_sriov(ibdev);
2999 mlx4_ib_mad_cleanup(ibdev);
3000 ib_unregister_device(&ibdev->ib_dev);
3001 mlx4_ib_diag_cleanup(ibdev);
3002
3003 mlx4_qp_release_range(dev, ibdev->steer_qpn_base,
3004 ibdev->steer_qpn_count);
3005 kfree(ibdev->ib_uc_qpns_bitmap);
3006
3007 iounmap(ibdev->uar_map);
3008 for (p = 0; p < ibdev->num_ports; ++p)
3009 mlx4_ib_delete_counters_table(ibdev, &ibdev->counters_table[p]);
3010
3011 mlx4_foreach_port(p, dev, MLX4_PORT_TYPE_IB)
3012 mlx4_CLOSE_PORT(dev, p);
3013
3014 mlx4_ib_free_eqs(dev, ibdev);
3015
3016 mlx4_uar_free(dev, &ibdev->priv_uar);
3017 mlx4_pd_free(dev, ibdev->priv_pdn);
3018 ib_dealloc_device(&ibdev->ib_dev);
3019 }
3020
do_slave_init(struct mlx4_ib_dev * ibdev,int slave,int do_init)3021 static void do_slave_init(struct mlx4_ib_dev *ibdev, int slave, int do_init)
3022 {
3023 struct mlx4_ib_demux_work **dm = NULL;
3024 struct mlx4_dev *dev = ibdev->dev;
3025 int i;
3026 unsigned long flags;
3027 struct mlx4_active_ports actv_ports;
3028 unsigned int ports;
3029 unsigned int first_port;
3030
3031 if (!mlx4_is_master(dev))
3032 return;
3033
3034 actv_ports = mlx4_get_active_ports(dev, slave);
3035 ports = bitmap_weight(actv_ports.ports, dev->caps.num_ports);
3036 first_port = find_first_bit(actv_ports.ports, dev->caps.num_ports);
3037
3038 dm = kcalloc(ports, sizeof(*dm), GFP_ATOMIC);
3039 if (!dm)
3040 return;
3041
3042 for (i = 0; i < ports; i++) {
3043 dm[i] = kmalloc(sizeof (struct mlx4_ib_demux_work), GFP_ATOMIC);
3044 if (!dm[i]) {
3045 while (--i >= 0)
3046 kfree(dm[i]);
3047 goto out;
3048 }
3049 INIT_WORK(&dm[i]->work, mlx4_ib_tunnels_update_work);
3050 dm[i]->port = first_port + i + 1;
3051 dm[i]->slave = slave;
3052 dm[i]->do_init = do_init;
3053 dm[i]->dev = ibdev;
3054 }
3055 /* initialize or tear down tunnel QPs for the slave */
3056 spin_lock_irqsave(&ibdev->sriov.going_down_lock, flags);
3057 if (!ibdev->sriov.is_going_down) {
3058 for (i = 0; i < ports; i++)
3059 queue_work(ibdev->sriov.demux[i].ud_wq, &dm[i]->work);
3060 spin_unlock_irqrestore(&ibdev->sriov.going_down_lock, flags);
3061 } else {
3062 spin_unlock_irqrestore(&ibdev->sriov.going_down_lock, flags);
3063 for (i = 0; i < ports; i++)
3064 kfree(dm[i]);
3065 }
3066 out:
3067 kfree(dm);
3068 return;
3069 }
3070
mlx4_ib_handle_catas_error(struct mlx4_ib_dev * ibdev)3071 static void mlx4_ib_handle_catas_error(struct mlx4_ib_dev *ibdev)
3072 {
3073 struct mlx4_ib_qp *mqp;
3074 unsigned long flags_qp;
3075 unsigned long flags_cq;
3076 struct mlx4_ib_cq *send_mcq, *recv_mcq;
3077 struct list_head cq_notify_list;
3078 struct mlx4_cq *mcq;
3079 unsigned long flags;
3080
3081 pr_warn("mlx4_ib_handle_catas_error was started\n");
3082 INIT_LIST_HEAD(&cq_notify_list);
3083
3084 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
3085 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
3086
3087 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
3088 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
3089 if (mqp->sq.tail != mqp->sq.head) {
3090 send_mcq = to_mcq(mqp->ibqp.send_cq);
3091 spin_lock_irqsave(&send_mcq->lock, flags_cq);
3092 if (send_mcq->mcq.comp &&
3093 mqp->ibqp.send_cq->comp_handler) {
3094 if (!send_mcq->mcq.reset_notify_added) {
3095 send_mcq->mcq.reset_notify_added = 1;
3096 list_add_tail(&send_mcq->mcq.reset_notify,
3097 &cq_notify_list);
3098 }
3099 }
3100 spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
3101 }
3102 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
3103 /* Now, handle the QP's receive queue */
3104 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
3105 /* no handling is needed for SRQ */
3106 if (!mqp->ibqp.srq) {
3107 if (mqp->rq.tail != mqp->rq.head) {
3108 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
3109 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
3110 if (recv_mcq->mcq.comp &&
3111 mqp->ibqp.recv_cq->comp_handler) {
3112 if (!recv_mcq->mcq.reset_notify_added) {
3113 recv_mcq->mcq.reset_notify_added = 1;
3114 list_add_tail(&recv_mcq->mcq.reset_notify,
3115 &cq_notify_list);
3116 }
3117 }
3118 spin_unlock_irqrestore(&recv_mcq->lock,
3119 flags_cq);
3120 }
3121 }
3122 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
3123 }
3124
3125 list_for_each_entry(mcq, &cq_notify_list, reset_notify) {
3126 mcq->comp(mcq);
3127 }
3128 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
3129 pr_warn("mlx4_ib_handle_catas_error ended\n");
3130 }
3131
handle_bonded_port_state_event(struct work_struct * work)3132 static void handle_bonded_port_state_event(struct work_struct *work)
3133 {
3134 struct ib_event_work *ew =
3135 container_of(work, struct ib_event_work, work);
3136 struct mlx4_ib_dev *ibdev = ew->ib_dev;
3137 enum ib_port_state bonded_port_state = IB_PORT_NOP;
3138 int i;
3139 struct ib_event ibev;
3140
3141 kfree(ew);
3142 spin_lock_bh(&ibdev->iboe.lock);
3143 for (i = 0; i < MLX4_MAX_PORTS; ++i) {
3144 struct net_device *curr_netdev = ibdev->iboe.netdevs[i];
3145 enum ib_port_state curr_port_state;
3146
3147 if (!curr_netdev)
3148 continue;
3149
3150 curr_port_state =
3151 (netif_running(curr_netdev) &&
3152 netif_carrier_ok(curr_netdev)) ?
3153 IB_PORT_ACTIVE : IB_PORT_DOWN;
3154
3155 bonded_port_state = (bonded_port_state != IB_PORT_ACTIVE) ?
3156 curr_port_state : IB_PORT_ACTIVE;
3157 }
3158 spin_unlock_bh(&ibdev->iboe.lock);
3159
3160 ibev.device = &ibdev->ib_dev;
3161 ibev.element.port_num = 1;
3162 ibev.event = (bonded_port_state == IB_PORT_ACTIVE) ?
3163 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
3164
3165 ib_dispatch_event(&ibev);
3166 }
3167
mlx4_ib_sl2vl_update(struct mlx4_ib_dev * mdev,int port)3168 void mlx4_ib_sl2vl_update(struct mlx4_ib_dev *mdev, int port)
3169 {
3170 u64 sl2vl;
3171 int err;
3172
3173 err = mlx4_ib_query_sl2vl(&mdev->ib_dev, port, &sl2vl);
3174 if (err) {
3175 pr_err("Unable to get current sl to vl mapping for port %d. Using all zeroes (%d)\n",
3176 port, err);
3177 sl2vl = 0;
3178 }
3179 atomic64_set(&mdev->sl2vl[port - 1], sl2vl);
3180 }
3181
ib_sl2vl_update_work(struct work_struct * work)3182 static void ib_sl2vl_update_work(struct work_struct *work)
3183 {
3184 struct ib_event_work *ew = container_of(work, struct ib_event_work, work);
3185 struct mlx4_ib_dev *mdev = ew->ib_dev;
3186 int port = ew->port;
3187
3188 mlx4_ib_sl2vl_update(mdev, port);
3189
3190 kfree(ew);
3191 }
3192
mlx4_sched_ib_sl2vl_update_work(struct mlx4_ib_dev * ibdev,int port)3193 void mlx4_sched_ib_sl2vl_update_work(struct mlx4_ib_dev *ibdev,
3194 int port)
3195 {
3196 struct ib_event_work *ew;
3197
3198 ew = kmalloc(sizeof(*ew), GFP_ATOMIC);
3199 if (ew) {
3200 INIT_WORK(&ew->work, ib_sl2vl_update_work);
3201 ew->port = port;
3202 ew->ib_dev = ibdev;
3203 queue_work(wq, &ew->work);
3204 }
3205 }
3206
mlx4_ib_event(struct mlx4_dev * dev,void * ibdev_ptr,enum mlx4_dev_event event,unsigned long param)3207 static void mlx4_ib_event(struct mlx4_dev *dev, void *ibdev_ptr,
3208 enum mlx4_dev_event event, unsigned long param)
3209 {
3210 struct ib_event ibev;
3211 struct mlx4_ib_dev *ibdev = to_mdev((struct ib_device *) ibdev_ptr);
3212 struct mlx4_eqe *eqe = NULL;
3213 struct ib_event_work *ew;
3214 int p = 0;
3215
3216 if (mlx4_is_bonded(dev) &&
3217 ((event == MLX4_DEV_EVENT_PORT_UP) ||
3218 (event == MLX4_DEV_EVENT_PORT_DOWN))) {
3219 ew = kmalloc(sizeof(*ew), GFP_ATOMIC);
3220 if (!ew)
3221 return;
3222 INIT_WORK(&ew->work, handle_bonded_port_state_event);
3223 ew->ib_dev = ibdev;
3224 queue_work(wq, &ew->work);
3225 return;
3226 }
3227
3228 if (event == MLX4_DEV_EVENT_PORT_MGMT_CHANGE)
3229 eqe = (struct mlx4_eqe *)param;
3230 else
3231 p = (int) param;
3232
3233 switch (event) {
3234 case MLX4_DEV_EVENT_PORT_UP:
3235 if (p > ibdev->num_ports)
3236 return;
3237 if (!mlx4_is_slave(dev) &&
3238 rdma_port_get_link_layer(&ibdev->ib_dev, p) ==
3239 IB_LINK_LAYER_INFINIBAND) {
3240 if (mlx4_is_master(dev))
3241 mlx4_ib_invalidate_all_guid_record(ibdev, p);
3242 if (ibdev->dev->flags & MLX4_FLAG_SECURE_HOST &&
3243 !(ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SL_TO_VL_CHANGE_EVENT))
3244 mlx4_sched_ib_sl2vl_update_work(ibdev, p);
3245 }
3246 ibev.event = IB_EVENT_PORT_ACTIVE;
3247 break;
3248
3249 case MLX4_DEV_EVENT_PORT_DOWN:
3250 if (p > ibdev->num_ports)
3251 return;
3252 ibev.event = IB_EVENT_PORT_ERR;
3253 break;
3254
3255 case MLX4_DEV_EVENT_CATASTROPHIC_ERROR:
3256 ibdev->ib_active = false;
3257 ibev.event = IB_EVENT_DEVICE_FATAL;
3258 mlx4_ib_handle_catas_error(ibdev);
3259 break;
3260
3261 case MLX4_DEV_EVENT_PORT_MGMT_CHANGE:
3262 ew = kmalloc(sizeof *ew, GFP_ATOMIC);
3263 if (!ew)
3264 return;
3265
3266 INIT_WORK(&ew->work, handle_port_mgmt_change_event);
3267 memcpy(&ew->ib_eqe, eqe, sizeof *eqe);
3268 ew->ib_dev = ibdev;
3269 /* need to queue only for port owner, which uses GEN_EQE */
3270 if (mlx4_is_master(dev))
3271 queue_work(wq, &ew->work);
3272 else
3273 handle_port_mgmt_change_event(&ew->work);
3274 return;
3275
3276 case MLX4_DEV_EVENT_SLAVE_INIT:
3277 /* here, p is the slave id */
3278 do_slave_init(ibdev, p, 1);
3279 if (mlx4_is_master(dev)) {
3280 int i;
3281
3282 for (i = 1; i <= ibdev->num_ports; i++) {
3283 if (rdma_port_get_link_layer(&ibdev->ib_dev, i)
3284 == IB_LINK_LAYER_INFINIBAND)
3285 mlx4_ib_slave_alias_guid_event(ibdev,
3286 p, i,
3287 1);
3288 }
3289 }
3290 return;
3291
3292 case MLX4_DEV_EVENT_SLAVE_SHUTDOWN:
3293 if (mlx4_is_master(dev)) {
3294 int i;
3295
3296 for (i = 1; i <= ibdev->num_ports; i++) {
3297 if (rdma_port_get_link_layer(&ibdev->ib_dev, i)
3298 == IB_LINK_LAYER_INFINIBAND)
3299 mlx4_ib_slave_alias_guid_event(ibdev,
3300 p, i,
3301 0);
3302 }
3303 }
3304 /* here, p is the slave id */
3305 do_slave_init(ibdev, p, 0);
3306 return;
3307
3308 default:
3309 return;
3310 }
3311
3312 ibev.device = ibdev_ptr;
3313 ibev.element.port_num = mlx4_is_bonded(ibdev->dev) ? 1 : (u8)p;
3314
3315 ib_dispatch_event(&ibev);
3316 }
3317
3318 static struct mlx4_interface mlx4_ib_interface = {
3319 .add = mlx4_ib_add,
3320 .remove = mlx4_ib_remove,
3321 .event = mlx4_ib_event,
3322 .protocol = MLX4_PROT_IB_IPV6,
3323 .flags = MLX4_INTFF_BONDING
3324 };
3325
mlx4_ib_init(void)3326 static int __init mlx4_ib_init(void)
3327 {
3328 int err;
3329
3330 wq = alloc_ordered_workqueue("mlx4_ib", WQ_MEM_RECLAIM);
3331 if (!wq)
3332 return -ENOMEM;
3333
3334 err = mlx4_ib_mcg_init();
3335 if (err)
3336 goto clean_wq;
3337
3338 err = mlx4_register_interface(&mlx4_ib_interface);
3339 if (err)
3340 goto clean_mcg;
3341
3342 return 0;
3343
3344 clean_mcg:
3345 mlx4_ib_mcg_destroy();
3346
3347 clean_wq:
3348 destroy_workqueue(wq);
3349 return err;
3350 }
3351
mlx4_ib_cleanup(void)3352 static void __exit mlx4_ib_cleanup(void)
3353 {
3354 mlx4_unregister_interface(&mlx4_ib_interface);
3355 mlx4_ib_mcg_destroy();
3356 destroy_workqueue(wq);
3357 }
3358
3359 module_init(mlx4_ib_init);
3360 module_exit(mlx4_ib_cleanup);
3361