1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2014-2015 The Linux Foundation. All rights reserved.
4 * Copyright (C) 2013 Red Hat
5 * Author: Rob Clark <robdclark@gmail.com>
6 */
7
8 #include <drm/drm_damage_helper.h>
9 #include <drm/drm_fourcc.h>
10 #include <drm/drm_print.h>
11
12 #include "mdp5_kms.h"
13
14 struct mdp5_plane {
15 struct drm_plane base;
16
17 uint32_t nformats;
18 uint32_t formats[32];
19 };
20 #define to_mdp5_plane(x) container_of(x, struct mdp5_plane, base)
21
22 static int mdp5_plane_mode_set(struct drm_plane *plane,
23 struct drm_crtc *crtc, struct drm_framebuffer *fb,
24 struct drm_rect *src, struct drm_rect *dest);
25
get_kms(struct drm_plane * plane)26 static struct mdp5_kms *get_kms(struct drm_plane *plane)
27 {
28 struct msm_drm_private *priv = plane->dev->dev_private;
29 return to_mdp5_kms(to_mdp_kms(priv->kms));
30 }
31
plane_enabled(struct drm_plane_state * state)32 static bool plane_enabled(struct drm_plane_state *state)
33 {
34 return state->visible;
35 }
36
mdp5_plane_destroy(struct drm_plane * plane)37 static void mdp5_plane_destroy(struct drm_plane *plane)
38 {
39 struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane);
40
41 drm_plane_cleanup(plane);
42
43 kfree(mdp5_plane);
44 }
45
mdp5_plane_install_rotation_property(struct drm_device * dev,struct drm_plane * plane)46 static void mdp5_plane_install_rotation_property(struct drm_device *dev,
47 struct drm_plane *plane)
48 {
49 drm_plane_create_rotation_property(plane,
50 DRM_MODE_ROTATE_0,
51 DRM_MODE_ROTATE_0 |
52 DRM_MODE_ROTATE_180 |
53 DRM_MODE_REFLECT_X |
54 DRM_MODE_REFLECT_Y);
55 }
56
57 /* helper to install properties which are common to planes and crtcs */
mdp5_plane_install_properties(struct drm_plane * plane,struct drm_mode_object * obj)58 static void mdp5_plane_install_properties(struct drm_plane *plane,
59 struct drm_mode_object *obj)
60 {
61 struct drm_device *dev = plane->dev;
62 struct msm_drm_private *dev_priv = dev->dev_private;
63 struct drm_property *prop;
64
65 #define INSTALL_PROPERTY(name, NAME, init_val, fnc, ...) do { \
66 prop = dev_priv->plane_property[PLANE_PROP_##NAME]; \
67 if (!prop) { \
68 prop = drm_property_##fnc(dev, 0, #name, \
69 ##__VA_ARGS__); \
70 if (!prop) { \
71 dev_warn(dev->dev, \
72 "Create property %s failed\n", \
73 #name); \
74 return; \
75 } \
76 dev_priv->plane_property[PLANE_PROP_##NAME] = prop; \
77 } \
78 drm_object_attach_property(&plane->base, prop, init_val); \
79 } while (0)
80
81 #define INSTALL_RANGE_PROPERTY(name, NAME, min, max, init_val) \
82 INSTALL_PROPERTY(name, NAME, init_val, \
83 create_range, min, max)
84
85 #define INSTALL_ENUM_PROPERTY(name, NAME, init_val) \
86 INSTALL_PROPERTY(name, NAME, init_val, \
87 create_enum, name##_prop_enum_list, \
88 ARRAY_SIZE(name##_prop_enum_list))
89
90 INSTALL_RANGE_PROPERTY(zpos, ZPOS, 1, 255, 1);
91
92 mdp5_plane_install_rotation_property(dev, plane);
93
94 #undef INSTALL_RANGE_PROPERTY
95 #undef INSTALL_ENUM_PROPERTY
96 #undef INSTALL_PROPERTY
97 }
98
mdp5_plane_atomic_set_property(struct drm_plane * plane,struct drm_plane_state * state,struct drm_property * property,uint64_t val)99 static int mdp5_plane_atomic_set_property(struct drm_plane *plane,
100 struct drm_plane_state *state, struct drm_property *property,
101 uint64_t val)
102 {
103 struct drm_device *dev = plane->dev;
104 struct mdp5_plane_state *pstate;
105 struct msm_drm_private *dev_priv = dev->dev_private;
106 int ret = 0;
107
108 pstate = to_mdp5_plane_state(state);
109
110 #define SET_PROPERTY(name, NAME, type) do { \
111 if (dev_priv->plane_property[PLANE_PROP_##NAME] == property) { \
112 pstate->name = (type)val; \
113 DBG("Set property %s %d", #name, (type)val); \
114 goto done; \
115 } \
116 } while (0)
117
118 SET_PROPERTY(zpos, ZPOS, uint8_t);
119
120 DRM_DEV_ERROR(dev->dev, "Invalid property\n");
121 ret = -EINVAL;
122 done:
123 return ret;
124 #undef SET_PROPERTY
125 }
126
mdp5_plane_atomic_get_property(struct drm_plane * plane,const struct drm_plane_state * state,struct drm_property * property,uint64_t * val)127 static int mdp5_plane_atomic_get_property(struct drm_plane *plane,
128 const struct drm_plane_state *state,
129 struct drm_property *property, uint64_t *val)
130 {
131 struct drm_device *dev = plane->dev;
132 struct mdp5_plane_state *pstate;
133 struct msm_drm_private *dev_priv = dev->dev_private;
134 int ret = 0;
135
136 pstate = to_mdp5_plane_state(state);
137
138 #define GET_PROPERTY(name, NAME, type) do { \
139 if (dev_priv->plane_property[PLANE_PROP_##NAME] == property) { \
140 *val = pstate->name; \
141 DBG("Get property %s %lld", #name, *val); \
142 goto done; \
143 } \
144 } while (0)
145
146 GET_PROPERTY(zpos, ZPOS, uint8_t);
147
148 DRM_DEV_ERROR(dev->dev, "Invalid property\n");
149 ret = -EINVAL;
150 done:
151 return ret;
152 #undef SET_PROPERTY
153 }
154
155 static void
mdp5_plane_atomic_print_state(struct drm_printer * p,const struct drm_plane_state * state)156 mdp5_plane_atomic_print_state(struct drm_printer *p,
157 const struct drm_plane_state *state)
158 {
159 struct mdp5_plane_state *pstate = to_mdp5_plane_state(state);
160 struct mdp5_kms *mdp5_kms = get_kms(state->plane);
161
162 drm_printf(p, "\thwpipe=%s\n", pstate->hwpipe ?
163 pstate->hwpipe->name : "(null)");
164 if (mdp5_kms->caps & MDP_CAP_SRC_SPLIT)
165 drm_printf(p, "\tright-hwpipe=%s\n",
166 pstate->r_hwpipe ? pstate->r_hwpipe->name :
167 "(null)");
168 drm_printf(p, "\tpremultiplied=%u\n", pstate->premultiplied);
169 drm_printf(p, "\tzpos=%u\n", pstate->zpos);
170 drm_printf(p, "\talpha=%u\n", pstate->alpha);
171 drm_printf(p, "\tstage=%s\n", stage2name(pstate->stage));
172 }
173
mdp5_plane_reset(struct drm_plane * plane)174 static void mdp5_plane_reset(struct drm_plane *plane)
175 {
176 struct mdp5_plane_state *mdp5_state;
177
178 if (plane->state && plane->state->fb)
179 drm_framebuffer_put(plane->state->fb);
180
181 kfree(to_mdp5_plane_state(plane->state));
182 plane->state = NULL;
183 mdp5_state = kzalloc(sizeof(*mdp5_state), GFP_KERNEL);
184 if (!mdp5_state)
185 return;
186
187 /* assign default blend parameters */
188 mdp5_state->alpha = 255;
189 mdp5_state->premultiplied = 0;
190
191 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
192 mdp5_state->zpos = STAGE_BASE;
193 else
194 mdp5_state->zpos = STAGE0 + drm_plane_index(plane);
195
196 mdp5_state->base.plane = plane;
197
198 plane->state = &mdp5_state->base;
199 }
200
201 static struct drm_plane_state *
mdp5_plane_duplicate_state(struct drm_plane * plane)202 mdp5_plane_duplicate_state(struct drm_plane *plane)
203 {
204 struct mdp5_plane_state *mdp5_state;
205
206 if (WARN_ON(!plane->state))
207 return NULL;
208
209 mdp5_state = kmemdup(to_mdp5_plane_state(plane->state),
210 sizeof(*mdp5_state), GFP_KERNEL);
211 if (!mdp5_state)
212 return NULL;
213
214 __drm_atomic_helper_plane_duplicate_state(plane, &mdp5_state->base);
215
216 return &mdp5_state->base;
217 }
218
mdp5_plane_destroy_state(struct drm_plane * plane,struct drm_plane_state * state)219 static void mdp5_plane_destroy_state(struct drm_plane *plane,
220 struct drm_plane_state *state)
221 {
222 struct mdp5_plane_state *pstate = to_mdp5_plane_state(state);
223
224 __drm_atomic_helper_plane_destroy_state(state);
225
226 kfree(pstate);
227 }
228
229 static const struct drm_plane_funcs mdp5_plane_funcs = {
230 .update_plane = drm_atomic_helper_update_plane,
231 .disable_plane = drm_atomic_helper_disable_plane,
232 .destroy = mdp5_plane_destroy,
233 .atomic_set_property = mdp5_plane_atomic_set_property,
234 .atomic_get_property = mdp5_plane_atomic_get_property,
235 .reset = mdp5_plane_reset,
236 .atomic_duplicate_state = mdp5_plane_duplicate_state,
237 .atomic_destroy_state = mdp5_plane_destroy_state,
238 .atomic_print_state = mdp5_plane_atomic_print_state,
239 };
240
mdp5_plane_cleanup_fb(struct drm_plane * plane,struct drm_plane_state * old_state)241 static void mdp5_plane_cleanup_fb(struct drm_plane *plane,
242 struct drm_plane_state *old_state)
243 {
244 struct mdp5_kms *mdp5_kms = get_kms(plane);
245 struct msm_kms *kms = &mdp5_kms->base.base;
246 struct drm_framebuffer *fb = old_state->fb;
247
248 if (!fb)
249 return;
250
251 DBG("%s: cleanup: FB[%u]", plane->name, fb->base.id);
252 msm_framebuffer_cleanup(fb, kms->aspace);
253 }
254
mdp5_plane_atomic_check_with_state(struct drm_crtc_state * crtc_state,struct drm_plane_state * state)255 static int mdp5_plane_atomic_check_with_state(struct drm_crtc_state *crtc_state,
256 struct drm_plane_state *state)
257 {
258 struct mdp5_plane_state *mdp5_state = to_mdp5_plane_state(state);
259 struct drm_plane *plane = state->plane;
260 struct drm_plane_state *old_state = plane->state;
261 struct mdp5_cfg *config = mdp5_cfg_get_config(get_kms(plane)->cfg);
262 bool new_hwpipe = false;
263 bool need_right_hwpipe = false;
264 uint32_t max_width, max_height;
265 bool out_of_bounds = false;
266 uint32_t caps = 0;
267 int min_scale, max_scale;
268 int ret;
269
270 DBG("%s: check (%d -> %d)", plane->name,
271 plane_enabled(old_state), plane_enabled(state));
272
273 max_width = config->hw->lm.max_width << 16;
274 max_height = config->hw->lm.max_height << 16;
275
276 /* Make sure source dimensions are within bounds. */
277 if (state->src_h > max_height)
278 out_of_bounds = true;
279
280 if (state->src_w > max_width) {
281 /* If source split is supported, we can go up to 2x
282 * the max LM width, but we'd need to stage another
283 * hwpipe to the right LM. So, the drm_plane would
284 * consist of 2 hwpipes.
285 */
286 if (config->hw->mdp.caps & MDP_CAP_SRC_SPLIT &&
287 (state->src_w <= 2 * max_width))
288 need_right_hwpipe = true;
289 else
290 out_of_bounds = true;
291 }
292
293 if (out_of_bounds) {
294 struct drm_rect src = drm_plane_state_src(state);
295 DBG("Invalid source size "DRM_RECT_FP_FMT,
296 DRM_RECT_FP_ARG(&src));
297 return -ERANGE;
298 }
299
300 min_scale = FRAC_16_16(1, 8);
301 max_scale = FRAC_16_16(8, 1);
302
303 ret = drm_atomic_helper_check_plane_state(state, crtc_state,
304 min_scale, max_scale,
305 true, true);
306 if (ret)
307 return ret;
308
309 if (plane_enabled(state)) {
310 unsigned int rotation;
311 const struct mdp_format *format;
312 struct mdp5_kms *mdp5_kms = get_kms(plane);
313 uint32_t blkcfg = 0;
314
315 format = to_mdp_format(msm_framebuffer_format(state->fb));
316 if (MDP_FORMAT_IS_YUV(format))
317 caps |= MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC;
318
319 if (((state->src_w >> 16) != state->crtc_w) ||
320 ((state->src_h >> 16) != state->crtc_h))
321 caps |= MDP_PIPE_CAP_SCALE;
322
323 rotation = drm_rotation_simplify(state->rotation,
324 DRM_MODE_ROTATE_0 |
325 DRM_MODE_REFLECT_X |
326 DRM_MODE_REFLECT_Y);
327
328 if (rotation & DRM_MODE_REFLECT_X)
329 caps |= MDP_PIPE_CAP_HFLIP;
330
331 if (rotation & DRM_MODE_REFLECT_Y)
332 caps |= MDP_PIPE_CAP_VFLIP;
333
334 if (plane->type == DRM_PLANE_TYPE_CURSOR)
335 caps |= MDP_PIPE_CAP_CURSOR;
336
337 /* (re)allocate hw pipe if we don't have one or caps-mismatch: */
338 if (!mdp5_state->hwpipe || (caps & ~mdp5_state->hwpipe->caps))
339 new_hwpipe = true;
340
341 /*
342 * (re)allocte hw pipe if we're either requesting for 2 hw pipes
343 * or we're switching from 2 hw pipes to 1 hw pipe because the
344 * new src_w can be supported by 1 hw pipe itself.
345 */
346 if ((need_right_hwpipe && !mdp5_state->r_hwpipe) ||
347 (!need_right_hwpipe && mdp5_state->r_hwpipe))
348 new_hwpipe = true;
349
350 if (mdp5_kms->smp) {
351 const struct mdp_format *format =
352 to_mdp_format(msm_framebuffer_format(state->fb));
353
354 blkcfg = mdp5_smp_calculate(mdp5_kms->smp, format,
355 state->src_w >> 16, false);
356
357 if (mdp5_state->hwpipe && (mdp5_state->hwpipe->blkcfg != blkcfg))
358 new_hwpipe = true;
359 }
360
361 /* (re)assign hwpipe if needed, otherwise keep old one: */
362 if (new_hwpipe) {
363 /* TODO maybe we want to re-assign hwpipe sometimes
364 * in cases when we no-longer need some caps to make
365 * it available for other planes?
366 */
367 struct mdp5_hw_pipe *old_hwpipe = mdp5_state->hwpipe;
368 struct mdp5_hw_pipe *old_right_hwpipe =
369 mdp5_state->r_hwpipe;
370 struct mdp5_hw_pipe *new_hwpipe = NULL;
371 struct mdp5_hw_pipe *new_right_hwpipe = NULL;
372
373 ret = mdp5_pipe_assign(state->state, plane, caps,
374 blkcfg, &new_hwpipe,
375 need_right_hwpipe ?
376 &new_right_hwpipe : NULL);
377 if (ret) {
378 DBG("%s: failed to assign hwpipe(s)!",
379 plane->name);
380 return ret;
381 }
382
383 mdp5_state->hwpipe = new_hwpipe;
384 if (need_right_hwpipe)
385 mdp5_state->r_hwpipe = new_right_hwpipe;
386 else
387 /*
388 * set it to NULL so that the driver knows we
389 * don't have a right hwpipe when committing a
390 * new state
391 */
392 mdp5_state->r_hwpipe = NULL;
393
394
395 ret = mdp5_pipe_release(state->state, old_hwpipe);
396 if (ret)
397 return ret;
398
399 ret = mdp5_pipe_release(state->state, old_right_hwpipe);
400 if (ret)
401 return ret;
402
403 }
404 } else {
405 ret = mdp5_pipe_release(state->state, mdp5_state->hwpipe);
406 if (ret)
407 return ret;
408
409 ret = mdp5_pipe_release(state->state, mdp5_state->r_hwpipe);
410 if (ret)
411 return ret;
412
413 mdp5_state->hwpipe = mdp5_state->r_hwpipe = NULL;
414 }
415
416 return 0;
417 }
418
mdp5_plane_atomic_check(struct drm_plane * plane,struct drm_plane_state * state)419 static int mdp5_plane_atomic_check(struct drm_plane *plane,
420 struct drm_plane_state *state)
421 {
422 struct drm_crtc *crtc;
423 struct drm_crtc_state *crtc_state;
424
425 crtc = state->crtc ? state->crtc : plane->state->crtc;
426 if (!crtc)
427 return 0;
428
429 crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc);
430 if (WARN_ON(!crtc_state))
431 return -EINVAL;
432
433 return mdp5_plane_atomic_check_with_state(crtc_state, state);
434 }
435
mdp5_plane_atomic_update(struct drm_plane * plane,struct drm_plane_state * old_state)436 static void mdp5_plane_atomic_update(struct drm_plane *plane,
437 struct drm_plane_state *old_state)
438 {
439 struct drm_plane_state *state = plane->state;
440
441 DBG("%s: update", plane->name);
442
443 if (plane_enabled(state)) {
444 int ret;
445
446 ret = mdp5_plane_mode_set(plane,
447 state->crtc, state->fb,
448 &state->src, &state->dst);
449 /* atomic_check should have ensured that this doesn't fail */
450 WARN_ON(ret < 0);
451 }
452 }
453
mdp5_plane_atomic_async_check(struct drm_plane * plane,struct drm_plane_state * state)454 static int mdp5_plane_atomic_async_check(struct drm_plane *plane,
455 struct drm_plane_state *state)
456 {
457 struct mdp5_plane_state *mdp5_state = to_mdp5_plane_state(state);
458 struct drm_crtc_state *crtc_state;
459 int min_scale, max_scale;
460 int ret;
461
462 crtc_state = drm_atomic_get_existing_crtc_state(state->state,
463 state->crtc);
464 if (WARN_ON(!crtc_state))
465 return -EINVAL;
466
467 if (!crtc_state->active)
468 return -EINVAL;
469
470 mdp5_state = to_mdp5_plane_state(state);
471
472 /* don't use fast path if we don't have a hwpipe allocated yet */
473 if (!mdp5_state->hwpipe)
474 return -EINVAL;
475
476 /* only allow changing of position(crtc x/y or src x/y) in fast path */
477 if (plane->state->crtc != state->crtc ||
478 plane->state->src_w != state->src_w ||
479 plane->state->src_h != state->src_h ||
480 plane->state->crtc_w != state->crtc_w ||
481 plane->state->crtc_h != state->crtc_h ||
482 !plane->state->fb ||
483 plane->state->fb != state->fb)
484 return -EINVAL;
485
486 min_scale = FRAC_16_16(1, 8);
487 max_scale = FRAC_16_16(8, 1);
488
489 ret = drm_atomic_helper_check_plane_state(state, crtc_state,
490 min_scale, max_scale,
491 true, true);
492 if (ret)
493 return ret;
494
495 /*
496 * if the visibility of the plane changes (i.e, if the cursor is
497 * clipped out completely, we can't take the async path because
498 * we need to stage/unstage the plane from the Layer Mixer(s). We
499 * also assign/unassign the hwpipe(s) tied to the plane. We avoid
500 * taking the fast path for both these reasons.
501 */
502 if (state->visible != plane->state->visible)
503 return -EINVAL;
504
505 return 0;
506 }
507
mdp5_plane_atomic_async_update(struct drm_plane * plane,struct drm_plane_state * new_state)508 static void mdp5_plane_atomic_async_update(struct drm_plane *plane,
509 struct drm_plane_state *new_state)
510 {
511 struct drm_framebuffer *old_fb = plane->state->fb;
512
513 plane->state->src_x = new_state->src_x;
514 plane->state->src_y = new_state->src_y;
515 plane->state->crtc_x = new_state->crtc_x;
516 plane->state->crtc_y = new_state->crtc_y;
517
518 if (plane_enabled(new_state)) {
519 struct mdp5_ctl *ctl;
520 struct mdp5_pipeline *pipeline =
521 mdp5_crtc_get_pipeline(new_state->crtc);
522 int ret;
523
524 ret = mdp5_plane_mode_set(plane, new_state->crtc, new_state->fb,
525 &new_state->src, &new_state->dst);
526 WARN_ON(ret < 0);
527
528 ctl = mdp5_crtc_get_ctl(new_state->crtc);
529
530 mdp5_ctl_commit(ctl, pipeline, mdp5_plane_get_flush(plane), true);
531 }
532
533 *to_mdp5_plane_state(plane->state) =
534 *to_mdp5_plane_state(new_state);
535
536 new_state->fb = old_fb;
537 }
538
539 static const struct drm_plane_helper_funcs mdp5_plane_helper_funcs = {
540 .prepare_fb = msm_atomic_prepare_fb,
541 .cleanup_fb = mdp5_plane_cleanup_fb,
542 .atomic_check = mdp5_plane_atomic_check,
543 .atomic_update = mdp5_plane_atomic_update,
544 .atomic_async_check = mdp5_plane_atomic_async_check,
545 .atomic_async_update = mdp5_plane_atomic_async_update,
546 };
547
set_scanout_locked(struct mdp5_kms * mdp5_kms,enum mdp5_pipe pipe,struct drm_framebuffer * fb)548 static void set_scanout_locked(struct mdp5_kms *mdp5_kms,
549 enum mdp5_pipe pipe,
550 struct drm_framebuffer *fb)
551 {
552 struct msm_kms *kms = &mdp5_kms->base.base;
553
554 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_STRIDE_A(pipe),
555 MDP5_PIPE_SRC_STRIDE_A_P0(fb->pitches[0]) |
556 MDP5_PIPE_SRC_STRIDE_A_P1(fb->pitches[1]));
557
558 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_STRIDE_B(pipe),
559 MDP5_PIPE_SRC_STRIDE_B_P2(fb->pitches[2]) |
560 MDP5_PIPE_SRC_STRIDE_B_P3(fb->pitches[3]));
561
562 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC0_ADDR(pipe),
563 msm_framebuffer_iova(fb, kms->aspace, 0));
564 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC1_ADDR(pipe),
565 msm_framebuffer_iova(fb, kms->aspace, 1));
566 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC2_ADDR(pipe),
567 msm_framebuffer_iova(fb, kms->aspace, 2));
568 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC3_ADDR(pipe),
569 msm_framebuffer_iova(fb, kms->aspace, 3));
570 }
571
572 /* Note: mdp5_plane->pipe_lock must be locked */
csc_disable(struct mdp5_kms * mdp5_kms,enum mdp5_pipe pipe)573 static void csc_disable(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe)
574 {
575 uint32_t value = mdp5_read(mdp5_kms, REG_MDP5_PIPE_OP_MODE(pipe)) &
576 ~MDP5_PIPE_OP_MODE_CSC_1_EN;
577
578 mdp5_write(mdp5_kms, REG_MDP5_PIPE_OP_MODE(pipe), value);
579 }
580
581 /* Note: mdp5_plane->pipe_lock must be locked */
csc_enable(struct mdp5_kms * mdp5_kms,enum mdp5_pipe pipe,struct csc_cfg * csc)582 static void csc_enable(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe,
583 struct csc_cfg *csc)
584 {
585 uint32_t i, mode = 0; /* RGB, no CSC */
586 uint32_t *matrix;
587
588 if (unlikely(!csc))
589 return;
590
591 if ((csc->type == CSC_YUV2RGB) || (CSC_YUV2YUV == csc->type))
592 mode |= MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT(DATA_FORMAT_YUV);
593 if ((csc->type == CSC_RGB2YUV) || (CSC_YUV2YUV == csc->type))
594 mode |= MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT(DATA_FORMAT_YUV);
595 mode |= MDP5_PIPE_OP_MODE_CSC_1_EN;
596 mdp5_write(mdp5_kms, REG_MDP5_PIPE_OP_MODE(pipe), mode);
597
598 matrix = csc->matrix;
599 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_0(pipe),
600 MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11(matrix[0]) |
601 MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12(matrix[1]));
602 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_1(pipe),
603 MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13(matrix[2]) |
604 MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21(matrix[3]));
605 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_2(pipe),
606 MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22(matrix[4]) |
607 MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23(matrix[5]));
608 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_3(pipe),
609 MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31(matrix[6]) |
610 MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32(matrix[7]));
611 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_4(pipe),
612 MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33(matrix[8]));
613
614 for (i = 0; i < ARRAY_SIZE(csc->pre_bias); i++) {
615 uint32_t *pre_clamp = csc->pre_clamp;
616 uint32_t *post_clamp = csc->post_clamp;
617
618 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_PRE_CLAMP(pipe, i),
619 MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH(pre_clamp[2*i+1]) |
620 MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW(pre_clamp[2*i]));
621
622 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_POST_CLAMP(pipe, i),
623 MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH(post_clamp[2*i+1]) |
624 MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW(post_clamp[2*i]));
625
626 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_PRE_BIAS(pipe, i),
627 MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE(csc->pre_bias[i]));
628
629 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_POST_BIAS(pipe, i),
630 MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE(csc->post_bias[i]));
631 }
632 }
633
634 #define PHASE_STEP_SHIFT 21
635 #define DOWN_SCALE_RATIO_MAX 32 /* 2^(26-21) */
636
calc_phase_step(uint32_t src,uint32_t dst,uint32_t * out_phase)637 static int calc_phase_step(uint32_t src, uint32_t dst, uint32_t *out_phase)
638 {
639 uint32_t unit;
640
641 if (src == 0 || dst == 0)
642 return -EINVAL;
643
644 /*
645 * PHASE_STEP_X/Y is coded on 26 bits (25:0),
646 * where 2^21 represents the unity "1" in fixed-point hardware design.
647 * This leaves 5 bits for the integer part (downscale case):
648 * -> maximum downscale ratio = 0b1_1111 = 31
649 */
650 if (src > (dst * DOWN_SCALE_RATIO_MAX))
651 return -EOVERFLOW;
652
653 unit = 1 << PHASE_STEP_SHIFT;
654 *out_phase = mult_frac(unit, src, dst);
655
656 return 0;
657 }
658
calc_scalex_steps(struct drm_plane * plane,uint32_t pixel_format,uint32_t src,uint32_t dest,uint32_t phasex_steps[COMP_MAX])659 static int calc_scalex_steps(struct drm_plane *plane,
660 uint32_t pixel_format, uint32_t src, uint32_t dest,
661 uint32_t phasex_steps[COMP_MAX])
662 {
663 const struct drm_format_info *info = drm_format_info(pixel_format);
664 struct mdp5_kms *mdp5_kms = get_kms(plane);
665 struct device *dev = mdp5_kms->dev->dev;
666 uint32_t phasex_step;
667 int ret;
668
669 ret = calc_phase_step(src, dest, &phasex_step);
670 if (ret) {
671 DRM_DEV_ERROR(dev, "X scaling (%d->%d) failed: %d\n", src, dest, ret);
672 return ret;
673 }
674
675 phasex_steps[COMP_0] = phasex_step;
676 phasex_steps[COMP_3] = phasex_step;
677 phasex_steps[COMP_1_2] = phasex_step / info->hsub;
678
679 return 0;
680 }
681
calc_scaley_steps(struct drm_plane * plane,uint32_t pixel_format,uint32_t src,uint32_t dest,uint32_t phasey_steps[COMP_MAX])682 static int calc_scaley_steps(struct drm_plane *plane,
683 uint32_t pixel_format, uint32_t src, uint32_t dest,
684 uint32_t phasey_steps[COMP_MAX])
685 {
686 const struct drm_format_info *info = drm_format_info(pixel_format);
687 struct mdp5_kms *mdp5_kms = get_kms(plane);
688 struct device *dev = mdp5_kms->dev->dev;
689 uint32_t phasey_step;
690 int ret;
691
692 ret = calc_phase_step(src, dest, &phasey_step);
693 if (ret) {
694 DRM_DEV_ERROR(dev, "Y scaling (%d->%d) failed: %d\n", src, dest, ret);
695 return ret;
696 }
697
698 phasey_steps[COMP_0] = phasey_step;
699 phasey_steps[COMP_3] = phasey_step;
700 phasey_steps[COMP_1_2] = phasey_step / info->vsub;
701
702 return 0;
703 }
704
get_scale_config(const struct mdp_format * format,uint32_t src,uint32_t dst,bool horz)705 static uint32_t get_scale_config(const struct mdp_format *format,
706 uint32_t src, uint32_t dst, bool horz)
707 {
708 const struct drm_format_info *info = drm_format_info(format->base.pixel_format);
709 bool scaling = format->is_yuv ? true : (src != dst);
710 uint32_t sub;
711 uint32_t ya_filter, uv_filter;
712 bool yuv = format->is_yuv;
713
714 if (!scaling)
715 return 0;
716
717 if (yuv) {
718 sub = horz ? info->hsub : info->vsub;
719 uv_filter = ((src / sub) <= dst) ?
720 SCALE_FILTER_BIL : SCALE_FILTER_PCMN;
721 }
722 ya_filter = (src <= dst) ? SCALE_FILTER_BIL : SCALE_FILTER_PCMN;
723
724 if (horz)
725 return MDP5_PIPE_SCALE_CONFIG_SCALEX_EN |
726 MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0(ya_filter) |
727 MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3(ya_filter) |
728 COND(yuv, MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2(uv_filter));
729 else
730 return MDP5_PIPE_SCALE_CONFIG_SCALEY_EN |
731 MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0(ya_filter) |
732 MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3(ya_filter) |
733 COND(yuv, MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2(uv_filter));
734 }
735
calc_pixel_ext(const struct mdp_format * format,uint32_t src,uint32_t dst,uint32_t phase_step[2],int pix_ext_edge1[COMP_MAX],int pix_ext_edge2[COMP_MAX],bool horz)736 static void calc_pixel_ext(const struct mdp_format *format,
737 uint32_t src, uint32_t dst, uint32_t phase_step[2],
738 int pix_ext_edge1[COMP_MAX], int pix_ext_edge2[COMP_MAX],
739 bool horz)
740 {
741 bool scaling = format->is_yuv ? true : (src != dst);
742 int i;
743
744 /*
745 * Note:
746 * We assume here that:
747 * 1. PCMN filter is used for downscale
748 * 2. bilinear filter is used for upscale
749 * 3. we are in a single pipe configuration
750 */
751
752 for (i = 0; i < COMP_MAX; i++) {
753 pix_ext_edge1[i] = 0;
754 pix_ext_edge2[i] = scaling ? 1 : 0;
755 }
756 }
757
mdp5_write_pixel_ext(struct mdp5_kms * mdp5_kms,enum mdp5_pipe pipe,const struct mdp_format * format,uint32_t src_w,int pe_left[COMP_MAX],int pe_right[COMP_MAX],uint32_t src_h,int pe_top[COMP_MAX],int pe_bottom[COMP_MAX])758 static void mdp5_write_pixel_ext(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe,
759 const struct mdp_format *format,
760 uint32_t src_w, int pe_left[COMP_MAX], int pe_right[COMP_MAX],
761 uint32_t src_h, int pe_top[COMP_MAX], int pe_bottom[COMP_MAX])
762 {
763 const struct drm_format_info *info = drm_format_info(format->base.pixel_format);
764 uint32_t lr, tb, req;
765 int i;
766
767 for (i = 0; i < COMP_MAX; i++) {
768 uint32_t roi_w = src_w;
769 uint32_t roi_h = src_h;
770
771 if (format->is_yuv && i == COMP_1_2) {
772 roi_w /= info->hsub;
773 roi_h /= info->vsub;
774 }
775
776 lr = (pe_left[i] >= 0) ?
777 MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT(pe_left[i]) :
778 MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF(pe_left[i]);
779
780 lr |= (pe_right[i] >= 0) ?
781 MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT(pe_right[i]) :
782 MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF(pe_right[i]);
783
784 tb = (pe_top[i] >= 0) ?
785 MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT(pe_top[i]) :
786 MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF(pe_top[i]);
787
788 tb |= (pe_bottom[i] >= 0) ?
789 MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT(pe_bottom[i]) :
790 MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF(pe_bottom[i]);
791
792 req = MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT(roi_w +
793 pe_left[i] + pe_right[i]);
794
795 req |= MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM(roi_h +
796 pe_top[i] + pe_bottom[i]);
797
798 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SW_PIX_EXT_LR(pipe, i), lr);
799 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SW_PIX_EXT_TB(pipe, i), tb);
800 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS(pipe, i), req);
801
802 DBG("comp-%d (L/R): rpt=%d/%d, ovf=%d/%d, req=%d", i,
803 FIELD(lr, MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT),
804 FIELD(lr, MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT),
805 FIELD(lr, MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF),
806 FIELD(lr, MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF),
807 FIELD(req, MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT));
808
809 DBG("comp-%d (T/B): rpt=%d/%d, ovf=%d/%d, req=%d", i,
810 FIELD(tb, MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT),
811 FIELD(tb, MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT),
812 FIELD(tb, MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF),
813 FIELD(tb, MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF),
814 FIELD(req, MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM));
815 }
816 }
817
818 struct pixel_ext {
819 int left[COMP_MAX];
820 int right[COMP_MAX];
821 int top[COMP_MAX];
822 int bottom[COMP_MAX];
823 };
824
825 struct phase_step {
826 u32 x[COMP_MAX];
827 u32 y[COMP_MAX];
828 };
829
mdp5_hwpipe_mode_set(struct mdp5_kms * mdp5_kms,struct mdp5_hw_pipe * hwpipe,struct drm_framebuffer * fb,struct phase_step * step,struct pixel_ext * pe,u32 scale_config,u32 hdecm,u32 vdecm,bool hflip,bool vflip,int crtc_x,int crtc_y,unsigned int crtc_w,unsigned int crtc_h,u32 src_img_w,u32 src_img_h,u32 src_x,u32 src_y,u32 src_w,u32 src_h)830 static void mdp5_hwpipe_mode_set(struct mdp5_kms *mdp5_kms,
831 struct mdp5_hw_pipe *hwpipe,
832 struct drm_framebuffer *fb,
833 struct phase_step *step,
834 struct pixel_ext *pe,
835 u32 scale_config, u32 hdecm, u32 vdecm,
836 bool hflip, bool vflip,
837 int crtc_x, int crtc_y,
838 unsigned int crtc_w, unsigned int crtc_h,
839 u32 src_img_w, u32 src_img_h,
840 u32 src_x, u32 src_y,
841 u32 src_w, u32 src_h)
842 {
843 enum mdp5_pipe pipe = hwpipe->pipe;
844 bool has_pe = hwpipe->caps & MDP_PIPE_CAP_SW_PIX_EXT;
845 const struct mdp_format *format =
846 to_mdp_format(msm_framebuffer_format(fb));
847
848 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_IMG_SIZE(pipe),
849 MDP5_PIPE_SRC_IMG_SIZE_WIDTH(src_img_w) |
850 MDP5_PIPE_SRC_IMG_SIZE_HEIGHT(src_img_h));
851
852 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_SIZE(pipe),
853 MDP5_PIPE_SRC_SIZE_WIDTH(src_w) |
854 MDP5_PIPE_SRC_SIZE_HEIGHT(src_h));
855
856 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_XY(pipe),
857 MDP5_PIPE_SRC_XY_X(src_x) |
858 MDP5_PIPE_SRC_XY_Y(src_y));
859
860 mdp5_write(mdp5_kms, REG_MDP5_PIPE_OUT_SIZE(pipe),
861 MDP5_PIPE_OUT_SIZE_WIDTH(crtc_w) |
862 MDP5_PIPE_OUT_SIZE_HEIGHT(crtc_h));
863
864 mdp5_write(mdp5_kms, REG_MDP5_PIPE_OUT_XY(pipe),
865 MDP5_PIPE_OUT_XY_X(crtc_x) |
866 MDP5_PIPE_OUT_XY_Y(crtc_y));
867
868 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_FORMAT(pipe),
869 MDP5_PIPE_SRC_FORMAT_A_BPC(format->bpc_a) |
870 MDP5_PIPE_SRC_FORMAT_R_BPC(format->bpc_r) |
871 MDP5_PIPE_SRC_FORMAT_G_BPC(format->bpc_g) |
872 MDP5_PIPE_SRC_FORMAT_B_BPC(format->bpc_b) |
873 COND(format->alpha_enable, MDP5_PIPE_SRC_FORMAT_ALPHA_ENABLE) |
874 MDP5_PIPE_SRC_FORMAT_CPP(format->cpp - 1) |
875 MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT(format->unpack_count - 1) |
876 COND(format->unpack_tight, MDP5_PIPE_SRC_FORMAT_UNPACK_TIGHT) |
877 MDP5_PIPE_SRC_FORMAT_FETCH_TYPE(format->fetch_type) |
878 MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP(format->chroma_sample));
879
880 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_UNPACK(pipe),
881 MDP5_PIPE_SRC_UNPACK_ELEM0(format->unpack[0]) |
882 MDP5_PIPE_SRC_UNPACK_ELEM1(format->unpack[1]) |
883 MDP5_PIPE_SRC_UNPACK_ELEM2(format->unpack[2]) |
884 MDP5_PIPE_SRC_UNPACK_ELEM3(format->unpack[3]));
885
886 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_OP_MODE(pipe),
887 (hflip ? MDP5_PIPE_SRC_OP_MODE_FLIP_LR : 0) |
888 (vflip ? MDP5_PIPE_SRC_OP_MODE_FLIP_UD : 0) |
889 COND(has_pe, MDP5_PIPE_SRC_OP_MODE_SW_PIX_EXT_OVERRIDE) |
890 MDP5_PIPE_SRC_OP_MODE_BWC(BWC_LOSSLESS));
891
892 /* not using secure mode: */
893 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_ADDR_SW_STATUS(pipe), 0);
894
895 if (hwpipe->caps & MDP_PIPE_CAP_SW_PIX_EXT)
896 mdp5_write_pixel_ext(mdp5_kms, pipe, format,
897 src_w, pe->left, pe->right,
898 src_h, pe->top, pe->bottom);
899
900 if (hwpipe->caps & MDP_PIPE_CAP_SCALE) {
901 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_PHASE_STEP_X(pipe),
902 step->x[COMP_0]);
903 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_PHASE_STEP_Y(pipe),
904 step->y[COMP_0]);
905 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_X(pipe),
906 step->x[COMP_1_2]);
907 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_Y(pipe),
908 step->y[COMP_1_2]);
909 mdp5_write(mdp5_kms, REG_MDP5_PIPE_DECIMATION(pipe),
910 MDP5_PIPE_DECIMATION_VERT(vdecm) |
911 MDP5_PIPE_DECIMATION_HORZ(hdecm));
912 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CONFIG(pipe),
913 scale_config);
914 }
915
916 if (hwpipe->caps & MDP_PIPE_CAP_CSC) {
917 if (MDP_FORMAT_IS_YUV(format))
918 csc_enable(mdp5_kms, pipe,
919 mdp_get_default_csc_cfg(CSC_YUV2RGB));
920 else
921 csc_disable(mdp5_kms, pipe);
922 }
923
924 set_scanout_locked(mdp5_kms, pipe, fb);
925 }
926
mdp5_plane_mode_set(struct drm_plane * plane,struct drm_crtc * crtc,struct drm_framebuffer * fb,struct drm_rect * src,struct drm_rect * dest)927 static int mdp5_plane_mode_set(struct drm_plane *plane,
928 struct drm_crtc *crtc, struct drm_framebuffer *fb,
929 struct drm_rect *src, struct drm_rect *dest)
930 {
931 struct drm_plane_state *pstate = plane->state;
932 struct mdp5_hw_pipe *hwpipe = to_mdp5_plane_state(pstate)->hwpipe;
933 struct mdp5_kms *mdp5_kms = get_kms(plane);
934 enum mdp5_pipe pipe = hwpipe->pipe;
935 struct mdp5_hw_pipe *right_hwpipe;
936 const struct mdp_format *format;
937 uint32_t nplanes, config = 0;
938 struct phase_step step = { { 0 } };
939 struct pixel_ext pe = { { 0 } };
940 uint32_t hdecm = 0, vdecm = 0;
941 uint32_t pix_format;
942 unsigned int rotation;
943 bool vflip, hflip;
944 int crtc_x, crtc_y;
945 unsigned int crtc_w, crtc_h;
946 uint32_t src_x, src_y;
947 uint32_t src_w, src_h;
948 uint32_t src_img_w, src_img_h;
949 int ret;
950
951 nplanes = fb->format->num_planes;
952
953 /* bad formats should already be rejected: */
954 if (WARN_ON(nplanes > pipe2nclients(pipe)))
955 return -EINVAL;
956
957 format = to_mdp_format(msm_framebuffer_format(fb));
958 pix_format = format->base.pixel_format;
959
960 src_x = src->x1;
961 src_y = src->y1;
962 src_w = drm_rect_width(src);
963 src_h = drm_rect_height(src);
964
965 crtc_x = dest->x1;
966 crtc_y = dest->y1;
967 crtc_w = drm_rect_width(dest);
968 crtc_h = drm_rect_height(dest);
969
970 /* src values are in Q16 fixed point, convert to integer: */
971 src_x = src_x >> 16;
972 src_y = src_y >> 16;
973 src_w = src_w >> 16;
974 src_h = src_h >> 16;
975
976 src_img_w = min(fb->width, src_w);
977 src_img_h = min(fb->height, src_h);
978
979 DBG("%s: FB[%u] %u,%u,%u,%u -> CRTC[%u] %d,%d,%u,%u", plane->name,
980 fb->base.id, src_x, src_y, src_w, src_h,
981 crtc->base.id, crtc_x, crtc_y, crtc_w, crtc_h);
982
983 right_hwpipe = to_mdp5_plane_state(pstate)->r_hwpipe;
984 if (right_hwpipe) {
985 /*
986 * if the plane comprises of 2 hw pipes, assume that the width
987 * is split equally across them. The only parameters that varies
988 * between the 2 pipes are src_x and crtc_x
989 */
990 crtc_w /= 2;
991 src_w /= 2;
992 src_img_w /= 2;
993 }
994
995 ret = calc_scalex_steps(plane, pix_format, src_w, crtc_w, step.x);
996 if (ret)
997 return ret;
998
999 ret = calc_scaley_steps(plane, pix_format, src_h, crtc_h, step.y);
1000 if (ret)
1001 return ret;
1002
1003 if (hwpipe->caps & MDP_PIPE_CAP_SW_PIX_EXT) {
1004 calc_pixel_ext(format, src_w, crtc_w, step.x,
1005 pe.left, pe.right, true);
1006 calc_pixel_ext(format, src_h, crtc_h, step.y,
1007 pe.top, pe.bottom, false);
1008 }
1009
1010 /* TODO calc hdecm, vdecm */
1011
1012 /* SCALE is used to both scale and up-sample chroma components */
1013 config |= get_scale_config(format, src_w, crtc_w, true);
1014 config |= get_scale_config(format, src_h, crtc_h, false);
1015 DBG("scale config = %x", config);
1016
1017 rotation = drm_rotation_simplify(pstate->rotation,
1018 DRM_MODE_ROTATE_0 |
1019 DRM_MODE_REFLECT_X |
1020 DRM_MODE_REFLECT_Y);
1021 hflip = !!(rotation & DRM_MODE_REFLECT_X);
1022 vflip = !!(rotation & DRM_MODE_REFLECT_Y);
1023
1024 mdp5_hwpipe_mode_set(mdp5_kms, hwpipe, fb, &step, &pe,
1025 config, hdecm, vdecm, hflip, vflip,
1026 crtc_x, crtc_y, crtc_w, crtc_h,
1027 src_img_w, src_img_h,
1028 src_x, src_y, src_w, src_h);
1029 if (right_hwpipe)
1030 mdp5_hwpipe_mode_set(mdp5_kms, right_hwpipe, fb, &step, &pe,
1031 config, hdecm, vdecm, hflip, vflip,
1032 crtc_x + crtc_w, crtc_y, crtc_w, crtc_h,
1033 src_img_w, src_img_h,
1034 src_x + src_w, src_y, src_w, src_h);
1035
1036 return ret;
1037 }
1038
1039 /*
1040 * Use this func and the one below only after the atomic state has been
1041 * successfully swapped
1042 */
mdp5_plane_pipe(struct drm_plane * plane)1043 enum mdp5_pipe mdp5_plane_pipe(struct drm_plane *plane)
1044 {
1045 struct mdp5_plane_state *pstate = to_mdp5_plane_state(plane->state);
1046
1047 if (WARN_ON(!pstate->hwpipe))
1048 return SSPP_NONE;
1049
1050 return pstate->hwpipe->pipe;
1051 }
1052
mdp5_plane_right_pipe(struct drm_plane * plane)1053 enum mdp5_pipe mdp5_plane_right_pipe(struct drm_plane *plane)
1054 {
1055 struct mdp5_plane_state *pstate = to_mdp5_plane_state(plane->state);
1056
1057 if (!pstate->r_hwpipe)
1058 return SSPP_NONE;
1059
1060 return pstate->r_hwpipe->pipe;
1061 }
1062
mdp5_plane_get_flush(struct drm_plane * plane)1063 uint32_t mdp5_plane_get_flush(struct drm_plane *plane)
1064 {
1065 struct mdp5_plane_state *pstate = to_mdp5_plane_state(plane->state);
1066 u32 mask;
1067
1068 if (WARN_ON(!pstate->hwpipe))
1069 return 0;
1070
1071 mask = pstate->hwpipe->flush_mask;
1072
1073 if (pstate->r_hwpipe)
1074 mask |= pstate->r_hwpipe->flush_mask;
1075
1076 return mask;
1077 }
1078
1079 /* initialize plane */
mdp5_plane_init(struct drm_device * dev,enum drm_plane_type type)1080 struct drm_plane *mdp5_plane_init(struct drm_device *dev,
1081 enum drm_plane_type type)
1082 {
1083 struct drm_plane *plane = NULL;
1084 struct mdp5_plane *mdp5_plane;
1085 int ret;
1086
1087 mdp5_plane = kzalloc(sizeof(*mdp5_plane), GFP_KERNEL);
1088 if (!mdp5_plane) {
1089 ret = -ENOMEM;
1090 goto fail;
1091 }
1092
1093 plane = &mdp5_plane->base;
1094
1095 mdp5_plane->nformats = mdp_get_formats(mdp5_plane->formats,
1096 ARRAY_SIZE(mdp5_plane->formats), false);
1097
1098 ret = drm_universal_plane_init(dev, plane, 0xff, &mdp5_plane_funcs,
1099 mdp5_plane->formats, mdp5_plane->nformats,
1100 NULL, type, NULL);
1101 if (ret)
1102 goto fail;
1103
1104 drm_plane_helper_add(plane, &mdp5_plane_helper_funcs);
1105
1106 mdp5_plane_install_properties(plane, &plane->base);
1107
1108 drm_plane_enable_fb_damage_clips(plane);
1109
1110 return plane;
1111
1112 fail:
1113 if (plane)
1114 mdp5_plane_destroy(plane);
1115
1116 return ERR_PTR(ret);
1117 }
1118