1 /*
2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include "en.h"
34 #include "en/port.h"
35 #include "en/xsk/pool.h"
36 #include "lib/clock.h"
37
mlx5e_ethtool_get_drvinfo(struct mlx5e_priv * priv,struct ethtool_drvinfo * drvinfo)38 void mlx5e_ethtool_get_drvinfo(struct mlx5e_priv *priv,
39 struct ethtool_drvinfo *drvinfo)
40 {
41 struct mlx5_core_dev *mdev = priv->mdev;
42
43 strlcpy(drvinfo->driver, KBUILD_MODNAME, sizeof(drvinfo->driver));
44 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
45 "%d.%d.%04d (%.16s)",
46 fw_rev_maj(mdev), fw_rev_min(mdev), fw_rev_sub(mdev),
47 mdev->board_id);
48 strlcpy(drvinfo->bus_info, dev_name(mdev->device),
49 sizeof(drvinfo->bus_info));
50 }
51
mlx5e_get_drvinfo(struct net_device * dev,struct ethtool_drvinfo * drvinfo)52 static void mlx5e_get_drvinfo(struct net_device *dev,
53 struct ethtool_drvinfo *drvinfo)
54 {
55 struct mlx5e_priv *priv = netdev_priv(dev);
56
57 mlx5e_ethtool_get_drvinfo(priv, drvinfo);
58 }
59
60 struct ptys2ethtool_config {
61 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported);
62 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertised);
63 };
64
65 static
66 struct ptys2ethtool_config ptys2legacy_ethtool_table[MLX5E_LINK_MODES_NUMBER];
67 static
68 struct ptys2ethtool_config ptys2ext_ethtool_table[MLX5E_EXT_LINK_MODES_NUMBER];
69
70 #define MLX5_BUILD_PTYS2ETHTOOL_CONFIG(reg_, table, ...) \
71 ({ \
72 struct ptys2ethtool_config *cfg; \
73 const unsigned int modes[] = { __VA_ARGS__ }; \
74 unsigned int i, bit, idx; \
75 cfg = &ptys2##table##_ethtool_table[reg_]; \
76 bitmap_zero(cfg->supported, \
77 __ETHTOOL_LINK_MODE_MASK_NBITS); \
78 bitmap_zero(cfg->advertised, \
79 __ETHTOOL_LINK_MODE_MASK_NBITS); \
80 for (i = 0 ; i < ARRAY_SIZE(modes) ; ++i) { \
81 bit = modes[i] % 64; \
82 idx = modes[i] / 64; \
83 __set_bit(bit, &cfg->supported[idx]); \
84 __set_bit(bit, &cfg->advertised[idx]); \
85 } \
86 })
87
mlx5e_build_ptys2ethtool_map(void)88 void mlx5e_build_ptys2ethtool_map(void)
89 {
90 memset(ptys2legacy_ethtool_table, 0, sizeof(ptys2legacy_ethtool_table));
91 memset(ptys2ext_ethtool_table, 0, sizeof(ptys2ext_ethtool_table));
92 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_CX_SGMII, legacy,
93 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT);
94 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_KX, legacy,
95 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT);
96 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_CX4, legacy,
97 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT);
98 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_KX4, legacy,
99 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT);
100 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_KR, legacy,
101 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
102 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_20GBASE_KR2, legacy,
103 ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT);
104 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_CR4, legacy,
105 ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT);
106 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_KR4, legacy,
107 ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT);
108 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_56GBASE_R4, legacy,
109 ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT);
110 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_CR, legacy,
111 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
112 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_SR, legacy,
113 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
114 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_ER, legacy,
115 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
116 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_SR4, legacy,
117 ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT);
118 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_LR4, legacy,
119 ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT);
120 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_SR2, legacy,
121 ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT);
122 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_CR4, legacy,
123 ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT);
124 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_SR4, legacy,
125 ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT);
126 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_KR4, legacy,
127 ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT);
128 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_LR4, legacy,
129 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT);
130 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_T, legacy,
131 ETHTOOL_LINK_MODE_10000baseT_Full_BIT);
132 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_CR, legacy,
133 ETHTOOL_LINK_MODE_25000baseCR_Full_BIT);
134 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_KR, legacy,
135 ETHTOOL_LINK_MODE_25000baseKR_Full_BIT);
136 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_SR, legacy,
137 ETHTOOL_LINK_MODE_25000baseSR_Full_BIT);
138 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_CR2, legacy,
139 ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT);
140 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_KR2, legacy,
141 ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT);
142 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_SGMII_100M, ext,
143 ETHTOOL_LINK_MODE_100baseT_Full_BIT);
144 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_X_SGMII, ext,
145 ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
146 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
147 ETHTOOL_LINK_MODE_1000baseX_Full_BIT);
148 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_5GBASE_R, ext,
149 ETHTOOL_LINK_MODE_5000baseT_Full_BIT);
150 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_XFI_XAUI_1, ext,
151 ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
152 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
153 ETHTOOL_LINK_MODE_10000baseR_FEC_BIT,
154 ETHTOOL_LINK_MODE_10000baseCR_Full_BIT,
155 ETHTOOL_LINK_MODE_10000baseSR_Full_BIT,
156 ETHTOOL_LINK_MODE_10000baseLR_Full_BIT,
157 ETHTOOL_LINK_MODE_10000baseER_Full_BIT);
158 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_XLAUI_4_XLPPI_4, ext,
159 ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
160 ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
161 ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
162 ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT);
163 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GAUI_1_25GBASE_CR_KR, ext,
164 ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
165 ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
166 ETHTOOL_LINK_MODE_25000baseSR_Full_BIT);
167 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2,
168 ext,
169 ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
170 ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
171 ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT);
172 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR, ext,
173 ETHTOOL_LINK_MODE_50000baseKR_Full_BIT,
174 ETHTOOL_LINK_MODE_50000baseSR_Full_BIT,
175 ETHTOOL_LINK_MODE_50000baseCR_Full_BIT,
176 ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT,
177 ETHTOOL_LINK_MODE_50000baseDR_Full_BIT);
178 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_CAUI_4_100GBASE_CR4_KR4, ext,
179 ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
180 ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
181 ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
182 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT);
183 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GAUI_2_100GBASE_CR2_KR2, ext,
184 ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT,
185 ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT,
186 ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT,
187 ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT,
188 ETHTOOL_LINK_MODE_100000baseDR2_Full_BIT);
189 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_200GAUI_4_200GBASE_CR4_KR4, ext,
190 ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT,
191 ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT,
192 ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT,
193 ETHTOOL_LINK_MODE_200000baseDR4_Full_BIT,
194 ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT);
195 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GAUI_1_100GBASE_CR_KR, ext,
196 ETHTOOL_LINK_MODE_100000baseKR_Full_BIT,
197 ETHTOOL_LINK_MODE_100000baseSR_Full_BIT,
198 ETHTOOL_LINK_MODE_100000baseLR_ER_FR_Full_BIT,
199 ETHTOOL_LINK_MODE_100000baseDR_Full_BIT,
200 ETHTOOL_LINK_MODE_100000baseCR_Full_BIT);
201 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_200GAUI_2_200GBASE_CR2_KR2, ext,
202 ETHTOOL_LINK_MODE_200000baseKR2_Full_BIT,
203 ETHTOOL_LINK_MODE_200000baseSR2_Full_BIT,
204 ETHTOOL_LINK_MODE_200000baseLR2_ER2_FR2_Full_BIT,
205 ETHTOOL_LINK_MODE_200000baseDR2_Full_BIT,
206 ETHTOOL_LINK_MODE_200000baseCR2_Full_BIT);
207 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_400GAUI_4_400GBASE_CR4_KR4, ext,
208 ETHTOOL_LINK_MODE_400000baseKR4_Full_BIT,
209 ETHTOOL_LINK_MODE_400000baseSR4_Full_BIT,
210 ETHTOOL_LINK_MODE_400000baseLR4_ER4_FR4_Full_BIT,
211 ETHTOOL_LINK_MODE_400000baseDR4_Full_BIT,
212 ETHTOOL_LINK_MODE_400000baseCR4_Full_BIT);
213 }
214
mlx5e_ethtool_get_speed_arr(struct mlx5_core_dev * mdev,struct ptys2ethtool_config ** arr,u32 * size)215 static void mlx5e_ethtool_get_speed_arr(struct mlx5_core_dev *mdev,
216 struct ptys2ethtool_config **arr,
217 u32 *size)
218 {
219 bool ext = mlx5e_ptys_ext_supported(mdev);
220
221 *arr = ext ? ptys2ext_ethtool_table : ptys2legacy_ethtool_table;
222 *size = ext ? ARRAY_SIZE(ptys2ext_ethtool_table) :
223 ARRAY_SIZE(ptys2legacy_ethtool_table);
224 }
225
226 typedef int (*mlx5e_pflag_handler)(struct net_device *netdev, bool enable);
227
228 struct pflag_desc {
229 char name[ETH_GSTRING_LEN];
230 mlx5e_pflag_handler handler;
231 };
232
233 static const struct pflag_desc mlx5e_priv_flags[MLX5E_NUM_PFLAGS];
234
mlx5e_ethtool_get_sset_count(struct mlx5e_priv * priv,int sset)235 int mlx5e_ethtool_get_sset_count(struct mlx5e_priv *priv, int sset)
236 {
237 switch (sset) {
238 case ETH_SS_STATS:
239 return mlx5e_stats_total_num(priv);
240 case ETH_SS_PRIV_FLAGS:
241 return MLX5E_NUM_PFLAGS;
242 case ETH_SS_TEST:
243 return mlx5e_self_test_num(priv);
244 default:
245 return -EOPNOTSUPP;
246 }
247 }
248
mlx5e_get_sset_count(struct net_device * dev,int sset)249 static int mlx5e_get_sset_count(struct net_device *dev, int sset)
250 {
251 struct mlx5e_priv *priv = netdev_priv(dev);
252
253 return mlx5e_ethtool_get_sset_count(priv, sset);
254 }
255
mlx5e_ethtool_get_strings(struct mlx5e_priv * priv,u32 stringset,u8 * data)256 void mlx5e_ethtool_get_strings(struct mlx5e_priv *priv, u32 stringset, u8 *data)
257 {
258 int i;
259
260 switch (stringset) {
261 case ETH_SS_PRIV_FLAGS:
262 for (i = 0; i < MLX5E_NUM_PFLAGS; i++)
263 strcpy(data + i * ETH_GSTRING_LEN,
264 mlx5e_priv_flags[i].name);
265 break;
266
267 case ETH_SS_TEST:
268 for (i = 0; i < mlx5e_self_test_num(priv); i++)
269 strcpy(data + i * ETH_GSTRING_LEN,
270 mlx5e_self_tests[i]);
271 break;
272
273 case ETH_SS_STATS:
274 mlx5e_stats_fill_strings(priv, data);
275 break;
276 }
277 }
278
mlx5e_get_strings(struct net_device * dev,u32 stringset,u8 * data)279 static void mlx5e_get_strings(struct net_device *dev, u32 stringset, u8 *data)
280 {
281 struct mlx5e_priv *priv = netdev_priv(dev);
282
283 mlx5e_ethtool_get_strings(priv, stringset, data);
284 }
285
mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv * priv,struct ethtool_stats * stats,u64 * data)286 void mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv *priv,
287 struct ethtool_stats *stats, u64 *data)
288 {
289 int idx = 0;
290
291 mutex_lock(&priv->state_lock);
292 mlx5e_stats_update(priv);
293 mutex_unlock(&priv->state_lock);
294
295 mlx5e_stats_fill(priv, data, idx);
296 }
297
mlx5e_get_ethtool_stats(struct net_device * dev,struct ethtool_stats * stats,u64 * data)298 static void mlx5e_get_ethtool_stats(struct net_device *dev,
299 struct ethtool_stats *stats,
300 u64 *data)
301 {
302 struct mlx5e_priv *priv = netdev_priv(dev);
303
304 mlx5e_ethtool_get_ethtool_stats(priv, stats, data);
305 }
306
mlx5e_ethtool_get_ringparam(struct mlx5e_priv * priv,struct ethtool_ringparam * param)307 void mlx5e_ethtool_get_ringparam(struct mlx5e_priv *priv,
308 struct ethtool_ringparam *param)
309 {
310 param->rx_max_pending = 1 << MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE;
311 param->tx_max_pending = 1 << MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE;
312 param->rx_pending = 1 << priv->channels.params.log_rq_mtu_frames;
313 param->tx_pending = 1 << priv->channels.params.log_sq_size;
314 }
315
mlx5e_get_ringparam(struct net_device * dev,struct ethtool_ringparam * param)316 static void mlx5e_get_ringparam(struct net_device *dev,
317 struct ethtool_ringparam *param)
318 {
319 struct mlx5e_priv *priv = netdev_priv(dev);
320
321 mlx5e_ethtool_get_ringparam(priv, param);
322 }
323
mlx5e_ethtool_set_ringparam(struct mlx5e_priv * priv,struct ethtool_ringparam * param)324 int mlx5e_ethtool_set_ringparam(struct mlx5e_priv *priv,
325 struct ethtool_ringparam *param)
326 {
327 struct mlx5e_channels new_channels = {};
328 u8 log_rq_size;
329 u8 log_sq_size;
330 int err = 0;
331
332 if (param->rx_jumbo_pending) {
333 netdev_info(priv->netdev, "%s: rx_jumbo_pending not supported\n",
334 __func__);
335 return -EINVAL;
336 }
337 if (param->rx_mini_pending) {
338 netdev_info(priv->netdev, "%s: rx_mini_pending not supported\n",
339 __func__);
340 return -EINVAL;
341 }
342
343 if (param->rx_pending < (1 << MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE)) {
344 netdev_info(priv->netdev, "%s: rx_pending (%d) < min (%d)\n",
345 __func__, param->rx_pending,
346 1 << MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE);
347 return -EINVAL;
348 }
349
350 if (param->tx_pending < (1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE)) {
351 netdev_info(priv->netdev, "%s: tx_pending (%d) < min (%d)\n",
352 __func__, param->tx_pending,
353 1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE);
354 return -EINVAL;
355 }
356
357 log_rq_size = order_base_2(param->rx_pending);
358 log_sq_size = order_base_2(param->tx_pending);
359
360 if (log_rq_size == priv->channels.params.log_rq_mtu_frames &&
361 log_sq_size == priv->channels.params.log_sq_size)
362 return 0;
363
364 mutex_lock(&priv->state_lock);
365
366 new_channels.params = priv->channels.params;
367 new_channels.params.log_rq_mtu_frames = log_rq_size;
368 new_channels.params.log_sq_size = log_sq_size;
369
370 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
371 priv->channels.params = new_channels.params;
372 goto unlock;
373 }
374
375 err = mlx5e_safe_switch_channels(priv, &new_channels, NULL, NULL);
376
377 unlock:
378 mutex_unlock(&priv->state_lock);
379
380 return err;
381 }
382
mlx5e_set_ringparam(struct net_device * dev,struct ethtool_ringparam * param)383 static int mlx5e_set_ringparam(struct net_device *dev,
384 struct ethtool_ringparam *param)
385 {
386 struct mlx5e_priv *priv = netdev_priv(dev);
387
388 return mlx5e_ethtool_set_ringparam(priv, param);
389 }
390
mlx5e_ethtool_get_channels(struct mlx5e_priv * priv,struct ethtool_channels * ch)391 void mlx5e_ethtool_get_channels(struct mlx5e_priv *priv,
392 struct ethtool_channels *ch)
393 {
394 mutex_lock(&priv->state_lock);
395
396 ch->max_combined = priv->max_nch;
397 ch->combined_count = priv->channels.params.num_channels;
398 if (priv->xsk.refcnt) {
399 /* The upper half are XSK queues. */
400 ch->max_combined *= 2;
401 ch->combined_count *= 2;
402 }
403
404 mutex_unlock(&priv->state_lock);
405 }
406
mlx5e_get_channels(struct net_device * dev,struct ethtool_channels * ch)407 static void mlx5e_get_channels(struct net_device *dev,
408 struct ethtool_channels *ch)
409 {
410 struct mlx5e_priv *priv = netdev_priv(dev);
411
412 mlx5e_ethtool_get_channels(priv, ch);
413 }
414
mlx5e_ethtool_set_channels(struct mlx5e_priv * priv,struct ethtool_channels * ch)415 int mlx5e_ethtool_set_channels(struct mlx5e_priv *priv,
416 struct ethtool_channels *ch)
417 {
418 struct mlx5e_params *cur_params = &priv->channels.params;
419 unsigned int count = ch->combined_count;
420 struct mlx5e_channels new_channels = {};
421 bool arfs_enabled;
422 int err = 0;
423
424 if (!count) {
425 netdev_info(priv->netdev, "%s: combined_count=0 not supported\n",
426 __func__);
427 return -EINVAL;
428 }
429
430 if (cur_params->num_channels == count)
431 return 0;
432
433 mutex_lock(&priv->state_lock);
434
435 /* Don't allow changing the number of channels if there is an active
436 * XSK, because the numeration of the XSK and regular RQs will change.
437 */
438 if (priv->xsk.refcnt) {
439 err = -EINVAL;
440 netdev_err(priv->netdev, "%s: AF_XDP is active, cannot change the number of channels\n",
441 __func__);
442 goto out;
443 }
444
445 new_channels.params = *cur_params;
446 new_channels.params.num_channels = count;
447
448 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
449 struct mlx5e_params old_params;
450
451 old_params = *cur_params;
452 *cur_params = new_channels.params;
453 err = mlx5e_num_channels_changed(priv);
454 if (err)
455 *cur_params = old_params;
456
457 goto out;
458 }
459
460 arfs_enabled = priv->netdev->features & NETIF_F_NTUPLE;
461 if (arfs_enabled)
462 mlx5e_arfs_disable(priv);
463
464 /* Switch to new channels, set new parameters and close old ones */
465 err = mlx5e_safe_switch_channels(priv, &new_channels,
466 mlx5e_num_channels_changed_ctx, NULL);
467
468 if (arfs_enabled) {
469 int err2 = mlx5e_arfs_enable(priv);
470
471 if (err2)
472 netdev_err(priv->netdev, "%s: mlx5e_arfs_enable failed: %d\n",
473 __func__, err2);
474 }
475
476 out:
477 mutex_unlock(&priv->state_lock);
478
479 return err;
480 }
481
mlx5e_set_channels(struct net_device * dev,struct ethtool_channels * ch)482 static int mlx5e_set_channels(struct net_device *dev,
483 struct ethtool_channels *ch)
484 {
485 struct mlx5e_priv *priv = netdev_priv(dev);
486
487 return mlx5e_ethtool_set_channels(priv, ch);
488 }
489
mlx5e_ethtool_get_coalesce(struct mlx5e_priv * priv,struct ethtool_coalesce * coal)490 int mlx5e_ethtool_get_coalesce(struct mlx5e_priv *priv,
491 struct ethtool_coalesce *coal)
492 {
493 struct dim_cq_moder *rx_moder, *tx_moder;
494
495 if (!MLX5_CAP_GEN(priv->mdev, cq_moderation))
496 return -EOPNOTSUPP;
497
498 rx_moder = &priv->channels.params.rx_cq_moderation;
499 coal->rx_coalesce_usecs = rx_moder->usec;
500 coal->rx_max_coalesced_frames = rx_moder->pkts;
501 coal->use_adaptive_rx_coalesce = priv->channels.params.rx_dim_enabled;
502
503 tx_moder = &priv->channels.params.tx_cq_moderation;
504 coal->tx_coalesce_usecs = tx_moder->usec;
505 coal->tx_max_coalesced_frames = tx_moder->pkts;
506 coal->use_adaptive_tx_coalesce = priv->channels.params.tx_dim_enabled;
507
508 return 0;
509 }
510
mlx5e_get_coalesce(struct net_device * netdev,struct ethtool_coalesce * coal)511 static int mlx5e_get_coalesce(struct net_device *netdev,
512 struct ethtool_coalesce *coal)
513 {
514 struct mlx5e_priv *priv = netdev_priv(netdev);
515
516 return mlx5e_ethtool_get_coalesce(priv, coal);
517 }
518
519 #define MLX5E_MAX_COAL_TIME MLX5_MAX_CQ_PERIOD
520 #define MLX5E_MAX_COAL_FRAMES MLX5_MAX_CQ_COUNT
521
522 static void
mlx5e_set_priv_channels_tx_coalesce(struct mlx5e_priv * priv,struct ethtool_coalesce * coal)523 mlx5e_set_priv_channels_tx_coalesce(struct mlx5e_priv *priv, struct ethtool_coalesce *coal)
524 {
525 struct mlx5_core_dev *mdev = priv->mdev;
526 int tc;
527 int i;
528
529 for (i = 0; i < priv->channels.num; ++i) {
530 struct mlx5e_channel *c = priv->channels.c[i];
531
532 for (tc = 0; tc < c->num_tc; tc++) {
533 mlx5_core_modify_cq_moderation(mdev,
534 &c->sq[tc].cq.mcq,
535 coal->tx_coalesce_usecs,
536 coal->tx_max_coalesced_frames);
537 }
538 }
539 }
540
541 static void
mlx5e_set_priv_channels_rx_coalesce(struct mlx5e_priv * priv,struct ethtool_coalesce * coal)542 mlx5e_set_priv_channels_rx_coalesce(struct mlx5e_priv *priv, struct ethtool_coalesce *coal)
543 {
544 struct mlx5_core_dev *mdev = priv->mdev;
545 int i;
546
547 for (i = 0; i < priv->channels.num; ++i) {
548 struct mlx5e_channel *c = priv->channels.c[i];
549
550 mlx5_core_modify_cq_moderation(mdev, &c->rq.cq.mcq,
551 coal->rx_coalesce_usecs,
552 coal->rx_max_coalesced_frames);
553 }
554 }
555
mlx5e_ethtool_set_coalesce(struct mlx5e_priv * priv,struct ethtool_coalesce * coal)556 int mlx5e_ethtool_set_coalesce(struct mlx5e_priv *priv,
557 struct ethtool_coalesce *coal)
558 {
559 struct dim_cq_moder *rx_moder, *tx_moder;
560 struct mlx5_core_dev *mdev = priv->mdev;
561 struct mlx5e_channels new_channels = {};
562 bool reset_rx, reset_tx;
563 int err = 0;
564
565 if (!MLX5_CAP_GEN(mdev, cq_moderation))
566 return -EOPNOTSUPP;
567
568 if (coal->tx_coalesce_usecs > MLX5E_MAX_COAL_TIME ||
569 coal->rx_coalesce_usecs > MLX5E_MAX_COAL_TIME) {
570 netdev_info(priv->netdev, "%s: maximum coalesce time supported is %lu usecs\n",
571 __func__, MLX5E_MAX_COAL_TIME);
572 return -ERANGE;
573 }
574
575 if (coal->tx_max_coalesced_frames > MLX5E_MAX_COAL_FRAMES ||
576 coal->rx_max_coalesced_frames > MLX5E_MAX_COAL_FRAMES) {
577 netdev_info(priv->netdev, "%s: maximum coalesced frames supported is %lu\n",
578 __func__, MLX5E_MAX_COAL_FRAMES);
579 return -ERANGE;
580 }
581
582 mutex_lock(&priv->state_lock);
583 new_channels.params = priv->channels.params;
584
585 rx_moder = &new_channels.params.rx_cq_moderation;
586 rx_moder->usec = coal->rx_coalesce_usecs;
587 rx_moder->pkts = coal->rx_max_coalesced_frames;
588 new_channels.params.rx_dim_enabled = !!coal->use_adaptive_rx_coalesce;
589
590 tx_moder = &new_channels.params.tx_cq_moderation;
591 tx_moder->usec = coal->tx_coalesce_usecs;
592 tx_moder->pkts = coal->tx_max_coalesced_frames;
593 new_channels.params.tx_dim_enabled = !!coal->use_adaptive_tx_coalesce;
594
595 reset_rx = !!coal->use_adaptive_rx_coalesce != priv->channels.params.rx_dim_enabled;
596 reset_tx = !!coal->use_adaptive_tx_coalesce != priv->channels.params.tx_dim_enabled;
597
598 if (reset_rx) {
599 u8 mode = MLX5E_GET_PFLAG(&new_channels.params,
600 MLX5E_PFLAG_RX_CQE_BASED_MODER);
601
602 mlx5e_reset_rx_moderation(&new_channels.params, mode);
603 }
604 if (reset_tx) {
605 u8 mode = MLX5E_GET_PFLAG(&new_channels.params,
606 MLX5E_PFLAG_TX_CQE_BASED_MODER);
607
608 mlx5e_reset_tx_moderation(&new_channels.params, mode);
609 }
610
611 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
612 priv->channels.params = new_channels.params;
613 goto out;
614 }
615
616 if (!reset_rx && !reset_tx) {
617 if (!coal->use_adaptive_rx_coalesce)
618 mlx5e_set_priv_channels_rx_coalesce(priv, coal);
619 if (!coal->use_adaptive_tx_coalesce)
620 mlx5e_set_priv_channels_tx_coalesce(priv, coal);
621 priv->channels.params = new_channels.params;
622 goto out;
623 }
624
625 err = mlx5e_safe_switch_channels(priv, &new_channels, NULL, NULL);
626
627 out:
628 mutex_unlock(&priv->state_lock);
629 return err;
630 }
631
mlx5e_set_coalesce(struct net_device * netdev,struct ethtool_coalesce * coal)632 static int mlx5e_set_coalesce(struct net_device *netdev,
633 struct ethtool_coalesce *coal)
634 {
635 struct mlx5e_priv *priv = netdev_priv(netdev);
636
637 return mlx5e_ethtool_set_coalesce(priv, coal);
638 }
639
ptys2ethtool_supported_link(struct mlx5_core_dev * mdev,unsigned long * supported_modes,u32 eth_proto_cap)640 static void ptys2ethtool_supported_link(struct mlx5_core_dev *mdev,
641 unsigned long *supported_modes,
642 u32 eth_proto_cap)
643 {
644 unsigned long proto_cap = eth_proto_cap;
645 struct ptys2ethtool_config *table;
646 u32 max_size;
647 int proto;
648
649 mlx5e_ethtool_get_speed_arr(mdev, &table, &max_size);
650 for_each_set_bit(proto, &proto_cap, max_size)
651 bitmap_or(supported_modes, supported_modes,
652 table[proto].supported,
653 __ETHTOOL_LINK_MODE_MASK_NBITS);
654 }
655
ptys2ethtool_adver_link(unsigned long * advertising_modes,u32 eth_proto_cap,bool ext)656 static void ptys2ethtool_adver_link(unsigned long *advertising_modes,
657 u32 eth_proto_cap, bool ext)
658 {
659 unsigned long proto_cap = eth_proto_cap;
660 struct ptys2ethtool_config *table;
661 u32 max_size;
662 int proto;
663
664 table = ext ? ptys2ext_ethtool_table : ptys2legacy_ethtool_table;
665 max_size = ext ? ARRAY_SIZE(ptys2ext_ethtool_table) :
666 ARRAY_SIZE(ptys2legacy_ethtool_table);
667
668 for_each_set_bit(proto, &proto_cap, max_size)
669 bitmap_or(advertising_modes, advertising_modes,
670 table[proto].advertised,
671 __ETHTOOL_LINK_MODE_MASK_NBITS);
672 }
673
674 static const u32 pplm_fec_2_ethtool[] = {
675 [MLX5E_FEC_NOFEC] = ETHTOOL_FEC_OFF,
676 [MLX5E_FEC_FIRECODE] = ETHTOOL_FEC_BASER,
677 [MLX5E_FEC_RS_528_514] = ETHTOOL_FEC_RS,
678 [MLX5E_FEC_RS_544_514] = ETHTOOL_FEC_RS,
679 [MLX5E_FEC_LLRS_272_257_1] = ETHTOOL_FEC_LLRS,
680 };
681
pplm2ethtool_fec(u_long fec_mode,unsigned long size)682 static u32 pplm2ethtool_fec(u_long fec_mode, unsigned long size)
683 {
684 int mode = 0;
685
686 if (!fec_mode)
687 return ETHTOOL_FEC_AUTO;
688
689 mode = find_first_bit(&fec_mode, size);
690
691 if (mode < ARRAY_SIZE(pplm_fec_2_ethtool))
692 return pplm_fec_2_ethtool[mode];
693
694 return 0;
695 }
696
697 #define MLX5E_ADVERTISE_SUPPORTED_FEC(mlx5_fec, ethtool_fec) \
698 do { \
699 if (mlx5e_fec_in_caps(dev, 1 << (mlx5_fec))) \
700 __set_bit(ethtool_fec, \
701 link_ksettings->link_modes.supported);\
702 } while (0)
703
704 static const u32 pplm_fec_2_ethtool_linkmodes[] = {
705 [MLX5E_FEC_NOFEC] = ETHTOOL_LINK_MODE_FEC_NONE_BIT,
706 [MLX5E_FEC_FIRECODE] = ETHTOOL_LINK_MODE_FEC_BASER_BIT,
707 [MLX5E_FEC_RS_528_514] = ETHTOOL_LINK_MODE_FEC_RS_BIT,
708 [MLX5E_FEC_RS_544_514] = ETHTOOL_LINK_MODE_FEC_RS_BIT,
709 [MLX5E_FEC_LLRS_272_257_1] = ETHTOOL_LINK_MODE_FEC_LLRS_BIT,
710 };
711
get_fec_supported_advertised(struct mlx5_core_dev * dev,struct ethtool_link_ksettings * link_ksettings)712 static int get_fec_supported_advertised(struct mlx5_core_dev *dev,
713 struct ethtool_link_ksettings *link_ksettings)
714 {
715 unsigned long active_fec_long;
716 u32 active_fec;
717 u32 bitn;
718 int err;
719
720 err = mlx5e_get_fec_mode(dev, &active_fec, NULL);
721 if (err)
722 return (err == -EOPNOTSUPP) ? 0 : err;
723
724 MLX5E_ADVERTISE_SUPPORTED_FEC(MLX5E_FEC_NOFEC,
725 ETHTOOL_LINK_MODE_FEC_NONE_BIT);
726 MLX5E_ADVERTISE_SUPPORTED_FEC(MLX5E_FEC_FIRECODE,
727 ETHTOOL_LINK_MODE_FEC_BASER_BIT);
728 MLX5E_ADVERTISE_SUPPORTED_FEC(MLX5E_FEC_RS_528_514,
729 ETHTOOL_LINK_MODE_FEC_RS_BIT);
730 MLX5E_ADVERTISE_SUPPORTED_FEC(MLX5E_FEC_LLRS_272_257_1,
731 ETHTOOL_LINK_MODE_FEC_LLRS_BIT);
732
733 active_fec_long = active_fec;
734 /* active fec is a bit set, find out which bit is set and
735 * advertise the corresponding ethtool bit
736 */
737 bitn = find_first_bit(&active_fec_long, sizeof(active_fec_long) * BITS_PER_BYTE);
738 if (bitn < ARRAY_SIZE(pplm_fec_2_ethtool_linkmodes))
739 __set_bit(pplm_fec_2_ethtool_linkmodes[bitn],
740 link_ksettings->link_modes.advertising);
741
742 return 0;
743 }
744
ptys2ethtool_supported_advertised_port(struct mlx5_core_dev * mdev,struct ethtool_link_ksettings * link_ksettings,u32 eth_proto_cap,u8 connector_type)745 static void ptys2ethtool_supported_advertised_port(struct mlx5_core_dev *mdev,
746 struct ethtool_link_ksettings *link_ksettings,
747 u32 eth_proto_cap, u8 connector_type)
748 {
749 if (!MLX5_CAP_PCAM_FEATURE(mdev, ptys_connector_type)) {
750 if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_10GBASE_CR)
751 | MLX5E_PROT_MASK(MLX5E_10GBASE_SR)
752 | MLX5E_PROT_MASK(MLX5E_40GBASE_CR4)
753 | MLX5E_PROT_MASK(MLX5E_40GBASE_SR4)
754 | MLX5E_PROT_MASK(MLX5E_100GBASE_SR4)
755 | MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) {
756 ethtool_link_ksettings_add_link_mode(link_ksettings,
757 supported,
758 FIBRE);
759 ethtool_link_ksettings_add_link_mode(link_ksettings,
760 advertising,
761 FIBRE);
762 }
763
764 if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_100GBASE_KR4)
765 | MLX5E_PROT_MASK(MLX5E_40GBASE_KR4)
766 | MLX5E_PROT_MASK(MLX5E_10GBASE_KR)
767 | MLX5E_PROT_MASK(MLX5E_10GBASE_KX4)
768 | MLX5E_PROT_MASK(MLX5E_1000BASE_KX))) {
769 ethtool_link_ksettings_add_link_mode(link_ksettings,
770 supported,
771 Backplane);
772 ethtool_link_ksettings_add_link_mode(link_ksettings,
773 advertising,
774 Backplane);
775 }
776 return;
777 }
778
779 switch (connector_type) {
780 case MLX5E_PORT_TP:
781 ethtool_link_ksettings_add_link_mode(link_ksettings,
782 supported, TP);
783 ethtool_link_ksettings_add_link_mode(link_ksettings,
784 advertising, TP);
785 break;
786 case MLX5E_PORT_AUI:
787 ethtool_link_ksettings_add_link_mode(link_ksettings,
788 supported, AUI);
789 ethtool_link_ksettings_add_link_mode(link_ksettings,
790 advertising, AUI);
791 break;
792 case MLX5E_PORT_BNC:
793 ethtool_link_ksettings_add_link_mode(link_ksettings,
794 supported, BNC);
795 ethtool_link_ksettings_add_link_mode(link_ksettings,
796 advertising, BNC);
797 break;
798 case MLX5E_PORT_MII:
799 ethtool_link_ksettings_add_link_mode(link_ksettings,
800 supported, MII);
801 ethtool_link_ksettings_add_link_mode(link_ksettings,
802 advertising, MII);
803 break;
804 case MLX5E_PORT_FIBRE:
805 ethtool_link_ksettings_add_link_mode(link_ksettings,
806 supported, FIBRE);
807 ethtool_link_ksettings_add_link_mode(link_ksettings,
808 advertising, FIBRE);
809 break;
810 case MLX5E_PORT_DA:
811 ethtool_link_ksettings_add_link_mode(link_ksettings,
812 supported, Backplane);
813 ethtool_link_ksettings_add_link_mode(link_ksettings,
814 advertising, Backplane);
815 break;
816 case MLX5E_PORT_NONE:
817 case MLX5E_PORT_OTHER:
818 default:
819 break;
820 }
821 }
822
get_speed_duplex(struct net_device * netdev,u32 eth_proto_oper,bool force_legacy,u16 data_rate_oper,struct ethtool_link_ksettings * link_ksettings)823 static void get_speed_duplex(struct net_device *netdev,
824 u32 eth_proto_oper, bool force_legacy,
825 u16 data_rate_oper,
826 struct ethtool_link_ksettings *link_ksettings)
827 {
828 struct mlx5e_priv *priv = netdev_priv(netdev);
829 u32 speed = SPEED_UNKNOWN;
830 u8 duplex = DUPLEX_UNKNOWN;
831
832 if (!netif_carrier_ok(netdev))
833 goto out;
834
835 speed = mlx5e_port_ptys2speed(priv->mdev, eth_proto_oper, force_legacy);
836 if (!speed) {
837 if (data_rate_oper)
838 speed = 100 * data_rate_oper;
839 else
840 speed = SPEED_UNKNOWN;
841 goto out;
842 }
843
844 duplex = DUPLEX_FULL;
845
846 out:
847 link_ksettings->base.speed = speed;
848 link_ksettings->base.duplex = duplex;
849 }
850
get_supported(struct mlx5_core_dev * mdev,u32 eth_proto_cap,struct ethtool_link_ksettings * link_ksettings)851 static void get_supported(struct mlx5_core_dev *mdev, u32 eth_proto_cap,
852 struct ethtool_link_ksettings *link_ksettings)
853 {
854 unsigned long *supported = link_ksettings->link_modes.supported;
855 ptys2ethtool_supported_link(mdev, supported, eth_proto_cap);
856
857 ethtool_link_ksettings_add_link_mode(link_ksettings, supported, Pause);
858 }
859
get_advertising(u32 eth_proto_cap,u8 tx_pause,u8 rx_pause,struct ethtool_link_ksettings * link_ksettings,bool ext)860 static void get_advertising(u32 eth_proto_cap, u8 tx_pause, u8 rx_pause,
861 struct ethtool_link_ksettings *link_ksettings,
862 bool ext)
863 {
864 unsigned long *advertising = link_ksettings->link_modes.advertising;
865 ptys2ethtool_adver_link(advertising, eth_proto_cap, ext);
866
867 if (rx_pause)
868 ethtool_link_ksettings_add_link_mode(link_ksettings, advertising, Pause);
869 if (tx_pause ^ rx_pause)
870 ethtool_link_ksettings_add_link_mode(link_ksettings, advertising, Asym_Pause);
871 }
872
873 static int ptys2connector_type[MLX5E_CONNECTOR_TYPE_NUMBER] = {
874 [MLX5E_PORT_UNKNOWN] = PORT_OTHER,
875 [MLX5E_PORT_NONE] = PORT_NONE,
876 [MLX5E_PORT_TP] = PORT_TP,
877 [MLX5E_PORT_AUI] = PORT_AUI,
878 [MLX5E_PORT_BNC] = PORT_BNC,
879 [MLX5E_PORT_MII] = PORT_MII,
880 [MLX5E_PORT_FIBRE] = PORT_FIBRE,
881 [MLX5E_PORT_DA] = PORT_DA,
882 [MLX5E_PORT_OTHER] = PORT_OTHER,
883 };
884
get_connector_port(struct mlx5_core_dev * mdev,u32 eth_proto,u8 connector_type)885 static u8 get_connector_port(struct mlx5_core_dev *mdev, u32 eth_proto, u8 connector_type)
886 {
887 if (MLX5_CAP_PCAM_FEATURE(mdev, ptys_connector_type))
888 return ptys2connector_type[connector_type];
889
890 if (eth_proto &
891 (MLX5E_PROT_MASK(MLX5E_10GBASE_SR) |
892 MLX5E_PROT_MASK(MLX5E_40GBASE_SR4) |
893 MLX5E_PROT_MASK(MLX5E_100GBASE_SR4) |
894 MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) {
895 return PORT_FIBRE;
896 }
897
898 if (eth_proto &
899 (MLX5E_PROT_MASK(MLX5E_40GBASE_CR4) |
900 MLX5E_PROT_MASK(MLX5E_10GBASE_CR) |
901 MLX5E_PROT_MASK(MLX5E_100GBASE_CR4))) {
902 return PORT_DA;
903 }
904
905 if (eth_proto &
906 (MLX5E_PROT_MASK(MLX5E_10GBASE_KX4) |
907 MLX5E_PROT_MASK(MLX5E_10GBASE_KR) |
908 MLX5E_PROT_MASK(MLX5E_40GBASE_KR4) |
909 MLX5E_PROT_MASK(MLX5E_100GBASE_KR4))) {
910 return PORT_NONE;
911 }
912
913 return PORT_OTHER;
914 }
915
get_lp_advertising(struct mlx5_core_dev * mdev,u32 eth_proto_lp,struct ethtool_link_ksettings * link_ksettings)916 static void get_lp_advertising(struct mlx5_core_dev *mdev, u32 eth_proto_lp,
917 struct ethtool_link_ksettings *link_ksettings)
918 {
919 unsigned long *lp_advertising = link_ksettings->link_modes.lp_advertising;
920 bool ext = mlx5e_ptys_ext_supported(mdev);
921
922 ptys2ethtool_adver_link(lp_advertising, eth_proto_lp, ext);
923 }
924
mlx5e_ethtool_get_link_ksettings(struct mlx5e_priv * priv,struct ethtool_link_ksettings * link_ksettings)925 int mlx5e_ethtool_get_link_ksettings(struct mlx5e_priv *priv,
926 struct ethtool_link_ksettings *link_ksettings)
927 {
928 struct mlx5_core_dev *mdev = priv->mdev;
929 u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {};
930 u32 eth_proto_admin;
931 u8 an_disable_admin;
932 u16 data_rate_oper;
933 u32 eth_proto_oper;
934 u32 eth_proto_cap;
935 u8 connector_type;
936 u32 rx_pause = 0;
937 u32 tx_pause = 0;
938 u32 eth_proto_lp;
939 bool admin_ext;
940 u8 an_status;
941 bool ext;
942 int err;
943
944 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1);
945 if (err) {
946 netdev_err(priv->netdev, "%s: query port ptys failed: %d\n",
947 __func__, err);
948 goto err_query_regs;
949 }
950 ext = !!MLX5_GET_ETH_PROTO(ptys_reg, out, true, eth_proto_capability);
951 eth_proto_cap = MLX5_GET_ETH_PROTO(ptys_reg, out, ext,
952 eth_proto_capability);
953 eth_proto_admin = MLX5_GET_ETH_PROTO(ptys_reg, out, ext,
954 eth_proto_admin);
955 /* Fields: eth_proto_admin and ext_eth_proto_admin are
956 * mutually exclusive. Hence try reading legacy advertising
957 * when extended advertising is zero.
958 * admin_ext indicates which proto_admin (ext vs. legacy)
959 * should be read and interpreted
960 */
961 admin_ext = ext;
962 if (ext && !eth_proto_admin) {
963 eth_proto_admin = MLX5_GET_ETH_PROTO(ptys_reg, out, false,
964 eth_proto_admin);
965 admin_ext = false;
966 }
967
968 eth_proto_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, admin_ext,
969 eth_proto_oper);
970 eth_proto_lp = MLX5_GET(ptys_reg, out, eth_proto_lp_advertise);
971 an_disable_admin = MLX5_GET(ptys_reg, out, an_disable_admin);
972 an_status = MLX5_GET(ptys_reg, out, an_status);
973 connector_type = MLX5_GET(ptys_reg, out, connector_type);
974 data_rate_oper = MLX5_GET(ptys_reg, out, data_rate_oper);
975
976 mlx5_query_port_pause(mdev, &rx_pause, &tx_pause);
977
978 ethtool_link_ksettings_zero_link_mode(link_ksettings, supported);
979 ethtool_link_ksettings_zero_link_mode(link_ksettings, advertising);
980
981 get_supported(mdev, eth_proto_cap, link_ksettings);
982 get_advertising(eth_proto_admin, tx_pause, rx_pause, link_ksettings,
983 admin_ext);
984 get_speed_duplex(priv->netdev, eth_proto_oper, !admin_ext,
985 data_rate_oper, link_ksettings);
986
987 eth_proto_oper = eth_proto_oper ? eth_proto_oper : eth_proto_cap;
988 connector_type = connector_type < MLX5E_CONNECTOR_TYPE_NUMBER ?
989 connector_type : MLX5E_PORT_UNKNOWN;
990 link_ksettings->base.port = get_connector_port(mdev, eth_proto_oper, connector_type);
991 ptys2ethtool_supported_advertised_port(mdev, link_ksettings, eth_proto_admin,
992 connector_type);
993 get_lp_advertising(mdev, eth_proto_lp, link_ksettings);
994
995 if (an_status == MLX5_AN_COMPLETE)
996 ethtool_link_ksettings_add_link_mode(link_ksettings,
997 lp_advertising, Autoneg);
998
999 link_ksettings->base.autoneg = an_disable_admin ? AUTONEG_DISABLE :
1000 AUTONEG_ENABLE;
1001 ethtool_link_ksettings_add_link_mode(link_ksettings, supported,
1002 Autoneg);
1003
1004 err = get_fec_supported_advertised(mdev, link_ksettings);
1005 if (err) {
1006 netdev_dbg(priv->netdev, "%s: FEC caps query failed: %d\n",
1007 __func__, err);
1008 err = 0; /* don't fail caps query because of FEC error */
1009 }
1010
1011 if (!an_disable_admin)
1012 ethtool_link_ksettings_add_link_mode(link_ksettings,
1013 advertising, Autoneg);
1014
1015 err_query_regs:
1016 return err;
1017 }
1018
mlx5e_get_link_ksettings(struct net_device * netdev,struct ethtool_link_ksettings * link_ksettings)1019 static int mlx5e_get_link_ksettings(struct net_device *netdev,
1020 struct ethtool_link_ksettings *link_ksettings)
1021 {
1022 struct mlx5e_priv *priv = netdev_priv(netdev);
1023
1024 return mlx5e_ethtool_get_link_ksettings(priv, link_ksettings);
1025 }
1026
mlx5e_speed_validate(struct net_device * netdev,bool ext,const unsigned long link_modes,u8 autoneg)1027 static int mlx5e_speed_validate(struct net_device *netdev, bool ext,
1028 const unsigned long link_modes, u8 autoneg)
1029 {
1030 /* Extended link-mode has no speed limitations. */
1031 if (ext)
1032 return 0;
1033
1034 if ((link_modes & MLX5E_PROT_MASK(MLX5E_56GBASE_R4)) &&
1035 autoneg != AUTONEG_ENABLE) {
1036 netdev_err(netdev, "%s: 56G link speed requires autoneg enabled\n",
1037 __func__);
1038 return -EINVAL;
1039 }
1040 return 0;
1041 }
1042
mlx5e_ethtool2ptys_adver_link(const unsigned long * link_modes)1043 static u32 mlx5e_ethtool2ptys_adver_link(const unsigned long *link_modes)
1044 {
1045 u32 i, ptys_modes = 0;
1046
1047 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
1048 if (*ptys2legacy_ethtool_table[i].advertised == 0)
1049 continue;
1050 if (bitmap_intersects(ptys2legacy_ethtool_table[i].advertised,
1051 link_modes,
1052 __ETHTOOL_LINK_MODE_MASK_NBITS))
1053 ptys_modes |= MLX5E_PROT_MASK(i);
1054 }
1055
1056 return ptys_modes;
1057 }
1058
mlx5e_ethtool2ptys_ext_adver_link(const unsigned long * link_modes)1059 static u32 mlx5e_ethtool2ptys_ext_adver_link(const unsigned long *link_modes)
1060 {
1061 u32 i, ptys_modes = 0;
1062 unsigned long modes[2];
1063
1064 for (i = 0; i < MLX5E_EXT_LINK_MODES_NUMBER; ++i) {
1065 if (ptys2ext_ethtool_table[i].advertised[0] == 0 &&
1066 ptys2ext_ethtool_table[i].advertised[1] == 0)
1067 continue;
1068 memset(modes, 0, sizeof(modes));
1069 bitmap_and(modes, ptys2ext_ethtool_table[i].advertised,
1070 link_modes, __ETHTOOL_LINK_MODE_MASK_NBITS);
1071
1072 if (modes[0] == ptys2ext_ethtool_table[i].advertised[0] &&
1073 modes[1] == ptys2ext_ethtool_table[i].advertised[1])
1074 ptys_modes |= MLX5E_PROT_MASK(i);
1075 }
1076 return ptys_modes;
1077 }
1078
ext_link_mode_requested(const unsigned long * adver)1079 static bool ext_link_mode_requested(const unsigned long *adver)
1080 {
1081 #define MLX5E_MIN_PTYS_EXT_LINK_MODE_BIT ETHTOOL_LINK_MODE_50000baseKR_Full_BIT
1082 int size = __ETHTOOL_LINK_MODE_MASK_NBITS - MLX5E_MIN_PTYS_EXT_LINK_MODE_BIT;
1083 __ETHTOOL_DECLARE_LINK_MODE_MASK(modes) = {0,};
1084
1085 bitmap_set(modes, MLX5E_MIN_PTYS_EXT_LINK_MODE_BIT, size);
1086 return bitmap_intersects(modes, adver, __ETHTOOL_LINK_MODE_MASK_NBITS);
1087 }
1088
ext_requested(u8 autoneg,const unsigned long * adver,bool ext_supported)1089 static bool ext_requested(u8 autoneg, const unsigned long *adver, bool ext_supported)
1090 {
1091 bool ext_link_mode = ext_link_mode_requested(adver);
1092
1093 return autoneg == AUTONEG_ENABLE ? ext_link_mode : ext_supported;
1094 }
1095
mlx5e_ethtool_set_link_ksettings(struct mlx5e_priv * priv,const struct ethtool_link_ksettings * link_ksettings)1096 int mlx5e_ethtool_set_link_ksettings(struct mlx5e_priv *priv,
1097 const struct ethtool_link_ksettings *link_ksettings)
1098 {
1099 struct mlx5_core_dev *mdev = priv->mdev;
1100 struct mlx5e_port_eth_proto eproto;
1101 const unsigned long *adver;
1102 bool an_changes = false;
1103 u8 an_disable_admin;
1104 bool ext_supported;
1105 u8 an_disable_cap;
1106 bool an_disable;
1107 u32 link_modes;
1108 u8 an_status;
1109 u8 autoneg;
1110 u32 speed;
1111 bool ext;
1112 int err;
1113
1114 u32 (*ethtool2ptys_adver_func)(const unsigned long *adver);
1115
1116 adver = link_ksettings->link_modes.advertising;
1117 autoneg = link_ksettings->base.autoneg;
1118 speed = link_ksettings->base.speed;
1119
1120 ext_supported = mlx5e_ptys_ext_supported(mdev);
1121 ext = ext_requested(autoneg, adver, ext_supported);
1122 if (!ext_supported && ext)
1123 return -EOPNOTSUPP;
1124
1125 ethtool2ptys_adver_func = ext ? mlx5e_ethtool2ptys_ext_adver_link :
1126 mlx5e_ethtool2ptys_adver_link;
1127 err = mlx5_port_query_eth_proto(mdev, 1, ext, &eproto);
1128 if (err) {
1129 netdev_err(priv->netdev, "%s: query port eth proto failed: %d\n",
1130 __func__, err);
1131 goto out;
1132 }
1133 link_modes = autoneg == AUTONEG_ENABLE ? ethtool2ptys_adver_func(adver) :
1134 mlx5e_port_speed2linkmodes(mdev, speed, !ext);
1135
1136 err = mlx5e_speed_validate(priv->netdev, ext, link_modes, autoneg);
1137 if (err)
1138 goto out;
1139
1140 link_modes = link_modes & eproto.cap;
1141 if (!link_modes) {
1142 netdev_err(priv->netdev, "%s: Not supported link mode(s) requested",
1143 __func__);
1144 err = -EINVAL;
1145 goto out;
1146 }
1147
1148 mlx5_port_query_eth_autoneg(mdev, &an_status, &an_disable_cap,
1149 &an_disable_admin);
1150
1151 an_disable = autoneg == AUTONEG_DISABLE;
1152 an_changes = ((!an_disable && an_disable_admin) ||
1153 (an_disable && !an_disable_admin));
1154
1155 if (!an_changes && link_modes == eproto.admin)
1156 goto out;
1157
1158 mlx5_port_set_eth_ptys(mdev, an_disable, link_modes, ext);
1159 mlx5_toggle_port_link(mdev);
1160
1161 out:
1162 return err;
1163 }
1164
mlx5e_set_link_ksettings(struct net_device * netdev,const struct ethtool_link_ksettings * link_ksettings)1165 static int mlx5e_set_link_ksettings(struct net_device *netdev,
1166 const struct ethtool_link_ksettings *link_ksettings)
1167 {
1168 struct mlx5e_priv *priv = netdev_priv(netdev);
1169
1170 return mlx5e_ethtool_set_link_ksettings(priv, link_ksettings);
1171 }
1172
mlx5e_ethtool_get_rxfh_key_size(struct mlx5e_priv * priv)1173 u32 mlx5e_ethtool_get_rxfh_key_size(struct mlx5e_priv *priv)
1174 {
1175 return sizeof(priv->rss_params.toeplitz_hash_key);
1176 }
1177
mlx5e_get_rxfh_key_size(struct net_device * netdev)1178 static u32 mlx5e_get_rxfh_key_size(struct net_device *netdev)
1179 {
1180 struct mlx5e_priv *priv = netdev_priv(netdev);
1181
1182 return mlx5e_ethtool_get_rxfh_key_size(priv);
1183 }
1184
mlx5e_ethtool_get_rxfh_indir_size(struct mlx5e_priv * priv)1185 u32 mlx5e_ethtool_get_rxfh_indir_size(struct mlx5e_priv *priv)
1186 {
1187 return MLX5E_INDIR_RQT_SIZE;
1188 }
1189
mlx5e_get_rxfh_indir_size(struct net_device * netdev)1190 static u32 mlx5e_get_rxfh_indir_size(struct net_device *netdev)
1191 {
1192 struct mlx5e_priv *priv = netdev_priv(netdev);
1193
1194 return mlx5e_ethtool_get_rxfh_indir_size(priv);
1195 }
1196
mlx5e_get_rxfh(struct net_device * netdev,u32 * indir,u8 * key,u8 * hfunc)1197 int mlx5e_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key,
1198 u8 *hfunc)
1199 {
1200 struct mlx5e_priv *priv = netdev_priv(netdev);
1201 struct mlx5e_rss_params *rss = &priv->rss_params;
1202
1203 if (indir)
1204 memcpy(indir, rss->indirection_rqt,
1205 sizeof(rss->indirection_rqt));
1206
1207 if (key)
1208 memcpy(key, rss->toeplitz_hash_key,
1209 sizeof(rss->toeplitz_hash_key));
1210
1211 if (hfunc)
1212 *hfunc = rss->hfunc;
1213
1214 return 0;
1215 }
1216
mlx5e_set_rxfh(struct net_device * dev,const u32 * indir,const u8 * key,const u8 hfunc)1217 int mlx5e_set_rxfh(struct net_device *dev, const u32 *indir,
1218 const u8 *key, const u8 hfunc)
1219 {
1220 struct mlx5e_priv *priv = netdev_priv(dev);
1221 struct mlx5e_rss_params *rss = &priv->rss_params;
1222 int inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1223 bool refresh_tirs = false;
1224 bool refresh_rqt = false;
1225 void *in;
1226
1227 if ((hfunc != ETH_RSS_HASH_NO_CHANGE) &&
1228 (hfunc != ETH_RSS_HASH_XOR) &&
1229 (hfunc != ETH_RSS_HASH_TOP))
1230 return -EINVAL;
1231
1232 in = kvzalloc(inlen, GFP_KERNEL);
1233 if (!in)
1234 return -ENOMEM;
1235
1236 mutex_lock(&priv->state_lock);
1237
1238 if (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != rss->hfunc) {
1239 rss->hfunc = hfunc;
1240 refresh_rqt = true;
1241 refresh_tirs = true;
1242 }
1243
1244 if (indir) {
1245 memcpy(rss->indirection_rqt, indir,
1246 sizeof(rss->indirection_rqt));
1247 refresh_rqt = true;
1248 }
1249
1250 if (key) {
1251 memcpy(rss->toeplitz_hash_key, key,
1252 sizeof(rss->toeplitz_hash_key));
1253 refresh_tirs = refresh_tirs || rss->hfunc == ETH_RSS_HASH_TOP;
1254 }
1255
1256 if (refresh_rqt && test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1257 struct mlx5e_redirect_rqt_param rrp = {
1258 .is_rss = true,
1259 {
1260 .rss = {
1261 .hfunc = rss->hfunc,
1262 .channels = &priv->channels,
1263 },
1264 },
1265 };
1266 u32 rqtn = priv->indir_rqt.rqtn;
1267
1268 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
1269 }
1270
1271 if (refresh_tirs)
1272 mlx5e_modify_tirs_hash(priv, in);
1273
1274 mutex_unlock(&priv->state_lock);
1275
1276 kvfree(in);
1277
1278 return 0;
1279 }
1280
1281 #define MLX5E_PFC_PREVEN_AUTO_TOUT_MSEC 100
1282 #define MLX5E_PFC_PREVEN_TOUT_MAX_MSEC 8000
1283 #define MLX5E_PFC_PREVEN_MINOR_PRECENT 85
1284 #define MLX5E_PFC_PREVEN_TOUT_MIN_MSEC 80
1285 #define MLX5E_DEVICE_STALL_MINOR_WATERMARK(critical_tout) \
1286 max_t(u16, MLX5E_PFC_PREVEN_TOUT_MIN_MSEC, \
1287 (critical_tout * MLX5E_PFC_PREVEN_MINOR_PRECENT) / 100)
1288
mlx5e_get_pfc_prevention_tout(struct net_device * netdev,u16 * pfc_prevention_tout)1289 static int mlx5e_get_pfc_prevention_tout(struct net_device *netdev,
1290 u16 *pfc_prevention_tout)
1291 {
1292 struct mlx5e_priv *priv = netdev_priv(netdev);
1293 struct mlx5_core_dev *mdev = priv->mdev;
1294
1295 if (!MLX5_CAP_PCAM_FEATURE((priv)->mdev, pfcc_mask) ||
1296 !MLX5_CAP_DEBUG((priv)->mdev, stall_detect))
1297 return -EOPNOTSUPP;
1298
1299 return mlx5_query_port_stall_watermark(mdev, pfc_prevention_tout, NULL);
1300 }
1301
mlx5e_set_pfc_prevention_tout(struct net_device * netdev,u16 pfc_preven)1302 static int mlx5e_set_pfc_prevention_tout(struct net_device *netdev,
1303 u16 pfc_preven)
1304 {
1305 struct mlx5e_priv *priv = netdev_priv(netdev);
1306 struct mlx5_core_dev *mdev = priv->mdev;
1307 u16 critical_tout;
1308 u16 minor;
1309
1310 if (!MLX5_CAP_PCAM_FEATURE((priv)->mdev, pfcc_mask) ||
1311 !MLX5_CAP_DEBUG((priv)->mdev, stall_detect))
1312 return -EOPNOTSUPP;
1313
1314 critical_tout = (pfc_preven == PFC_STORM_PREVENTION_AUTO) ?
1315 MLX5E_PFC_PREVEN_AUTO_TOUT_MSEC :
1316 pfc_preven;
1317
1318 if (critical_tout != PFC_STORM_PREVENTION_DISABLE &&
1319 (critical_tout > MLX5E_PFC_PREVEN_TOUT_MAX_MSEC ||
1320 critical_tout < MLX5E_PFC_PREVEN_TOUT_MIN_MSEC)) {
1321 netdev_info(netdev, "%s: pfc prevention tout not in range (%d-%d)\n",
1322 __func__, MLX5E_PFC_PREVEN_TOUT_MIN_MSEC,
1323 MLX5E_PFC_PREVEN_TOUT_MAX_MSEC);
1324 return -EINVAL;
1325 }
1326
1327 minor = MLX5E_DEVICE_STALL_MINOR_WATERMARK(critical_tout);
1328 return mlx5_set_port_stall_watermark(mdev, critical_tout,
1329 minor);
1330 }
1331
mlx5e_get_tunable(struct net_device * dev,const struct ethtool_tunable * tuna,void * data)1332 static int mlx5e_get_tunable(struct net_device *dev,
1333 const struct ethtool_tunable *tuna,
1334 void *data)
1335 {
1336 int err;
1337
1338 switch (tuna->id) {
1339 case ETHTOOL_PFC_PREVENTION_TOUT:
1340 err = mlx5e_get_pfc_prevention_tout(dev, data);
1341 break;
1342 default:
1343 err = -EINVAL;
1344 break;
1345 }
1346
1347 return err;
1348 }
1349
mlx5e_set_tunable(struct net_device * dev,const struct ethtool_tunable * tuna,const void * data)1350 static int mlx5e_set_tunable(struct net_device *dev,
1351 const struct ethtool_tunable *tuna,
1352 const void *data)
1353 {
1354 struct mlx5e_priv *priv = netdev_priv(dev);
1355 int err;
1356
1357 mutex_lock(&priv->state_lock);
1358
1359 switch (tuna->id) {
1360 case ETHTOOL_PFC_PREVENTION_TOUT:
1361 err = mlx5e_set_pfc_prevention_tout(dev, *(u16 *)data);
1362 break;
1363 default:
1364 err = -EINVAL;
1365 break;
1366 }
1367
1368 mutex_unlock(&priv->state_lock);
1369 return err;
1370 }
1371
mlx5e_get_pause_stats(struct net_device * netdev,struct ethtool_pause_stats * pause_stats)1372 static void mlx5e_get_pause_stats(struct net_device *netdev,
1373 struct ethtool_pause_stats *pause_stats)
1374 {
1375 struct mlx5e_priv *priv = netdev_priv(netdev);
1376
1377 mlx5e_stats_pause_get(priv, pause_stats);
1378 }
1379
mlx5e_ethtool_get_pauseparam(struct mlx5e_priv * priv,struct ethtool_pauseparam * pauseparam)1380 void mlx5e_ethtool_get_pauseparam(struct mlx5e_priv *priv,
1381 struct ethtool_pauseparam *pauseparam)
1382 {
1383 struct mlx5_core_dev *mdev = priv->mdev;
1384 int err;
1385
1386 err = mlx5_query_port_pause(mdev, &pauseparam->rx_pause,
1387 &pauseparam->tx_pause);
1388 if (err) {
1389 netdev_err(priv->netdev, "%s: mlx5_query_port_pause failed:0x%x\n",
1390 __func__, err);
1391 }
1392 }
1393
mlx5e_get_pauseparam(struct net_device * netdev,struct ethtool_pauseparam * pauseparam)1394 static void mlx5e_get_pauseparam(struct net_device *netdev,
1395 struct ethtool_pauseparam *pauseparam)
1396 {
1397 struct mlx5e_priv *priv = netdev_priv(netdev);
1398
1399 mlx5e_ethtool_get_pauseparam(priv, pauseparam);
1400 }
1401
mlx5e_ethtool_set_pauseparam(struct mlx5e_priv * priv,struct ethtool_pauseparam * pauseparam)1402 int mlx5e_ethtool_set_pauseparam(struct mlx5e_priv *priv,
1403 struct ethtool_pauseparam *pauseparam)
1404 {
1405 struct mlx5_core_dev *mdev = priv->mdev;
1406 int err;
1407
1408 if (!MLX5_CAP_GEN(mdev, vport_group_manager))
1409 return -EOPNOTSUPP;
1410
1411 if (pauseparam->autoneg)
1412 return -EINVAL;
1413
1414 err = mlx5_set_port_pause(mdev,
1415 pauseparam->rx_pause ? 1 : 0,
1416 pauseparam->tx_pause ? 1 : 0);
1417 if (err) {
1418 netdev_err(priv->netdev, "%s: mlx5_set_port_pause failed:0x%x\n",
1419 __func__, err);
1420 }
1421
1422 return err;
1423 }
1424
mlx5e_set_pauseparam(struct net_device * netdev,struct ethtool_pauseparam * pauseparam)1425 static int mlx5e_set_pauseparam(struct net_device *netdev,
1426 struct ethtool_pauseparam *pauseparam)
1427 {
1428 struct mlx5e_priv *priv = netdev_priv(netdev);
1429
1430 return mlx5e_ethtool_set_pauseparam(priv, pauseparam);
1431 }
1432
mlx5e_ethtool_get_ts_info(struct mlx5e_priv * priv,struct ethtool_ts_info * info)1433 int mlx5e_ethtool_get_ts_info(struct mlx5e_priv *priv,
1434 struct ethtool_ts_info *info)
1435 {
1436 struct mlx5_core_dev *mdev = priv->mdev;
1437
1438 info->phc_index = mlx5_clock_get_ptp_index(mdev);
1439
1440 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz) ||
1441 info->phc_index == -1)
1442 return 0;
1443
1444 info->so_timestamping = SOF_TIMESTAMPING_TX_HARDWARE |
1445 SOF_TIMESTAMPING_RX_HARDWARE |
1446 SOF_TIMESTAMPING_RAW_HARDWARE;
1447
1448 info->tx_types = BIT(HWTSTAMP_TX_OFF) |
1449 BIT(HWTSTAMP_TX_ON);
1450
1451 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) |
1452 BIT(HWTSTAMP_FILTER_ALL);
1453
1454 return 0;
1455 }
1456
mlx5e_get_ts_info(struct net_device * dev,struct ethtool_ts_info * info)1457 static int mlx5e_get_ts_info(struct net_device *dev,
1458 struct ethtool_ts_info *info)
1459 {
1460 struct mlx5e_priv *priv = netdev_priv(dev);
1461
1462 return mlx5e_ethtool_get_ts_info(priv, info);
1463 }
1464
mlx5e_get_wol_supported(struct mlx5_core_dev * mdev)1465 static __u32 mlx5e_get_wol_supported(struct mlx5_core_dev *mdev)
1466 {
1467 __u32 ret = 0;
1468
1469 if (MLX5_CAP_GEN(mdev, wol_g))
1470 ret |= WAKE_MAGIC;
1471
1472 if (MLX5_CAP_GEN(mdev, wol_s))
1473 ret |= WAKE_MAGICSECURE;
1474
1475 if (MLX5_CAP_GEN(mdev, wol_a))
1476 ret |= WAKE_ARP;
1477
1478 if (MLX5_CAP_GEN(mdev, wol_b))
1479 ret |= WAKE_BCAST;
1480
1481 if (MLX5_CAP_GEN(mdev, wol_m))
1482 ret |= WAKE_MCAST;
1483
1484 if (MLX5_CAP_GEN(mdev, wol_u))
1485 ret |= WAKE_UCAST;
1486
1487 if (MLX5_CAP_GEN(mdev, wol_p))
1488 ret |= WAKE_PHY;
1489
1490 return ret;
1491 }
1492
mlx5e_reformat_wol_mode_mlx5_to_linux(u8 mode)1493 static __u32 mlx5e_reformat_wol_mode_mlx5_to_linux(u8 mode)
1494 {
1495 __u32 ret = 0;
1496
1497 if (mode & MLX5_WOL_MAGIC)
1498 ret |= WAKE_MAGIC;
1499
1500 if (mode & MLX5_WOL_SECURED_MAGIC)
1501 ret |= WAKE_MAGICSECURE;
1502
1503 if (mode & MLX5_WOL_ARP)
1504 ret |= WAKE_ARP;
1505
1506 if (mode & MLX5_WOL_BROADCAST)
1507 ret |= WAKE_BCAST;
1508
1509 if (mode & MLX5_WOL_MULTICAST)
1510 ret |= WAKE_MCAST;
1511
1512 if (mode & MLX5_WOL_UNICAST)
1513 ret |= WAKE_UCAST;
1514
1515 if (mode & MLX5_WOL_PHY_ACTIVITY)
1516 ret |= WAKE_PHY;
1517
1518 return ret;
1519 }
1520
mlx5e_reformat_wol_mode_linux_to_mlx5(__u32 mode)1521 static u8 mlx5e_reformat_wol_mode_linux_to_mlx5(__u32 mode)
1522 {
1523 u8 ret = 0;
1524
1525 if (mode & WAKE_MAGIC)
1526 ret |= MLX5_WOL_MAGIC;
1527
1528 if (mode & WAKE_MAGICSECURE)
1529 ret |= MLX5_WOL_SECURED_MAGIC;
1530
1531 if (mode & WAKE_ARP)
1532 ret |= MLX5_WOL_ARP;
1533
1534 if (mode & WAKE_BCAST)
1535 ret |= MLX5_WOL_BROADCAST;
1536
1537 if (mode & WAKE_MCAST)
1538 ret |= MLX5_WOL_MULTICAST;
1539
1540 if (mode & WAKE_UCAST)
1541 ret |= MLX5_WOL_UNICAST;
1542
1543 if (mode & WAKE_PHY)
1544 ret |= MLX5_WOL_PHY_ACTIVITY;
1545
1546 return ret;
1547 }
1548
mlx5e_get_wol(struct net_device * netdev,struct ethtool_wolinfo * wol)1549 static void mlx5e_get_wol(struct net_device *netdev,
1550 struct ethtool_wolinfo *wol)
1551 {
1552 struct mlx5e_priv *priv = netdev_priv(netdev);
1553 struct mlx5_core_dev *mdev = priv->mdev;
1554 u8 mlx5_wol_mode;
1555 int err;
1556
1557 memset(wol, 0, sizeof(*wol));
1558
1559 wol->supported = mlx5e_get_wol_supported(mdev);
1560 if (!wol->supported)
1561 return;
1562
1563 err = mlx5_query_port_wol(mdev, &mlx5_wol_mode);
1564 if (err)
1565 return;
1566
1567 wol->wolopts = mlx5e_reformat_wol_mode_mlx5_to_linux(mlx5_wol_mode);
1568 }
1569
mlx5e_set_wol(struct net_device * netdev,struct ethtool_wolinfo * wol)1570 static int mlx5e_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1571 {
1572 struct mlx5e_priv *priv = netdev_priv(netdev);
1573 struct mlx5_core_dev *mdev = priv->mdev;
1574 __u32 wol_supported = mlx5e_get_wol_supported(mdev);
1575 u32 mlx5_wol_mode;
1576
1577 if (!wol_supported)
1578 return -EOPNOTSUPP;
1579
1580 if (wol->wolopts & ~wol_supported)
1581 return -EINVAL;
1582
1583 mlx5_wol_mode = mlx5e_reformat_wol_mode_linux_to_mlx5(wol->wolopts);
1584
1585 return mlx5_set_port_wol(mdev, mlx5_wol_mode);
1586 }
1587
mlx5e_get_fecparam(struct net_device * netdev,struct ethtool_fecparam * fecparam)1588 static int mlx5e_get_fecparam(struct net_device *netdev,
1589 struct ethtool_fecparam *fecparam)
1590 {
1591 struct mlx5e_priv *priv = netdev_priv(netdev);
1592 struct mlx5_core_dev *mdev = priv->mdev;
1593 u16 fec_configured;
1594 u32 fec_active;
1595 int err;
1596
1597 err = mlx5e_get_fec_mode(mdev, &fec_active, &fec_configured);
1598
1599 if (err)
1600 return err;
1601
1602 fecparam->active_fec = pplm2ethtool_fec((unsigned long)fec_active,
1603 sizeof(unsigned long) * BITS_PER_BYTE);
1604
1605 if (!fecparam->active_fec)
1606 return -EOPNOTSUPP;
1607
1608 fecparam->fec = pplm2ethtool_fec((unsigned long)fec_configured,
1609 sizeof(unsigned long) * BITS_PER_BYTE);
1610
1611 return 0;
1612 }
1613
mlx5e_set_fecparam(struct net_device * netdev,struct ethtool_fecparam * fecparam)1614 static int mlx5e_set_fecparam(struct net_device *netdev,
1615 struct ethtool_fecparam *fecparam)
1616 {
1617 struct mlx5e_priv *priv = netdev_priv(netdev);
1618 struct mlx5_core_dev *mdev = priv->mdev;
1619 unsigned long fec_bitmap;
1620 u16 fec_policy = 0;
1621 int mode;
1622 int err;
1623
1624 bitmap_from_arr32(&fec_bitmap, &fecparam->fec, sizeof(fecparam->fec) * BITS_PER_BYTE);
1625 if (bitmap_weight(&fec_bitmap, ETHTOOL_FEC_LLRS_BIT + 1) > 1)
1626 return -EOPNOTSUPP;
1627
1628 for (mode = 0; mode < ARRAY_SIZE(pplm_fec_2_ethtool); mode++) {
1629 if (!(pplm_fec_2_ethtool[mode] & fecparam->fec))
1630 continue;
1631 fec_policy |= (1 << mode);
1632 break;
1633 }
1634
1635 err = mlx5e_set_fec_mode(mdev, fec_policy);
1636
1637 if (err)
1638 return err;
1639
1640 mlx5_toggle_port_link(mdev);
1641
1642 return 0;
1643 }
1644
mlx5e_get_msglevel(struct net_device * dev)1645 static u32 mlx5e_get_msglevel(struct net_device *dev)
1646 {
1647 return ((struct mlx5e_priv *)netdev_priv(dev))->msglevel;
1648 }
1649
mlx5e_set_msglevel(struct net_device * dev,u32 val)1650 static void mlx5e_set_msglevel(struct net_device *dev, u32 val)
1651 {
1652 ((struct mlx5e_priv *)netdev_priv(dev))->msglevel = val;
1653 }
1654
mlx5e_set_phys_id(struct net_device * dev,enum ethtool_phys_id_state state)1655 static int mlx5e_set_phys_id(struct net_device *dev,
1656 enum ethtool_phys_id_state state)
1657 {
1658 struct mlx5e_priv *priv = netdev_priv(dev);
1659 struct mlx5_core_dev *mdev = priv->mdev;
1660 u16 beacon_duration;
1661
1662 if (!MLX5_CAP_GEN(mdev, beacon_led))
1663 return -EOPNOTSUPP;
1664
1665 switch (state) {
1666 case ETHTOOL_ID_ACTIVE:
1667 beacon_duration = MLX5_BEACON_DURATION_INF;
1668 break;
1669 case ETHTOOL_ID_INACTIVE:
1670 beacon_duration = MLX5_BEACON_DURATION_OFF;
1671 break;
1672 default:
1673 return -EOPNOTSUPP;
1674 }
1675
1676 return mlx5_set_port_beacon(mdev, beacon_duration);
1677 }
1678
mlx5e_get_module_info(struct net_device * netdev,struct ethtool_modinfo * modinfo)1679 static int mlx5e_get_module_info(struct net_device *netdev,
1680 struct ethtool_modinfo *modinfo)
1681 {
1682 struct mlx5e_priv *priv = netdev_priv(netdev);
1683 struct mlx5_core_dev *dev = priv->mdev;
1684 int size_read = 0;
1685 u8 data[4] = {0};
1686
1687 size_read = mlx5_query_module_eeprom(dev, 0, 2, data);
1688 if (size_read < 2)
1689 return -EIO;
1690
1691 /* data[0] = identifier byte */
1692 switch (data[0]) {
1693 case MLX5_MODULE_ID_QSFP:
1694 modinfo->type = ETH_MODULE_SFF_8436;
1695 modinfo->eeprom_len = ETH_MODULE_SFF_8436_MAX_LEN;
1696 break;
1697 case MLX5_MODULE_ID_QSFP_PLUS:
1698 case MLX5_MODULE_ID_QSFP28:
1699 /* data[1] = revision id */
1700 if (data[0] == MLX5_MODULE_ID_QSFP28 || data[1] >= 0x3) {
1701 modinfo->type = ETH_MODULE_SFF_8636;
1702 modinfo->eeprom_len = ETH_MODULE_SFF_8636_MAX_LEN;
1703 } else {
1704 modinfo->type = ETH_MODULE_SFF_8436;
1705 modinfo->eeprom_len = ETH_MODULE_SFF_8436_MAX_LEN;
1706 }
1707 break;
1708 case MLX5_MODULE_ID_SFP:
1709 modinfo->type = ETH_MODULE_SFF_8472;
1710 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
1711 break;
1712 default:
1713 netdev_err(priv->netdev, "%s: cable type not recognized:0x%x\n",
1714 __func__, data[0]);
1715 return -EINVAL;
1716 }
1717
1718 return 0;
1719 }
1720
mlx5e_get_module_eeprom(struct net_device * netdev,struct ethtool_eeprom * ee,u8 * data)1721 static int mlx5e_get_module_eeprom(struct net_device *netdev,
1722 struct ethtool_eeprom *ee,
1723 u8 *data)
1724 {
1725 struct mlx5e_priv *priv = netdev_priv(netdev);
1726 struct mlx5_core_dev *mdev = priv->mdev;
1727 int offset = ee->offset;
1728 int size_read;
1729 int i = 0;
1730
1731 if (!ee->len)
1732 return -EINVAL;
1733
1734 memset(data, 0, ee->len);
1735
1736 while (i < ee->len) {
1737 size_read = mlx5_query_module_eeprom(mdev, offset, ee->len - i,
1738 data + i);
1739
1740 if (!size_read)
1741 /* Done reading */
1742 return 0;
1743
1744 if (size_read < 0) {
1745 netdev_err(priv->netdev, "%s: mlx5_query_eeprom failed:0x%x\n",
1746 __func__, size_read);
1747 return size_read;
1748 }
1749
1750 i += size_read;
1751 offset += size_read;
1752 }
1753
1754 return 0;
1755 }
1756
mlx5e_ethtool_flash_device(struct mlx5e_priv * priv,struct ethtool_flash * flash)1757 int mlx5e_ethtool_flash_device(struct mlx5e_priv *priv,
1758 struct ethtool_flash *flash)
1759 {
1760 struct mlx5_core_dev *mdev = priv->mdev;
1761 struct net_device *dev = priv->netdev;
1762 const struct firmware *fw;
1763 int err;
1764
1765 if (flash->region != ETHTOOL_FLASH_ALL_REGIONS)
1766 return -EOPNOTSUPP;
1767
1768 err = request_firmware_direct(&fw, flash->data, &dev->dev);
1769 if (err)
1770 return err;
1771
1772 dev_hold(dev);
1773 rtnl_unlock();
1774
1775 err = mlx5_firmware_flash(mdev, fw, NULL);
1776 release_firmware(fw);
1777
1778 rtnl_lock();
1779 dev_put(dev);
1780 return err;
1781 }
1782
mlx5e_flash_device(struct net_device * dev,struct ethtool_flash * flash)1783 static int mlx5e_flash_device(struct net_device *dev,
1784 struct ethtool_flash *flash)
1785 {
1786 struct mlx5e_priv *priv = netdev_priv(dev);
1787
1788 return mlx5e_ethtool_flash_device(priv, flash);
1789 }
1790
set_pflag_cqe_based_moder(struct net_device * netdev,bool enable,bool is_rx_cq)1791 static int set_pflag_cqe_based_moder(struct net_device *netdev, bool enable,
1792 bool is_rx_cq)
1793 {
1794 struct mlx5e_priv *priv = netdev_priv(netdev);
1795 struct mlx5_core_dev *mdev = priv->mdev;
1796 struct mlx5e_channels new_channels = {};
1797 bool mode_changed;
1798 u8 cq_period_mode, current_cq_period_mode;
1799
1800 cq_period_mode = enable ?
1801 MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
1802 MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1803 current_cq_period_mode = is_rx_cq ?
1804 priv->channels.params.rx_cq_moderation.cq_period_mode :
1805 priv->channels.params.tx_cq_moderation.cq_period_mode;
1806 mode_changed = cq_period_mode != current_cq_period_mode;
1807
1808 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE &&
1809 !MLX5_CAP_GEN(mdev, cq_period_start_from_cqe))
1810 return -EOPNOTSUPP;
1811
1812 if (!mode_changed)
1813 return 0;
1814
1815 new_channels.params = priv->channels.params;
1816 if (is_rx_cq)
1817 mlx5e_set_rx_cq_mode_params(&new_channels.params, cq_period_mode);
1818 else
1819 mlx5e_set_tx_cq_mode_params(&new_channels.params, cq_period_mode);
1820
1821 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1822 priv->channels.params = new_channels.params;
1823 return 0;
1824 }
1825
1826 return mlx5e_safe_switch_channels(priv, &new_channels, NULL, NULL);
1827 }
1828
set_pflag_tx_cqe_based_moder(struct net_device * netdev,bool enable)1829 static int set_pflag_tx_cqe_based_moder(struct net_device *netdev, bool enable)
1830 {
1831 return set_pflag_cqe_based_moder(netdev, enable, false);
1832 }
1833
set_pflag_rx_cqe_based_moder(struct net_device * netdev,bool enable)1834 static int set_pflag_rx_cqe_based_moder(struct net_device *netdev, bool enable)
1835 {
1836 return set_pflag_cqe_based_moder(netdev, enable, true);
1837 }
1838
mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv * priv,bool new_val)1839 int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool new_val)
1840 {
1841 bool curr_val = MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS);
1842 struct mlx5e_channels new_channels = {};
1843 int err = 0;
1844
1845 if (!MLX5_CAP_GEN(priv->mdev, cqe_compression))
1846 return new_val ? -EOPNOTSUPP : 0;
1847
1848 if (curr_val == new_val)
1849 return 0;
1850
1851 new_channels.params = priv->channels.params;
1852 MLX5E_SET_PFLAG(&new_channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS, new_val);
1853
1854 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1855 priv->channels.params = new_channels.params;
1856 return 0;
1857 }
1858
1859 err = mlx5e_safe_switch_channels(priv, &new_channels, NULL, NULL);
1860 if (err)
1861 return err;
1862
1863 mlx5e_dbg(DRV, priv, "MLX5E: RxCqeCmprss was turned %s\n",
1864 MLX5E_GET_PFLAG(&priv->channels.params,
1865 MLX5E_PFLAG_RX_CQE_COMPRESS) ? "ON" : "OFF");
1866
1867 return 0;
1868 }
1869
set_pflag_rx_cqe_compress(struct net_device * netdev,bool enable)1870 static int set_pflag_rx_cqe_compress(struct net_device *netdev,
1871 bool enable)
1872 {
1873 struct mlx5e_priv *priv = netdev_priv(netdev);
1874 struct mlx5_core_dev *mdev = priv->mdev;
1875 int err;
1876
1877 if (!MLX5_CAP_GEN(mdev, cqe_compression))
1878 return -EOPNOTSUPP;
1879
1880 if (enable && priv->tstamp.rx_filter != HWTSTAMP_FILTER_NONE) {
1881 netdev_err(netdev, "Can't enable cqe compression while timestamping is enabled.\n");
1882 return -EINVAL;
1883 }
1884
1885 err = mlx5e_modify_rx_cqe_compression_locked(priv, enable);
1886 if (err)
1887 return err;
1888
1889 priv->channels.params.rx_cqe_compress_def = enable;
1890
1891 return 0;
1892 }
1893
set_pflag_rx_striding_rq(struct net_device * netdev,bool enable)1894 static int set_pflag_rx_striding_rq(struct net_device *netdev, bool enable)
1895 {
1896 struct mlx5e_priv *priv = netdev_priv(netdev);
1897 struct mlx5_core_dev *mdev = priv->mdev;
1898 struct mlx5e_channels new_channels = {};
1899
1900 if (enable) {
1901 if (!mlx5e_check_fragmented_striding_rq_cap(mdev))
1902 return -EOPNOTSUPP;
1903 if (!mlx5e_striding_rq_possible(mdev, &priv->channels.params))
1904 return -EINVAL;
1905 } else if (priv->channels.params.lro_en) {
1906 netdev_warn(netdev, "Can't set legacy RQ with LRO, disable LRO first\n");
1907 return -EINVAL;
1908 }
1909
1910 new_channels.params = priv->channels.params;
1911
1912 MLX5E_SET_PFLAG(&new_channels.params, MLX5E_PFLAG_RX_STRIDING_RQ, enable);
1913 mlx5e_set_rq_type(mdev, &new_channels.params);
1914
1915 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1916 priv->channels.params = new_channels.params;
1917 return 0;
1918 }
1919
1920 return mlx5e_safe_switch_channels(priv, &new_channels, NULL, NULL);
1921 }
1922
set_pflag_rx_no_csum_complete(struct net_device * netdev,bool enable)1923 static int set_pflag_rx_no_csum_complete(struct net_device *netdev, bool enable)
1924 {
1925 struct mlx5e_priv *priv = netdev_priv(netdev);
1926 struct mlx5e_channels *channels = &priv->channels;
1927 struct mlx5e_channel *c;
1928 int i;
1929
1930 if (!test_bit(MLX5E_STATE_OPENED, &priv->state) ||
1931 priv->channels.params.xdp_prog)
1932 return 0;
1933
1934 for (i = 0; i < channels->num; i++) {
1935 c = channels->c[i];
1936 if (enable)
1937 __set_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &c->rq.state);
1938 else
1939 __clear_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &c->rq.state);
1940 }
1941
1942 return 0;
1943 }
1944
set_pflag_tx_mpwqe_common(struct net_device * netdev,u32 flag,bool enable)1945 static int set_pflag_tx_mpwqe_common(struct net_device *netdev, u32 flag, bool enable)
1946 {
1947 struct mlx5e_priv *priv = netdev_priv(netdev);
1948 struct mlx5_core_dev *mdev = priv->mdev;
1949 struct mlx5e_channels new_channels = {};
1950 int err;
1951
1952 if (enable && !MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe))
1953 return -EOPNOTSUPP;
1954
1955 new_channels.params = priv->channels.params;
1956
1957 MLX5E_SET_PFLAG(&new_channels.params, flag, enable);
1958
1959 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1960 priv->channels.params = new_channels.params;
1961 return 0;
1962 }
1963
1964 err = mlx5e_safe_switch_channels(priv, &new_channels, NULL, NULL);
1965 return err;
1966 }
1967
set_pflag_xdp_tx_mpwqe(struct net_device * netdev,bool enable)1968 static int set_pflag_xdp_tx_mpwqe(struct net_device *netdev, bool enable)
1969 {
1970 return set_pflag_tx_mpwqe_common(netdev, MLX5E_PFLAG_XDP_TX_MPWQE, enable);
1971 }
1972
set_pflag_skb_tx_mpwqe(struct net_device * netdev,bool enable)1973 static int set_pflag_skb_tx_mpwqe(struct net_device *netdev, bool enable)
1974 {
1975 return set_pflag_tx_mpwqe_common(netdev, MLX5E_PFLAG_SKB_TX_MPWQE, enable);
1976 }
1977
1978 static const struct pflag_desc mlx5e_priv_flags[MLX5E_NUM_PFLAGS] = {
1979 { "rx_cqe_moder", set_pflag_rx_cqe_based_moder },
1980 { "tx_cqe_moder", set_pflag_tx_cqe_based_moder },
1981 { "rx_cqe_compress", set_pflag_rx_cqe_compress },
1982 { "rx_striding_rq", set_pflag_rx_striding_rq },
1983 { "rx_no_csum_complete", set_pflag_rx_no_csum_complete },
1984 { "xdp_tx_mpwqe", set_pflag_xdp_tx_mpwqe },
1985 { "skb_tx_mpwqe", set_pflag_skb_tx_mpwqe },
1986 };
1987
mlx5e_handle_pflag(struct net_device * netdev,u32 wanted_flags,enum mlx5e_priv_flag flag)1988 static int mlx5e_handle_pflag(struct net_device *netdev,
1989 u32 wanted_flags,
1990 enum mlx5e_priv_flag flag)
1991 {
1992 struct mlx5e_priv *priv = netdev_priv(netdev);
1993 bool enable = !!(wanted_flags & BIT(flag));
1994 u32 changes = wanted_flags ^ priv->channels.params.pflags;
1995 int err;
1996
1997 if (!(changes & BIT(flag)))
1998 return 0;
1999
2000 err = mlx5e_priv_flags[flag].handler(netdev, enable);
2001 if (err) {
2002 netdev_err(netdev, "%s private flag '%s' failed err %d\n",
2003 enable ? "Enable" : "Disable", mlx5e_priv_flags[flag].name, err);
2004 return err;
2005 }
2006
2007 MLX5E_SET_PFLAG(&priv->channels.params, flag, enable);
2008 return 0;
2009 }
2010
mlx5e_set_priv_flags(struct net_device * netdev,u32 pflags)2011 static int mlx5e_set_priv_flags(struct net_device *netdev, u32 pflags)
2012 {
2013 struct mlx5e_priv *priv = netdev_priv(netdev);
2014 enum mlx5e_priv_flag pflag;
2015 int err;
2016
2017 mutex_lock(&priv->state_lock);
2018
2019 for (pflag = 0; pflag < MLX5E_NUM_PFLAGS; pflag++) {
2020 err = mlx5e_handle_pflag(netdev, pflags, pflag);
2021 if (err)
2022 break;
2023 }
2024
2025 mutex_unlock(&priv->state_lock);
2026
2027 /* Need to fix some features.. */
2028 netdev_update_features(netdev);
2029
2030 return err;
2031 }
2032
mlx5e_get_priv_flags(struct net_device * netdev)2033 static u32 mlx5e_get_priv_flags(struct net_device *netdev)
2034 {
2035 struct mlx5e_priv *priv = netdev_priv(netdev);
2036
2037 return priv->channels.params.pflags;
2038 }
2039
mlx5e_get_rxnfc(struct net_device * dev,struct ethtool_rxnfc * info,u32 * rule_locs)2040 int mlx5e_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
2041 u32 *rule_locs)
2042 {
2043 struct mlx5e_priv *priv = netdev_priv(dev);
2044
2045 /* ETHTOOL_GRXRINGS is needed by ethtool -x which is not part
2046 * of rxnfc. We keep this logic out of mlx5e_ethtool_get_rxnfc,
2047 * to avoid breaking "ethtool -x" when mlx5e_ethtool_get_rxnfc
2048 * is compiled out via CONFIG_MLX5_EN_RXNFC=n.
2049 */
2050 if (info->cmd == ETHTOOL_GRXRINGS) {
2051 info->data = priv->channels.params.num_channels;
2052 return 0;
2053 }
2054
2055 return mlx5e_ethtool_get_rxnfc(dev, info, rule_locs);
2056 }
2057
mlx5e_set_rxnfc(struct net_device * dev,struct ethtool_rxnfc * cmd)2058 int mlx5e_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
2059 {
2060 return mlx5e_ethtool_set_rxnfc(dev, cmd);
2061 }
2062
2063 const struct ethtool_ops mlx5e_ethtool_ops = {
2064 .supported_coalesce_params = ETHTOOL_COALESCE_USECS |
2065 ETHTOOL_COALESCE_MAX_FRAMES |
2066 ETHTOOL_COALESCE_USE_ADAPTIVE,
2067 .get_drvinfo = mlx5e_get_drvinfo,
2068 .get_link = ethtool_op_get_link,
2069 .get_strings = mlx5e_get_strings,
2070 .get_sset_count = mlx5e_get_sset_count,
2071 .get_ethtool_stats = mlx5e_get_ethtool_stats,
2072 .get_ringparam = mlx5e_get_ringparam,
2073 .set_ringparam = mlx5e_set_ringparam,
2074 .get_channels = mlx5e_get_channels,
2075 .set_channels = mlx5e_set_channels,
2076 .get_coalesce = mlx5e_get_coalesce,
2077 .set_coalesce = mlx5e_set_coalesce,
2078 .get_link_ksettings = mlx5e_get_link_ksettings,
2079 .set_link_ksettings = mlx5e_set_link_ksettings,
2080 .get_rxfh_key_size = mlx5e_get_rxfh_key_size,
2081 .get_rxfh_indir_size = mlx5e_get_rxfh_indir_size,
2082 .get_rxfh = mlx5e_get_rxfh,
2083 .set_rxfh = mlx5e_set_rxfh,
2084 .get_rxnfc = mlx5e_get_rxnfc,
2085 .set_rxnfc = mlx5e_set_rxnfc,
2086 .get_tunable = mlx5e_get_tunable,
2087 .set_tunable = mlx5e_set_tunable,
2088 .get_pause_stats = mlx5e_get_pause_stats,
2089 .get_pauseparam = mlx5e_get_pauseparam,
2090 .set_pauseparam = mlx5e_set_pauseparam,
2091 .get_ts_info = mlx5e_get_ts_info,
2092 .set_phys_id = mlx5e_set_phys_id,
2093 .get_wol = mlx5e_get_wol,
2094 .set_wol = mlx5e_set_wol,
2095 .get_module_info = mlx5e_get_module_info,
2096 .get_module_eeprom = mlx5e_get_module_eeprom,
2097 .flash_device = mlx5e_flash_device,
2098 .get_priv_flags = mlx5e_get_priv_flags,
2099 .set_priv_flags = mlx5e_set_priv_flags,
2100 .self_test = mlx5e_self_test,
2101 .get_msglevel = mlx5e_get_msglevel,
2102 .set_msglevel = mlx5e_set_msglevel,
2103 .get_fecparam = mlx5e_get_fecparam,
2104 .set_fecparam = mlx5e_set_fecparam,
2105 };
2106