1 /*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "reg_helper.h"
27 #include "dcn10_mpc.h"
28
29 #define REG(reg)\
30 mpc10->mpc_regs->reg
31
32 #define CTX \
33 mpc10->base.ctx
34
35 #undef FN
36 #define FN(reg_name, field_name) \
37 mpc10->mpc_shift->field_name, mpc10->mpc_mask->field_name
38
39
mpc1_set_bg_color(struct mpc * mpc,struct tg_color * bg_color,int mpcc_id)40 void mpc1_set_bg_color(struct mpc *mpc,
41 struct tg_color *bg_color,
42 int mpcc_id)
43 {
44 struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
45 struct mpcc *bottommost_mpcc = mpc1_get_mpcc(mpc, mpcc_id);
46 uint32_t bg_r_cr, bg_g_y, bg_b_cb;
47
48 /* find bottommost mpcc. */
49 while (bottommost_mpcc->mpcc_bot) {
50 bottommost_mpcc = bottommost_mpcc->mpcc_bot;
51 }
52
53 /* mpc color is 12 bit. tg_color is 10 bit */
54 /* todo: might want to use 16 bit to represent color and have each
55 * hw block translate to correct color depth.
56 */
57 bg_r_cr = bg_color->color_r_cr << 2;
58 bg_g_y = bg_color->color_g_y << 2;
59 bg_b_cb = bg_color->color_b_cb << 2;
60
61 REG_SET(MPCC_BG_R_CR[bottommost_mpcc->mpcc_id], 0,
62 MPCC_BG_R_CR, bg_r_cr);
63 REG_SET(MPCC_BG_G_Y[bottommost_mpcc->mpcc_id], 0,
64 MPCC_BG_G_Y, bg_g_y);
65 REG_SET(MPCC_BG_B_CB[bottommost_mpcc->mpcc_id], 0,
66 MPCC_BG_B_CB, bg_b_cb);
67 }
68
mpc1_update_blending(struct mpc * mpc,struct mpcc_blnd_cfg * blnd_cfg,int mpcc_id)69 static void mpc1_update_blending(
70 struct mpc *mpc,
71 struct mpcc_blnd_cfg *blnd_cfg,
72 int mpcc_id)
73 {
74 struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
75 struct mpcc *mpcc = mpc1_get_mpcc(mpc, mpcc_id);
76
77 REG_UPDATE_5(MPCC_CONTROL[mpcc_id],
78 MPCC_ALPHA_BLND_MODE, blnd_cfg->alpha_mode,
79 MPCC_ALPHA_MULTIPLIED_MODE, blnd_cfg->pre_multiplied_alpha,
80 MPCC_BLND_ACTIVE_OVERLAP_ONLY, blnd_cfg->overlap_only,
81 MPCC_GLOBAL_ALPHA, blnd_cfg->global_alpha,
82 MPCC_GLOBAL_GAIN, blnd_cfg->global_gain);
83
84 mpc1_set_bg_color(mpc, &blnd_cfg->black_color, mpcc_id);
85 mpcc->blnd_cfg = *blnd_cfg;
86 }
87
mpc1_update_stereo_mix(struct mpc * mpc,struct mpcc_sm_cfg * sm_cfg,int mpcc_id)88 void mpc1_update_stereo_mix(
89 struct mpc *mpc,
90 struct mpcc_sm_cfg *sm_cfg,
91 int mpcc_id)
92 {
93 struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
94
95 REG_UPDATE_6(MPCC_SM_CONTROL[mpcc_id],
96 MPCC_SM_EN, sm_cfg->enable,
97 MPCC_SM_MODE, sm_cfg->sm_mode,
98 MPCC_SM_FRAME_ALT, sm_cfg->frame_alt,
99 MPCC_SM_FIELD_ALT, sm_cfg->field_alt,
100 MPCC_SM_FORCE_NEXT_FRAME_POL, sm_cfg->force_next_frame_porlarity,
101 MPCC_SM_FORCE_NEXT_TOP_POL, sm_cfg->force_next_field_polarity);
102 }
mpc1_assert_idle_mpcc(struct mpc * mpc,int id)103 void mpc1_assert_idle_mpcc(struct mpc *mpc, int id)
104 {
105 struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
106
107 ASSERT(!(mpc10->mpcc_in_use_mask & 1 << id));
108 REG_WAIT(MPCC_STATUS[id],
109 MPCC_IDLE, 1,
110 1, 100000);
111 }
112
mpc1_get_mpcc(struct mpc * mpc,int mpcc_id)113 struct mpcc *mpc1_get_mpcc(struct mpc *mpc, int mpcc_id)
114 {
115 struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
116
117 ASSERT(mpcc_id < mpc10->num_mpcc);
118 return &(mpc->mpcc_array[mpcc_id]);
119 }
120
mpc1_get_mpcc_for_dpp(struct mpc_tree * tree,int dpp_id)121 struct mpcc *mpc1_get_mpcc_for_dpp(struct mpc_tree *tree, int dpp_id)
122 {
123 struct mpcc *tmp_mpcc = tree->opp_list;
124
125 while (tmp_mpcc != NULL) {
126 if (tmp_mpcc->dpp_id == dpp_id)
127 return tmp_mpcc;
128
129 /* avoid circular linked list */
130 ASSERT(tmp_mpcc != tmp_mpcc->mpcc_bot);
131 if (tmp_mpcc == tmp_mpcc->mpcc_bot)
132 break;
133
134 tmp_mpcc = tmp_mpcc->mpcc_bot;
135 }
136 return NULL;
137 }
138
mpc1_is_mpcc_idle(struct mpc * mpc,int mpcc_id)139 bool mpc1_is_mpcc_idle(struct mpc *mpc, int mpcc_id)
140 {
141 struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
142 unsigned int top_sel;
143 unsigned int opp_id;
144 unsigned int idle;
145
146 REG_GET(MPCC_TOP_SEL[mpcc_id], MPCC_TOP_SEL, &top_sel);
147 REG_GET(MPCC_OPP_ID[mpcc_id], MPCC_OPP_ID, &opp_id);
148 REG_GET(MPCC_STATUS[mpcc_id], MPCC_IDLE, &idle);
149 if (top_sel == 0xf && opp_id == 0xf && idle)
150 return true;
151 else
152 return false;
153 }
154
mpc1_assert_mpcc_idle_before_connect(struct mpc * mpc,int mpcc_id)155 void mpc1_assert_mpcc_idle_before_connect(struct mpc *mpc, int mpcc_id)
156 {
157 struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
158 unsigned int top_sel, mpc_busy, mpc_idle;
159
160 REG_GET(MPCC_TOP_SEL[mpcc_id],
161 MPCC_TOP_SEL, &top_sel);
162
163 if (top_sel == 0xf) {
164 REG_GET_2(MPCC_STATUS[mpcc_id],
165 MPCC_BUSY, &mpc_busy,
166 MPCC_IDLE, &mpc_idle);
167
168 ASSERT(mpc_busy == 0);
169 ASSERT(mpc_idle == 1);
170 }
171 }
172
173 /*
174 * Insert DPP into MPC tree based on specified blending position.
175 * Only used for planes that are part of blending chain for OPP output
176 *
177 * Parameters:
178 * [in/out] mpc - MPC context.
179 * [in/out] tree - MPC tree structure that plane will be added to.
180 * [in] blnd_cfg - MPCC blending configuration for the new blending layer.
181 * [in] sm_cfg - MPCC stereo mix configuration for the new blending layer.
182 * stereo mix must disable for the very bottom layer of the tree config.
183 * [in] insert_above_mpcc - Insert new plane above this MPCC. If NULL, insert as bottom plane.
184 * [in] dpp_id - DPP instance for the plane to be added.
185 * [in] mpcc_id - The MPCC physical instance to use for blending.
186 *
187 * Return: struct mpcc* - MPCC that was added.
188 */
mpc1_insert_plane(struct mpc * mpc,struct mpc_tree * tree,struct mpcc_blnd_cfg * blnd_cfg,struct mpcc_sm_cfg * sm_cfg,struct mpcc * insert_above_mpcc,int dpp_id,int mpcc_id)189 struct mpcc *mpc1_insert_plane(
190 struct mpc *mpc,
191 struct mpc_tree *tree,
192 struct mpcc_blnd_cfg *blnd_cfg,
193 struct mpcc_sm_cfg *sm_cfg,
194 struct mpcc *insert_above_mpcc,
195 int dpp_id,
196 int mpcc_id)
197 {
198 struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
199 struct mpcc *new_mpcc = NULL;
200
201 /* sanity check parameters */
202 ASSERT(mpcc_id < mpc10->num_mpcc);
203 ASSERT(!(mpc10->mpcc_in_use_mask & 1 << mpcc_id));
204
205 if (insert_above_mpcc) {
206 /* check insert_above_mpcc exist in tree->opp_list */
207 struct mpcc *temp_mpcc = tree->opp_list;
208
209 if (temp_mpcc != insert_above_mpcc)
210 while (temp_mpcc && temp_mpcc->mpcc_bot != insert_above_mpcc)
211 temp_mpcc = temp_mpcc->mpcc_bot;
212 if (temp_mpcc == NULL)
213 return NULL;
214 }
215
216 /* Get and update MPCC struct parameters */
217 new_mpcc = mpc1_get_mpcc(mpc, mpcc_id);
218 new_mpcc->dpp_id = dpp_id;
219
220 /* program mux and MPCC_MODE */
221 if (insert_above_mpcc) {
222 new_mpcc->mpcc_bot = insert_above_mpcc;
223 REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, insert_above_mpcc->mpcc_id);
224 REG_UPDATE(MPCC_CONTROL[mpcc_id], MPCC_MODE, MPCC_BLEND_MODE_TOP_BOT_BLENDING);
225 } else {
226 new_mpcc->mpcc_bot = NULL;
227 REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf);
228 REG_UPDATE(MPCC_CONTROL[mpcc_id], MPCC_MODE, MPCC_BLEND_MODE_TOP_LAYER_ONLY);
229 }
230 REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, dpp_id);
231 REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, tree->opp_id);
232
233 /* Configure VUPDATE lock set for this MPCC to map to the OPP */
234 REG_SET(MPCC_UPDATE_LOCK_SEL[mpcc_id], 0, MPCC_UPDATE_LOCK_SEL, tree->opp_id);
235
236 /* update mpc tree mux setting */
237 if (tree->opp_list == insert_above_mpcc) {
238 /* insert the toppest mpcc */
239 tree->opp_list = new_mpcc;
240 REG_UPDATE(MUX[tree->opp_id], MPC_OUT_MUX, mpcc_id);
241 } else {
242 /* find insert position */
243 struct mpcc *temp_mpcc = tree->opp_list;
244
245 while (temp_mpcc && temp_mpcc->mpcc_bot != insert_above_mpcc)
246 temp_mpcc = temp_mpcc->mpcc_bot;
247 if (temp_mpcc && temp_mpcc->mpcc_bot == insert_above_mpcc) {
248 REG_SET(MPCC_BOT_SEL[temp_mpcc->mpcc_id], 0, MPCC_BOT_SEL, mpcc_id);
249 temp_mpcc->mpcc_bot = new_mpcc;
250 if (!insert_above_mpcc)
251 REG_UPDATE(MPCC_CONTROL[temp_mpcc->mpcc_id],
252 MPCC_MODE, MPCC_BLEND_MODE_TOP_BOT_BLENDING);
253 }
254 }
255
256 /* update the blending configuration */
257 mpc->funcs->update_blending(mpc, blnd_cfg, mpcc_id);
258
259 /* update the stereo mix settings, if provided */
260 if (sm_cfg != NULL) {
261 new_mpcc->sm_cfg = *sm_cfg;
262 mpc1_update_stereo_mix(mpc, sm_cfg, mpcc_id);
263 }
264
265 /* mark this mpcc as in use */
266 mpc10->mpcc_in_use_mask |= 1 << mpcc_id;
267
268 return new_mpcc;
269 }
270
271 /*
272 * Remove a specified MPCC from the MPC tree.
273 *
274 * Parameters:
275 * [in/out] mpc - MPC context.
276 * [in/out] tree - MPC tree structure that plane will be removed from.
277 * [in/out] mpcc - MPCC to be removed from tree.
278 *
279 * Return: void
280 */
mpc1_remove_mpcc(struct mpc * mpc,struct mpc_tree * tree,struct mpcc * mpcc_to_remove)281 void mpc1_remove_mpcc(
282 struct mpc *mpc,
283 struct mpc_tree *tree,
284 struct mpcc *mpcc_to_remove)
285 {
286 struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
287 bool found = false;
288 int mpcc_id = mpcc_to_remove->mpcc_id;
289
290 if (tree->opp_list == mpcc_to_remove) {
291 found = true;
292 /* remove MPCC from top of tree */
293 if (mpcc_to_remove->mpcc_bot) {
294 /* set the next MPCC in list to be the top MPCC */
295 tree->opp_list = mpcc_to_remove->mpcc_bot;
296 REG_UPDATE(MUX[tree->opp_id], MPC_OUT_MUX, tree->opp_list->mpcc_id);
297 } else {
298 /* there are no other MPCC is list */
299 tree->opp_list = NULL;
300 REG_UPDATE(MUX[tree->opp_id], MPC_OUT_MUX, 0xf);
301 }
302 } else {
303 /* find mpcc to remove MPCC list */
304 struct mpcc *temp_mpcc = tree->opp_list;
305
306 while (temp_mpcc && temp_mpcc->mpcc_bot != mpcc_to_remove)
307 temp_mpcc = temp_mpcc->mpcc_bot;
308
309 if (temp_mpcc && temp_mpcc->mpcc_bot == mpcc_to_remove) {
310 found = true;
311 temp_mpcc->mpcc_bot = mpcc_to_remove->mpcc_bot;
312 if (mpcc_to_remove->mpcc_bot) {
313 /* remove MPCC in middle of list */
314 REG_SET(MPCC_BOT_SEL[temp_mpcc->mpcc_id], 0,
315 MPCC_BOT_SEL, mpcc_to_remove->mpcc_bot->mpcc_id);
316 } else {
317 /* remove MPCC from bottom of list */
318 REG_SET(MPCC_BOT_SEL[temp_mpcc->mpcc_id], 0,
319 MPCC_BOT_SEL, 0xf);
320 REG_UPDATE(MPCC_CONTROL[temp_mpcc->mpcc_id],
321 MPCC_MODE, MPCC_BLEND_MODE_TOP_LAYER_PASSTHROUGH);
322 }
323 }
324 }
325
326 if (found) {
327 /* turn off MPCC mux registers */
328 REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, 0xf);
329 REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf);
330 REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, 0xf);
331 REG_SET(MPCC_UPDATE_LOCK_SEL[mpcc_id], 0, MPCC_UPDATE_LOCK_SEL, 0xf);
332
333 /* mark this mpcc as not in use */
334 mpc10->mpcc_in_use_mask &= ~(1 << mpcc_id);
335 mpcc_to_remove->dpp_id = 0xf;
336 mpcc_to_remove->mpcc_bot = NULL;
337 } else {
338 /* In case of resume from S3/S4, remove mpcc from bios left over */
339 REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, 0xf);
340 REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf);
341 REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, 0xf);
342 REG_SET(MPCC_UPDATE_LOCK_SEL[mpcc_id], 0, MPCC_UPDATE_LOCK_SEL, 0xf);
343 }
344 }
345
mpc1_init_mpcc(struct mpcc * mpcc,int mpcc_inst)346 static void mpc1_init_mpcc(struct mpcc *mpcc, int mpcc_inst)
347 {
348 mpcc->mpcc_id = mpcc_inst;
349 mpcc->dpp_id = 0xf;
350 mpcc->mpcc_bot = NULL;
351 mpcc->blnd_cfg.overlap_only = false;
352 mpcc->blnd_cfg.global_alpha = 0xff;
353 mpcc->blnd_cfg.global_gain = 0xff;
354 mpcc->sm_cfg.enable = false;
355 }
356
357 /*
358 * Reset the MPCC HW status by disconnecting all muxes.
359 *
360 * Parameters:
361 * [in/out] mpc - MPC context.
362 *
363 * Return: void
364 */
mpc1_mpc_init(struct mpc * mpc)365 void mpc1_mpc_init(struct mpc *mpc)
366 {
367 struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
368 int mpcc_id;
369 int opp_id;
370
371 mpc10->mpcc_in_use_mask = 0;
372 for (mpcc_id = 0; mpcc_id < mpc10->num_mpcc; mpcc_id++) {
373 REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, 0xf);
374 REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf);
375 REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, 0xf);
376 REG_SET(MPCC_UPDATE_LOCK_SEL[mpcc_id], 0, MPCC_UPDATE_LOCK_SEL, 0xf);
377
378 mpc1_init_mpcc(&(mpc->mpcc_array[mpcc_id]), mpcc_id);
379 }
380
381 for (opp_id = 0; opp_id < MAX_OPP; opp_id++) {
382 if (REG(MUX[opp_id]))
383 REG_UPDATE(MUX[opp_id], MPC_OUT_MUX, 0xf);
384 }
385 }
386
mpc1_mpc_init_single_inst(struct mpc * mpc,unsigned int mpcc_id)387 void mpc1_mpc_init_single_inst(struct mpc *mpc, unsigned int mpcc_id)
388 {
389 struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
390 int opp_id;
391
392 REG_GET(MPCC_OPP_ID[mpcc_id], MPCC_OPP_ID, &opp_id);
393
394 REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, 0xf);
395 REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf);
396 REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, 0xf);
397 REG_SET(MPCC_UPDATE_LOCK_SEL[mpcc_id], 0, MPCC_UPDATE_LOCK_SEL, 0xf);
398
399 mpc1_init_mpcc(&(mpc->mpcc_array[mpcc_id]), mpcc_id);
400
401 if (opp_id < MAX_OPP && REG(MUX[opp_id]))
402 REG_UPDATE(MUX[opp_id], MPC_OUT_MUX, 0xf);
403 }
404
405
mpc1_init_mpcc_list_from_hw(struct mpc * mpc,struct mpc_tree * tree)406 void mpc1_init_mpcc_list_from_hw(
407 struct mpc *mpc,
408 struct mpc_tree *tree)
409 {
410 struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
411 unsigned int opp_id;
412 unsigned int top_sel;
413 unsigned int bot_sel;
414 unsigned int out_mux;
415 struct mpcc *mpcc;
416 int mpcc_id;
417 int bot_mpcc_id;
418
419 REG_GET(MUX[tree->opp_id], MPC_OUT_MUX, &out_mux);
420
421 if (out_mux != 0xf) {
422 for (mpcc_id = 0; mpcc_id < mpc10->num_mpcc; mpcc_id++) {
423 REG_GET(MPCC_OPP_ID[mpcc_id], MPCC_OPP_ID, &opp_id);
424 REG_GET(MPCC_TOP_SEL[mpcc_id], MPCC_TOP_SEL, &top_sel);
425 REG_GET(MPCC_BOT_SEL[mpcc_id], MPCC_BOT_SEL, &bot_sel);
426
427 if (bot_sel == mpcc_id)
428 bot_sel = 0xf;
429
430 if ((opp_id == tree->opp_id) && (top_sel != 0xf)) {
431 mpcc = mpc1_get_mpcc(mpc, mpcc_id);
432 mpcc->dpp_id = top_sel;
433 mpc10->mpcc_in_use_mask |= 1 << mpcc_id;
434
435 if (out_mux == mpcc_id)
436 tree->opp_list = mpcc;
437 if (bot_sel != 0xf && bot_sel < mpc10->num_mpcc) {
438 bot_mpcc_id = bot_sel;
439 REG_GET(MPCC_OPP_ID[bot_mpcc_id], MPCC_OPP_ID, &opp_id);
440 REG_GET(MPCC_TOP_SEL[bot_mpcc_id], MPCC_TOP_SEL, &top_sel);
441 if ((opp_id == tree->opp_id) && (top_sel != 0xf)) {
442 struct mpcc *mpcc_bottom = mpc1_get_mpcc(mpc, bot_mpcc_id);
443
444 mpcc->mpcc_bot = mpcc_bottom;
445 }
446 }
447 }
448 }
449 }
450 }
451
mpc1_read_mpcc_state(struct mpc * mpc,int mpcc_inst,struct mpcc_state * s)452 void mpc1_read_mpcc_state(
453 struct mpc *mpc,
454 int mpcc_inst,
455 struct mpcc_state *s)
456 {
457 struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
458
459 REG_GET(MPCC_OPP_ID[mpcc_inst], MPCC_OPP_ID, &s->opp_id);
460 REG_GET(MPCC_TOP_SEL[mpcc_inst], MPCC_TOP_SEL, &s->dpp_id);
461 REG_GET(MPCC_BOT_SEL[mpcc_inst], MPCC_BOT_SEL, &s->bot_mpcc_id);
462 REG_GET_4(MPCC_CONTROL[mpcc_inst], MPCC_MODE, &s->mode,
463 MPCC_ALPHA_BLND_MODE, &s->alpha_mode,
464 MPCC_ALPHA_MULTIPLIED_MODE, &s->pre_multiplied_alpha,
465 MPCC_BLND_ACTIVE_OVERLAP_ONLY, &s->overlap_only);
466 REG_GET_2(MPCC_STATUS[mpcc_inst], MPCC_IDLE, &s->idle,
467 MPCC_BUSY, &s->busy);
468 }
469
mpc1_cursor_lock(struct mpc * mpc,int opp_id,bool lock)470 void mpc1_cursor_lock(struct mpc *mpc, int opp_id, bool lock)
471 {
472 struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
473
474 REG_SET(CUR[opp_id], 0, CUR_VUPDATE_LOCK_SET, lock ? 1 : 0);
475 }
476
477 static const struct mpc_funcs dcn10_mpc_funcs = {
478 .read_mpcc_state = mpc1_read_mpcc_state,
479 .insert_plane = mpc1_insert_plane,
480 .remove_mpcc = mpc1_remove_mpcc,
481 .mpc_init = mpc1_mpc_init,
482 .mpc_init_single_inst = mpc1_mpc_init_single_inst,
483 .get_mpcc_for_dpp = mpc1_get_mpcc_for_dpp,
484 .wait_for_idle = mpc1_assert_idle_mpcc,
485 .assert_mpcc_idle_before_connect = mpc1_assert_mpcc_idle_before_connect,
486 .init_mpcc_list_from_hw = mpc1_init_mpcc_list_from_hw,
487 .update_blending = mpc1_update_blending,
488 .cursor_lock = mpc1_cursor_lock,
489 .set_denorm = NULL,
490 .set_denorm_clamp = NULL,
491 .set_output_csc = NULL,
492 .set_output_gamma = NULL,
493 };
494
dcn10_mpc_construct(struct dcn10_mpc * mpc10,struct dc_context * ctx,const struct dcn_mpc_registers * mpc_regs,const struct dcn_mpc_shift * mpc_shift,const struct dcn_mpc_mask * mpc_mask,int num_mpcc)495 void dcn10_mpc_construct(struct dcn10_mpc *mpc10,
496 struct dc_context *ctx,
497 const struct dcn_mpc_registers *mpc_regs,
498 const struct dcn_mpc_shift *mpc_shift,
499 const struct dcn_mpc_mask *mpc_mask,
500 int num_mpcc)
501 {
502 int i;
503
504 mpc10->base.ctx = ctx;
505
506 mpc10->base.funcs = &dcn10_mpc_funcs;
507
508 mpc10->mpc_regs = mpc_regs;
509 mpc10->mpc_shift = mpc_shift;
510 mpc10->mpc_mask = mpc_mask;
511
512 mpc10->mpcc_in_use_mask = 0;
513 mpc10->num_mpcc = num_mpcc;
514
515 for (i = 0; i < MAX_MPCC; i++)
516 mpc1_init_mpcc(&mpc10->base.mpcc_array[i], i);
517 }
518
519