1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include <linux/math64.h>
25 #include <linux/pci.h>
26 #include <linux/seq_file.h>
27
28 #include "atom.h"
29 #include "ni_dpm.h"
30 #include "nid.h"
31 #include "r600_dpm.h"
32 #include "radeon.h"
33 #include "radeon_asic.h"
34
35 #define MC_CG_ARB_FREQ_F0 0x0a
36 #define MC_CG_ARB_FREQ_F1 0x0b
37 #define MC_CG_ARB_FREQ_F2 0x0c
38 #define MC_CG_ARB_FREQ_F3 0x0d
39
40 #define SMC_RAM_END 0xC000
41
42 static const struct ni_cac_weights cac_weights_cayman_xt =
43 {
44 0x15,
45 0x2,
46 0x19,
47 0x2,
48 0x8,
49 0x14,
50 0x2,
51 0x16,
52 0xE,
53 0x17,
54 0x13,
55 0x2B,
56 0x10,
57 0x7,
58 0x5,
59 0x5,
60 0x5,
61 0x2,
62 0x3,
63 0x9,
64 0x10,
65 0x10,
66 0x2B,
67 0xA,
68 0x9,
69 0x4,
70 0xD,
71 0xD,
72 0x3E,
73 0x18,
74 0x14,
75 0,
76 0x3,
77 0x3,
78 0x5,
79 0,
80 0x2,
81 0,
82 0,
83 0,
84 0,
85 0,
86 0,
87 0,
88 0,
89 0,
90 0x1CC,
91 0,
92 0x164,
93 1,
94 1,
95 1,
96 1,
97 12,
98 12,
99 12,
100 0x12,
101 0x1F,
102 132,
103 5,
104 7,
105 0,
106 { 0, 0, 0, 0, 0, 0, 0, 0 },
107 { 0, 0, 0, 0 },
108 true
109 };
110
111 static const struct ni_cac_weights cac_weights_cayman_pro =
112 {
113 0x16,
114 0x4,
115 0x10,
116 0x2,
117 0xA,
118 0x16,
119 0x2,
120 0x18,
121 0x10,
122 0x1A,
123 0x16,
124 0x2D,
125 0x12,
126 0xA,
127 0x6,
128 0x6,
129 0x6,
130 0x2,
131 0x4,
132 0xB,
133 0x11,
134 0x11,
135 0x2D,
136 0xC,
137 0xC,
138 0x7,
139 0x10,
140 0x10,
141 0x3F,
142 0x1A,
143 0x16,
144 0,
145 0x7,
146 0x4,
147 0x6,
148 1,
149 0x2,
150 0x1,
151 0,
152 0,
153 0,
154 0,
155 0,
156 0,
157 0x30,
158 0,
159 0x1CF,
160 0,
161 0x166,
162 1,
163 1,
164 1,
165 1,
166 12,
167 12,
168 12,
169 0x15,
170 0x1F,
171 132,
172 6,
173 6,
174 0,
175 { 0, 0, 0, 0, 0, 0, 0, 0 },
176 { 0, 0, 0, 0 },
177 true
178 };
179
180 static const struct ni_cac_weights cac_weights_cayman_le =
181 {
182 0x7,
183 0xE,
184 0x1,
185 0xA,
186 0x1,
187 0x3F,
188 0x2,
189 0x18,
190 0x10,
191 0x1A,
192 0x1,
193 0x3F,
194 0x1,
195 0xE,
196 0x6,
197 0x6,
198 0x6,
199 0x2,
200 0x4,
201 0x9,
202 0x1A,
203 0x1A,
204 0x2C,
205 0xA,
206 0x11,
207 0x8,
208 0x19,
209 0x19,
210 0x1,
211 0x1,
212 0x1A,
213 0,
214 0x8,
215 0x5,
216 0x8,
217 0x1,
218 0x3,
219 0x1,
220 0,
221 0,
222 0,
223 0,
224 0,
225 0,
226 0x38,
227 0x38,
228 0x239,
229 0x3,
230 0x18A,
231 1,
232 1,
233 1,
234 1,
235 12,
236 12,
237 12,
238 0x15,
239 0x22,
240 132,
241 6,
242 6,
243 0,
244 { 0, 0, 0, 0, 0, 0, 0, 0 },
245 { 0, 0, 0, 0 },
246 true
247 };
248
249 #define NISLANDS_MGCG_SEQUENCE 300
250
251 static const u32 cayman_cgcg_cgls_default[] =
252 {
253 0x000008f8, 0x00000010, 0xffffffff,
254 0x000008fc, 0x00000000, 0xffffffff,
255 0x000008f8, 0x00000011, 0xffffffff,
256 0x000008fc, 0x00000000, 0xffffffff,
257 0x000008f8, 0x00000012, 0xffffffff,
258 0x000008fc, 0x00000000, 0xffffffff,
259 0x000008f8, 0x00000013, 0xffffffff,
260 0x000008fc, 0x00000000, 0xffffffff,
261 0x000008f8, 0x00000014, 0xffffffff,
262 0x000008fc, 0x00000000, 0xffffffff,
263 0x000008f8, 0x00000015, 0xffffffff,
264 0x000008fc, 0x00000000, 0xffffffff,
265 0x000008f8, 0x00000016, 0xffffffff,
266 0x000008fc, 0x00000000, 0xffffffff,
267 0x000008f8, 0x00000017, 0xffffffff,
268 0x000008fc, 0x00000000, 0xffffffff,
269 0x000008f8, 0x00000018, 0xffffffff,
270 0x000008fc, 0x00000000, 0xffffffff,
271 0x000008f8, 0x00000019, 0xffffffff,
272 0x000008fc, 0x00000000, 0xffffffff,
273 0x000008f8, 0x0000001a, 0xffffffff,
274 0x000008fc, 0x00000000, 0xffffffff,
275 0x000008f8, 0x0000001b, 0xffffffff,
276 0x000008fc, 0x00000000, 0xffffffff,
277 0x000008f8, 0x00000020, 0xffffffff,
278 0x000008fc, 0x00000000, 0xffffffff,
279 0x000008f8, 0x00000021, 0xffffffff,
280 0x000008fc, 0x00000000, 0xffffffff,
281 0x000008f8, 0x00000022, 0xffffffff,
282 0x000008fc, 0x00000000, 0xffffffff,
283 0x000008f8, 0x00000023, 0xffffffff,
284 0x000008fc, 0x00000000, 0xffffffff,
285 0x000008f8, 0x00000024, 0xffffffff,
286 0x000008fc, 0x00000000, 0xffffffff,
287 0x000008f8, 0x00000025, 0xffffffff,
288 0x000008fc, 0x00000000, 0xffffffff,
289 0x000008f8, 0x00000026, 0xffffffff,
290 0x000008fc, 0x00000000, 0xffffffff,
291 0x000008f8, 0x00000027, 0xffffffff,
292 0x000008fc, 0x00000000, 0xffffffff,
293 0x000008f8, 0x00000028, 0xffffffff,
294 0x000008fc, 0x00000000, 0xffffffff,
295 0x000008f8, 0x00000029, 0xffffffff,
296 0x000008fc, 0x00000000, 0xffffffff,
297 0x000008f8, 0x0000002a, 0xffffffff,
298 0x000008fc, 0x00000000, 0xffffffff,
299 0x000008f8, 0x0000002b, 0xffffffff,
300 0x000008fc, 0x00000000, 0xffffffff
301 };
302 #define CAYMAN_CGCG_CGLS_DEFAULT_LENGTH sizeof(cayman_cgcg_cgls_default) / (3 * sizeof(u32))
303
304 static const u32 cayman_cgcg_cgls_disable[] =
305 {
306 0x000008f8, 0x00000010, 0xffffffff,
307 0x000008fc, 0xffffffff, 0xffffffff,
308 0x000008f8, 0x00000011, 0xffffffff,
309 0x000008fc, 0xffffffff, 0xffffffff,
310 0x000008f8, 0x00000012, 0xffffffff,
311 0x000008fc, 0xffffffff, 0xffffffff,
312 0x000008f8, 0x00000013, 0xffffffff,
313 0x000008fc, 0xffffffff, 0xffffffff,
314 0x000008f8, 0x00000014, 0xffffffff,
315 0x000008fc, 0xffffffff, 0xffffffff,
316 0x000008f8, 0x00000015, 0xffffffff,
317 0x000008fc, 0xffffffff, 0xffffffff,
318 0x000008f8, 0x00000016, 0xffffffff,
319 0x000008fc, 0xffffffff, 0xffffffff,
320 0x000008f8, 0x00000017, 0xffffffff,
321 0x000008fc, 0xffffffff, 0xffffffff,
322 0x000008f8, 0x00000018, 0xffffffff,
323 0x000008fc, 0xffffffff, 0xffffffff,
324 0x000008f8, 0x00000019, 0xffffffff,
325 0x000008fc, 0xffffffff, 0xffffffff,
326 0x000008f8, 0x0000001a, 0xffffffff,
327 0x000008fc, 0xffffffff, 0xffffffff,
328 0x000008f8, 0x0000001b, 0xffffffff,
329 0x000008fc, 0xffffffff, 0xffffffff,
330 0x000008f8, 0x00000020, 0xffffffff,
331 0x000008fc, 0x00000000, 0xffffffff,
332 0x000008f8, 0x00000021, 0xffffffff,
333 0x000008fc, 0x00000000, 0xffffffff,
334 0x000008f8, 0x00000022, 0xffffffff,
335 0x000008fc, 0x00000000, 0xffffffff,
336 0x000008f8, 0x00000023, 0xffffffff,
337 0x000008fc, 0x00000000, 0xffffffff,
338 0x000008f8, 0x00000024, 0xffffffff,
339 0x000008fc, 0x00000000, 0xffffffff,
340 0x000008f8, 0x00000025, 0xffffffff,
341 0x000008fc, 0x00000000, 0xffffffff,
342 0x000008f8, 0x00000026, 0xffffffff,
343 0x000008fc, 0x00000000, 0xffffffff,
344 0x000008f8, 0x00000027, 0xffffffff,
345 0x000008fc, 0x00000000, 0xffffffff,
346 0x000008f8, 0x00000028, 0xffffffff,
347 0x000008fc, 0x00000000, 0xffffffff,
348 0x000008f8, 0x00000029, 0xffffffff,
349 0x000008fc, 0x00000000, 0xffffffff,
350 0x000008f8, 0x0000002a, 0xffffffff,
351 0x000008fc, 0x00000000, 0xffffffff,
352 0x000008f8, 0x0000002b, 0xffffffff,
353 0x000008fc, 0x00000000, 0xffffffff,
354 0x00000644, 0x000f7902, 0x001f4180,
355 0x00000644, 0x000f3802, 0x001f4180
356 };
357 #define CAYMAN_CGCG_CGLS_DISABLE_LENGTH sizeof(cayman_cgcg_cgls_disable) / (3 * sizeof(u32))
358
359 static const u32 cayman_cgcg_cgls_enable[] =
360 {
361 0x00000644, 0x000f7882, 0x001f4080,
362 0x000008f8, 0x00000010, 0xffffffff,
363 0x000008fc, 0x00000000, 0xffffffff,
364 0x000008f8, 0x00000011, 0xffffffff,
365 0x000008fc, 0x00000000, 0xffffffff,
366 0x000008f8, 0x00000012, 0xffffffff,
367 0x000008fc, 0x00000000, 0xffffffff,
368 0x000008f8, 0x00000013, 0xffffffff,
369 0x000008fc, 0x00000000, 0xffffffff,
370 0x000008f8, 0x00000014, 0xffffffff,
371 0x000008fc, 0x00000000, 0xffffffff,
372 0x000008f8, 0x00000015, 0xffffffff,
373 0x000008fc, 0x00000000, 0xffffffff,
374 0x000008f8, 0x00000016, 0xffffffff,
375 0x000008fc, 0x00000000, 0xffffffff,
376 0x000008f8, 0x00000017, 0xffffffff,
377 0x000008fc, 0x00000000, 0xffffffff,
378 0x000008f8, 0x00000018, 0xffffffff,
379 0x000008fc, 0x00000000, 0xffffffff,
380 0x000008f8, 0x00000019, 0xffffffff,
381 0x000008fc, 0x00000000, 0xffffffff,
382 0x000008f8, 0x0000001a, 0xffffffff,
383 0x000008fc, 0x00000000, 0xffffffff,
384 0x000008f8, 0x0000001b, 0xffffffff,
385 0x000008fc, 0x00000000, 0xffffffff,
386 0x000008f8, 0x00000020, 0xffffffff,
387 0x000008fc, 0xffffffff, 0xffffffff,
388 0x000008f8, 0x00000021, 0xffffffff,
389 0x000008fc, 0xffffffff, 0xffffffff,
390 0x000008f8, 0x00000022, 0xffffffff,
391 0x000008fc, 0xffffffff, 0xffffffff,
392 0x000008f8, 0x00000023, 0xffffffff,
393 0x000008fc, 0xffffffff, 0xffffffff,
394 0x000008f8, 0x00000024, 0xffffffff,
395 0x000008fc, 0xffffffff, 0xffffffff,
396 0x000008f8, 0x00000025, 0xffffffff,
397 0x000008fc, 0xffffffff, 0xffffffff,
398 0x000008f8, 0x00000026, 0xffffffff,
399 0x000008fc, 0xffffffff, 0xffffffff,
400 0x000008f8, 0x00000027, 0xffffffff,
401 0x000008fc, 0xffffffff, 0xffffffff,
402 0x000008f8, 0x00000028, 0xffffffff,
403 0x000008fc, 0xffffffff, 0xffffffff,
404 0x000008f8, 0x00000029, 0xffffffff,
405 0x000008fc, 0xffffffff, 0xffffffff,
406 0x000008f8, 0x0000002a, 0xffffffff,
407 0x000008fc, 0xffffffff, 0xffffffff,
408 0x000008f8, 0x0000002b, 0xffffffff,
409 0x000008fc, 0xffffffff, 0xffffffff
410 };
411 #define CAYMAN_CGCG_CGLS_ENABLE_LENGTH sizeof(cayman_cgcg_cgls_enable) / (3 * sizeof(u32))
412
413 static const u32 cayman_mgcg_default[] =
414 {
415 0x0000802c, 0xc0000000, 0xffffffff,
416 0x00003fc4, 0xc0000000, 0xffffffff,
417 0x00005448, 0x00000100, 0xffffffff,
418 0x000055e4, 0x00000100, 0xffffffff,
419 0x0000160c, 0x00000100, 0xffffffff,
420 0x00008984, 0x06000100, 0xffffffff,
421 0x0000c164, 0x00000100, 0xffffffff,
422 0x00008a18, 0x00000100, 0xffffffff,
423 0x0000897c, 0x06000100, 0xffffffff,
424 0x00008b28, 0x00000100, 0xffffffff,
425 0x00009144, 0x00800200, 0xffffffff,
426 0x00009a60, 0x00000100, 0xffffffff,
427 0x00009868, 0x00000100, 0xffffffff,
428 0x00008d58, 0x00000100, 0xffffffff,
429 0x00009510, 0x00000100, 0xffffffff,
430 0x0000949c, 0x00000100, 0xffffffff,
431 0x00009654, 0x00000100, 0xffffffff,
432 0x00009030, 0x00000100, 0xffffffff,
433 0x00009034, 0x00000100, 0xffffffff,
434 0x00009038, 0x00000100, 0xffffffff,
435 0x0000903c, 0x00000100, 0xffffffff,
436 0x00009040, 0x00000100, 0xffffffff,
437 0x0000a200, 0x00000100, 0xffffffff,
438 0x0000a204, 0x00000100, 0xffffffff,
439 0x0000a208, 0x00000100, 0xffffffff,
440 0x0000a20c, 0x00000100, 0xffffffff,
441 0x00009744, 0x00000100, 0xffffffff,
442 0x00003f80, 0x00000100, 0xffffffff,
443 0x0000a210, 0x00000100, 0xffffffff,
444 0x0000a214, 0x00000100, 0xffffffff,
445 0x000004d8, 0x00000100, 0xffffffff,
446 0x00009664, 0x00000100, 0xffffffff,
447 0x00009698, 0x00000100, 0xffffffff,
448 0x000004d4, 0x00000200, 0xffffffff,
449 0x000004d0, 0x00000000, 0xffffffff,
450 0x000030cc, 0x00000104, 0xffffffff,
451 0x0000d0c0, 0x00000100, 0xffffffff,
452 0x0000d8c0, 0x00000100, 0xffffffff,
453 0x0000802c, 0x40000000, 0xffffffff,
454 0x00003fc4, 0x40000000, 0xffffffff,
455 0x0000915c, 0x00010000, 0xffffffff,
456 0x00009160, 0x00030002, 0xffffffff,
457 0x00009164, 0x00050004, 0xffffffff,
458 0x00009168, 0x00070006, 0xffffffff,
459 0x00009178, 0x00070000, 0xffffffff,
460 0x0000917c, 0x00030002, 0xffffffff,
461 0x00009180, 0x00050004, 0xffffffff,
462 0x0000918c, 0x00010006, 0xffffffff,
463 0x00009190, 0x00090008, 0xffffffff,
464 0x00009194, 0x00070000, 0xffffffff,
465 0x00009198, 0x00030002, 0xffffffff,
466 0x0000919c, 0x00050004, 0xffffffff,
467 0x000091a8, 0x00010006, 0xffffffff,
468 0x000091ac, 0x00090008, 0xffffffff,
469 0x000091b0, 0x00070000, 0xffffffff,
470 0x000091b4, 0x00030002, 0xffffffff,
471 0x000091b8, 0x00050004, 0xffffffff,
472 0x000091c4, 0x00010006, 0xffffffff,
473 0x000091c8, 0x00090008, 0xffffffff,
474 0x000091cc, 0x00070000, 0xffffffff,
475 0x000091d0, 0x00030002, 0xffffffff,
476 0x000091d4, 0x00050004, 0xffffffff,
477 0x000091e0, 0x00010006, 0xffffffff,
478 0x000091e4, 0x00090008, 0xffffffff,
479 0x000091e8, 0x00000000, 0xffffffff,
480 0x000091ec, 0x00070000, 0xffffffff,
481 0x000091f0, 0x00030002, 0xffffffff,
482 0x000091f4, 0x00050004, 0xffffffff,
483 0x00009200, 0x00010006, 0xffffffff,
484 0x00009204, 0x00090008, 0xffffffff,
485 0x00009208, 0x00070000, 0xffffffff,
486 0x0000920c, 0x00030002, 0xffffffff,
487 0x00009210, 0x00050004, 0xffffffff,
488 0x0000921c, 0x00010006, 0xffffffff,
489 0x00009220, 0x00090008, 0xffffffff,
490 0x00009224, 0x00070000, 0xffffffff,
491 0x00009228, 0x00030002, 0xffffffff,
492 0x0000922c, 0x00050004, 0xffffffff,
493 0x00009238, 0x00010006, 0xffffffff,
494 0x0000923c, 0x00090008, 0xffffffff,
495 0x00009240, 0x00070000, 0xffffffff,
496 0x00009244, 0x00030002, 0xffffffff,
497 0x00009248, 0x00050004, 0xffffffff,
498 0x00009254, 0x00010006, 0xffffffff,
499 0x00009258, 0x00090008, 0xffffffff,
500 0x0000925c, 0x00070000, 0xffffffff,
501 0x00009260, 0x00030002, 0xffffffff,
502 0x00009264, 0x00050004, 0xffffffff,
503 0x00009270, 0x00010006, 0xffffffff,
504 0x00009274, 0x00090008, 0xffffffff,
505 0x00009278, 0x00070000, 0xffffffff,
506 0x0000927c, 0x00030002, 0xffffffff,
507 0x00009280, 0x00050004, 0xffffffff,
508 0x0000928c, 0x00010006, 0xffffffff,
509 0x00009290, 0x00090008, 0xffffffff,
510 0x000092a8, 0x00070000, 0xffffffff,
511 0x000092ac, 0x00030002, 0xffffffff,
512 0x000092b0, 0x00050004, 0xffffffff,
513 0x000092bc, 0x00010006, 0xffffffff,
514 0x000092c0, 0x00090008, 0xffffffff,
515 0x000092c4, 0x00070000, 0xffffffff,
516 0x000092c8, 0x00030002, 0xffffffff,
517 0x000092cc, 0x00050004, 0xffffffff,
518 0x000092d8, 0x00010006, 0xffffffff,
519 0x000092dc, 0x00090008, 0xffffffff,
520 0x00009294, 0x00000000, 0xffffffff,
521 0x0000802c, 0x40010000, 0xffffffff,
522 0x00003fc4, 0x40010000, 0xffffffff,
523 0x0000915c, 0x00010000, 0xffffffff,
524 0x00009160, 0x00030002, 0xffffffff,
525 0x00009164, 0x00050004, 0xffffffff,
526 0x00009168, 0x00070006, 0xffffffff,
527 0x00009178, 0x00070000, 0xffffffff,
528 0x0000917c, 0x00030002, 0xffffffff,
529 0x00009180, 0x00050004, 0xffffffff,
530 0x0000918c, 0x00010006, 0xffffffff,
531 0x00009190, 0x00090008, 0xffffffff,
532 0x00009194, 0x00070000, 0xffffffff,
533 0x00009198, 0x00030002, 0xffffffff,
534 0x0000919c, 0x00050004, 0xffffffff,
535 0x000091a8, 0x00010006, 0xffffffff,
536 0x000091ac, 0x00090008, 0xffffffff,
537 0x000091b0, 0x00070000, 0xffffffff,
538 0x000091b4, 0x00030002, 0xffffffff,
539 0x000091b8, 0x00050004, 0xffffffff,
540 0x000091c4, 0x00010006, 0xffffffff,
541 0x000091c8, 0x00090008, 0xffffffff,
542 0x000091cc, 0x00070000, 0xffffffff,
543 0x000091d0, 0x00030002, 0xffffffff,
544 0x000091d4, 0x00050004, 0xffffffff,
545 0x000091e0, 0x00010006, 0xffffffff,
546 0x000091e4, 0x00090008, 0xffffffff,
547 0x000091e8, 0x00000000, 0xffffffff,
548 0x000091ec, 0x00070000, 0xffffffff,
549 0x000091f0, 0x00030002, 0xffffffff,
550 0x000091f4, 0x00050004, 0xffffffff,
551 0x00009200, 0x00010006, 0xffffffff,
552 0x00009204, 0x00090008, 0xffffffff,
553 0x00009208, 0x00070000, 0xffffffff,
554 0x0000920c, 0x00030002, 0xffffffff,
555 0x00009210, 0x00050004, 0xffffffff,
556 0x0000921c, 0x00010006, 0xffffffff,
557 0x00009220, 0x00090008, 0xffffffff,
558 0x00009224, 0x00070000, 0xffffffff,
559 0x00009228, 0x00030002, 0xffffffff,
560 0x0000922c, 0x00050004, 0xffffffff,
561 0x00009238, 0x00010006, 0xffffffff,
562 0x0000923c, 0x00090008, 0xffffffff,
563 0x00009240, 0x00070000, 0xffffffff,
564 0x00009244, 0x00030002, 0xffffffff,
565 0x00009248, 0x00050004, 0xffffffff,
566 0x00009254, 0x00010006, 0xffffffff,
567 0x00009258, 0x00090008, 0xffffffff,
568 0x0000925c, 0x00070000, 0xffffffff,
569 0x00009260, 0x00030002, 0xffffffff,
570 0x00009264, 0x00050004, 0xffffffff,
571 0x00009270, 0x00010006, 0xffffffff,
572 0x00009274, 0x00090008, 0xffffffff,
573 0x00009278, 0x00070000, 0xffffffff,
574 0x0000927c, 0x00030002, 0xffffffff,
575 0x00009280, 0x00050004, 0xffffffff,
576 0x0000928c, 0x00010006, 0xffffffff,
577 0x00009290, 0x00090008, 0xffffffff,
578 0x000092a8, 0x00070000, 0xffffffff,
579 0x000092ac, 0x00030002, 0xffffffff,
580 0x000092b0, 0x00050004, 0xffffffff,
581 0x000092bc, 0x00010006, 0xffffffff,
582 0x000092c0, 0x00090008, 0xffffffff,
583 0x000092c4, 0x00070000, 0xffffffff,
584 0x000092c8, 0x00030002, 0xffffffff,
585 0x000092cc, 0x00050004, 0xffffffff,
586 0x000092d8, 0x00010006, 0xffffffff,
587 0x000092dc, 0x00090008, 0xffffffff,
588 0x00009294, 0x00000000, 0xffffffff,
589 0x0000802c, 0xc0000000, 0xffffffff,
590 0x00003fc4, 0xc0000000, 0xffffffff,
591 0x000008f8, 0x00000010, 0xffffffff,
592 0x000008fc, 0x00000000, 0xffffffff,
593 0x000008f8, 0x00000011, 0xffffffff,
594 0x000008fc, 0x00000000, 0xffffffff,
595 0x000008f8, 0x00000012, 0xffffffff,
596 0x000008fc, 0x00000000, 0xffffffff,
597 0x000008f8, 0x00000013, 0xffffffff,
598 0x000008fc, 0x00000000, 0xffffffff,
599 0x000008f8, 0x00000014, 0xffffffff,
600 0x000008fc, 0x00000000, 0xffffffff,
601 0x000008f8, 0x00000015, 0xffffffff,
602 0x000008fc, 0x00000000, 0xffffffff,
603 0x000008f8, 0x00000016, 0xffffffff,
604 0x000008fc, 0x00000000, 0xffffffff,
605 0x000008f8, 0x00000017, 0xffffffff,
606 0x000008fc, 0x00000000, 0xffffffff,
607 0x000008f8, 0x00000018, 0xffffffff,
608 0x000008fc, 0x00000000, 0xffffffff,
609 0x000008f8, 0x00000019, 0xffffffff,
610 0x000008fc, 0x00000000, 0xffffffff,
611 0x000008f8, 0x0000001a, 0xffffffff,
612 0x000008fc, 0x00000000, 0xffffffff,
613 0x000008f8, 0x0000001b, 0xffffffff,
614 0x000008fc, 0x00000000, 0xffffffff
615 };
616 #define CAYMAN_MGCG_DEFAULT_LENGTH sizeof(cayman_mgcg_default) / (3 * sizeof(u32))
617
618 static const u32 cayman_mgcg_disable[] =
619 {
620 0x0000802c, 0xc0000000, 0xffffffff,
621 0x000008f8, 0x00000000, 0xffffffff,
622 0x000008fc, 0xffffffff, 0xffffffff,
623 0x000008f8, 0x00000001, 0xffffffff,
624 0x000008fc, 0xffffffff, 0xffffffff,
625 0x000008f8, 0x00000002, 0xffffffff,
626 0x000008fc, 0xffffffff, 0xffffffff,
627 0x000008f8, 0x00000003, 0xffffffff,
628 0x000008fc, 0xffffffff, 0xffffffff,
629 0x00009150, 0x00600000, 0xffffffff
630 };
631 #define CAYMAN_MGCG_DISABLE_LENGTH sizeof(cayman_mgcg_disable) / (3 * sizeof(u32))
632
633 static const u32 cayman_mgcg_enable[] =
634 {
635 0x0000802c, 0xc0000000, 0xffffffff,
636 0x000008f8, 0x00000000, 0xffffffff,
637 0x000008fc, 0x00000000, 0xffffffff,
638 0x000008f8, 0x00000001, 0xffffffff,
639 0x000008fc, 0x00000000, 0xffffffff,
640 0x000008f8, 0x00000002, 0xffffffff,
641 0x000008fc, 0x00600000, 0xffffffff,
642 0x000008f8, 0x00000003, 0xffffffff,
643 0x000008fc, 0x00000000, 0xffffffff,
644 0x00009150, 0x96944200, 0xffffffff
645 };
646
647 #define CAYMAN_MGCG_ENABLE_LENGTH sizeof(cayman_mgcg_enable) / (3 * sizeof(u32))
648
649 #define NISLANDS_SYSLS_SEQUENCE 100
650
651 static const u32 cayman_sysls_default[] =
652 {
653 /* Register, Value, Mask bits */
654 0x000055e8, 0x00000000, 0xffffffff,
655 0x0000d0bc, 0x00000000, 0xffffffff,
656 0x0000d8bc, 0x00000000, 0xffffffff,
657 0x000015c0, 0x000c1401, 0xffffffff,
658 0x0000264c, 0x000c0400, 0xffffffff,
659 0x00002648, 0x000c0400, 0xffffffff,
660 0x00002650, 0x000c0400, 0xffffffff,
661 0x000020b8, 0x000c0400, 0xffffffff,
662 0x000020bc, 0x000c0400, 0xffffffff,
663 0x000020c0, 0x000c0c80, 0xffffffff,
664 0x0000f4a0, 0x000000c0, 0xffffffff,
665 0x0000f4a4, 0x00680fff, 0xffffffff,
666 0x00002f50, 0x00000404, 0xffffffff,
667 0x000004c8, 0x00000001, 0xffffffff,
668 0x000064ec, 0x00000000, 0xffffffff,
669 0x00000c7c, 0x00000000, 0xffffffff,
670 0x00008dfc, 0x00000000, 0xffffffff
671 };
672 #define CAYMAN_SYSLS_DEFAULT_LENGTH sizeof(cayman_sysls_default) / (3 * sizeof(u32))
673
674 static const u32 cayman_sysls_disable[] =
675 {
676 /* Register, Value, Mask bits */
677 0x0000d0c0, 0x00000000, 0xffffffff,
678 0x0000d8c0, 0x00000000, 0xffffffff,
679 0x000055e8, 0x00000000, 0xffffffff,
680 0x0000d0bc, 0x00000000, 0xffffffff,
681 0x0000d8bc, 0x00000000, 0xffffffff,
682 0x000015c0, 0x00041401, 0xffffffff,
683 0x0000264c, 0x00040400, 0xffffffff,
684 0x00002648, 0x00040400, 0xffffffff,
685 0x00002650, 0x00040400, 0xffffffff,
686 0x000020b8, 0x00040400, 0xffffffff,
687 0x000020bc, 0x00040400, 0xffffffff,
688 0x000020c0, 0x00040c80, 0xffffffff,
689 0x0000f4a0, 0x000000c0, 0xffffffff,
690 0x0000f4a4, 0x00680000, 0xffffffff,
691 0x00002f50, 0x00000404, 0xffffffff,
692 0x000004c8, 0x00000001, 0xffffffff,
693 0x000064ec, 0x00007ffd, 0xffffffff,
694 0x00000c7c, 0x0000ff00, 0xffffffff,
695 0x00008dfc, 0x0000007f, 0xffffffff
696 };
697 #define CAYMAN_SYSLS_DISABLE_LENGTH sizeof(cayman_sysls_disable) / (3 * sizeof(u32))
698
699 static const u32 cayman_sysls_enable[] =
700 {
701 /* Register, Value, Mask bits */
702 0x000055e8, 0x00000001, 0xffffffff,
703 0x0000d0bc, 0x00000100, 0xffffffff,
704 0x0000d8bc, 0x00000100, 0xffffffff,
705 0x000015c0, 0x000c1401, 0xffffffff,
706 0x0000264c, 0x000c0400, 0xffffffff,
707 0x00002648, 0x000c0400, 0xffffffff,
708 0x00002650, 0x000c0400, 0xffffffff,
709 0x000020b8, 0x000c0400, 0xffffffff,
710 0x000020bc, 0x000c0400, 0xffffffff,
711 0x000020c0, 0x000c0c80, 0xffffffff,
712 0x0000f4a0, 0x000000c0, 0xffffffff,
713 0x0000f4a4, 0x00680fff, 0xffffffff,
714 0x00002f50, 0x00000903, 0xffffffff,
715 0x000004c8, 0x00000000, 0xffffffff,
716 0x000064ec, 0x00000000, 0xffffffff,
717 0x00000c7c, 0x00000000, 0xffffffff,
718 0x00008dfc, 0x00000000, 0xffffffff
719 };
720 #define CAYMAN_SYSLS_ENABLE_LENGTH sizeof(cayman_sysls_enable) / (3 * sizeof(u32))
721
722 struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev);
723 struct evergreen_power_info *evergreen_get_pi(struct radeon_device *rdev);
724
725 extern int ni_mc_load_microcode(struct radeon_device *rdev);
726
ni_get_pi(struct radeon_device * rdev)727 struct ni_power_info *ni_get_pi(struct radeon_device *rdev)
728 {
729 struct ni_power_info *pi = rdev->pm.dpm.priv;
730
731 return pi;
732 }
733
ni_get_ps(struct radeon_ps * rps)734 struct ni_ps *ni_get_ps(struct radeon_ps *rps)
735 {
736 struct ni_ps *ps = rps->ps_priv;
737
738 return ps;
739 }
740
ni_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients * coeff,u16 v,s32 t,u32 ileakage,u32 * leakage)741 static void ni_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff,
742 u16 v, s32 t,
743 u32 ileakage,
744 u32 *leakage)
745 {
746 s64 kt, kv, leakage_w, i_leakage, vddc, temperature;
747
748 i_leakage = div64_s64(drm_int2fixp(ileakage), 1000);
749 vddc = div64_s64(drm_int2fixp(v), 1000);
750 temperature = div64_s64(drm_int2fixp(t), 1000);
751
752 kt = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->at), 1000),
753 drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bt), 1000), temperature)));
754 kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 1000),
755 drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 1000), vddc)));
756
757 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
758
759 *leakage = drm_fixp2int(leakage_w * 1000);
760 }
761
ni_calculate_leakage_for_v_and_t(struct radeon_device * rdev,const struct ni_leakage_coeffients * coeff,u16 v,s32 t,u32 i_leakage,u32 * leakage)762 static void ni_calculate_leakage_for_v_and_t(struct radeon_device *rdev,
763 const struct ni_leakage_coeffients *coeff,
764 u16 v,
765 s32 t,
766 u32 i_leakage,
767 u32 *leakage)
768 {
769 ni_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage);
770 }
771
ni_dpm_vblank_too_short(struct radeon_device * rdev)772 bool ni_dpm_vblank_too_short(struct radeon_device *rdev)
773 {
774 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
775 u32 vblank_time = r600_dpm_get_vblank_time(rdev);
776 /* we never hit the non-gddr5 limit so disable it */
777 u32 switch_limit = pi->mem_gddr5 ? 450 : 0;
778
779 if (vblank_time < switch_limit)
780 return true;
781 else
782 return false;
783
784 }
785
ni_apply_state_adjust_rules(struct radeon_device * rdev,struct radeon_ps * rps)786 static void ni_apply_state_adjust_rules(struct radeon_device *rdev,
787 struct radeon_ps *rps)
788 {
789 struct ni_ps *ps = ni_get_ps(rps);
790 struct radeon_clock_and_voltage_limits *max_limits;
791 bool disable_mclk_switching;
792 u32 mclk;
793 u16 vddci;
794 int i;
795
796 if ((rdev->pm.dpm.new_active_crtc_count > 1) ||
797 ni_dpm_vblank_too_short(rdev))
798 disable_mclk_switching = true;
799 else
800 disable_mclk_switching = false;
801
802 if (rdev->pm.dpm.ac_power)
803 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
804 else
805 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
806
807 if (rdev->pm.dpm.ac_power == false) {
808 for (i = 0; i < ps->performance_level_count; i++) {
809 if (ps->performance_levels[i].mclk > max_limits->mclk)
810 ps->performance_levels[i].mclk = max_limits->mclk;
811 if (ps->performance_levels[i].sclk > max_limits->sclk)
812 ps->performance_levels[i].sclk = max_limits->sclk;
813 if (ps->performance_levels[i].vddc > max_limits->vddc)
814 ps->performance_levels[i].vddc = max_limits->vddc;
815 if (ps->performance_levels[i].vddci > max_limits->vddci)
816 ps->performance_levels[i].vddci = max_limits->vddci;
817 }
818 }
819
820 /* XXX validate the min clocks required for display */
821
822 /* adjust low state */
823 if (disable_mclk_switching) {
824 ps->performance_levels[0].mclk =
825 ps->performance_levels[ps->performance_level_count - 1].mclk;
826 ps->performance_levels[0].vddci =
827 ps->performance_levels[ps->performance_level_count - 1].vddci;
828 }
829
830 btc_skip_blacklist_clocks(rdev, max_limits->sclk, max_limits->mclk,
831 &ps->performance_levels[0].sclk,
832 &ps->performance_levels[0].mclk);
833
834 for (i = 1; i < ps->performance_level_count; i++) {
835 if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk)
836 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk;
837 if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc)
838 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc;
839 }
840
841 /* adjust remaining states */
842 if (disable_mclk_switching) {
843 mclk = ps->performance_levels[0].mclk;
844 vddci = ps->performance_levels[0].vddci;
845 for (i = 1; i < ps->performance_level_count; i++) {
846 if (mclk < ps->performance_levels[i].mclk)
847 mclk = ps->performance_levels[i].mclk;
848 if (vddci < ps->performance_levels[i].vddci)
849 vddci = ps->performance_levels[i].vddci;
850 }
851 for (i = 0; i < ps->performance_level_count; i++) {
852 ps->performance_levels[i].mclk = mclk;
853 ps->performance_levels[i].vddci = vddci;
854 }
855 } else {
856 for (i = 1; i < ps->performance_level_count; i++) {
857 if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk)
858 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk;
859 if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci)
860 ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci;
861 }
862 }
863
864 for (i = 1; i < ps->performance_level_count; i++)
865 btc_skip_blacklist_clocks(rdev, max_limits->sclk, max_limits->mclk,
866 &ps->performance_levels[i].sclk,
867 &ps->performance_levels[i].mclk);
868
869 for (i = 0; i < ps->performance_level_count; i++)
870 btc_adjust_clock_combinations(rdev, max_limits,
871 &ps->performance_levels[i]);
872
873 for (i = 0; i < ps->performance_level_count; i++) {
874 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
875 ps->performance_levels[i].sclk,
876 max_limits->vddc, &ps->performance_levels[i].vddc);
877 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
878 ps->performance_levels[i].mclk,
879 max_limits->vddci, &ps->performance_levels[i].vddci);
880 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
881 ps->performance_levels[i].mclk,
882 max_limits->vddc, &ps->performance_levels[i].vddc);
883 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk,
884 rdev->clock.current_dispclk,
885 max_limits->vddc, &ps->performance_levels[i].vddc);
886 }
887
888 for (i = 0; i < ps->performance_level_count; i++) {
889 btc_apply_voltage_delta_rules(rdev,
890 max_limits->vddc, max_limits->vddci,
891 &ps->performance_levels[i].vddc,
892 &ps->performance_levels[i].vddci);
893 }
894
895 ps->dc_compatible = true;
896 for (i = 0; i < ps->performance_level_count; i++) {
897 if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc)
898 ps->dc_compatible = false;
899
900 if (ps->performance_levels[i].vddc < rdev->pm.dpm.dyn_state.min_vddc_for_pcie_gen2)
901 ps->performance_levels[i].flags &= ~ATOM_PPLIB_R600_FLAGS_PCIEGEN2;
902 }
903 }
904
ni_cg_clockgating_default(struct radeon_device * rdev)905 static void ni_cg_clockgating_default(struct radeon_device *rdev)
906 {
907 u32 count;
908 const u32 *ps = NULL;
909
910 ps = (const u32 *)&cayman_cgcg_cgls_default;
911 count = CAYMAN_CGCG_CGLS_DEFAULT_LENGTH;
912
913 btc_program_mgcg_hw_sequence(rdev, ps, count);
914 }
915
ni_gfx_clockgating_enable(struct radeon_device * rdev,bool enable)916 static void ni_gfx_clockgating_enable(struct radeon_device *rdev,
917 bool enable)
918 {
919 u32 count;
920 const u32 *ps = NULL;
921
922 if (enable) {
923 ps = (const u32 *)&cayman_cgcg_cgls_enable;
924 count = CAYMAN_CGCG_CGLS_ENABLE_LENGTH;
925 } else {
926 ps = (const u32 *)&cayman_cgcg_cgls_disable;
927 count = CAYMAN_CGCG_CGLS_DISABLE_LENGTH;
928 }
929
930 btc_program_mgcg_hw_sequence(rdev, ps, count);
931 }
932
ni_mg_clockgating_default(struct radeon_device * rdev)933 static void ni_mg_clockgating_default(struct radeon_device *rdev)
934 {
935 u32 count;
936 const u32 *ps = NULL;
937
938 ps = (const u32 *)&cayman_mgcg_default;
939 count = CAYMAN_MGCG_DEFAULT_LENGTH;
940
941 btc_program_mgcg_hw_sequence(rdev, ps, count);
942 }
943
ni_mg_clockgating_enable(struct radeon_device * rdev,bool enable)944 static void ni_mg_clockgating_enable(struct radeon_device *rdev,
945 bool enable)
946 {
947 u32 count;
948 const u32 *ps = NULL;
949
950 if (enable) {
951 ps = (const u32 *)&cayman_mgcg_enable;
952 count = CAYMAN_MGCG_ENABLE_LENGTH;
953 } else {
954 ps = (const u32 *)&cayman_mgcg_disable;
955 count = CAYMAN_MGCG_DISABLE_LENGTH;
956 }
957
958 btc_program_mgcg_hw_sequence(rdev, ps, count);
959 }
960
ni_ls_clockgating_default(struct radeon_device * rdev)961 static void ni_ls_clockgating_default(struct radeon_device *rdev)
962 {
963 u32 count;
964 const u32 *ps = NULL;
965
966 ps = (const u32 *)&cayman_sysls_default;
967 count = CAYMAN_SYSLS_DEFAULT_LENGTH;
968
969 btc_program_mgcg_hw_sequence(rdev, ps, count);
970 }
971
ni_ls_clockgating_enable(struct radeon_device * rdev,bool enable)972 static void ni_ls_clockgating_enable(struct radeon_device *rdev,
973 bool enable)
974 {
975 u32 count;
976 const u32 *ps = NULL;
977
978 if (enable) {
979 ps = (const u32 *)&cayman_sysls_enable;
980 count = CAYMAN_SYSLS_ENABLE_LENGTH;
981 } else {
982 ps = (const u32 *)&cayman_sysls_disable;
983 count = CAYMAN_SYSLS_DISABLE_LENGTH;
984 }
985
986 btc_program_mgcg_hw_sequence(rdev, ps, count);
987
988 }
989
ni_patch_single_dependency_table_based_on_leakage(struct radeon_device * rdev,struct radeon_clock_voltage_dependency_table * table)990 static int ni_patch_single_dependency_table_based_on_leakage(struct radeon_device *rdev,
991 struct radeon_clock_voltage_dependency_table *table)
992 {
993 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
994 u32 i;
995
996 if (table) {
997 for (i = 0; i < table->count; i++) {
998 if (0xff01 == table->entries[i].v) {
999 if (pi->max_vddc == 0)
1000 return -EINVAL;
1001 table->entries[i].v = pi->max_vddc;
1002 }
1003 }
1004 }
1005 return 0;
1006 }
1007
ni_patch_dependency_tables_based_on_leakage(struct radeon_device * rdev)1008 static int ni_patch_dependency_tables_based_on_leakage(struct radeon_device *rdev)
1009 {
1010 int ret = 0;
1011
1012 ret = ni_patch_single_dependency_table_based_on_leakage(rdev,
1013 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk);
1014
1015 ret = ni_patch_single_dependency_table_based_on_leakage(rdev,
1016 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk);
1017 return ret;
1018 }
1019
ni_stop_dpm(struct radeon_device * rdev)1020 static void ni_stop_dpm(struct radeon_device *rdev)
1021 {
1022 WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN);
1023 }
1024
1025 #if 0
1026 static int ni_notify_hw_of_power_source(struct radeon_device *rdev,
1027 bool ac_power)
1028 {
1029 if (ac_power)
1030 return (rv770_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ?
1031 0 : -EINVAL;
1032
1033 return 0;
1034 }
1035 #endif
1036
ni_send_msg_to_smc_with_parameter(struct radeon_device * rdev,PPSMC_Msg msg,u32 parameter)1037 static PPSMC_Result ni_send_msg_to_smc_with_parameter(struct radeon_device *rdev,
1038 PPSMC_Msg msg, u32 parameter)
1039 {
1040 WREG32(SMC_SCRATCH0, parameter);
1041 return rv770_send_msg_to_smc(rdev, msg);
1042 }
1043
ni_restrict_performance_levels_before_switch(struct radeon_device * rdev)1044 static int ni_restrict_performance_levels_before_switch(struct radeon_device *rdev)
1045 {
1046 if (rv770_send_msg_to_smc(rdev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK)
1047 return -EINVAL;
1048
1049 return (ni_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ?
1050 0 : -EINVAL;
1051 }
1052
ni_dpm_force_performance_level(struct radeon_device * rdev,enum radeon_dpm_forced_level level)1053 int ni_dpm_force_performance_level(struct radeon_device *rdev,
1054 enum radeon_dpm_forced_level level)
1055 {
1056 if (level == RADEON_DPM_FORCED_LEVEL_HIGH) {
1057 if (ni_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 0) != PPSMC_Result_OK)
1058 return -EINVAL;
1059
1060 if (ni_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK)
1061 return -EINVAL;
1062 } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) {
1063 if (ni_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
1064 return -EINVAL;
1065
1066 if (ni_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK)
1067 return -EINVAL;
1068 } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) {
1069 if (ni_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
1070 return -EINVAL;
1071
1072 if (ni_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 0) != PPSMC_Result_OK)
1073 return -EINVAL;
1074 }
1075
1076 rdev->pm.dpm.forced_level = level;
1077
1078 return 0;
1079 }
1080
ni_stop_smc(struct radeon_device * rdev)1081 static void ni_stop_smc(struct radeon_device *rdev)
1082 {
1083 u32 tmp;
1084 int i;
1085
1086 for (i = 0; i < rdev->usec_timeout; i++) {
1087 tmp = RREG32(LB_SYNC_RESET_SEL) & LB_SYNC_RESET_SEL_MASK;
1088 if (tmp != 1)
1089 break;
1090 udelay(1);
1091 }
1092
1093 udelay(100);
1094
1095 r7xx_stop_smc(rdev);
1096 }
1097
ni_process_firmware_header(struct radeon_device * rdev)1098 static int ni_process_firmware_header(struct radeon_device *rdev)
1099 {
1100 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1101 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1102 struct ni_power_info *ni_pi = ni_get_pi(rdev);
1103 u32 tmp;
1104 int ret;
1105
1106 ret = rv770_read_smc_sram_dword(rdev,
1107 NISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
1108 NISLANDS_SMC_FIRMWARE_HEADER_stateTable,
1109 &tmp, pi->sram_end);
1110
1111 if (ret)
1112 return ret;
1113
1114 pi->state_table_start = (u16)tmp;
1115
1116 ret = rv770_read_smc_sram_dword(rdev,
1117 NISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
1118 NISLANDS_SMC_FIRMWARE_HEADER_softRegisters,
1119 &tmp, pi->sram_end);
1120
1121 if (ret)
1122 return ret;
1123
1124 pi->soft_regs_start = (u16)tmp;
1125
1126 ret = rv770_read_smc_sram_dword(rdev,
1127 NISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
1128 NISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable,
1129 &tmp, pi->sram_end);
1130
1131 if (ret)
1132 return ret;
1133
1134 eg_pi->mc_reg_table_start = (u16)tmp;
1135
1136 ret = rv770_read_smc_sram_dword(rdev,
1137 NISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
1138 NISLANDS_SMC_FIRMWARE_HEADER_fanTable,
1139 &tmp, pi->sram_end);
1140
1141 if (ret)
1142 return ret;
1143
1144 ni_pi->fan_table_start = (u16)tmp;
1145
1146 ret = rv770_read_smc_sram_dword(rdev,
1147 NISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
1148 NISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable,
1149 &tmp, pi->sram_end);
1150
1151 if (ret)
1152 return ret;
1153
1154 ni_pi->arb_table_start = (u16)tmp;
1155
1156 ret = rv770_read_smc_sram_dword(rdev,
1157 NISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
1158 NISLANDS_SMC_FIRMWARE_HEADER_cacTable,
1159 &tmp, pi->sram_end);
1160
1161 if (ret)
1162 return ret;
1163
1164 ni_pi->cac_table_start = (u16)tmp;
1165
1166 ret = rv770_read_smc_sram_dword(rdev,
1167 NISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
1168 NISLANDS_SMC_FIRMWARE_HEADER_spllTable,
1169 &tmp, pi->sram_end);
1170
1171 if (ret)
1172 return ret;
1173
1174 ni_pi->spll_table_start = (u16)tmp;
1175
1176
1177 return ret;
1178 }
1179
ni_read_clock_registers(struct radeon_device * rdev)1180 static void ni_read_clock_registers(struct radeon_device *rdev)
1181 {
1182 struct ni_power_info *ni_pi = ni_get_pi(rdev);
1183
1184 ni_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL);
1185 ni_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2);
1186 ni_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3);
1187 ni_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4);
1188 ni_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM);
1189 ni_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2);
1190 ni_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);
1191 ni_pi->clock_registers.mpll_ad_func_cntl_2 = RREG32(MPLL_AD_FUNC_CNTL_2);
1192 ni_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);
1193 ni_pi->clock_registers.mpll_dq_func_cntl_2 = RREG32(MPLL_DQ_FUNC_CNTL_2);
1194 ni_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);
1195 ni_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL);
1196 ni_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);
1197 ni_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);
1198 }
1199
1200 #if 0
1201 static int ni_enter_ulp_state(struct radeon_device *rdev)
1202 {
1203 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1204
1205 if (pi->gfx_clock_gating) {
1206 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN);
1207 WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON);
1208 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON);
1209 RREG32(GB_ADDR_CONFIG);
1210 }
1211
1212 WREG32_P(SMC_MSG, HOST_SMC_MSG(PPSMC_MSG_SwitchToMinimumPower),
1213 ~HOST_SMC_MSG_MASK);
1214
1215 udelay(25000);
1216
1217 return 0;
1218 }
1219 #endif
1220
ni_program_response_times(struct radeon_device * rdev)1221 static void ni_program_response_times(struct radeon_device *rdev)
1222 {
1223 u32 voltage_response_time, backbias_response_time, acpi_delay_time, vbi_time_out;
1224 u32 vddc_dly, bb_dly, acpi_dly, vbi_dly, mclk_switch_limit;
1225 u32 reference_clock;
1226
1227 rv770_write_smc_soft_register(rdev, NI_SMC_SOFT_REGISTER_mvdd_chg_time, 1);
1228
1229 voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time;
1230 backbias_response_time = (u32)rdev->pm.dpm.backbias_response_time;
1231
1232 if (voltage_response_time == 0)
1233 voltage_response_time = 1000;
1234
1235 if (backbias_response_time == 0)
1236 backbias_response_time = 1000;
1237
1238 acpi_delay_time = 15000;
1239 vbi_time_out = 100000;
1240
1241 reference_clock = radeon_get_xclk(rdev);
1242
1243 vddc_dly = (voltage_response_time * reference_clock) / 1600;
1244 bb_dly = (backbias_response_time * reference_clock) / 1600;
1245 acpi_dly = (acpi_delay_time * reference_clock) / 1600;
1246 vbi_dly = (vbi_time_out * reference_clock) / 1600;
1247
1248 mclk_switch_limit = (460 * reference_clock) / 100;
1249
1250 rv770_write_smc_soft_register(rdev, NI_SMC_SOFT_REGISTER_delay_vreg, vddc_dly);
1251 rv770_write_smc_soft_register(rdev, NI_SMC_SOFT_REGISTER_delay_bbias, bb_dly);
1252 rv770_write_smc_soft_register(rdev, NI_SMC_SOFT_REGISTER_delay_acpi, acpi_dly);
1253 rv770_write_smc_soft_register(rdev, NI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly);
1254 rv770_write_smc_soft_register(rdev, NI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA);
1255 rv770_write_smc_soft_register(rdev, NI_SMC_SOFT_REGISTER_mclk_switch_lim, mclk_switch_limit);
1256 }
1257
ni_populate_smc_voltage_table(struct radeon_device * rdev,struct atom_voltage_table * voltage_table,NISLANDS_SMC_STATETABLE * table)1258 static void ni_populate_smc_voltage_table(struct radeon_device *rdev,
1259 struct atom_voltage_table *voltage_table,
1260 NISLANDS_SMC_STATETABLE *table)
1261 {
1262 unsigned int i;
1263
1264 for (i = 0; i < voltage_table->count; i++) {
1265 table->highSMIO[i] = 0;
1266 table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low);
1267 }
1268 }
1269
ni_populate_smc_voltage_tables(struct radeon_device * rdev,NISLANDS_SMC_STATETABLE * table)1270 static void ni_populate_smc_voltage_tables(struct radeon_device *rdev,
1271 NISLANDS_SMC_STATETABLE *table)
1272 {
1273 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1274 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1275 unsigned char i;
1276
1277 if (eg_pi->vddc_voltage_table.count) {
1278 ni_populate_smc_voltage_table(rdev, &eg_pi->vddc_voltage_table, table);
1279 table->voltageMaskTable.highMask[NISLANDS_SMC_VOLTAGEMASK_VDDC] = 0;
1280 table->voltageMaskTable.lowMask[NISLANDS_SMC_VOLTAGEMASK_VDDC] =
1281 cpu_to_be32(eg_pi->vddc_voltage_table.mask_low);
1282
1283 for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) {
1284 if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) {
1285 table->maxVDDCIndexInPPTable = i;
1286 break;
1287 }
1288 }
1289 }
1290
1291 if (eg_pi->vddci_voltage_table.count) {
1292 ni_populate_smc_voltage_table(rdev, &eg_pi->vddci_voltage_table, table);
1293
1294 table->voltageMaskTable.highMask[NISLANDS_SMC_VOLTAGEMASK_VDDCI] = 0;
1295 table->voltageMaskTable.lowMask[NISLANDS_SMC_VOLTAGEMASK_VDDCI] =
1296 cpu_to_be32(eg_pi->vddci_voltage_table.mask_low);
1297 }
1298 }
1299
ni_populate_voltage_value(struct radeon_device * rdev,struct atom_voltage_table * table,u16 value,NISLANDS_SMC_VOLTAGE_VALUE * voltage)1300 static int ni_populate_voltage_value(struct radeon_device *rdev,
1301 struct atom_voltage_table *table,
1302 u16 value,
1303 NISLANDS_SMC_VOLTAGE_VALUE *voltage)
1304 {
1305 unsigned int i;
1306
1307 for (i = 0; i < table->count; i++) {
1308 if (value <= table->entries[i].value) {
1309 voltage->index = (u8)i;
1310 voltage->value = cpu_to_be16(table->entries[i].value);
1311 break;
1312 }
1313 }
1314
1315 if (i >= table->count)
1316 return -EINVAL;
1317
1318 return 0;
1319 }
1320
ni_populate_mvdd_value(struct radeon_device * rdev,u32 mclk,NISLANDS_SMC_VOLTAGE_VALUE * voltage)1321 static void ni_populate_mvdd_value(struct radeon_device *rdev,
1322 u32 mclk,
1323 NISLANDS_SMC_VOLTAGE_VALUE *voltage)
1324 {
1325 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1326 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1327
1328 if (!pi->mvdd_control) {
1329 voltage->index = eg_pi->mvdd_high_index;
1330 voltage->value = cpu_to_be16(MVDD_HIGH_VALUE);
1331 return;
1332 }
1333
1334 if (mclk <= pi->mvdd_split_frequency) {
1335 voltage->index = eg_pi->mvdd_low_index;
1336 voltage->value = cpu_to_be16(MVDD_LOW_VALUE);
1337 } else {
1338 voltage->index = eg_pi->mvdd_high_index;
1339 voltage->value = cpu_to_be16(MVDD_HIGH_VALUE);
1340 }
1341 }
1342
ni_get_std_voltage_value(struct radeon_device * rdev,NISLANDS_SMC_VOLTAGE_VALUE * voltage,u16 * std_voltage)1343 static int ni_get_std_voltage_value(struct radeon_device *rdev,
1344 NISLANDS_SMC_VOLTAGE_VALUE *voltage,
1345 u16 *std_voltage)
1346 {
1347 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries &&
1348 ((u32)voltage->index < rdev->pm.dpm.dyn_state.cac_leakage_table.count))
1349 *std_voltage = rdev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc;
1350 else
1351 *std_voltage = be16_to_cpu(voltage->value);
1352
1353 return 0;
1354 }
1355
ni_populate_std_voltage_value(struct radeon_device * rdev,u16 value,u8 index,NISLANDS_SMC_VOLTAGE_VALUE * voltage)1356 static void ni_populate_std_voltage_value(struct radeon_device *rdev,
1357 u16 value, u8 index,
1358 NISLANDS_SMC_VOLTAGE_VALUE *voltage)
1359 {
1360 voltage->index = index;
1361 voltage->value = cpu_to_be16(value);
1362 }
1363
ni_get_smc_power_scaling_factor(struct radeon_device * rdev)1364 static u32 ni_get_smc_power_scaling_factor(struct radeon_device *rdev)
1365 {
1366 u32 xclk_period;
1367 u32 xclk = radeon_get_xclk(rdev);
1368 u32 tmp = RREG32(CG_CAC_CTRL) & TID_CNT_MASK;
1369
1370 xclk_period = (1000000000UL / xclk);
1371 xclk_period /= 10000UL;
1372
1373 return tmp * xclk_period;
1374 }
1375
ni_scale_power_for_smc(u32 power_in_watts,u32 scaling_factor)1376 static u32 ni_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor)
1377 {
1378 return (power_in_watts * scaling_factor) << 2;
1379 }
1380
ni_calculate_power_boost_limit(struct radeon_device * rdev,struct radeon_ps * radeon_state,u32 near_tdp_limit)1381 static u32 ni_calculate_power_boost_limit(struct radeon_device *rdev,
1382 struct radeon_ps *radeon_state,
1383 u32 near_tdp_limit)
1384 {
1385 struct ni_ps *state = ni_get_ps(radeon_state);
1386 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1387 struct ni_power_info *ni_pi = ni_get_pi(rdev);
1388 u32 power_boost_limit = 0;
1389 int ret;
1390
1391 if (ni_pi->enable_power_containment &&
1392 ni_pi->use_power_boost_limit) {
1393 NISLANDS_SMC_VOLTAGE_VALUE vddc;
1394 u16 std_vddc_med;
1395 u16 std_vddc_high;
1396 u64 tmp, n, d;
1397
1398 if (state->performance_level_count < 3)
1399 return 0;
1400
1401 ret = ni_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
1402 state->performance_levels[state->performance_level_count - 2].vddc,
1403 &vddc);
1404 if (ret)
1405 return 0;
1406
1407 ret = ni_get_std_voltage_value(rdev, &vddc, &std_vddc_med);
1408 if (ret)
1409 return 0;
1410
1411 ret = ni_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
1412 state->performance_levels[state->performance_level_count - 1].vddc,
1413 &vddc);
1414 if (ret)
1415 return 0;
1416
1417 ret = ni_get_std_voltage_value(rdev, &vddc, &std_vddc_high);
1418 if (ret)
1419 return 0;
1420
1421 n = ((u64)near_tdp_limit * ((u64)std_vddc_med * (u64)std_vddc_med) * 90);
1422 d = ((u64)std_vddc_high * (u64)std_vddc_high * 100);
1423 tmp = div64_u64(n, d);
1424
1425 if (tmp >> 32)
1426 return 0;
1427 power_boost_limit = (u32)tmp;
1428 }
1429
1430 return power_boost_limit;
1431 }
1432
ni_calculate_adjusted_tdp_limits(struct radeon_device * rdev,bool adjust_polarity,u32 tdp_adjustment,u32 * tdp_limit,u32 * near_tdp_limit)1433 static int ni_calculate_adjusted_tdp_limits(struct radeon_device *rdev,
1434 bool adjust_polarity,
1435 u32 tdp_adjustment,
1436 u32 *tdp_limit,
1437 u32 *near_tdp_limit)
1438 {
1439 if (tdp_adjustment > (u32)rdev->pm.dpm.tdp_od_limit)
1440 return -EINVAL;
1441
1442 if (adjust_polarity) {
1443 *tdp_limit = ((100 + tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100;
1444 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit + (*tdp_limit - rdev->pm.dpm.tdp_limit);
1445 } else {
1446 *tdp_limit = ((100 - tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100;
1447 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit - (rdev->pm.dpm.tdp_limit - *tdp_limit);
1448 }
1449
1450 return 0;
1451 }
1452
ni_populate_smc_tdp_limits(struct radeon_device * rdev,struct radeon_ps * radeon_state)1453 static int ni_populate_smc_tdp_limits(struct radeon_device *rdev,
1454 struct radeon_ps *radeon_state)
1455 {
1456 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1457 struct ni_power_info *ni_pi = ni_get_pi(rdev);
1458
1459 if (ni_pi->enable_power_containment) {
1460 NISLANDS_SMC_STATETABLE *smc_table = &ni_pi->smc_statetable;
1461 u32 scaling_factor = ni_get_smc_power_scaling_factor(rdev);
1462 u32 tdp_limit;
1463 u32 near_tdp_limit;
1464 u32 power_boost_limit;
1465 int ret;
1466
1467 if (scaling_factor == 0)
1468 return -EINVAL;
1469
1470 memset(smc_table, 0, sizeof(NISLANDS_SMC_STATETABLE));
1471
1472 ret = ni_calculate_adjusted_tdp_limits(rdev,
1473 false, /* ??? */
1474 rdev->pm.dpm.tdp_adjustment,
1475 &tdp_limit,
1476 &near_tdp_limit);
1477 if (ret)
1478 return ret;
1479
1480 power_boost_limit = ni_calculate_power_boost_limit(rdev, radeon_state,
1481 near_tdp_limit);
1482
1483 smc_table->dpm2Params.TDPLimit =
1484 cpu_to_be32(ni_scale_power_for_smc(tdp_limit, scaling_factor));
1485 smc_table->dpm2Params.NearTDPLimit =
1486 cpu_to_be32(ni_scale_power_for_smc(near_tdp_limit, scaling_factor));
1487 smc_table->dpm2Params.SafePowerLimit =
1488 cpu_to_be32(ni_scale_power_for_smc((near_tdp_limit * NISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100,
1489 scaling_factor));
1490 smc_table->dpm2Params.PowerBoostLimit =
1491 cpu_to_be32(ni_scale_power_for_smc(power_boost_limit, scaling_factor));
1492
1493 ret = rv770_copy_bytes_to_smc(rdev,
1494 (u16)(pi->state_table_start + offsetof(NISLANDS_SMC_STATETABLE, dpm2Params) +
1495 offsetof(PP_NIslands_DPM2Parameters, TDPLimit)),
1496 (u8 *)(&smc_table->dpm2Params.TDPLimit),
1497 sizeof(u32) * 4, pi->sram_end);
1498 if (ret)
1499 return ret;
1500 }
1501
1502 return 0;
1503 }
1504
ni_copy_and_switch_arb_sets(struct radeon_device * rdev,u32 arb_freq_src,u32 arb_freq_dest)1505 int ni_copy_and_switch_arb_sets(struct radeon_device *rdev,
1506 u32 arb_freq_src, u32 arb_freq_dest)
1507 {
1508 u32 mc_arb_dram_timing;
1509 u32 mc_arb_dram_timing2;
1510 u32 burst_time;
1511 u32 mc_cg_config;
1512
1513 switch (arb_freq_src) {
1514 case MC_CG_ARB_FREQ_F0:
1515 mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING);
1516 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
1517 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE0_MASK) >> STATE0_SHIFT;
1518 break;
1519 case MC_CG_ARB_FREQ_F1:
1520 mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_1);
1521 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_1);
1522 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE1_MASK) >> STATE1_SHIFT;
1523 break;
1524 case MC_CG_ARB_FREQ_F2:
1525 mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_2);
1526 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_2);
1527 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE2_MASK) >> STATE2_SHIFT;
1528 break;
1529 case MC_CG_ARB_FREQ_F3:
1530 mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_3);
1531 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_3);
1532 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE3_MASK) >> STATE3_SHIFT;
1533 break;
1534 default:
1535 return -EINVAL;
1536 }
1537
1538 switch (arb_freq_dest) {
1539 case MC_CG_ARB_FREQ_F0:
1540 WREG32(MC_ARB_DRAM_TIMING, mc_arb_dram_timing);
1541 WREG32(MC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);
1542 WREG32_P(MC_ARB_BURST_TIME, STATE0(burst_time), ~STATE0_MASK);
1543 break;
1544 case MC_CG_ARB_FREQ_F1:
1545 WREG32(MC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);
1546 WREG32(MC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);
1547 WREG32_P(MC_ARB_BURST_TIME, STATE1(burst_time), ~STATE1_MASK);
1548 break;
1549 case MC_CG_ARB_FREQ_F2:
1550 WREG32(MC_ARB_DRAM_TIMING_2, mc_arb_dram_timing);
1551 WREG32(MC_ARB_DRAM_TIMING2_2, mc_arb_dram_timing2);
1552 WREG32_P(MC_ARB_BURST_TIME, STATE2(burst_time), ~STATE2_MASK);
1553 break;
1554 case MC_CG_ARB_FREQ_F3:
1555 WREG32(MC_ARB_DRAM_TIMING_3, mc_arb_dram_timing);
1556 WREG32(MC_ARB_DRAM_TIMING2_3, mc_arb_dram_timing2);
1557 WREG32_P(MC_ARB_BURST_TIME, STATE3(burst_time), ~STATE3_MASK);
1558 break;
1559 default:
1560 return -EINVAL;
1561 }
1562
1563 mc_cg_config = RREG32(MC_CG_CONFIG) | 0x0000000F;
1564 WREG32(MC_CG_CONFIG, mc_cg_config);
1565 WREG32_P(MC_ARB_CG, CG_ARB_REQ(arb_freq_dest), ~CG_ARB_REQ_MASK);
1566
1567 return 0;
1568 }
1569
ni_init_arb_table_index(struct radeon_device * rdev)1570 static int ni_init_arb_table_index(struct radeon_device *rdev)
1571 {
1572 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1573 struct ni_power_info *ni_pi = ni_get_pi(rdev);
1574 u32 tmp;
1575 int ret;
1576
1577 ret = rv770_read_smc_sram_dword(rdev, ni_pi->arb_table_start,
1578 &tmp, pi->sram_end);
1579 if (ret)
1580 return ret;
1581
1582 tmp &= 0x00FFFFFF;
1583 tmp |= ((u32)MC_CG_ARB_FREQ_F1) << 24;
1584
1585 return rv770_write_smc_sram_dword(rdev, ni_pi->arb_table_start,
1586 tmp, pi->sram_end);
1587 }
1588
ni_initial_switch_from_arb_f0_to_f1(struct radeon_device * rdev)1589 static int ni_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev)
1590 {
1591 return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
1592 }
1593
ni_force_switch_to_arb_f0(struct radeon_device * rdev)1594 static int ni_force_switch_to_arb_f0(struct radeon_device *rdev)
1595 {
1596 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1597 struct ni_power_info *ni_pi = ni_get_pi(rdev);
1598 u32 tmp;
1599 int ret;
1600
1601 ret = rv770_read_smc_sram_dword(rdev, ni_pi->arb_table_start,
1602 &tmp, pi->sram_end);
1603 if (ret)
1604 return ret;
1605
1606 tmp = (tmp >> 24) & 0xff;
1607
1608 if (tmp == MC_CG_ARB_FREQ_F0)
1609 return 0;
1610
1611 return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0);
1612 }
1613
ni_populate_memory_timing_parameters(struct radeon_device * rdev,struct rv7xx_pl * pl,SMC_NIslands_MCArbDramTimingRegisterSet * arb_regs)1614 static int ni_populate_memory_timing_parameters(struct radeon_device *rdev,
1615 struct rv7xx_pl *pl,
1616 SMC_NIslands_MCArbDramTimingRegisterSet *arb_regs)
1617 {
1618 u32 dram_timing;
1619 u32 dram_timing2;
1620
1621 arb_regs->mc_arb_rfsh_rate =
1622 (u8)rv770_calculate_memory_refresh_rate(rdev, pl->sclk);
1623
1624
1625 radeon_atom_set_engine_dram_timings(rdev, pl->sclk, pl->mclk);
1626
1627 dram_timing = RREG32(MC_ARB_DRAM_TIMING);
1628 dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
1629
1630 arb_regs->mc_arb_dram_timing = cpu_to_be32(dram_timing);
1631 arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2);
1632
1633 return 0;
1634 }
1635
ni_do_program_memory_timing_parameters(struct radeon_device * rdev,struct radeon_ps * radeon_state,unsigned int first_arb_set)1636 static int ni_do_program_memory_timing_parameters(struct radeon_device *rdev,
1637 struct radeon_ps *radeon_state,
1638 unsigned int first_arb_set)
1639 {
1640 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1641 struct ni_power_info *ni_pi = ni_get_pi(rdev);
1642 struct ni_ps *state = ni_get_ps(radeon_state);
1643 SMC_NIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
1644 int i, ret = 0;
1645
1646 for (i = 0; i < state->performance_level_count; i++) {
1647 ret = ni_populate_memory_timing_parameters(rdev, &state->performance_levels[i], &arb_regs);
1648 if (ret)
1649 break;
1650
1651 ret = rv770_copy_bytes_to_smc(rdev,
1652 (u16)(ni_pi->arb_table_start +
1653 offsetof(SMC_NIslands_MCArbDramTimingRegisters, data) +
1654 sizeof(SMC_NIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i)),
1655 (u8 *)&arb_regs,
1656 (u16)sizeof(SMC_NIslands_MCArbDramTimingRegisterSet),
1657 pi->sram_end);
1658 if (ret)
1659 break;
1660 }
1661 return ret;
1662 }
1663
ni_program_memory_timing_parameters(struct radeon_device * rdev,struct radeon_ps * radeon_new_state)1664 static int ni_program_memory_timing_parameters(struct radeon_device *rdev,
1665 struct radeon_ps *radeon_new_state)
1666 {
1667 return ni_do_program_memory_timing_parameters(rdev, radeon_new_state,
1668 NISLANDS_DRIVER_STATE_ARB_INDEX);
1669 }
1670
ni_populate_initial_mvdd_value(struct radeon_device * rdev,struct NISLANDS_SMC_VOLTAGE_VALUE * voltage)1671 static void ni_populate_initial_mvdd_value(struct radeon_device *rdev,
1672 struct NISLANDS_SMC_VOLTAGE_VALUE *voltage)
1673 {
1674 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1675
1676 voltage->index = eg_pi->mvdd_high_index;
1677 voltage->value = cpu_to_be16(MVDD_HIGH_VALUE);
1678 }
1679
ni_populate_smc_initial_state(struct radeon_device * rdev,struct radeon_ps * radeon_initial_state,NISLANDS_SMC_STATETABLE * table)1680 static int ni_populate_smc_initial_state(struct radeon_device *rdev,
1681 struct radeon_ps *radeon_initial_state,
1682 NISLANDS_SMC_STATETABLE *table)
1683 {
1684 struct ni_ps *initial_state = ni_get_ps(radeon_initial_state);
1685 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1686 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1687 struct ni_power_info *ni_pi = ni_get_pi(rdev);
1688 u32 reg;
1689 int ret;
1690
1691 table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
1692 cpu_to_be32(ni_pi->clock_registers.mpll_ad_func_cntl);
1693 table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL_2 =
1694 cpu_to_be32(ni_pi->clock_registers.mpll_ad_func_cntl_2);
1695 table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
1696 cpu_to_be32(ni_pi->clock_registers.mpll_dq_func_cntl);
1697 table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL_2 =
1698 cpu_to_be32(ni_pi->clock_registers.mpll_dq_func_cntl_2);
1699 table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
1700 cpu_to_be32(ni_pi->clock_registers.mclk_pwrmgt_cntl);
1701 table->initialState.levels[0].mclk.vDLL_CNTL =
1702 cpu_to_be32(ni_pi->clock_registers.dll_cntl);
1703 table->initialState.levels[0].mclk.vMPLL_SS =
1704 cpu_to_be32(ni_pi->clock_registers.mpll_ss1);
1705 table->initialState.levels[0].mclk.vMPLL_SS2 =
1706 cpu_to_be32(ni_pi->clock_registers.mpll_ss2);
1707 table->initialState.levels[0].mclk.mclk_value =
1708 cpu_to_be32(initial_state->performance_levels[0].mclk);
1709
1710 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
1711 cpu_to_be32(ni_pi->clock_registers.cg_spll_func_cntl);
1712 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
1713 cpu_to_be32(ni_pi->clock_registers.cg_spll_func_cntl_2);
1714 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
1715 cpu_to_be32(ni_pi->clock_registers.cg_spll_func_cntl_3);
1716 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
1717 cpu_to_be32(ni_pi->clock_registers.cg_spll_func_cntl_4);
1718 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM =
1719 cpu_to_be32(ni_pi->clock_registers.cg_spll_spread_spectrum);
1720 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 =
1721 cpu_to_be32(ni_pi->clock_registers.cg_spll_spread_spectrum_2);
1722 table->initialState.levels[0].sclk.sclk_value =
1723 cpu_to_be32(initial_state->performance_levels[0].sclk);
1724 table->initialState.levels[0].arbRefreshState =
1725 NISLANDS_INITIAL_STATE_ARB_INDEX;
1726
1727 table->initialState.levels[0].ACIndex = 0;
1728
1729 ret = ni_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
1730 initial_state->performance_levels[0].vddc,
1731 &table->initialState.levels[0].vddc);
1732 if (!ret) {
1733 u16 std_vddc;
1734
1735 ret = ni_get_std_voltage_value(rdev,
1736 &table->initialState.levels[0].vddc,
1737 &std_vddc);
1738 if (!ret)
1739 ni_populate_std_voltage_value(rdev, std_vddc,
1740 table->initialState.levels[0].vddc.index,
1741 &table->initialState.levels[0].std_vddc);
1742 }
1743
1744 if (eg_pi->vddci_control)
1745 ni_populate_voltage_value(rdev,
1746 &eg_pi->vddci_voltage_table,
1747 initial_state->performance_levels[0].vddci,
1748 &table->initialState.levels[0].vddci);
1749
1750 ni_populate_initial_mvdd_value(rdev, &table->initialState.levels[0].mvdd);
1751
1752 reg = CG_R(0xffff) | CG_L(0);
1753 table->initialState.levels[0].aT = cpu_to_be32(reg);
1754
1755 table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp);
1756
1757 if (pi->boot_in_gen2)
1758 table->initialState.levels[0].gen2PCIE = 1;
1759 else
1760 table->initialState.levels[0].gen2PCIE = 0;
1761
1762 if (pi->mem_gddr5) {
1763 table->initialState.levels[0].strobeMode =
1764 cypress_get_strobe_mode_settings(rdev,
1765 initial_state->performance_levels[0].mclk);
1766
1767 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold)
1768 table->initialState.levels[0].mcFlags = NISLANDS_SMC_MC_EDC_RD_FLAG | NISLANDS_SMC_MC_EDC_WR_FLAG;
1769 else
1770 table->initialState.levels[0].mcFlags = 0;
1771 }
1772
1773 table->initialState.levelCount = 1;
1774
1775 table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC;
1776
1777 table->initialState.levels[0].dpm2.MaxPS = 0;
1778 table->initialState.levels[0].dpm2.NearTDPDec = 0;
1779 table->initialState.levels[0].dpm2.AboveSafeInc = 0;
1780 table->initialState.levels[0].dpm2.BelowSafeInc = 0;
1781
1782 reg = MIN_POWER_MASK | MAX_POWER_MASK;
1783 table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
1784
1785 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
1786 table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
1787
1788 return 0;
1789 }
1790
ni_populate_smc_acpi_state(struct radeon_device * rdev,NISLANDS_SMC_STATETABLE * table)1791 static int ni_populate_smc_acpi_state(struct radeon_device *rdev,
1792 NISLANDS_SMC_STATETABLE *table)
1793 {
1794 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1795 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1796 struct ni_power_info *ni_pi = ni_get_pi(rdev);
1797 u32 mpll_ad_func_cntl = ni_pi->clock_registers.mpll_ad_func_cntl;
1798 u32 mpll_ad_func_cntl_2 = ni_pi->clock_registers.mpll_ad_func_cntl_2;
1799 u32 mpll_dq_func_cntl = ni_pi->clock_registers.mpll_dq_func_cntl;
1800 u32 mpll_dq_func_cntl_2 = ni_pi->clock_registers.mpll_dq_func_cntl_2;
1801 u32 spll_func_cntl = ni_pi->clock_registers.cg_spll_func_cntl;
1802 u32 spll_func_cntl_2 = ni_pi->clock_registers.cg_spll_func_cntl_2;
1803 u32 spll_func_cntl_3 = ni_pi->clock_registers.cg_spll_func_cntl_3;
1804 u32 spll_func_cntl_4 = ni_pi->clock_registers.cg_spll_func_cntl_4;
1805 u32 mclk_pwrmgt_cntl = ni_pi->clock_registers.mclk_pwrmgt_cntl;
1806 u32 dll_cntl = ni_pi->clock_registers.dll_cntl;
1807 u32 reg;
1808 int ret;
1809
1810 table->ACPIState = table->initialState;
1811
1812 table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC;
1813
1814 if (pi->acpi_vddc) {
1815 ret = ni_populate_voltage_value(rdev,
1816 &eg_pi->vddc_voltage_table,
1817 pi->acpi_vddc, &table->ACPIState.levels[0].vddc);
1818 if (!ret) {
1819 u16 std_vddc;
1820
1821 ret = ni_get_std_voltage_value(rdev,
1822 &table->ACPIState.levels[0].vddc, &std_vddc);
1823 if (!ret)
1824 ni_populate_std_voltage_value(rdev, std_vddc,
1825 table->ACPIState.levels[0].vddc.index,
1826 &table->ACPIState.levels[0].std_vddc);
1827 }
1828
1829 if (pi->pcie_gen2) {
1830 if (pi->acpi_pcie_gen2)
1831 table->ACPIState.levels[0].gen2PCIE = 1;
1832 else
1833 table->ACPIState.levels[0].gen2PCIE = 0;
1834 } else {
1835 table->ACPIState.levels[0].gen2PCIE = 0;
1836 }
1837 } else {
1838 ret = ni_populate_voltage_value(rdev,
1839 &eg_pi->vddc_voltage_table,
1840 pi->min_vddc_in_table,
1841 &table->ACPIState.levels[0].vddc);
1842 if (!ret) {
1843 u16 std_vddc;
1844
1845 ret = ni_get_std_voltage_value(rdev,
1846 &table->ACPIState.levels[0].vddc,
1847 &std_vddc);
1848 if (!ret)
1849 ni_populate_std_voltage_value(rdev, std_vddc,
1850 table->ACPIState.levels[0].vddc.index,
1851 &table->ACPIState.levels[0].std_vddc);
1852 }
1853 table->ACPIState.levels[0].gen2PCIE = 0;
1854 }
1855
1856 if (eg_pi->acpi_vddci) {
1857 if (eg_pi->vddci_control)
1858 ni_populate_voltage_value(rdev,
1859 &eg_pi->vddci_voltage_table,
1860 eg_pi->acpi_vddci,
1861 &table->ACPIState.levels[0].vddci);
1862 }
1863
1864
1865 mpll_ad_func_cntl &= ~PDNB;
1866
1867 mpll_ad_func_cntl_2 |= BIAS_GEN_PDNB | RESET_EN;
1868
1869 if (pi->mem_gddr5)
1870 mpll_dq_func_cntl &= ~PDNB;
1871 mpll_dq_func_cntl_2 |= BIAS_GEN_PDNB | RESET_EN | BYPASS;
1872
1873
1874 mclk_pwrmgt_cntl |= (MRDCKA0_RESET |
1875 MRDCKA1_RESET |
1876 MRDCKB0_RESET |
1877 MRDCKB1_RESET |
1878 MRDCKC0_RESET |
1879 MRDCKC1_RESET |
1880 MRDCKD0_RESET |
1881 MRDCKD1_RESET);
1882
1883 mclk_pwrmgt_cntl &= ~(MRDCKA0_PDNB |
1884 MRDCKA1_PDNB |
1885 MRDCKB0_PDNB |
1886 MRDCKB1_PDNB |
1887 MRDCKC0_PDNB |
1888 MRDCKC1_PDNB |
1889 MRDCKD0_PDNB |
1890 MRDCKD1_PDNB);
1891
1892 dll_cntl |= (MRDCKA0_BYPASS |
1893 MRDCKA1_BYPASS |
1894 MRDCKB0_BYPASS |
1895 MRDCKB1_BYPASS |
1896 MRDCKC0_BYPASS |
1897 MRDCKC1_BYPASS |
1898 MRDCKD0_BYPASS |
1899 MRDCKD1_BYPASS);
1900
1901 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
1902 spll_func_cntl_2 |= SCLK_MUX_SEL(4);
1903
1904 table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl);
1905 table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL_2 = cpu_to_be32(mpll_ad_func_cntl_2);
1906 table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl);
1907 table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL_2 = cpu_to_be32(mpll_dq_func_cntl_2);
1908 table->ACPIState.levels[0].mclk.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
1909 table->ACPIState.levels[0].mclk.vDLL_CNTL = cpu_to_be32(dll_cntl);
1910
1911 table->ACPIState.levels[0].mclk.mclk_value = 0;
1912
1913 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl);
1914 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2);
1915 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3);
1916 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(spll_func_cntl_4);
1917
1918 table->ACPIState.levels[0].sclk.sclk_value = 0;
1919
1920 ni_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd);
1921
1922 if (eg_pi->dynamic_ac_timing)
1923 table->ACPIState.levels[0].ACIndex = 1;
1924
1925 table->ACPIState.levels[0].dpm2.MaxPS = 0;
1926 table->ACPIState.levels[0].dpm2.NearTDPDec = 0;
1927 table->ACPIState.levels[0].dpm2.AboveSafeInc = 0;
1928 table->ACPIState.levels[0].dpm2.BelowSafeInc = 0;
1929
1930 reg = MIN_POWER_MASK | MAX_POWER_MASK;
1931 table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
1932
1933 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
1934 table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
1935
1936 return 0;
1937 }
1938
ni_init_smc_table(struct radeon_device * rdev)1939 static int ni_init_smc_table(struct radeon_device *rdev)
1940 {
1941 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1942 struct ni_power_info *ni_pi = ni_get_pi(rdev);
1943 int ret;
1944 struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps;
1945 NISLANDS_SMC_STATETABLE *table = &ni_pi->smc_statetable;
1946
1947 memset(table, 0, sizeof(NISLANDS_SMC_STATETABLE));
1948
1949 ni_populate_smc_voltage_tables(rdev, table);
1950
1951 switch (rdev->pm.int_thermal_type) {
1952 case THERMAL_TYPE_NI:
1953 case THERMAL_TYPE_EMC2103_WITH_INTERNAL:
1954 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL;
1955 break;
1956 case THERMAL_TYPE_NONE:
1957 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE;
1958 break;
1959 default:
1960 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL;
1961 break;
1962 }
1963
1964 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
1965 table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
1966
1967 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT)
1968 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT;
1969
1970 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
1971 table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
1972
1973 if (pi->mem_gddr5)
1974 table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
1975
1976 ret = ni_populate_smc_initial_state(rdev, radeon_boot_state, table);
1977 if (ret)
1978 return ret;
1979
1980 ret = ni_populate_smc_acpi_state(rdev, table);
1981 if (ret)
1982 return ret;
1983
1984 table->driverState = table->initialState;
1985
1986 table->ULVState = table->initialState;
1987
1988 ret = ni_do_program_memory_timing_parameters(rdev, radeon_boot_state,
1989 NISLANDS_INITIAL_STATE_ARB_INDEX);
1990 if (ret)
1991 return ret;
1992
1993 return rv770_copy_bytes_to_smc(rdev, pi->state_table_start, (u8 *)table,
1994 sizeof(NISLANDS_SMC_STATETABLE), pi->sram_end);
1995 }
1996
ni_calculate_sclk_params(struct radeon_device * rdev,u32 engine_clock,NISLANDS_SMC_SCLK_VALUE * sclk)1997 static int ni_calculate_sclk_params(struct radeon_device *rdev,
1998 u32 engine_clock,
1999 NISLANDS_SMC_SCLK_VALUE *sclk)
2000 {
2001 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
2002 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2003 struct atom_clock_dividers dividers;
2004 u32 spll_func_cntl = ni_pi->clock_registers.cg_spll_func_cntl;
2005 u32 spll_func_cntl_2 = ni_pi->clock_registers.cg_spll_func_cntl_2;
2006 u32 spll_func_cntl_3 = ni_pi->clock_registers.cg_spll_func_cntl_3;
2007 u32 spll_func_cntl_4 = ni_pi->clock_registers.cg_spll_func_cntl_4;
2008 u32 cg_spll_spread_spectrum = ni_pi->clock_registers.cg_spll_spread_spectrum;
2009 u32 cg_spll_spread_spectrum_2 = ni_pi->clock_registers.cg_spll_spread_spectrum_2;
2010 u64 tmp;
2011 u32 reference_clock = rdev->clock.spll.reference_freq;
2012 u32 reference_divider;
2013 u32 fbdiv;
2014 int ret;
2015
2016 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
2017 engine_clock, false, ÷rs);
2018 if (ret)
2019 return ret;
2020
2021 reference_divider = 1 + dividers.ref_div;
2022
2023
2024 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16834;
2025 do_div(tmp, reference_clock);
2026 fbdiv = (u32) tmp;
2027
2028 spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK);
2029 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
2030 spll_func_cntl |= SPLL_PDIV_A(dividers.post_div);
2031
2032 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
2033 spll_func_cntl_2 |= SCLK_MUX_SEL(2);
2034
2035 spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK;
2036 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv);
2037 spll_func_cntl_3 |= SPLL_DITHEN;
2038
2039 if (pi->sclk_ss) {
2040 struct radeon_atom_ss ss;
2041 u32 vco_freq = engine_clock * dividers.post_div;
2042
2043 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
2044 ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
2045 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
2046 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
2047
2048 cg_spll_spread_spectrum &= ~CLK_S_MASK;
2049 cg_spll_spread_spectrum |= CLK_S(clk_s);
2050 cg_spll_spread_spectrum |= SSEN;
2051
2052 cg_spll_spread_spectrum_2 &= ~CLK_V_MASK;
2053 cg_spll_spread_spectrum_2 |= CLK_V(clk_v);
2054 }
2055 }
2056
2057 sclk->sclk_value = engine_clock;
2058 sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl;
2059 sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2;
2060 sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3;
2061 sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4;
2062 sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum;
2063 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2;
2064
2065 return 0;
2066 }
2067
ni_populate_sclk_value(struct radeon_device * rdev,u32 engine_clock,NISLANDS_SMC_SCLK_VALUE * sclk)2068 static int ni_populate_sclk_value(struct radeon_device *rdev,
2069 u32 engine_clock,
2070 NISLANDS_SMC_SCLK_VALUE *sclk)
2071 {
2072 NISLANDS_SMC_SCLK_VALUE sclk_tmp;
2073 int ret;
2074
2075 ret = ni_calculate_sclk_params(rdev, engine_clock, &sclk_tmp);
2076 if (!ret) {
2077 sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value);
2078 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL);
2079 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2);
2080 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3);
2081 sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4);
2082 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM);
2083 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2);
2084 }
2085
2086 return ret;
2087 }
2088
ni_init_smc_spll_table(struct radeon_device * rdev)2089 static int ni_init_smc_spll_table(struct radeon_device *rdev)
2090 {
2091 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
2092 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2093 SMC_NISLANDS_SPLL_DIV_TABLE *spll_table;
2094 NISLANDS_SMC_SCLK_VALUE sclk_params;
2095 u32 fb_div;
2096 u32 p_div;
2097 u32 clk_s;
2098 u32 clk_v;
2099 u32 sclk = 0;
2100 int i, ret;
2101 u32 tmp;
2102
2103 if (ni_pi->spll_table_start == 0)
2104 return -EINVAL;
2105
2106 spll_table = kzalloc(sizeof(SMC_NISLANDS_SPLL_DIV_TABLE), GFP_KERNEL);
2107 if (spll_table == NULL)
2108 return -ENOMEM;
2109
2110 for (i = 0; i < 256; i++) {
2111 ret = ni_calculate_sclk_params(rdev, sclk, &sclk_params);
2112 if (ret)
2113 break;
2114
2115 p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & SPLL_PDIV_A_MASK) >> SPLL_PDIV_A_SHIFT;
2116 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT;
2117 clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CLK_S_MASK) >> CLK_S_SHIFT;
2118 clk_v = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM_2 & CLK_V_MASK) >> CLK_V_SHIFT;
2119
2120 fb_div &= ~0x00001FFF;
2121 fb_div >>= 1;
2122 clk_v >>= 6;
2123
2124 if (p_div & ~(SMC_NISLANDS_SPLL_DIV_TABLE_PDIV_MASK >> SMC_NISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT))
2125 ret = -EINVAL;
2126
2127 if (clk_s & ~(SMC_NISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_NISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT))
2128 ret = -EINVAL;
2129
2130 if (fb_div & ~(SMC_NISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_NISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT))
2131 ret = -EINVAL;
2132
2133 if (clk_v & ~(SMC_NISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_NISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT))
2134 ret = -EINVAL;
2135
2136 if (ret)
2137 break;
2138
2139 tmp = ((fb_div << SMC_NISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_NISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) |
2140 ((p_div << SMC_NISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT) & SMC_NISLANDS_SPLL_DIV_TABLE_PDIV_MASK);
2141 spll_table->freq[i] = cpu_to_be32(tmp);
2142
2143 tmp = ((clk_v << SMC_NISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_NISLANDS_SPLL_DIV_TABLE_CLKV_MASK) |
2144 ((clk_s << SMC_NISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_NISLANDS_SPLL_DIV_TABLE_CLKS_MASK);
2145 spll_table->ss[i] = cpu_to_be32(tmp);
2146
2147 sclk += 512;
2148 }
2149
2150 if (!ret)
2151 ret = rv770_copy_bytes_to_smc(rdev, ni_pi->spll_table_start, (u8 *)spll_table,
2152 sizeof(SMC_NISLANDS_SPLL_DIV_TABLE), pi->sram_end);
2153
2154 kfree(spll_table);
2155
2156 return ret;
2157 }
2158
ni_populate_mclk_value(struct radeon_device * rdev,u32 engine_clock,u32 memory_clock,NISLANDS_SMC_MCLK_VALUE * mclk,bool strobe_mode,bool dll_state_on)2159 static int ni_populate_mclk_value(struct radeon_device *rdev,
2160 u32 engine_clock,
2161 u32 memory_clock,
2162 NISLANDS_SMC_MCLK_VALUE *mclk,
2163 bool strobe_mode,
2164 bool dll_state_on)
2165 {
2166 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
2167 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2168 u32 mpll_ad_func_cntl = ni_pi->clock_registers.mpll_ad_func_cntl;
2169 u32 mpll_ad_func_cntl_2 = ni_pi->clock_registers.mpll_ad_func_cntl_2;
2170 u32 mpll_dq_func_cntl = ni_pi->clock_registers.mpll_dq_func_cntl;
2171 u32 mpll_dq_func_cntl_2 = ni_pi->clock_registers.mpll_dq_func_cntl_2;
2172 u32 mclk_pwrmgt_cntl = ni_pi->clock_registers.mclk_pwrmgt_cntl;
2173 u32 dll_cntl = ni_pi->clock_registers.dll_cntl;
2174 u32 mpll_ss1 = ni_pi->clock_registers.mpll_ss1;
2175 u32 mpll_ss2 = ni_pi->clock_registers.mpll_ss2;
2176 struct atom_clock_dividers dividers;
2177 u32 ibias;
2178 u32 dll_speed;
2179 int ret;
2180 u32 mc_seq_misc7;
2181
2182 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_MEMORY_PLL_PARAM,
2183 memory_clock, strobe_mode, ÷rs);
2184 if (ret)
2185 return ret;
2186
2187 if (!strobe_mode) {
2188 mc_seq_misc7 = RREG32(MC_SEQ_MISC7);
2189
2190 if (mc_seq_misc7 & 0x8000000)
2191 dividers.post_div = 1;
2192 }
2193
2194 ibias = cypress_map_clkf_to_ibias(rdev, dividers.whole_fb_div);
2195
2196 mpll_ad_func_cntl &= ~(CLKR_MASK |
2197 YCLK_POST_DIV_MASK |
2198 CLKF_MASK |
2199 CLKFRAC_MASK |
2200 IBIAS_MASK);
2201 mpll_ad_func_cntl |= CLKR(dividers.ref_div);
2202 mpll_ad_func_cntl |= YCLK_POST_DIV(dividers.post_div);
2203 mpll_ad_func_cntl |= CLKF(dividers.whole_fb_div);
2204 mpll_ad_func_cntl |= CLKFRAC(dividers.frac_fb_div);
2205 mpll_ad_func_cntl |= IBIAS(ibias);
2206
2207 if (dividers.vco_mode)
2208 mpll_ad_func_cntl_2 |= VCO_MODE;
2209 else
2210 mpll_ad_func_cntl_2 &= ~VCO_MODE;
2211
2212 if (pi->mem_gddr5) {
2213 mpll_dq_func_cntl &= ~(CLKR_MASK |
2214 YCLK_POST_DIV_MASK |
2215 CLKF_MASK |
2216 CLKFRAC_MASK |
2217 IBIAS_MASK);
2218 mpll_dq_func_cntl |= CLKR(dividers.ref_div);
2219 mpll_dq_func_cntl |= YCLK_POST_DIV(dividers.post_div);
2220 mpll_dq_func_cntl |= CLKF(dividers.whole_fb_div);
2221 mpll_dq_func_cntl |= CLKFRAC(dividers.frac_fb_div);
2222 mpll_dq_func_cntl |= IBIAS(ibias);
2223
2224 if (strobe_mode)
2225 mpll_dq_func_cntl &= ~PDNB;
2226 else
2227 mpll_dq_func_cntl |= PDNB;
2228
2229 if (dividers.vco_mode)
2230 mpll_dq_func_cntl_2 |= VCO_MODE;
2231 else
2232 mpll_dq_func_cntl_2 &= ~VCO_MODE;
2233 }
2234
2235 if (pi->mclk_ss) {
2236 struct radeon_atom_ss ss;
2237 u32 vco_freq = memory_clock * dividers.post_div;
2238
2239 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
2240 ASIC_INTERNAL_MEMORY_SS, vco_freq)) {
2241 u32 reference_clock = rdev->clock.mpll.reference_freq;
2242 u32 decoded_ref = rv740_get_decoded_reference_divider(dividers.ref_div);
2243 u32 clk_s, clk_v;
2244
2245 if (!decoded_ref)
2246 return -EINVAL;
2247 clk_s = reference_clock * 5 / (decoded_ref * ss.rate);
2248 clk_v = ss.percentage *
2249 (0x4000 * dividers.whole_fb_div + 0x800 * dividers.frac_fb_div) / (clk_s * 625);
2250
2251 mpll_ss1 &= ~CLKV_MASK;
2252 mpll_ss1 |= CLKV(clk_v);
2253
2254 mpll_ss2 &= ~CLKS_MASK;
2255 mpll_ss2 |= CLKS(clk_s);
2256 }
2257 }
2258
2259 dll_speed = rv740_get_dll_speed(pi->mem_gddr5,
2260 memory_clock);
2261
2262 mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK;
2263 mclk_pwrmgt_cntl |= DLL_SPEED(dll_speed);
2264 if (dll_state_on)
2265 mclk_pwrmgt_cntl |= (MRDCKA0_PDNB |
2266 MRDCKA1_PDNB |
2267 MRDCKB0_PDNB |
2268 MRDCKB1_PDNB |
2269 MRDCKC0_PDNB |
2270 MRDCKC1_PDNB |
2271 MRDCKD0_PDNB |
2272 MRDCKD1_PDNB);
2273 else
2274 mclk_pwrmgt_cntl &= ~(MRDCKA0_PDNB |
2275 MRDCKA1_PDNB |
2276 MRDCKB0_PDNB |
2277 MRDCKB1_PDNB |
2278 MRDCKC0_PDNB |
2279 MRDCKC1_PDNB |
2280 MRDCKD0_PDNB |
2281 MRDCKD1_PDNB);
2282
2283
2284 mclk->mclk_value = cpu_to_be32(memory_clock);
2285 mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl);
2286 mclk->vMPLL_AD_FUNC_CNTL_2 = cpu_to_be32(mpll_ad_func_cntl_2);
2287 mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl);
2288 mclk->vMPLL_DQ_FUNC_CNTL_2 = cpu_to_be32(mpll_dq_func_cntl_2);
2289 mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
2290 mclk->vDLL_CNTL = cpu_to_be32(dll_cntl);
2291 mclk->vMPLL_SS = cpu_to_be32(mpll_ss1);
2292 mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2);
2293
2294 return 0;
2295 }
2296
ni_populate_smc_sp(struct radeon_device * rdev,struct radeon_ps * radeon_state,NISLANDS_SMC_SWSTATE * smc_state)2297 static void ni_populate_smc_sp(struct radeon_device *rdev,
2298 struct radeon_ps *radeon_state,
2299 NISLANDS_SMC_SWSTATE *smc_state)
2300 {
2301 struct ni_ps *ps = ni_get_ps(radeon_state);
2302 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
2303 int i;
2304
2305 for (i = 0; i < ps->performance_level_count - 1; i++)
2306 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp);
2307
2308 smc_state->levels[ps->performance_level_count - 1].bSP =
2309 cpu_to_be32(pi->psp);
2310 }
2311
ni_convert_power_level_to_smc(struct radeon_device * rdev,struct rv7xx_pl * pl,NISLANDS_SMC_HW_PERFORMANCE_LEVEL * level)2312 static int ni_convert_power_level_to_smc(struct radeon_device *rdev,
2313 struct rv7xx_pl *pl,
2314 NISLANDS_SMC_HW_PERFORMANCE_LEVEL *level)
2315 {
2316 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
2317 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2318 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2319 int ret;
2320 bool dll_state_on;
2321 u16 std_vddc;
2322 u32 tmp = RREG32(DC_STUTTER_CNTL);
2323
2324 level->gen2PCIE = pi->pcie_gen2 ?
2325 ((pl->flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) ? 1 : 0) : 0;
2326
2327 ret = ni_populate_sclk_value(rdev, pl->sclk, &level->sclk);
2328 if (ret)
2329 return ret;
2330
2331 level->mcFlags = 0;
2332 if (pi->mclk_stutter_mode_threshold &&
2333 (pl->mclk <= pi->mclk_stutter_mode_threshold) &&
2334 !eg_pi->uvd_enabled &&
2335 (tmp & DC_STUTTER_ENABLE_A) &&
2336 (tmp & DC_STUTTER_ENABLE_B))
2337 level->mcFlags |= NISLANDS_SMC_MC_STUTTER_EN;
2338
2339 if (pi->mem_gddr5) {
2340 if (pl->mclk > pi->mclk_edc_enable_threshold)
2341 level->mcFlags |= NISLANDS_SMC_MC_EDC_RD_FLAG;
2342 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold)
2343 level->mcFlags |= NISLANDS_SMC_MC_EDC_WR_FLAG;
2344
2345 level->strobeMode = cypress_get_strobe_mode_settings(rdev, pl->mclk);
2346
2347 if (level->strobeMode & NISLANDS_SMC_STROBE_ENABLE) {
2348 if (cypress_get_mclk_frequency_ratio(rdev, pl->mclk, true) >=
2349 ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))
2350 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
2351 else
2352 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
2353 } else {
2354 dll_state_on = false;
2355 if (pl->mclk > ni_pi->mclk_rtt_mode_threshold)
2356 level->mcFlags |= NISLANDS_SMC_MC_RTT_ENABLE;
2357 }
2358
2359 ret = ni_populate_mclk_value(rdev, pl->sclk, pl->mclk,
2360 &level->mclk,
2361 (level->strobeMode & NISLANDS_SMC_STROBE_ENABLE) != 0,
2362 dll_state_on);
2363 } else
2364 ret = ni_populate_mclk_value(rdev, pl->sclk, pl->mclk, &level->mclk, 1, 1);
2365
2366 if (ret)
2367 return ret;
2368
2369 ret = ni_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
2370 pl->vddc, &level->vddc);
2371 if (ret)
2372 return ret;
2373
2374 ret = ni_get_std_voltage_value(rdev, &level->vddc, &std_vddc);
2375 if (ret)
2376 return ret;
2377
2378 ni_populate_std_voltage_value(rdev, std_vddc,
2379 level->vddc.index, &level->std_vddc);
2380
2381 if (eg_pi->vddci_control) {
2382 ret = ni_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table,
2383 pl->vddci, &level->vddci);
2384 if (ret)
2385 return ret;
2386 }
2387
2388 ni_populate_mvdd_value(rdev, pl->mclk, &level->mvdd);
2389
2390 return ret;
2391 }
2392
ni_populate_smc_t(struct radeon_device * rdev,struct radeon_ps * radeon_state,NISLANDS_SMC_SWSTATE * smc_state)2393 static int ni_populate_smc_t(struct radeon_device *rdev,
2394 struct radeon_ps *radeon_state,
2395 NISLANDS_SMC_SWSTATE *smc_state)
2396 {
2397 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
2398 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2399 struct ni_ps *state = ni_get_ps(radeon_state);
2400 u32 a_t;
2401 u32 t_l, t_h;
2402 u32 high_bsp;
2403 int i, ret;
2404
2405 if (state->performance_level_count >= 9)
2406 return -EINVAL;
2407
2408 if (state->performance_level_count < 2) {
2409 a_t = CG_R(0xffff) | CG_L(0);
2410 smc_state->levels[0].aT = cpu_to_be32(a_t);
2411 return 0;
2412 }
2413
2414 smc_state->levels[0].aT = cpu_to_be32(0);
2415
2416 for (i = 0; i <= state->performance_level_count - 2; i++) {
2417 if (eg_pi->uvd_enabled)
2418 ret = r600_calculate_at(
2419 1000 * (i * (eg_pi->smu_uvd_hs ? 2 : 8) + 2),
2420 100 * R600_AH_DFLT,
2421 state->performance_levels[i + 1].sclk,
2422 state->performance_levels[i].sclk,
2423 &t_l,
2424 &t_h);
2425 else
2426 ret = r600_calculate_at(
2427 1000 * (i + 1),
2428 100 * R600_AH_DFLT,
2429 state->performance_levels[i + 1].sclk,
2430 state->performance_levels[i].sclk,
2431 &t_l,
2432 &t_h);
2433
2434 if (ret) {
2435 t_h = (i + 1) * 1000 - 50 * R600_AH_DFLT;
2436 t_l = (i + 1) * 1000 + 50 * R600_AH_DFLT;
2437 }
2438
2439 a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK;
2440 a_t |= CG_R(t_l * pi->bsp / 20000);
2441 smc_state->levels[i].aT = cpu_to_be32(a_t);
2442
2443 high_bsp = (i == state->performance_level_count - 2) ?
2444 pi->pbsp : pi->bsp;
2445
2446 a_t = CG_R(0xffff) | CG_L(t_h * high_bsp / 20000);
2447 smc_state->levels[i + 1].aT = cpu_to_be32(a_t);
2448 }
2449
2450 return 0;
2451 }
2452
ni_populate_power_containment_values(struct radeon_device * rdev,struct radeon_ps * radeon_state,NISLANDS_SMC_SWSTATE * smc_state)2453 static int ni_populate_power_containment_values(struct radeon_device *rdev,
2454 struct radeon_ps *radeon_state,
2455 NISLANDS_SMC_SWSTATE *smc_state)
2456 {
2457 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
2458 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2459 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2460 struct ni_ps *state = ni_get_ps(radeon_state);
2461 u32 prev_sclk;
2462 u32 max_sclk;
2463 u32 min_sclk;
2464 int i, ret;
2465 u32 tdp_limit;
2466 u32 near_tdp_limit;
2467 u32 power_boost_limit;
2468 u8 max_ps_percent;
2469
2470 if (ni_pi->enable_power_containment == false)
2471 return 0;
2472
2473 if (state->performance_level_count == 0)
2474 return -EINVAL;
2475
2476 if (smc_state->levelCount != state->performance_level_count)
2477 return -EINVAL;
2478
2479 ret = ni_calculate_adjusted_tdp_limits(rdev,
2480 false, /* ??? */
2481 rdev->pm.dpm.tdp_adjustment,
2482 &tdp_limit,
2483 &near_tdp_limit);
2484 if (ret)
2485 return ret;
2486
2487 power_boost_limit = ni_calculate_power_boost_limit(rdev, radeon_state, near_tdp_limit);
2488
2489 ret = rv770_write_smc_sram_dword(rdev,
2490 pi->state_table_start +
2491 offsetof(NISLANDS_SMC_STATETABLE, dpm2Params) +
2492 offsetof(PP_NIslands_DPM2Parameters, PowerBoostLimit),
2493 ni_scale_power_for_smc(power_boost_limit, ni_get_smc_power_scaling_factor(rdev)),
2494 pi->sram_end);
2495 if (ret)
2496 power_boost_limit = 0;
2497
2498 smc_state->levels[0].dpm2.MaxPS = 0;
2499 smc_state->levels[0].dpm2.NearTDPDec = 0;
2500 smc_state->levels[0].dpm2.AboveSafeInc = 0;
2501 smc_state->levels[0].dpm2.BelowSafeInc = 0;
2502 smc_state->levels[0].stateFlags |= power_boost_limit ? PPSMC_STATEFLAG_POWERBOOST : 0;
2503
2504 for (i = 1; i < state->performance_level_count; i++) {
2505 prev_sclk = state->performance_levels[i-1].sclk;
2506 max_sclk = state->performance_levels[i].sclk;
2507 max_ps_percent = (i != (state->performance_level_count - 1)) ?
2508 NISLANDS_DPM2_MAXPS_PERCENT_M : NISLANDS_DPM2_MAXPS_PERCENT_H;
2509
2510 if (max_sclk < prev_sclk)
2511 return -EINVAL;
2512
2513 if ((max_ps_percent == 0) || (prev_sclk == max_sclk) || eg_pi->uvd_enabled)
2514 min_sclk = max_sclk;
2515 else if (1 == i)
2516 min_sclk = prev_sclk;
2517 else
2518 min_sclk = (prev_sclk * (u32)max_ps_percent) / 100;
2519
2520 if (min_sclk < state->performance_levels[0].sclk)
2521 min_sclk = state->performance_levels[0].sclk;
2522
2523 if (min_sclk == 0)
2524 return -EINVAL;
2525
2526 smc_state->levels[i].dpm2.MaxPS =
2527 (u8)((NISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk);
2528 smc_state->levels[i].dpm2.NearTDPDec = NISLANDS_DPM2_NEAR_TDP_DEC;
2529 smc_state->levels[i].dpm2.AboveSafeInc = NISLANDS_DPM2_ABOVE_SAFE_INC;
2530 smc_state->levels[i].dpm2.BelowSafeInc = NISLANDS_DPM2_BELOW_SAFE_INC;
2531 smc_state->levels[i].stateFlags |=
2532 ((i != (state->performance_level_count - 1)) && power_boost_limit) ?
2533 PPSMC_STATEFLAG_POWERBOOST : 0;
2534 }
2535
2536 return 0;
2537 }
2538
ni_populate_sq_ramping_values(struct radeon_device * rdev,struct radeon_ps * radeon_state,NISLANDS_SMC_SWSTATE * smc_state)2539 static int ni_populate_sq_ramping_values(struct radeon_device *rdev,
2540 struct radeon_ps *radeon_state,
2541 NISLANDS_SMC_SWSTATE *smc_state)
2542 {
2543 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2544 struct ni_ps *state = ni_get_ps(radeon_state);
2545 u32 sq_power_throttle;
2546 u32 sq_power_throttle2;
2547 bool enable_sq_ramping = ni_pi->enable_sq_ramping;
2548 int i;
2549
2550 if (state->performance_level_count == 0)
2551 return -EINVAL;
2552
2553 if (smc_state->levelCount != state->performance_level_count)
2554 return -EINVAL;
2555
2556 if (rdev->pm.dpm.sq_ramping_threshold == 0)
2557 return -EINVAL;
2558
2559 if (NISLANDS_DPM2_SQ_RAMP_MAX_POWER > (MAX_POWER_MASK >> MAX_POWER_SHIFT))
2560 enable_sq_ramping = false;
2561
2562 if (NISLANDS_DPM2_SQ_RAMP_MIN_POWER > (MIN_POWER_MASK >> MIN_POWER_SHIFT))
2563 enable_sq_ramping = false;
2564
2565 if (NISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA > (MAX_POWER_DELTA_MASK >> MAX_POWER_DELTA_SHIFT))
2566 enable_sq_ramping = false;
2567
2568 if (NISLANDS_DPM2_SQ_RAMP_STI_SIZE > (STI_SIZE_MASK >> STI_SIZE_SHIFT))
2569 enable_sq_ramping = false;
2570
2571 if (NISLANDS_DPM2_SQ_RAMP_LTI_RATIO > (LTI_RATIO_MASK >> LTI_RATIO_SHIFT))
2572 enable_sq_ramping = false;
2573
2574 for (i = 0; i < state->performance_level_count; i++) {
2575 sq_power_throttle = 0;
2576 sq_power_throttle2 = 0;
2577
2578 if ((state->performance_levels[i].sclk >= rdev->pm.dpm.sq_ramping_threshold) &&
2579 enable_sq_ramping) {
2580 sq_power_throttle |= MAX_POWER(NISLANDS_DPM2_SQ_RAMP_MAX_POWER);
2581 sq_power_throttle |= MIN_POWER(NISLANDS_DPM2_SQ_RAMP_MIN_POWER);
2582 sq_power_throttle2 |= MAX_POWER_DELTA(NISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA);
2583 sq_power_throttle2 |= STI_SIZE(NISLANDS_DPM2_SQ_RAMP_STI_SIZE);
2584 sq_power_throttle2 |= LTI_RATIO(NISLANDS_DPM2_SQ_RAMP_LTI_RATIO);
2585 } else {
2586 sq_power_throttle |= MAX_POWER_MASK | MIN_POWER_MASK;
2587 sq_power_throttle2 |= MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
2588 }
2589
2590 smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle);
2591 smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2);
2592 }
2593
2594 return 0;
2595 }
2596
ni_enable_power_containment(struct radeon_device * rdev,struct radeon_ps * radeon_new_state,bool enable)2597 static int ni_enable_power_containment(struct radeon_device *rdev,
2598 struct radeon_ps *radeon_new_state,
2599 bool enable)
2600 {
2601 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2602 PPSMC_Result smc_result;
2603 int ret = 0;
2604
2605 if (ni_pi->enable_power_containment) {
2606 if (enable) {
2607 if (!r600_is_uvd_state(radeon_new_state->class, radeon_new_state->class2)) {
2608 smc_result = rv770_send_msg_to_smc(rdev, PPSMC_TDPClampingActive);
2609 if (smc_result != PPSMC_Result_OK) {
2610 ret = -EINVAL;
2611 ni_pi->pc_enabled = false;
2612 } else {
2613 ni_pi->pc_enabled = true;
2614 }
2615 }
2616 } else {
2617 smc_result = rv770_send_msg_to_smc(rdev, PPSMC_TDPClampingInactive);
2618 if (smc_result != PPSMC_Result_OK)
2619 ret = -EINVAL;
2620 ni_pi->pc_enabled = false;
2621 }
2622 }
2623
2624 return ret;
2625 }
2626
ni_convert_power_state_to_smc(struct radeon_device * rdev,struct radeon_ps * radeon_state,NISLANDS_SMC_SWSTATE * smc_state)2627 static int ni_convert_power_state_to_smc(struct radeon_device *rdev,
2628 struct radeon_ps *radeon_state,
2629 NISLANDS_SMC_SWSTATE *smc_state)
2630 {
2631 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2632 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2633 struct ni_ps *state = ni_get_ps(radeon_state);
2634 int i, ret;
2635 u32 threshold = state->performance_levels[state->performance_level_count - 1].sclk * 100 / 100;
2636
2637 if (!(radeon_state->caps & ATOM_PPLIB_DISALLOW_ON_DC))
2638 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC;
2639
2640 smc_state->levelCount = 0;
2641
2642 if (state->performance_level_count > NISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE)
2643 return -EINVAL;
2644
2645 for (i = 0; i < state->performance_level_count; i++) {
2646 ret = ni_convert_power_level_to_smc(rdev, &state->performance_levels[i],
2647 &smc_state->levels[i]);
2648 smc_state->levels[i].arbRefreshState =
2649 (u8)(NISLANDS_DRIVER_STATE_ARB_INDEX + i);
2650
2651 if (ret)
2652 return ret;
2653
2654 if (ni_pi->enable_power_containment)
2655 smc_state->levels[i].displayWatermark =
2656 (state->performance_levels[i].sclk < threshold) ?
2657 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
2658 else
2659 smc_state->levels[i].displayWatermark = (i < 2) ?
2660 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
2661
2662 if (eg_pi->dynamic_ac_timing)
2663 smc_state->levels[i].ACIndex = NISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i;
2664 else
2665 smc_state->levels[i].ACIndex = 0;
2666
2667 smc_state->levelCount++;
2668 }
2669
2670 rv770_write_smc_soft_register(rdev, NI_SMC_SOFT_REGISTER_watermark_threshold,
2671 cpu_to_be32(threshold / 512));
2672
2673 ni_populate_smc_sp(rdev, radeon_state, smc_state);
2674
2675 ret = ni_populate_power_containment_values(rdev, radeon_state, smc_state);
2676 if (ret)
2677 ni_pi->enable_power_containment = false;
2678
2679 ret = ni_populate_sq_ramping_values(rdev, radeon_state, smc_state);
2680 if (ret)
2681 ni_pi->enable_sq_ramping = false;
2682
2683 return ni_populate_smc_t(rdev, radeon_state, smc_state);
2684 }
2685
ni_upload_sw_state(struct radeon_device * rdev,struct radeon_ps * radeon_new_state)2686 static int ni_upload_sw_state(struct radeon_device *rdev,
2687 struct radeon_ps *radeon_new_state)
2688 {
2689 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
2690 u16 address = pi->state_table_start +
2691 offsetof(NISLANDS_SMC_STATETABLE, driverState);
2692 NISLANDS_SMC_SWSTATE *smc_state;
2693 size_t state_size = struct_size(smc_state, levels,
2694 NISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE);
2695 int ret;
2696
2697 smc_state = kzalloc(state_size, GFP_KERNEL);
2698 if (smc_state == NULL)
2699 return -ENOMEM;
2700
2701 ret = ni_convert_power_state_to_smc(rdev, radeon_new_state, smc_state);
2702 if (ret)
2703 goto done;
2704
2705 ret = rv770_copy_bytes_to_smc(rdev, address, (u8 *)smc_state, state_size, pi->sram_end);
2706
2707 done:
2708 kfree(smc_state);
2709
2710 return ret;
2711 }
2712
ni_set_mc_special_registers(struct radeon_device * rdev,struct ni_mc_reg_table * table)2713 static int ni_set_mc_special_registers(struct radeon_device *rdev,
2714 struct ni_mc_reg_table *table)
2715 {
2716 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
2717 u8 i, j, k;
2718 u32 temp_reg;
2719
2720 for (i = 0, j = table->last; i < table->last; i++) {
2721 switch (table->mc_reg_address[i].s1) {
2722 case MC_SEQ_MISC1 >> 2:
2723 if (j >= SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE)
2724 return -EINVAL;
2725 temp_reg = RREG32(MC_PMG_CMD_EMRS);
2726 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2;
2727 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
2728 for (k = 0; k < table->num_entries; k++)
2729 table->mc_reg_table_entry[k].mc_data[j] =
2730 ((temp_reg & 0xffff0000)) |
2731 ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
2732 j++;
2733 if (j >= SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE)
2734 return -EINVAL;
2735
2736 temp_reg = RREG32(MC_PMG_CMD_MRS);
2737 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2;
2738 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2;
2739 for(k = 0; k < table->num_entries; k++) {
2740 table->mc_reg_table_entry[k].mc_data[j] =
2741 (temp_reg & 0xffff0000) |
2742 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
2743 if (!pi->mem_gddr5)
2744 table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
2745 }
2746 j++;
2747 break;
2748 case MC_SEQ_RESERVE_M >> 2:
2749 if (j >= SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE)
2750 return -EINVAL;
2751 temp_reg = RREG32(MC_PMG_CMD_MRS1);
2752 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2;
2753 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
2754 for (k = 0; k < table->num_entries; k++)
2755 table->mc_reg_table_entry[k].mc_data[j] =
2756 (temp_reg & 0xffff0000) |
2757 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
2758 j++;
2759 break;
2760 default:
2761 break;
2762 }
2763 }
2764
2765 table->last = j;
2766
2767 return 0;
2768 }
2769
ni_check_s0_mc_reg_index(u16 in_reg,u16 * out_reg)2770 static bool ni_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg)
2771 {
2772 bool result = true;
2773
2774 switch (in_reg) {
2775 case MC_SEQ_RAS_TIMING >> 2:
2776 *out_reg = MC_SEQ_RAS_TIMING_LP >> 2;
2777 break;
2778 case MC_SEQ_CAS_TIMING >> 2:
2779 *out_reg = MC_SEQ_CAS_TIMING_LP >> 2;
2780 break;
2781 case MC_SEQ_MISC_TIMING >> 2:
2782 *out_reg = MC_SEQ_MISC_TIMING_LP >> 2;
2783 break;
2784 case MC_SEQ_MISC_TIMING2 >> 2:
2785 *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2;
2786 break;
2787 case MC_SEQ_RD_CTL_D0 >> 2:
2788 *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2;
2789 break;
2790 case MC_SEQ_RD_CTL_D1 >> 2:
2791 *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2;
2792 break;
2793 case MC_SEQ_WR_CTL_D0 >> 2:
2794 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2;
2795 break;
2796 case MC_SEQ_WR_CTL_D1 >> 2:
2797 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2;
2798 break;
2799 case MC_PMG_CMD_EMRS >> 2:
2800 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
2801 break;
2802 case MC_PMG_CMD_MRS >> 2:
2803 *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2;
2804 break;
2805 case MC_PMG_CMD_MRS1 >> 2:
2806 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
2807 break;
2808 case MC_SEQ_PMG_TIMING >> 2:
2809 *out_reg = MC_SEQ_PMG_TIMING_LP >> 2;
2810 break;
2811 case MC_PMG_CMD_MRS2 >> 2:
2812 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP >> 2;
2813 break;
2814 default:
2815 result = false;
2816 break;
2817 }
2818
2819 return result;
2820 }
2821
ni_set_valid_flag(struct ni_mc_reg_table * table)2822 static void ni_set_valid_flag(struct ni_mc_reg_table *table)
2823 {
2824 u8 i, j;
2825
2826 for (i = 0; i < table->last; i++) {
2827 for (j = 1; j < table->num_entries; j++) {
2828 if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) {
2829 table->valid_flag |= 1 << i;
2830 break;
2831 }
2832 }
2833 }
2834 }
2835
ni_set_s0_mc_reg_index(struct ni_mc_reg_table * table)2836 static void ni_set_s0_mc_reg_index(struct ni_mc_reg_table *table)
2837 {
2838 u32 i;
2839 u16 address;
2840
2841 for (i = 0; i < table->last; i++)
2842 table->mc_reg_address[i].s0 =
2843 ni_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?
2844 address : table->mc_reg_address[i].s1;
2845 }
2846
ni_copy_vbios_mc_reg_table(struct atom_mc_reg_table * table,struct ni_mc_reg_table * ni_table)2847 static int ni_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table,
2848 struct ni_mc_reg_table *ni_table)
2849 {
2850 u8 i, j;
2851
2852 if (table->last > SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE)
2853 return -EINVAL;
2854 if (table->num_entries > MAX_AC_TIMING_ENTRIES)
2855 return -EINVAL;
2856
2857 for (i = 0; i < table->last; i++)
2858 ni_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
2859 ni_table->last = table->last;
2860
2861 for (i = 0; i < table->num_entries; i++) {
2862 ni_table->mc_reg_table_entry[i].mclk_max =
2863 table->mc_reg_table_entry[i].mclk_max;
2864 for (j = 0; j < table->last; j++)
2865 ni_table->mc_reg_table_entry[i].mc_data[j] =
2866 table->mc_reg_table_entry[i].mc_data[j];
2867 }
2868 ni_table->num_entries = table->num_entries;
2869
2870 return 0;
2871 }
2872
ni_initialize_mc_reg_table(struct radeon_device * rdev)2873 static int ni_initialize_mc_reg_table(struct radeon_device *rdev)
2874 {
2875 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2876 int ret;
2877 struct atom_mc_reg_table *table;
2878 struct ni_mc_reg_table *ni_table = &ni_pi->mc_reg_table;
2879 u8 module_index = rv770_get_memory_module_index(rdev);
2880
2881 table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL);
2882 if (!table)
2883 return -ENOMEM;
2884
2885 WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));
2886 WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));
2887 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));
2888 WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
2889 WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));
2890 WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));
2891 WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));
2892 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));
2893 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
2894 WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));
2895 WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));
2896 WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING));
2897 WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));
2898
2899 ret = radeon_atom_init_mc_reg_table(rdev, module_index, table);
2900
2901 if (ret)
2902 goto init_mc_done;
2903
2904 ret = ni_copy_vbios_mc_reg_table(table, ni_table);
2905
2906 if (ret)
2907 goto init_mc_done;
2908
2909 ni_set_s0_mc_reg_index(ni_table);
2910
2911 ret = ni_set_mc_special_registers(rdev, ni_table);
2912
2913 if (ret)
2914 goto init_mc_done;
2915
2916 ni_set_valid_flag(ni_table);
2917
2918 init_mc_done:
2919 kfree(table);
2920
2921 return ret;
2922 }
2923
ni_populate_mc_reg_addresses(struct radeon_device * rdev,SMC_NIslands_MCRegisters * mc_reg_table)2924 static void ni_populate_mc_reg_addresses(struct radeon_device *rdev,
2925 SMC_NIslands_MCRegisters *mc_reg_table)
2926 {
2927 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2928 u32 i, j;
2929
2930 for (i = 0, j = 0; j < ni_pi->mc_reg_table.last; j++) {
2931 if (ni_pi->mc_reg_table.valid_flag & (1 << j)) {
2932 if (i >= SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE)
2933 break;
2934 mc_reg_table->address[i].s0 =
2935 cpu_to_be16(ni_pi->mc_reg_table.mc_reg_address[j].s0);
2936 mc_reg_table->address[i].s1 =
2937 cpu_to_be16(ni_pi->mc_reg_table.mc_reg_address[j].s1);
2938 i++;
2939 }
2940 }
2941 mc_reg_table->last = (u8)i;
2942 }
2943
2944
ni_convert_mc_registers(struct ni_mc_reg_entry * entry,SMC_NIslands_MCRegisterSet * data,u32 num_entries,u32 valid_flag)2945 static void ni_convert_mc_registers(struct ni_mc_reg_entry *entry,
2946 SMC_NIslands_MCRegisterSet *data,
2947 u32 num_entries, u32 valid_flag)
2948 {
2949 u32 i, j;
2950
2951 for (i = 0, j = 0; j < num_entries; j++) {
2952 if (valid_flag & (1 << j)) {
2953 data->value[i] = cpu_to_be32(entry->mc_data[j]);
2954 i++;
2955 }
2956 }
2957 }
2958
ni_convert_mc_reg_table_entry_to_smc(struct radeon_device * rdev,struct rv7xx_pl * pl,SMC_NIslands_MCRegisterSet * mc_reg_table_data)2959 static void ni_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev,
2960 struct rv7xx_pl *pl,
2961 SMC_NIslands_MCRegisterSet *mc_reg_table_data)
2962 {
2963 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2964 u32 i = 0;
2965
2966 for (i = 0; i < ni_pi->mc_reg_table.num_entries; i++) {
2967 if (pl->mclk <= ni_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)
2968 break;
2969 }
2970
2971 if ((i == ni_pi->mc_reg_table.num_entries) && (i > 0))
2972 --i;
2973
2974 ni_convert_mc_registers(&ni_pi->mc_reg_table.mc_reg_table_entry[i],
2975 mc_reg_table_data,
2976 ni_pi->mc_reg_table.last,
2977 ni_pi->mc_reg_table.valid_flag);
2978 }
2979
ni_convert_mc_reg_table_to_smc(struct radeon_device * rdev,struct radeon_ps * radeon_state,SMC_NIslands_MCRegisters * mc_reg_table)2980 static void ni_convert_mc_reg_table_to_smc(struct radeon_device *rdev,
2981 struct radeon_ps *radeon_state,
2982 SMC_NIslands_MCRegisters *mc_reg_table)
2983 {
2984 struct ni_ps *state = ni_get_ps(radeon_state);
2985 int i;
2986
2987 for (i = 0; i < state->performance_level_count; i++) {
2988 ni_convert_mc_reg_table_entry_to_smc(rdev,
2989 &state->performance_levels[i],
2990 &mc_reg_table->data[NISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i]);
2991 }
2992 }
2993
ni_populate_mc_reg_table(struct radeon_device * rdev,struct radeon_ps * radeon_boot_state)2994 static int ni_populate_mc_reg_table(struct radeon_device *rdev,
2995 struct radeon_ps *radeon_boot_state)
2996 {
2997 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
2998 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2999 struct ni_power_info *ni_pi = ni_get_pi(rdev);
3000 struct ni_ps *boot_state = ni_get_ps(radeon_boot_state);
3001 SMC_NIslands_MCRegisters *mc_reg_table = &ni_pi->smc_mc_reg_table;
3002
3003 memset(mc_reg_table, 0, sizeof(SMC_NIslands_MCRegisters));
3004
3005 rv770_write_smc_soft_register(rdev, NI_SMC_SOFT_REGISTER_seq_index, 1);
3006
3007 ni_populate_mc_reg_addresses(rdev, mc_reg_table);
3008
3009 ni_convert_mc_reg_table_entry_to_smc(rdev, &boot_state->performance_levels[0],
3010 &mc_reg_table->data[0]);
3011
3012 ni_convert_mc_registers(&ni_pi->mc_reg_table.mc_reg_table_entry[0],
3013 &mc_reg_table->data[1],
3014 ni_pi->mc_reg_table.last,
3015 ni_pi->mc_reg_table.valid_flag);
3016
3017 ni_convert_mc_reg_table_to_smc(rdev, radeon_boot_state, mc_reg_table);
3018
3019 return rv770_copy_bytes_to_smc(rdev, eg_pi->mc_reg_table_start,
3020 (u8 *)mc_reg_table,
3021 sizeof(SMC_NIslands_MCRegisters),
3022 pi->sram_end);
3023 }
3024
ni_upload_mc_reg_table(struct radeon_device * rdev,struct radeon_ps * radeon_new_state)3025 static int ni_upload_mc_reg_table(struct radeon_device *rdev,
3026 struct radeon_ps *radeon_new_state)
3027 {
3028 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3029 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3030 struct ni_power_info *ni_pi = ni_get_pi(rdev);
3031 struct ni_ps *ni_new_state = ni_get_ps(radeon_new_state);
3032 SMC_NIslands_MCRegisters *mc_reg_table = &ni_pi->smc_mc_reg_table;
3033 u16 address;
3034
3035 memset(mc_reg_table, 0, sizeof(SMC_NIslands_MCRegisters));
3036
3037 ni_convert_mc_reg_table_to_smc(rdev, radeon_new_state, mc_reg_table);
3038
3039 address = eg_pi->mc_reg_table_start +
3040 (u16)offsetof(SMC_NIslands_MCRegisters, data[NISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT]);
3041
3042 return rv770_copy_bytes_to_smc(rdev, address,
3043 (u8 *)&mc_reg_table->data[NISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT],
3044 sizeof(SMC_NIslands_MCRegisterSet) * ni_new_state->performance_level_count,
3045 pi->sram_end);
3046 }
3047
ni_init_driver_calculated_leakage_table(struct radeon_device * rdev,PP_NIslands_CACTABLES * cac_tables)3048 static int ni_init_driver_calculated_leakage_table(struct radeon_device *rdev,
3049 PP_NIslands_CACTABLES *cac_tables)
3050 {
3051 struct ni_power_info *ni_pi = ni_get_pi(rdev);
3052 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3053 u32 leakage = 0;
3054 unsigned int i, j, table_size;
3055 s32 t;
3056 u32 smc_leakage, max_leakage = 0;
3057 u32 scaling_factor;
3058
3059 table_size = eg_pi->vddc_voltage_table.count;
3060
3061 if (SMC_NISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES < table_size)
3062 table_size = SMC_NISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES;
3063
3064 scaling_factor = ni_get_smc_power_scaling_factor(rdev);
3065
3066 for (i = 0; i < SMC_NISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES; i++) {
3067 for (j = 0; j < table_size; j++) {
3068 t = (1000 * ((i + 1) * 8));
3069
3070 if (t < ni_pi->cac_data.leakage_minimum_temperature)
3071 t = ni_pi->cac_data.leakage_minimum_temperature;
3072
3073 ni_calculate_leakage_for_v_and_t(rdev,
3074 &ni_pi->cac_data.leakage_coefficients,
3075 eg_pi->vddc_voltage_table.entries[j].value,
3076 t,
3077 ni_pi->cac_data.i_leakage,
3078 &leakage);
3079
3080 smc_leakage = ni_scale_power_for_smc(leakage, scaling_factor) / 1000;
3081 if (smc_leakage > max_leakage)
3082 max_leakage = smc_leakage;
3083
3084 cac_tables->cac_lkge_lut[i][j] = cpu_to_be32(smc_leakage);
3085 }
3086 }
3087
3088 for (j = table_size; j < SMC_NISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
3089 for (i = 0; i < SMC_NISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES; i++)
3090 cac_tables->cac_lkge_lut[i][j] = cpu_to_be32(max_leakage);
3091 }
3092 return 0;
3093 }
3094
ni_init_simplified_leakage_table(struct radeon_device * rdev,PP_NIslands_CACTABLES * cac_tables)3095 static int ni_init_simplified_leakage_table(struct radeon_device *rdev,
3096 PP_NIslands_CACTABLES *cac_tables)
3097 {
3098 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3099 struct radeon_cac_leakage_table *leakage_table =
3100 &rdev->pm.dpm.dyn_state.cac_leakage_table;
3101 u32 i, j, table_size;
3102 u32 smc_leakage, max_leakage = 0;
3103 u32 scaling_factor;
3104
3105 if (!leakage_table)
3106 return -EINVAL;
3107
3108 table_size = leakage_table->count;
3109
3110 if (eg_pi->vddc_voltage_table.count != table_size)
3111 table_size = (eg_pi->vddc_voltage_table.count < leakage_table->count) ?
3112 eg_pi->vddc_voltage_table.count : leakage_table->count;
3113
3114 if (SMC_NISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES < table_size)
3115 table_size = SMC_NISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES;
3116
3117 if (table_size == 0)
3118 return -EINVAL;
3119
3120 scaling_factor = ni_get_smc_power_scaling_factor(rdev);
3121
3122 for (j = 0; j < table_size; j++) {
3123 smc_leakage = leakage_table->entries[j].leakage;
3124
3125 if (smc_leakage > max_leakage)
3126 max_leakage = smc_leakage;
3127
3128 for (i = 0; i < SMC_NISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES; i++)
3129 cac_tables->cac_lkge_lut[i][j] =
3130 cpu_to_be32(ni_scale_power_for_smc(smc_leakage, scaling_factor));
3131 }
3132
3133 for (j = table_size; j < SMC_NISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
3134 for (i = 0; i < SMC_NISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES; i++)
3135 cac_tables->cac_lkge_lut[i][j] =
3136 cpu_to_be32(ni_scale_power_for_smc(max_leakage, scaling_factor));
3137 }
3138 return 0;
3139 }
3140
ni_initialize_smc_cac_tables(struct radeon_device * rdev)3141 static int ni_initialize_smc_cac_tables(struct radeon_device *rdev)
3142 {
3143 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3144 struct ni_power_info *ni_pi = ni_get_pi(rdev);
3145 PP_NIslands_CACTABLES *cac_tables = NULL;
3146 int i, ret;
3147 u32 reg;
3148
3149 if (ni_pi->enable_cac == false)
3150 return 0;
3151
3152 cac_tables = kzalloc(sizeof(PP_NIslands_CACTABLES), GFP_KERNEL);
3153 if (!cac_tables)
3154 return -ENOMEM;
3155
3156 reg = RREG32(CG_CAC_CTRL) & ~(TID_CNT_MASK | TID_UNIT_MASK);
3157 reg |= (TID_CNT(ni_pi->cac_weights->tid_cnt) |
3158 TID_UNIT(ni_pi->cac_weights->tid_unit));
3159 WREG32(CG_CAC_CTRL, reg);
3160
3161 for (i = 0; i < NISLANDS_DCCAC_MAX_LEVELS; i++)
3162 ni_pi->dc_cac_table[i] = ni_pi->cac_weights->dc_cac[i];
3163
3164 for (i = 0; i < SMC_NISLANDS_BIF_LUT_NUM_OF_ENTRIES; i++)
3165 cac_tables->cac_bif_lut[i] = ni_pi->cac_weights->pcie_cac[i];
3166
3167 ni_pi->cac_data.i_leakage = rdev->pm.dpm.cac_leakage;
3168 ni_pi->cac_data.pwr_const = 0;
3169 ni_pi->cac_data.dc_cac_value = ni_pi->dc_cac_table[NISLANDS_DCCAC_LEVEL_0];
3170 ni_pi->cac_data.bif_cac_value = 0;
3171 ni_pi->cac_data.mc_wr_weight = ni_pi->cac_weights->mc_write_weight;
3172 ni_pi->cac_data.mc_rd_weight = ni_pi->cac_weights->mc_read_weight;
3173 ni_pi->cac_data.allow_ovrflw = 0;
3174 ni_pi->cac_data.l2num_win_tdp = ni_pi->lta_window_size;
3175 ni_pi->cac_data.num_win_tdp = 0;
3176 ni_pi->cac_data.lts_truncate_n = ni_pi->lts_truncate;
3177
3178 if (ni_pi->driver_calculate_cac_leakage)
3179 ret = ni_init_driver_calculated_leakage_table(rdev, cac_tables);
3180 else
3181 ret = ni_init_simplified_leakage_table(rdev, cac_tables);
3182
3183 if (ret)
3184 goto done_free;
3185
3186 cac_tables->pwr_const = cpu_to_be32(ni_pi->cac_data.pwr_const);
3187 cac_tables->dc_cacValue = cpu_to_be32(ni_pi->cac_data.dc_cac_value);
3188 cac_tables->bif_cacValue = cpu_to_be32(ni_pi->cac_data.bif_cac_value);
3189 cac_tables->AllowOvrflw = ni_pi->cac_data.allow_ovrflw;
3190 cac_tables->MCWrWeight = ni_pi->cac_data.mc_wr_weight;
3191 cac_tables->MCRdWeight = ni_pi->cac_data.mc_rd_weight;
3192 cac_tables->numWin_TDP = ni_pi->cac_data.num_win_tdp;
3193 cac_tables->l2numWin_TDP = ni_pi->cac_data.l2num_win_tdp;
3194 cac_tables->lts_truncate_n = ni_pi->cac_data.lts_truncate_n;
3195
3196 ret = rv770_copy_bytes_to_smc(rdev, ni_pi->cac_table_start, (u8 *)cac_tables,
3197 sizeof(PP_NIslands_CACTABLES), pi->sram_end);
3198
3199 done_free:
3200 if (ret) {
3201 ni_pi->enable_cac = false;
3202 ni_pi->enable_power_containment = false;
3203 }
3204
3205 kfree(cac_tables);
3206
3207 return 0;
3208 }
3209
ni_initialize_hardware_cac_manager(struct radeon_device * rdev)3210 static int ni_initialize_hardware_cac_manager(struct radeon_device *rdev)
3211 {
3212 struct ni_power_info *ni_pi = ni_get_pi(rdev);
3213 u32 reg;
3214
3215 if (!ni_pi->enable_cac ||
3216 !ni_pi->cac_configuration_required)
3217 return 0;
3218
3219 if (ni_pi->cac_weights == NULL)
3220 return -EINVAL;
3221
3222 reg = RREG32_CG(CG_CAC_REGION_1_WEIGHT_0) & ~(WEIGHT_TCP_SIG0_MASK |
3223 WEIGHT_TCP_SIG1_MASK |
3224 WEIGHT_TA_SIG_MASK);
3225 reg |= (WEIGHT_TCP_SIG0(ni_pi->cac_weights->weight_tcp_sig0) |
3226 WEIGHT_TCP_SIG1(ni_pi->cac_weights->weight_tcp_sig1) |
3227 WEIGHT_TA_SIG(ni_pi->cac_weights->weight_ta_sig));
3228 WREG32_CG(CG_CAC_REGION_1_WEIGHT_0, reg);
3229
3230 reg = RREG32_CG(CG_CAC_REGION_1_WEIGHT_1) & ~(WEIGHT_TCC_EN0_MASK |
3231 WEIGHT_TCC_EN1_MASK |
3232 WEIGHT_TCC_EN2_MASK);
3233 reg |= (WEIGHT_TCC_EN0(ni_pi->cac_weights->weight_tcc_en0) |
3234 WEIGHT_TCC_EN1(ni_pi->cac_weights->weight_tcc_en1) |
3235 WEIGHT_TCC_EN2(ni_pi->cac_weights->weight_tcc_en2));
3236 WREG32_CG(CG_CAC_REGION_1_WEIGHT_1, reg);
3237
3238 reg = RREG32_CG(CG_CAC_REGION_2_WEIGHT_0) & ~(WEIGHT_CB_EN0_MASK |
3239 WEIGHT_CB_EN1_MASK |
3240 WEIGHT_CB_EN2_MASK |
3241 WEIGHT_CB_EN3_MASK);
3242 reg |= (WEIGHT_CB_EN0(ni_pi->cac_weights->weight_cb_en0) |
3243 WEIGHT_CB_EN1(ni_pi->cac_weights->weight_cb_en1) |
3244 WEIGHT_CB_EN2(ni_pi->cac_weights->weight_cb_en2) |
3245 WEIGHT_CB_EN3(ni_pi->cac_weights->weight_cb_en3));
3246 WREG32_CG(CG_CAC_REGION_2_WEIGHT_0, reg);
3247
3248 reg = RREG32_CG(CG_CAC_REGION_2_WEIGHT_1) & ~(WEIGHT_DB_SIG0_MASK |
3249 WEIGHT_DB_SIG1_MASK |
3250 WEIGHT_DB_SIG2_MASK |
3251 WEIGHT_DB_SIG3_MASK);
3252 reg |= (WEIGHT_DB_SIG0(ni_pi->cac_weights->weight_db_sig0) |
3253 WEIGHT_DB_SIG1(ni_pi->cac_weights->weight_db_sig1) |
3254 WEIGHT_DB_SIG2(ni_pi->cac_weights->weight_db_sig2) |
3255 WEIGHT_DB_SIG3(ni_pi->cac_weights->weight_db_sig3));
3256 WREG32_CG(CG_CAC_REGION_2_WEIGHT_1, reg);
3257
3258 reg = RREG32_CG(CG_CAC_REGION_2_WEIGHT_2) & ~(WEIGHT_SXM_SIG0_MASK |
3259 WEIGHT_SXM_SIG1_MASK |
3260 WEIGHT_SXM_SIG2_MASK |
3261 WEIGHT_SXS_SIG0_MASK |
3262 WEIGHT_SXS_SIG1_MASK);
3263 reg |= (WEIGHT_SXM_SIG0(ni_pi->cac_weights->weight_sxm_sig0) |
3264 WEIGHT_SXM_SIG1(ni_pi->cac_weights->weight_sxm_sig1) |
3265 WEIGHT_SXM_SIG2(ni_pi->cac_weights->weight_sxm_sig2) |
3266 WEIGHT_SXS_SIG0(ni_pi->cac_weights->weight_sxs_sig0) |
3267 WEIGHT_SXS_SIG1(ni_pi->cac_weights->weight_sxs_sig1));
3268 WREG32_CG(CG_CAC_REGION_2_WEIGHT_2, reg);
3269
3270 reg = RREG32_CG(CG_CAC_REGION_3_WEIGHT_0) & ~(WEIGHT_XBR_0_MASK |
3271 WEIGHT_XBR_1_MASK |
3272 WEIGHT_XBR_2_MASK |
3273 WEIGHT_SPI_SIG0_MASK);
3274 reg |= (WEIGHT_XBR_0(ni_pi->cac_weights->weight_xbr_0) |
3275 WEIGHT_XBR_1(ni_pi->cac_weights->weight_xbr_1) |
3276 WEIGHT_XBR_2(ni_pi->cac_weights->weight_xbr_2) |
3277 WEIGHT_SPI_SIG0(ni_pi->cac_weights->weight_spi_sig0));
3278 WREG32_CG(CG_CAC_REGION_3_WEIGHT_0, reg);
3279
3280 reg = RREG32_CG(CG_CAC_REGION_3_WEIGHT_1) & ~(WEIGHT_SPI_SIG1_MASK |
3281 WEIGHT_SPI_SIG2_MASK |
3282 WEIGHT_SPI_SIG3_MASK |
3283 WEIGHT_SPI_SIG4_MASK |
3284 WEIGHT_SPI_SIG5_MASK);
3285 reg |= (WEIGHT_SPI_SIG1(ni_pi->cac_weights->weight_spi_sig1) |
3286 WEIGHT_SPI_SIG2(ni_pi->cac_weights->weight_spi_sig2) |
3287 WEIGHT_SPI_SIG3(ni_pi->cac_weights->weight_spi_sig3) |
3288 WEIGHT_SPI_SIG4(ni_pi->cac_weights->weight_spi_sig4) |
3289 WEIGHT_SPI_SIG5(ni_pi->cac_weights->weight_spi_sig5));
3290 WREG32_CG(CG_CAC_REGION_3_WEIGHT_1, reg);
3291
3292 reg = RREG32_CG(CG_CAC_REGION_4_WEIGHT_0) & ~(WEIGHT_LDS_SIG0_MASK |
3293 WEIGHT_LDS_SIG1_MASK |
3294 WEIGHT_SC_MASK);
3295 reg |= (WEIGHT_LDS_SIG0(ni_pi->cac_weights->weight_lds_sig0) |
3296 WEIGHT_LDS_SIG1(ni_pi->cac_weights->weight_lds_sig1) |
3297 WEIGHT_SC(ni_pi->cac_weights->weight_sc));
3298 WREG32_CG(CG_CAC_REGION_4_WEIGHT_0, reg);
3299
3300 reg = RREG32_CG(CG_CAC_REGION_4_WEIGHT_1) & ~(WEIGHT_BIF_MASK |
3301 WEIGHT_CP_MASK |
3302 WEIGHT_PA_SIG0_MASK |
3303 WEIGHT_PA_SIG1_MASK |
3304 WEIGHT_VGT_SIG0_MASK);
3305 reg |= (WEIGHT_BIF(ni_pi->cac_weights->weight_bif) |
3306 WEIGHT_CP(ni_pi->cac_weights->weight_cp) |
3307 WEIGHT_PA_SIG0(ni_pi->cac_weights->weight_pa_sig0) |
3308 WEIGHT_PA_SIG1(ni_pi->cac_weights->weight_pa_sig1) |
3309 WEIGHT_VGT_SIG0(ni_pi->cac_weights->weight_vgt_sig0));
3310 WREG32_CG(CG_CAC_REGION_4_WEIGHT_1, reg);
3311
3312 reg = RREG32_CG(CG_CAC_REGION_4_WEIGHT_2) & ~(WEIGHT_VGT_SIG1_MASK |
3313 WEIGHT_VGT_SIG2_MASK |
3314 WEIGHT_DC_SIG0_MASK |
3315 WEIGHT_DC_SIG1_MASK |
3316 WEIGHT_DC_SIG2_MASK);
3317 reg |= (WEIGHT_VGT_SIG1(ni_pi->cac_weights->weight_vgt_sig1) |
3318 WEIGHT_VGT_SIG2(ni_pi->cac_weights->weight_vgt_sig2) |
3319 WEIGHT_DC_SIG0(ni_pi->cac_weights->weight_dc_sig0) |
3320 WEIGHT_DC_SIG1(ni_pi->cac_weights->weight_dc_sig1) |
3321 WEIGHT_DC_SIG2(ni_pi->cac_weights->weight_dc_sig2));
3322 WREG32_CG(CG_CAC_REGION_4_WEIGHT_2, reg);
3323
3324 reg = RREG32_CG(CG_CAC_REGION_4_WEIGHT_3) & ~(WEIGHT_DC_SIG3_MASK |
3325 WEIGHT_UVD_SIG0_MASK |
3326 WEIGHT_UVD_SIG1_MASK |
3327 WEIGHT_SPARE0_MASK |
3328 WEIGHT_SPARE1_MASK);
3329 reg |= (WEIGHT_DC_SIG3(ni_pi->cac_weights->weight_dc_sig3) |
3330 WEIGHT_UVD_SIG0(ni_pi->cac_weights->weight_uvd_sig0) |
3331 WEIGHT_UVD_SIG1(ni_pi->cac_weights->weight_uvd_sig1) |
3332 WEIGHT_SPARE0(ni_pi->cac_weights->weight_spare0) |
3333 WEIGHT_SPARE1(ni_pi->cac_weights->weight_spare1));
3334 WREG32_CG(CG_CAC_REGION_4_WEIGHT_3, reg);
3335
3336 reg = RREG32_CG(CG_CAC_REGION_5_WEIGHT_0) & ~(WEIGHT_SQ_VSP_MASK |
3337 WEIGHT_SQ_VSP0_MASK);
3338 reg |= (WEIGHT_SQ_VSP(ni_pi->cac_weights->weight_sq_vsp) |
3339 WEIGHT_SQ_VSP0(ni_pi->cac_weights->weight_sq_vsp0));
3340 WREG32_CG(CG_CAC_REGION_5_WEIGHT_0, reg);
3341
3342 reg = RREG32_CG(CG_CAC_REGION_5_WEIGHT_1) & ~(WEIGHT_SQ_GPR_MASK);
3343 reg |= WEIGHT_SQ_GPR(ni_pi->cac_weights->weight_sq_gpr);
3344 WREG32_CG(CG_CAC_REGION_5_WEIGHT_1, reg);
3345
3346 reg = RREG32_CG(CG_CAC_REGION_4_OVERRIDE_4) & ~(OVR_MODE_SPARE_0_MASK |
3347 OVR_VAL_SPARE_0_MASK |
3348 OVR_MODE_SPARE_1_MASK |
3349 OVR_VAL_SPARE_1_MASK);
3350 reg |= (OVR_MODE_SPARE_0(ni_pi->cac_weights->ovr_mode_spare_0) |
3351 OVR_VAL_SPARE_0(ni_pi->cac_weights->ovr_val_spare_0) |
3352 OVR_MODE_SPARE_1(ni_pi->cac_weights->ovr_mode_spare_1) |
3353 OVR_VAL_SPARE_1(ni_pi->cac_weights->ovr_val_spare_1));
3354 WREG32_CG(CG_CAC_REGION_4_OVERRIDE_4, reg);
3355
3356 reg = RREG32(SQ_CAC_THRESHOLD) & ~(VSP_MASK |
3357 VSP0_MASK |
3358 GPR_MASK);
3359 reg |= (VSP(ni_pi->cac_weights->vsp) |
3360 VSP0(ni_pi->cac_weights->vsp0) |
3361 GPR(ni_pi->cac_weights->gpr));
3362 WREG32(SQ_CAC_THRESHOLD, reg);
3363
3364 reg = (MCDW_WR_ENABLE |
3365 MCDX_WR_ENABLE |
3366 MCDY_WR_ENABLE |
3367 MCDZ_WR_ENABLE |
3368 INDEX(0x09D4));
3369 WREG32(MC_CG_CONFIG, reg);
3370
3371 reg = (READ_WEIGHT(ni_pi->cac_weights->mc_read_weight) |
3372 WRITE_WEIGHT(ni_pi->cac_weights->mc_write_weight) |
3373 ALLOW_OVERFLOW);
3374 WREG32(MC_CG_DATAPORT, reg);
3375
3376 return 0;
3377 }
3378
ni_enable_smc_cac(struct radeon_device * rdev,struct radeon_ps * radeon_new_state,bool enable)3379 static int ni_enable_smc_cac(struct radeon_device *rdev,
3380 struct radeon_ps *radeon_new_state,
3381 bool enable)
3382 {
3383 struct ni_power_info *ni_pi = ni_get_pi(rdev);
3384 int ret = 0;
3385 PPSMC_Result smc_result;
3386
3387 if (ni_pi->enable_cac) {
3388 if (enable) {
3389 if (!r600_is_uvd_state(radeon_new_state->class, radeon_new_state->class2)) {
3390 smc_result = rv770_send_msg_to_smc(rdev, PPSMC_MSG_CollectCAC_PowerCorreln);
3391
3392 if (ni_pi->support_cac_long_term_average) {
3393 smc_result = rv770_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgEnable);
3394 if (PPSMC_Result_OK != smc_result)
3395 ni_pi->support_cac_long_term_average = false;
3396 }
3397
3398 smc_result = rv770_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac);
3399 if (PPSMC_Result_OK != smc_result)
3400 ret = -EINVAL;
3401
3402 ni_pi->cac_enabled = (PPSMC_Result_OK == smc_result) ? true : false;
3403 }
3404 } else if (ni_pi->cac_enabled) {
3405 smc_result = rv770_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac);
3406
3407 ni_pi->cac_enabled = false;
3408
3409 if (ni_pi->support_cac_long_term_average) {
3410 smc_result = rv770_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgDisable);
3411 if (PPSMC_Result_OK != smc_result)
3412 ni_pi->support_cac_long_term_average = false;
3413 }
3414 }
3415 }
3416
3417 return ret;
3418 }
3419
ni_pcie_performance_request(struct radeon_device * rdev,u8 perf_req,bool advertise)3420 static int ni_pcie_performance_request(struct radeon_device *rdev,
3421 u8 perf_req, bool advertise)
3422 {
3423 #if defined(CONFIG_ACPI)
3424 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3425
3426 if ((perf_req == PCIE_PERF_REQ_PECI_GEN1) ||
3427 (perf_req == PCIE_PERF_REQ_PECI_GEN2)) {
3428 if (eg_pi->pcie_performance_request_registered == false)
3429 radeon_acpi_pcie_notify_device_ready(rdev);
3430 eg_pi->pcie_performance_request_registered = true;
3431 return radeon_acpi_pcie_performance_request(rdev, perf_req, advertise);
3432 } else if ((perf_req == PCIE_PERF_REQ_REMOVE_REGISTRY) &&
3433 eg_pi->pcie_performance_request_registered) {
3434 eg_pi->pcie_performance_request_registered = false;
3435 return radeon_acpi_pcie_performance_request(rdev, perf_req, advertise);
3436 }
3437 #endif
3438 return 0;
3439 }
3440
ni_advertise_gen2_capability(struct radeon_device * rdev)3441 static int ni_advertise_gen2_capability(struct radeon_device *rdev)
3442 {
3443 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3444 u32 tmp;
3445
3446 tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
3447
3448 if ((tmp & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
3449 (tmp & LC_OTHER_SIDE_SUPPORTS_GEN2))
3450 pi->pcie_gen2 = true;
3451 else
3452 pi->pcie_gen2 = false;
3453
3454 if (!pi->pcie_gen2)
3455 ni_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, true);
3456
3457 return 0;
3458 }
3459
ni_enable_bif_dynamic_pcie_gen2(struct radeon_device * rdev,bool enable)3460 static void ni_enable_bif_dynamic_pcie_gen2(struct radeon_device *rdev,
3461 bool enable)
3462 {
3463 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3464 u32 tmp, bif;
3465
3466 tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
3467
3468 if ((tmp & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
3469 (tmp & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
3470 if (enable) {
3471 if (!pi->boot_in_gen2) {
3472 bif = RREG32(CG_BIF_REQ_AND_RSP) & ~CG_CLIENT_REQ_MASK;
3473 bif |= CG_CLIENT_REQ(0xd);
3474 WREG32(CG_BIF_REQ_AND_RSP, bif);
3475 }
3476 tmp &= ~LC_HW_VOLTAGE_IF_CONTROL_MASK;
3477 tmp |= LC_HW_VOLTAGE_IF_CONTROL(1);
3478 tmp |= LC_GEN2_EN_STRAP;
3479
3480 tmp |= LC_CLR_FAILED_SPD_CHANGE_CNT;
3481 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
3482 udelay(10);
3483 tmp &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
3484 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
3485 } else {
3486 if (!pi->boot_in_gen2) {
3487 bif = RREG32(CG_BIF_REQ_AND_RSP) & ~CG_CLIENT_REQ_MASK;
3488 bif |= CG_CLIENT_REQ(0xd);
3489 WREG32(CG_BIF_REQ_AND_RSP, bif);
3490
3491 tmp &= ~LC_HW_VOLTAGE_IF_CONTROL_MASK;
3492 tmp &= ~LC_GEN2_EN_STRAP;
3493 }
3494 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
3495 }
3496 }
3497 }
3498
ni_enable_dynamic_pcie_gen2(struct radeon_device * rdev,bool enable)3499 static void ni_enable_dynamic_pcie_gen2(struct radeon_device *rdev,
3500 bool enable)
3501 {
3502 ni_enable_bif_dynamic_pcie_gen2(rdev, enable);
3503
3504 if (enable)
3505 WREG32_P(GENERAL_PWRMGT, ENABLE_GEN2PCIE, ~ENABLE_GEN2PCIE);
3506 else
3507 WREG32_P(GENERAL_PWRMGT, 0, ~ENABLE_GEN2PCIE);
3508 }
3509
ni_set_uvd_clock_before_set_eng_clock(struct radeon_device * rdev,struct radeon_ps * new_ps,struct radeon_ps * old_ps)3510 void ni_set_uvd_clock_before_set_eng_clock(struct radeon_device *rdev,
3511 struct radeon_ps *new_ps,
3512 struct radeon_ps *old_ps)
3513 {
3514 struct ni_ps *new_state = ni_get_ps(new_ps);
3515 struct ni_ps *current_state = ni_get_ps(old_ps);
3516
3517 if ((new_ps->vclk == old_ps->vclk) &&
3518 (new_ps->dclk == old_ps->dclk))
3519 return;
3520
3521 if (new_state->performance_levels[new_state->performance_level_count - 1].sclk >=
3522 current_state->performance_levels[current_state->performance_level_count - 1].sclk)
3523 return;
3524
3525 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk);
3526 }
3527
ni_set_uvd_clock_after_set_eng_clock(struct radeon_device * rdev,struct radeon_ps * new_ps,struct radeon_ps * old_ps)3528 void ni_set_uvd_clock_after_set_eng_clock(struct radeon_device *rdev,
3529 struct radeon_ps *new_ps,
3530 struct radeon_ps *old_ps)
3531 {
3532 struct ni_ps *new_state = ni_get_ps(new_ps);
3533 struct ni_ps *current_state = ni_get_ps(old_ps);
3534
3535 if ((new_ps->vclk == old_ps->vclk) &&
3536 (new_ps->dclk == old_ps->dclk))
3537 return;
3538
3539 if (new_state->performance_levels[new_state->performance_level_count - 1].sclk <
3540 current_state->performance_levels[current_state->performance_level_count - 1].sclk)
3541 return;
3542
3543 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk);
3544 }
3545
ni_dpm_setup_asic(struct radeon_device * rdev)3546 void ni_dpm_setup_asic(struct radeon_device *rdev)
3547 {
3548 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3549 int r;
3550
3551 r = ni_mc_load_microcode(rdev);
3552 if (r)
3553 DRM_ERROR("Failed to load MC firmware!\n");
3554 ni_read_clock_registers(rdev);
3555 btc_read_arb_registers(rdev);
3556 rv770_get_memory_type(rdev);
3557 if (eg_pi->pcie_performance_request)
3558 ni_advertise_gen2_capability(rdev);
3559 rv770_get_pcie_gen2_status(rdev);
3560 rv770_enable_acpi_pm(rdev);
3561 }
3562
ni_update_current_ps(struct radeon_device * rdev,struct radeon_ps * rps)3563 void ni_update_current_ps(struct radeon_device *rdev,
3564 struct radeon_ps *rps)
3565 {
3566 struct ni_ps *new_ps = ni_get_ps(rps);
3567 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3568 struct ni_power_info *ni_pi = ni_get_pi(rdev);
3569
3570 eg_pi->current_rps = *rps;
3571 ni_pi->current_ps = *new_ps;
3572 eg_pi->current_rps.ps_priv = &ni_pi->current_ps;
3573 }
3574
ni_update_requested_ps(struct radeon_device * rdev,struct radeon_ps * rps)3575 void ni_update_requested_ps(struct radeon_device *rdev,
3576 struct radeon_ps *rps)
3577 {
3578 struct ni_ps *new_ps = ni_get_ps(rps);
3579 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3580 struct ni_power_info *ni_pi = ni_get_pi(rdev);
3581
3582 eg_pi->requested_rps = *rps;
3583 ni_pi->requested_ps = *new_ps;
3584 eg_pi->requested_rps.ps_priv = &ni_pi->requested_ps;
3585 }
3586
ni_dpm_enable(struct radeon_device * rdev)3587 int ni_dpm_enable(struct radeon_device *rdev)
3588 {
3589 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3590 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3591 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
3592 int ret;
3593
3594 if (pi->gfx_clock_gating)
3595 ni_cg_clockgating_default(rdev);
3596 if (btc_dpm_enabled(rdev))
3597 return -EINVAL;
3598 if (pi->mg_clock_gating)
3599 ni_mg_clockgating_default(rdev);
3600 if (eg_pi->ls_clock_gating)
3601 ni_ls_clockgating_default(rdev);
3602 if (pi->voltage_control) {
3603 rv770_enable_voltage_control(rdev, true);
3604 ret = cypress_construct_voltage_tables(rdev);
3605 if (ret) {
3606 DRM_ERROR("cypress_construct_voltage_tables failed\n");
3607 return ret;
3608 }
3609 }
3610 if (eg_pi->dynamic_ac_timing) {
3611 ret = ni_initialize_mc_reg_table(rdev);
3612 if (ret)
3613 eg_pi->dynamic_ac_timing = false;
3614 }
3615 if (pi->dynamic_ss)
3616 cypress_enable_spread_spectrum(rdev, true);
3617 if (pi->thermal_protection)
3618 rv770_enable_thermal_protection(rdev, true);
3619 rv770_setup_bsp(rdev);
3620 rv770_program_git(rdev);
3621 rv770_program_tp(rdev);
3622 rv770_program_tpp(rdev);
3623 rv770_program_sstp(rdev);
3624 cypress_enable_display_gap(rdev);
3625 rv770_program_vc(rdev);
3626 if (pi->dynamic_pcie_gen2)
3627 ni_enable_dynamic_pcie_gen2(rdev, true);
3628 ret = rv770_upload_firmware(rdev);
3629 if (ret) {
3630 DRM_ERROR("rv770_upload_firmware failed\n");
3631 return ret;
3632 }
3633 ret = ni_process_firmware_header(rdev);
3634 if (ret) {
3635 DRM_ERROR("ni_process_firmware_header failed\n");
3636 return ret;
3637 }
3638 ret = ni_initial_switch_from_arb_f0_to_f1(rdev);
3639 if (ret) {
3640 DRM_ERROR("ni_initial_switch_from_arb_f0_to_f1 failed\n");
3641 return ret;
3642 }
3643 ret = ni_init_smc_table(rdev);
3644 if (ret) {
3645 DRM_ERROR("ni_init_smc_table failed\n");
3646 return ret;
3647 }
3648 ret = ni_init_smc_spll_table(rdev);
3649 if (ret) {
3650 DRM_ERROR("ni_init_smc_spll_table failed\n");
3651 return ret;
3652 }
3653 ret = ni_init_arb_table_index(rdev);
3654 if (ret) {
3655 DRM_ERROR("ni_init_arb_table_index failed\n");
3656 return ret;
3657 }
3658 if (eg_pi->dynamic_ac_timing) {
3659 ret = ni_populate_mc_reg_table(rdev, boot_ps);
3660 if (ret) {
3661 DRM_ERROR("ni_populate_mc_reg_table failed\n");
3662 return ret;
3663 }
3664 }
3665 ret = ni_initialize_smc_cac_tables(rdev);
3666 if (ret) {
3667 DRM_ERROR("ni_initialize_smc_cac_tables failed\n");
3668 return ret;
3669 }
3670 ret = ni_initialize_hardware_cac_manager(rdev);
3671 if (ret) {
3672 DRM_ERROR("ni_initialize_hardware_cac_manager failed\n");
3673 return ret;
3674 }
3675 ret = ni_populate_smc_tdp_limits(rdev, boot_ps);
3676 if (ret) {
3677 DRM_ERROR("ni_populate_smc_tdp_limits failed\n");
3678 return ret;
3679 }
3680 ni_program_response_times(rdev);
3681 r7xx_start_smc(rdev);
3682 ret = cypress_notify_smc_display_change(rdev, false);
3683 if (ret) {
3684 DRM_ERROR("cypress_notify_smc_display_change failed\n");
3685 return ret;
3686 }
3687 cypress_enable_sclk_control(rdev, true);
3688 if (eg_pi->memory_transition)
3689 cypress_enable_mclk_control(rdev, true);
3690 cypress_start_dpm(rdev);
3691 if (pi->gfx_clock_gating)
3692 ni_gfx_clockgating_enable(rdev, true);
3693 if (pi->mg_clock_gating)
3694 ni_mg_clockgating_enable(rdev, true);
3695 if (eg_pi->ls_clock_gating)
3696 ni_ls_clockgating_enable(rdev, true);
3697
3698 rv770_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
3699
3700 ni_update_current_ps(rdev, boot_ps);
3701
3702 return 0;
3703 }
3704
ni_dpm_disable(struct radeon_device * rdev)3705 void ni_dpm_disable(struct radeon_device *rdev)
3706 {
3707 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3708 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3709 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
3710
3711 if (!btc_dpm_enabled(rdev))
3712 return;
3713 rv770_clear_vc(rdev);
3714 if (pi->thermal_protection)
3715 rv770_enable_thermal_protection(rdev, false);
3716 ni_enable_power_containment(rdev, boot_ps, false);
3717 ni_enable_smc_cac(rdev, boot_ps, false);
3718 cypress_enable_spread_spectrum(rdev, false);
3719 rv770_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false);
3720 if (pi->dynamic_pcie_gen2)
3721 ni_enable_dynamic_pcie_gen2(rdev, false);
3722
3723 if (rdev->irq.installed &&
3724 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
3725 rdev->irq.dpm_thermal = false;
3726 radeon_irq_set(rdev);
3727 }
3728
3729 if (pi->gfx_clock_gating)
3730 ni_gfx_clockgating_enable(rdev, false);
3731 if (pi->mg_clock_gating)
3732 ni_mg_clockgating_enable(rdev, false);
3733 if (eg_pi->ls_clock_gating)
3734 ni_ls_clockgating_enable(rdev, false);
3735 ni_stop_dpm(rdev);
3736 btc_reset_to_default(rdev);
3737 ni_stop_smc(rdev);
3738 ni_force_switch_to_arb_f0(rdev);
3739
3740 ni_update_current_ps(rdev, boot_ps);
3741 }
3742
ni_power_control_set_level(struct radeon_device * rdev)3743 static int ni_power_control_set_level(struct radeon_device *rdev)
3744 {
3745 struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps;
3746 int ret;
3747
3748 ret = ni_restrict_performance_levels_before_switch(rdev);
3749 if (ret)
3750 return ret;
3751 ret = rv770_halt_smc(rdev);
3752 if (ret)
3753 return ret;
3754 ret = ni_populate_smc_tdp_limits(rdev, new_ps);
3755 if (ret)
3756 return ret;
3757 ret = rv770_resume_smc(rdev);
3758 if (ret)
3759 return ret;
3760 ret = rv770_set_sw_state(rdev);
3761 if (ret)
3762 return ret;
3763
3764 return 0;
3765 }
3766
ni_dpm_pre_set_power_state(struct radeon_device * rdev)3767 int ni_dpm_pre_set_power_state(struct radeon_device *rdev)
3768 {
3769 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3770 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps;
3771 struct radeon_ps *new_ps = &requested_ps;
3772
3773 ni_update_requested_ps(rdev, new_ps);
3774
3775 ni_apply_state_adjust_rules(rdev, &eg_pi->requested_rps);
3776
3777 return 0;
3778 }
3779
ni_dpm_set_power_state(struct radeon_device * rdev)3780 int ni_dpm_set_power_state(struct radeon_device *rdev)
3781 {
3782 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3783 struct radeon_ps *new_ps = &eg_pi->requested_rps;
3784 struct radeon_ps *old_ps = &eg_pi->current_rps;
3785 int ret;
3786
3787 ret = ni_restrict_performance_levels_before_switch(rdev);
3788 if (ret) {
3789 DRM_ERROR("ni_restrict_performance_levels_before_switch failed\n");
3790 return ret;
3791 }
3792 ni_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps);
3793 ret = ni_enable_power_containment(rdev, new_ps, false);
3794 if (ret) {
3795 DRM_ERROR("ni_enable_power_containment failed\n");
3796 return ret;
3797 }
3798 ret = ni_enable_smc_cac(rdev, new_ps, false);
3799 if (ret) {
3800 DRM_ERROR("ni_enable_smc_cac failed\n");
3801 return ret;
3802 }
3803 ret = rv770_halt_smc(rdev);
3804 if (ret) {
3805 DRM_ERROR("rv770_halt_smc failed\n");
3806 return ret;
3807 }
3808 if (eg_pi->smu_uvd_hs)
3809 btc_notify_uvd_to_smc(rdev, new_ps);
3810 ret = ni_upload_sw_state(rdev, new_ps);
3811 if (ret) {
3812 DRM_ERROR("ni_upload_sw_state failed\n");
3813 return ret;
3814 }
3815 if (eg_pi->dynamic_ac_timing) {
3816 ret = ni_upload_mc_reg_table(rdev, new_ps);
3817 if (ret) {
3818 DRM_ERROR("ni_upload_mc_reg_table failed\n");
3819 return ret;
3820 }
3821 }
3822 ret = ni_program_memory_timing_parameters(rdev, new_ps);
3823 if (ret) {
3824 DRM_ERROR("ni_program_memory_timing_parameters failed\n");
3825 return ret;
3826 }
3827 ret = rv770_resume_smc(rdev);
3828 if (ret) {
3829 DRM_ERROR("rv770_resume_smc failed\n");
3830 return ret;
3831 }
3832 ret = rv770_set_sw_state(rdev);
3833 if (ret) {
3834 DRM_ERROR("rv770_set_sw_state failed\n");
3835 return ret;
3836 }
3837 ni_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);
3838 ret = ni_enable_smc_cac(rdev, new_ps, true);
3839 if (ret) {
3840 DRM_ERROR("ni_enable_smc_cac failed\n");
3841 return ret;
3842 }
3843 ret = ni_enable_power_containment(rdev, new_ps, true);
3844 if (ret) {
3845 DRM_ERROR("ni_enable_power_containment failed\n");
3846 return ret;
3847 }
3848
3849 /* update tdp */
3850 ret = ni_power_control_set_level(rdev);
3851 if (ret) {
3852 DRM_ERROR("ni_power_control_set_level failed\n");
3853 return ret;
3854 }
3855
3856 return 0;
3857 }
3858
ni_dpm_post_set_power_state(struct radeon_device * rdev)3859 void ni_dpm_post_set_power_state(struct radeon_device *rdev)
3860 {
3861 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3862 struct radeon_ps *new_ps = &eg_pi->requested_rps;
3863
3864 ni_update_current_ps(rdev, new_ps);
3865 }
3866
3867 #if 0
3868 void ni_dpm_reset_asic(struct radeon_device *rdev)
3869 {
3870 ni_restrict_performance_levels_before_switch(rdev);
3871 rv770_set_boot_state(rdev);
3872 }
3873 #endif
3874
3875 union power_info {
3876 struct _ATOM_POWERPLAY_INFO info;
3877 struct _ATOM_POWERPLAY_INFO_V2 info_2;
3878 struct _ATOM_POWERPLAY_INFO_V3 info_3;
3879 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
3880 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
3881 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
3882 };
3883
3884 union pplib_clock_info {
3885 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
3886 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
3887 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
3888 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
3889 };
3890
3891 union pplib_power_state {
3892 struct _ATOM_PPLIB_STATE v1;
3893 struct _ATOM_PPLIB_STATE_V2 v2;
3894 };
3895
ni_parse_pplib_non_clock_info(struct radeon_device * rdev,struct radeon_ps * rps,struct _ATOM_PPLIB_NONCLOCK_INFO * non_clock_info,u8 table_rev)3896 static void ni_parse_pplib_non_clock_info(struct radeon_device *rdev,
3897 struct radeon_ps *rps,
3898 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
3899 u8 table_rev)
3900 {
3901 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
3902 rps->class = le16_to_cpu(non_clock_info->usClassification);
3903 rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
3904
3905 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
3906 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
3907 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
3908 } else if (r600_is_uvd_state(rps->class, rps->class2)) {
3909 rps->vclk = RV770_DEFAULT_VCLK_FREQ;
3910 rps->dclk = RV770_DEFAULT_DCLK_FREQ;
3911 } else {
3912 rps->vclk = 0;
3913 rps->dclk = 0;
3914 }
3915
3916 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
3917 rdev->pm.dpm.boot_ps = rps;
3918 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
3919 rdev->pm.dpm.uvd_ps = rps;
3920 }
3921
ni_parse_pplib_clock_info(struct radeon_device * rdev,struct radeon_ps * rps,int index,union pplib_clock_info * clock_info)3922 static void ni_parse_pplib_clock_info(struct radeon_device *rdev,
3923 struct radeon_ps *rps, int index,
3924 union pplib_clock_info *clock_info)
3925 {
3926 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3927 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3928 struct ni_ps *ps = ni_get_ps(rps);
3929 struct rv7xx_pl *pl = &ps->performance_levels[index];
3930
3931 ps->performance_level_count = index + 1;
3932
3933 pl->sclk = le16_to_cpu(clock_info->evergreen.usEngineClockLow);
3934 pl->sclk |= clock_info->evergreen.ucEngineClockHigh << 16;
3935 pl->mclk = le16_to_cpu(clock_info->evergreen.usMemoryClockLow);
3936 pl->mclk |= clock_info->evergreen.ucMemoryClockHigh << 16;
3937
3938 pl->vddc = le16_to_cpu(clock_info->evergreen.usVDDC);
3939 pl->vddci = le16_to_cpu(clock_info->evergreen.usVDDCI);
3940 pl->flags = le32_to_cpu(clock_info->evergreen.ulFlags);
3941
3942 /* patch up vddc if necessary */
3943 if (pl->vddc == 0xff01) {
3944 if (pi->max_vddc)
3945 pl->vddc = pi->max_vddc;
3946 }
3947
3948 if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) {
3949 pi->acpi_vddc = pl->vddc;
3950 eg_pi->acpi_vddci = pl->vddci;
3951 if (ps->performance_levels[0].flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2)
3952 pi->acpi_pcie_gen2 = true;
3953 else
3954 pi->acpi_pcie_gen2 = false;
3955 }
3956
3957 if (rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) {
3958 eg_pi->ulv.supported = true;
3959 eg_pi->ulv.pl = pl;
3960 }
3961
3962 if (pi->min_vddc_in_table > pl->vddc)
3963 pi->min_vddc_in_table = pl->vddc;
3964
3965 if (pi->max_vddc_in_table < pl->vddc)
3966 pi->max_vddc_in_table = pl->vddc;
3967
3968 /* patch up boot state */
3969 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
3970 u16 vddc, vddci, mvdd;
3971 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd);
3972 pl->mclk = rdev->clock.default_mclk;
3973 pl->sclk = rdev->clock.default_sclk;
3974 pl->vddc = vddc;
3975 pl->vddci = vddci;
3976 }
3977
3978 if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) ==
3979 ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
3980 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk;
3981 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk;
3982 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc;
3983 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci;
3984 }
3985 }
3986
ni_parse_power_table(struct radeon_device * rdev)3987 static int ni_parse_power_table(struct radeon_device *rdev)
3988 {
3989 struct radeon_mode_info *mode_info = &rdev->mode_info;
3990 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
3991 union pplib_power_state *power_state;
3992 int i, j;
3993 union pplib_clock_info *clock_info;
3994 union power_info *power_info;
3995 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
3996 u16 data_offset;
3997 u8 frev, crev;
3998 struct ni_ps *ps;
3999
4000 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
4001 &frev, &crev, &data_offset))
4002 return -EINVAL;
4003 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
4004
4005 rdev->pm.dpm.ps = kcalloc(power_info->pplib.ucNumStates,
4006 sizeof(struct radeon_ps),
4007 GFP_KERNEL);
4008 if (!rdev->pm.dpm.ps)
4009 return -ENOMEM;
4010
4011 for (i = 0; i < power_info->pplib.ucNumStates; i++) {
4012 power_state = (union pplib_power_state *)
4013 (mode_info->atom_context->bios + data_offset +
4014 le16_to_cpu(power_info->pplib.usStateArrayOffset) +
4015 i * power_info->pplib.ucStateEntrySize);
4016 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
4017 (mode_info->atom_context->bios + data_offset +
4018 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) +
4019 (power_state->v1.ucNonClockStateIndex *
4020 power_info->pplib.ucNonClockSize));
4021 if (power_info->pplib.ucStateEntrySize - 1) {
4022 u8 *idx;
4023 ps = kzalloc(sizeof(struct ni_ps), GFP_KERNEL);
4024 if (ps == NULL) {
4025 kfree(rdev->pm.dpm.ps);
4026 return -ENOMEM;
4027 }
4028 rdev->pm.dpm.ps[i].ps_priv = ps;
4029 ni_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
4030 non_clock_info,
4031 power_info->pplib.ucNonClockSize);
4032 idx = (u8 *)&power_state->v1.ucClockStateIndices[0];
4033 for (j = 0; j < (power_info->pplib.ucStateEntrySize - 1); j++) {
4034 clock_info = (union pplib_clock_info *)
4035 (mode_info->atom_context->bios + data_offset +
4036 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) +
4037 (idx[j] * power_info->pplib.ucClockInfoSize));
4038 ni_parse_pplib_clock_info(rdev,
4039 &rdev->pm.dpm.ps[i], j,
4040 clock_info);
4041 }
4042 }
4043 }
4044 rdev->pm.dpm.num_ps = power_info->pplib.ucNumStates;
4045 return 0;
4046 }
4047
ni_dpm_init(struct radeon_device * rdev)4048 int ni_dpm_init(struct radeon_device *rdev)
4049 {
4050 struct rv7xx_power_info *pi;
4051 struct evergreen_power_info *eg_pi;
4052 struct ni_power_info *ni_pi;
4053 struct atom_clock_dividers dividers;
4054 int ret;
4055
4056 ni_pi = kzalloc(sizeof(struct ni_power_info), GFP_KERNEL);
4057 if (ni_pi == NULL)
4058 return -ENOMEM;
4059 rdev->pm.dpm.priv = ni_pi;
4060 eg_pi = &ni_pi->eg;
4061 pi = &eg_pi->rv7xx;
4062
4063 rv770_get_max_vddc(rdev);
4064
4065 eg_pi->ulv.supported = false;
4066 pi->acpi_vddc = 0;
4067 eg_pi->acpi_vddci = 0;
4068 pi->min_vddc_in_table = 0;
4069 pi->max_vddc_in_table = 0;
4070
4071 ret = r600_get_platform_caps(rdev);
4072 if (ret)
4073 return ret;
4074
4075 ret = ni_parse_power_table(rdev);
4076 if (ret)
4077 return ret;
4078 ret = r600_parse_extended_power_table(rdev);
4079 if (ret)
4080 return ret;
4081
4082 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =
4083 kcalloc(4,
4084 sizeof(struct radeon_clock_voltage_dependency_entry),
4085 GFP_KERNEL);
4086 if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) {
4087 r600_free_extended_power_table(rdev);
4088 return -ENOMEM;
4089 }
4090 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;
4091 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;
4092 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
4093 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;
4094 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;
4095 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;
4096 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;
4097 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;
4098 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;
4099
4100 ni_patch_dependency_tables_based_on_leakage(rdev);
4101
4102 if (rdev->pm.dpm.voltage_response_time == 0)
4103 rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT;
4104 if (rdev->pm.dpm.backbias_response_time == 0)
4105 rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT;
4106
4107 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
4108 0, false, ÷rs);
4109 if (ret)
4110 pi->ref_div = dividers.ref_div + 1;
4111 else
4112 pi->ref_div = R600_REFERENCEDIVIDER_DFLT;
4113
4114 pi->rlp = RV770_RLP_DFLT;
4115 pi->rmp = RV770_RMP_DFLT;
4116 pi->lhp = RV770_LHP_DFLT;
4117 pi->lmp = RV770_LMP_DFLT;
4118
4119 eg_pi->ats[0].rlp = RV770_RLP_DFLT;
4120 eg_pi->ats[0].rmp = RV770_RMP_DFLT;
4121 eg_pi->ats[0].lhp = RV770_LHP_DFLT;
4122 eg_pi->ats[0].lmp = RV770_LMP_DFLT;
4123
4124 eg_pi->ats[1].rlp = BTC_RLP_UVD_DFLT;
4125 eg_pi->ats[1].rmp = BTC_RMP_UVD_DFLT;
4126 eg_pi->ats[1].lhp = BTC_LHP_UVD_DFLT;
4127 eg_pi->ats[1].lmp = BTC_LMP_UVD_DFLT;
4128
4129 eg_pi->smu_uvd_hs = true;
4130
4131 if (rdev->pdev->device == 0x6707) {
4132 pi->mclk_strobe_mode_threshold = 55000;
4133 pi->mclk_edc_enable_threshold = 55000;
4134 eg_pi->mclk_edc_wr_enable_threshold = 55000;
4135 } else {
4136 pi->mclk_strobe_mode_threshold = 40000;
4137 pi->mclk_edc_enable_threshold = 40000;
4138 eg_pi->mclk_edc_wr_enable_threshold = 40000;
4139 }
4140 ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold;
4141
4142 pi->voltage_control =
4143 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 0);
4144
4145 pi->mvdd_control =
4146 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_MVDDC, 0);
4147
4148 eg_pi->vddci_control =
4149 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, 0);
4150
4151 rv770_get_engine_memory_ss(rdev);
4152
4153 pi->asi = RV770_ASI_DFLT;
4154 pi->pasi = CYPRESS_HASI_DFLT;
4155 pi->vrc = CYPRESS_VRC_DFLT;
4156
4157 pi->power_gating = false;
4158
4159 pi->gfx_clock_gating = true;
4160
4161 pi->mg_clock_gating = true;
4162 pi->mgcgtssm = true;
4163 eg_pi->ls_clock_gating = false;
4164 eg_pi->sclk_deep_sleep = false;
4165
4166 pi->dynamic_pcie_gen2 = true;
4167
4168 if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE)
4169 pi->thermal_protection = true;
4170 else
4171 pi->thermal_protection = false;
4172
4173 pi->display_gap = true;
4174
4175 pi->dcodt = true;
4176
4177 pi->ulps = true;
4178
4179 eg_pi->dynamic_ac_timing = true;
4180 eg_pi->abm = true;
4181 eg_pi->mcls = true;
4182 eg_pi->light_sleep = true;
4183 eg_pi->memory_transition = true;
4184 #if defined(CONFIG_ACPI)
4185 eg_pi->pcie_performance_request =
4186 radeon_acpi_is_pcie_performance_request_supported(rdev);
4187 #else
4188 eg_pi->pcie_performance_request = false;
4189 #endif
4190
4191 eg_pi->dll_default_on = false;
4192
4193 eg_pi->sclk_deep_sleep = false;
4194
4195 pi->mclk_stutter_mode_threshold = 0;
4196
4197 pi->sram_end = SMC_RAM_END;
4198
4199 rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 3;
4200 rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200;
4201 rdev->pm.dpm.dyn_state.min_vddc_for_pcie_gen2 = 900;
4202 rdev->pm.dpm.dyn_state.valid_sclk_values.count = ARRAY_SIZE(btc_valid_sclk);
4203 rdev->pm.dpm.dyn_state.valid_sclk_values.values = btc_valid_sclk;
4204 rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0;
4205 rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;
4206 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 12500;
4207
4208 ni_pi->cac_data.leakage_coefficients.at = 516;
4209 ni_pi->cac_data.leakage_coefficients.bt = 18;
4210 ni_pi->cac_data.leakage_coefficients.av = 51;
4211 ni_pi->cac_data.leakage_coefficients.bv = 2957;
4212
4213 switch (rdev->pdev->device) {
4214 case 0x6700:
4215 case 0x6701:
4216 case 0x6702:
4217 case 0x6703:
4218 case 0x6718:
4219 ni_pi->cac_weights = &cac_weights_cayman_xt;
4220 break;
4221 case 0x6705:
4222 case 0x6719:
4223 case 0x671D:
4224 case 0x671C:
4225 default:
4226 ni_pi->cac_weights = &cac_weights_cayman_pro;
4227 break;
4228 case 0x6704:
4229 case 0x6706:
4230 case 0x6707:
4231 case 0x6708:
4232 case 0x6709:
4233 ni_pi->cac_weights = &cac_weights_cayman_le;
4234 break;
4235 }
4236
4237 if (ni_pi->cac_weights->enable_power_containment_by_default) {
4238 ni_pi->enable_power_containment = true;
4239 ni_pi->enable_cac = true;
4240 ni_pi->enable_sq_ramping = true;
4241 } else {
4242 ni_pi->enable_power_containment = false;
4243 ni_pi->enable_cac = false;
4244 ni_pi->enable_sq_ramping = false;
4245 }
4246
4247 ni_pi->driver_calculate_cac_leakage = false;
4248 ni_pi->cac_configuration_required = true;
4249
4250 if (ni_pi->cac_configuration_required) {
4251 ni_pi->support_cac_long_term_average = true;
4252 ni_pi->lta_window_size = ni_pi->cac_weights->l2_lta_window_size;
4253 ni_pi->lts_truncate = ni_pi->cac_weights->lts_truncate;
4254 } else {
4255 ni_pi->support_cac_long_term_average = false;
4256 ni_pi->lta_window_size = 0;
4257 ni_pi->lts_truncate = 0;
4258 }
4259
4260 ni_pi->use_power_boost_limit = true;
4261
4262 /* make sure dc limits are valid */
4263 if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
4264 (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))
4265 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc =
4266 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
4267
4268 return 0;
4269 }
4270
ni_dpm_fini(struct radeon_device * rdev)4271 void ni_dpm_fini(struct radeon_device *rdev)
4272 {
4273 int i;
4274
4275 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
4276 kfree(rdev->pm.dpm.ps[i].ps_priv);
4277 }
4278 kfree(rdev->pm.dpm.ps);
4279 kfree(rdev->pm.dpm.priv);
4280 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);
4281 r600_free_extended_power_table(rdev);
4282 }
4283
ni_dpm_print_power_state(struct radeon_device * rdev,struct radeon_ps * rps)4284 void ni_dpm_print_power_state(struct radeon_device *rdev,
4285 struct radeon_ps *rps)
4286 {
4287 struct ni_ps *ps = ni_get_ps(rps);
4288 struct rv7xx_pl *pl;
4289 int i;
4290
4291 r600_dpm_print_class_info(rps->class, rps->class2);
4292 r600_dpm_print_cap_info(rps->caps);
4293 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
4294 for (i = 0; i < ps->performance_level_count; i++) {
4295 pl = &ps->performance_levels[i];
4296 if (rdev->family >= CHIP_TAHITI)
4297 printk("\t\tpower level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n",
4298 i, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);
4299 else
4300 printk("\t\tpower level %d sclk: %u mclk: %u vddc: %u vddci: %u\n",
4301 i, pl->sclk, pl->mclk, pl->vddc, pl->vddci);
4302 }
4303 r600_dpm_print_ps_status(rdev, rps);
4304 }
4305
ni_dpm_debugfs_print_current_performance_level(struct radeon_device * rdev,struct seq_file * m)4306 void ni_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
4307 struct seq_file *m)
4308 {
4309 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4310 struct radeon_ps *rps = &eg_pi->current_rps;
4311 struct ni_ps *ps = ni_get_ps(rps);
4312 struct rv7xx_pl *pl;
4313 u32 current_index =
4314 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
4315 CURRENT_STATE_INDEX_SHIFT;
4316
4317 if (current_index >= ps->performance_level_count) {
4318 seq_printf(m, "invalid dpm profile %d\n", current_index);
4319 } else {
4320 pl = &ps->performance_levels[current_index];
4321 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
4322 seq_printf(m, "power level %d sclk: %u mclk: %u vddc: %u vddci: %u\n",
4323 current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci);
4324 }
4325 }
4326
ni_dpm_get_current_sclk(struct radeon_device * rdev)4327 u32 ni_dpm_get_current_sclk(struct radeon_device *rdev)
4328 {
4329 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4330 struct radeon_ps *rps = &eg_pi->current_rps;
4331 struct ni_ps *ps = ni_get_ps(rps);
4332 struct rv7xx_pl *pl;
4333 u32 current_index =
4334 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
4335 CURRENT_STATE_INDEX_SHIFT;
4336
4337 if (current_index >= ps->performance_level_count) {
4338 return 0;
4339 } else {
4340 pl = &ps->performance_levels[current_index];
4341 return pl->sclk;
4342 }
4343 }
4344
ni_dpm_get_current_mclk(struct radeon_device * rdev)4345 u32 ni_dpm_get_current_mclk(struct radeon_device *rdev)
4346 {
4347 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4348 struct radeon_ps *rps = &eg_pi->current_rps;
4349 struct ni_ps *ps = ni_get_ps(rps);
4350 struct rv7xx_pl *pl;
4351 u32 current_index =
4352 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
4353 CURRENT_STATE_INDEX_SHIFT;
4354
4355 if (current_index >= ps->performance_level_count) {
4356 return 0;
4357 } else {
4358 pl = &ps->performance_levels[current_index];
4359 return pl->mclk;
4360 }
4361 }
4362
ni_dpm_get_sclk(struct radeon_device * rdev,bool low)4363 u32 ni_dpm_get_sclk(struct radeon_device *rdev, bool low)
4364 {
4365 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4366 struct ni_ps *requested_state = ni_get_ps(&eg_pi->requested_rps);
4367
4368 if (low)
4369 return requested_state->performance_levels[0].sclk;
4370 else
4371 return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk;
4372 }
4373
ni_dpm_get_mclk(struct radeon_device * rdev,bool low)4374 u32 ni_dpm_get_mclk(struct radeon_device *rdev, bool low)
4375 {
4376 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4377 struct ni_ps *requested_state = ni_get_ps(&eg_pi->requested_rps);
4378
4379 if (low)
4380 return requested_state->performance_levels[0].mclk;
4381 else
4382 return requested_state->performance_levels[requested_state->performance_level_count - 1].mclk;
4383 }
4384
4385