1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. */
3
4 #include <linux/clk.h>
5 #include <linux/interconnect.h>
6 #include <linux/pm_domain.h>
7 #include <linux/pm_opp.h>
8 #include <soc/qcom/cmd-db.h>
9 #include <drm/drm_gem.h>
10
11 #include "a6xx_gpu.h"
12 #include "a6xx_gmu.xml.h"
13 #include "msm_gem.h"
14 #include "msm_gpu_trace.h"
15 #include "msm_mmu.h"
16
a6xx_gmu_fault(struct a6xx_gmu * gmu)17 static void a6xx_gmu_fault(struct a6xx_gmu *gmu)
18 {
19 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
20 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
21 struct msm_gpu *gpu = &adreno_gpu->base;
22 struct drm_device *dev = gpu->dev;
23 struct msm_drm_private *priv = dev->dev_private;
24
25 /* FIXME: add a banner here */
26 gmu->hung = true;
27
28 /* Turn off the hangcheck timer while we are resetting */
29 del_timer(&gpu->hangcheck_timer);
30
31 /* Queue the GPU handler because we need to treat this as a recovery */
32 queue_work(priv->wq, &gpu->recover_work);
33 }
34
a6xx_gmu_irq(int irq,void * data)35 static irqreturn_t a6xx_gmu_irq(int irq, void *data)
36 {
37 struct a6xx_gmu *gmu = data;
38 u32 status;
39
40 status = gmu_read(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_STATUS);
41 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_CLR, status);
42
43 if (status & A6XX_GMU_AO_HOST_INTERRUPT_STATUS_WDOG_BITE) {
44 dev_err_ratelimited(gmu->dev, "GMU watchdog expired\n");
45
46 a6xx_gmu_fault(gmu);
47 }
48
49 if (status & A6XX_GMU_AO_HOST_INTERRUPT_STATUS_HOST_AHB_BUS_ERROR)
50 dev_err_ratelimited(gmu->dev, "GMU AHB bus error\n");
51
52 if (status & A6XX_GMU_AO_HOST_INTERRUPT_STATUS_FENCE_ERR)
53 dev_err_ratelimited(gmu->dev, "GMU fence error: 0x%x\n",
54 gmu_read(gmu, REG_A6XX_GMU_AHB_FENCE_STATUS));
55
56 return IRQ_HANDLED;
57 }
58
a6xx_hfi_irq(int irq,void * data)59 static irqreturn_t a6xx_hfi_irq(int irq, void *data)
60 {
61 struct a6xx_gmu *gmu = data;
62 u32 status;
63
64 status = gmu_read(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO);
65 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, status);
66
67 if (status & A6XX_GMU_GMU2HOST_INTR_INFO_CM3_FAULT) {
68 dev_err_ratelimited(gmu->dev, "GMU firmware fault\n");
69
70 a6xx_gmu_fault(gmu);
71 }
72
73 return IRQ_HANDLED;
74 }
75
a6xx_gmu_sptprac_is_on(struct a6xx_gmu * gmu)76 bool a6xx_gmu_sptprac_is_on(struct a6xx_gmu *gmu)
77 {
78 u32 val;
79
80 /* This can be called from gpu state code so make sure GMU is valid */
81 if (!gmu->initialized)
82 return false;
83
84 val = gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS);
85
86 return !(val &
87 (A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWER_OFF |
88 A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SP_CLOCK_OFF));
89 }
90
91 /* Check to see if the GX rail is still powered */
a6xx_gmu_gx_is_on(struct a6xx_gmu * gmu)92 bool a6xx_gmu_gx_is_on(struct a6xx_gmu *gmu)
93 {
94 u32 val;
95
96 /* This can be called from gpu state code so make sure GMU is valid */
97 if (!gmu->initialized)
98 return false;
99
100 val = gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS);
101
102 return !(val &
103 (A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_GDSC_POWER_OFF |
104 A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_CLK_OFF));
105 }
106
a6xx_gmu_set_freq(struct msm_gpu * gpu,struct dev_pm_opp * opp)107 void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp)
108 {
109 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
110 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
111 struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
112 u32 perf_index;
113 unsigned long gpu_freq;
114 int ret = 0;
115
116 gpu_freq = dev_pm_opp_get_freq(opp);
117
118 if (gpu_freq == gmu->freq)
119 return;
120
121 for (perf_index = 0; perf_index < gmu->nr_gpu_freqs - 1; perf_index++)
122 if (gpu_freq == gmu->gpu_freqs[perf_index])
123 break;
124
125 gmu->current_perf_index = perf_index;
126 gmu->freq = gmu->gpu_freqs[perf_index];
127
128 trace_msm_gmu_freq_change(gmu->freq, perf_index);
129
130 /*
131 * This can get called from devfreq while the hardware is idle. Don't
132 * bring up the power if it isn't already active
133 */
134 if (pm_runtime_get_if_in_use(gmu->dev) == 0)
135 return;
136
137 if (!gmu->legacy) {
138 a6xx_hfi_set_freq(gmu, perf_index);
139 dev_pm_opp_set_bw(&gpu->pdev->dev, opp);
140 pm_runtime_put(gmu->dev);
141 return;
142 }
143
144 gmu_write(gmu, REG_A6XX_GMU_DCVS_ACK_OPTION, 0);
145
146 gmu_write(gmu, REG_A6XX_GMU_DCVS_PERF_SETTING,
147 ((3 & 0xf) << 28) | perf_index);
148
149 /*
150 * Send an invalid index as a vote for the bus bandwidth and let the
151 * firmware decide on the right vote
152 */
153 gmu_write(gmu, REG_A6XX_GMU_DCVS_BW_SETTING, 0xff);
154
155 /* Set and clear the OOB for DCVS to trigger the GMU */
156 a6xx_gmu_set_oob(gmu, GMU_OOB_DCVS_SET);
157 a6xx_gmu_clear_oob(gmu, GMU_OOB_DCVS_SET);
158
159 ret = gmu_read(gmu, REG_A6XX_GMU_DCVS_RETURN);
160 if (ret)
161 dev_err(gmu->dev, "GMU set GPU frequency error: %d\n", ret);
162
163 dev_pm_opp_set_bw(&gpu->pdev->dev, opp);
164 pm_runtime_put(gmu->dev);
165 }
166
a6xx_gmu_get_freq(struct msm_gpu * gpu)167 unsigned long a6xx_gmu_get_freq(struct msm_gpu *gpu)
168 {
169 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
170 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
171 struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
172
173 return gmu->freq;
174 }
175
a6xx_gmu_check_idle_level(struct a6xx_gmu * gmu)176 static bool a6xx_gmu_check_idle_level(struct a6xx_gmu *gmu)
177 {
178 u32 val;
179 int local = gmu->idle_level;
180
181 /* SPTP and IFPC both report as IFPC */
182 if (gmu->idle_level == GMU_IDLE_STATE_SPTP)
183 local = GMU_IDLE_STATE_IFPC;
184
185 val = gmu_read(gmu, REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE);
186
187 if (val == local) {
188 if (gmu->idle_level != GMU_IDLE_STATE_IFPC ||
189 !a6xx_gmu_gx_is_on(gmu))
190 return true;
191 }
192
193 return false;
194 }
195
196 /* Wait for the GMU to get to its most idle state */
a6xx_gmu_wait_for_idle(struct a6xx_gmu * gmu)197 int a6xx_gmu_wait_for_idle(struct a6xx_gmu *gmu)
198 {
199 return spin_until(a6xx_gmu_check_idle_level(gmu));
200 }
201
a6xx_gmu_start(struct a6xx_gmu * gmu)202 static int a6xx_gmu_start(struct a6xx_gmu *gmu)
203 {
204 int ret;
205 u32 val;
206 u32 mask, reset_val;
207
208 val = gmu_read(gmu, REG_A6XX_GMU_CM3_DTCM_START + 0xff8);
209 if (val <= 0x20010004) {
210 mask = 0xffffffff;
211 reset_val = 0xbabeface;
212 } else {
213 mask = 0x1ff;
214 reset_val = 0x100;
215 }
216
217 gmu_write(gmu, REG_A6XX_GMU_CM3_SYSRESET, 1);
218
219 /* Set the log wptr index
220 * note: downstream saves the value in poweroff and restores it here
221 */
222 gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_RESP, 0);
223
224 gmu_write(gmu, REG_A6XX_GMU_CM3_SYSRESET, 0);
225
226 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_CM3_FW_INIT_RESULT, val,
227 (val & mask) == reset_val, 100, 10000);
228
229 if (ret)
230 DRM_DEV_ERROR(gmu->dev, "GMU firmware initialization timed out\n");
231
232 return ret;
233 }
234
a6xx_gmu_hfi_start(struct a6xx_gmu * gmu)235 static int a6xx_gmu_hfi_start(struct a6xx_gmu *gmu)
236 {
237 u32 val;
238 int ret;
239
240 gmu_write(gmu, REG_A6XX_GMU_HFI_CTRL_INIT, 1);
241
242 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_HFI_CTRL_STATUS, val,
243 val & 1, 100, 10000);
244 if (ret)
245 DRM_DEV_ERROR(gmu->dev, "Unable to start the HFI queues\n");
246
247 return ret;
248 }
249
250 /* Trigger a OOB (out of band) request to the GMU */
a6xx_gmu_set_oob(struct a6xx_gmu * gmu,enum a6xx_gmu_oob_state state)251 int a6xx_gmu_set_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state)
252 {
253 int ret;
254 u32 val;
255 int request, ack;
256 const char *name;
257
258 switch (state) {
259 case GMU_OOB_GPU_SET:
260 if (gmu->legacy) {
261 request = GMU_OOB_GPU_SET_REQUEST;
262 ack = GMU_OOB_GPU_SET_ACK;
263 } else {
264 request = GMU_OOB_GPU_SET_REQUEST_NEW;
265 ack = GMU_OOB_GPU_SET_ACK_NEW;
266 }
267 name = "GPU_SET";
268 break;
269 case GMU_OOB_PERFCOUNTER_SET:
270 if (gmu->legacy) {
271 request = GMU_OOB_PERFCOUNTER_REQUEST;
272 ack = GMU_OOB_PERFCOUNTER_ACK;
273 } else {
274 request = GMU_OOB_PERFCOUNTER_REQUEST_NEW;
275 ack = GMU_OOB_PERFCOUNTER_ACK_NEW;
276 }
277 name = "PERFCOUNTER";
278 break;
279 case GMU_OOB_BOOT_SLUMBER:
280 request = GMU_OOB_BOOT_SLUMBER_REQUEST;
281 ack = GMU_OOB_BOOT_SLUMBER_ACK;
282 name = "BOOT_SLUMBER";
283 break;
284 case GMU_OOB_DCVS_SET:
285 request = GMU_OOB_DCVS_REQUEST;
286 ack = GMU_OOB_DCVS_ACK;
287 name = "GPU_DCVS";
288 break;
289 default:
290 return -EINVAL;
291 }
292
293 /* Trigger the equested OOB operation */
294 gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 1 << request);
295
296 /* Wait for the acknowledge interrupt */
297 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO, val,
298 val & (1 << ack), 100, 10000);
299
300 if (ret)
301 DRM_DEV_ERROR(gmu->dev,
302 "Timeout waiting for GMU OOB set %s: 0x%x\n",
303 name,
304 gmu_read(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO));
305
306 /* Clear the acknowledge interrupt */
307 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, 1 << ack);
308
309 return ret;
310 }
311
312 /* Clear a pending OOB state in the GMU */
a6xx_gmu_clear_oob(struct a6xx_gmu * gmu,enum a6xx_gmu_oob_state state)313 void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state)
314 {
315 if (!gmu->legacy) {
316 if (state == GMU_OOB_GPU_SET) {
317 gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET,
318 1 << GMU_OOB_GPU_SET_CLEAR_NEW);
319 } else {
320 WARN_ON(state != GMU_OOB_PERFCOUNTER_SET);
321 gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET,
322 1 << GMU_OOB_PERFCOUNTER_CLEAR_NEW);
323 }
324 return;
325 }
326
327 switch (state) {
328 case GMU_OOB_GPU_SET:
329 gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET,
330 1 << GMU_OOB_GPU_SET_CLEAR);
331 break;
332 case GMU_OOB_PERFCOUNTER_SET:
333 gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET,
334 1 << GMU_OOB_PERFCOUNTER_CLEAR);
335 break;
336 case GMU_OOB_BOOT_SLUMBER:
337 gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET,
338 1 << GMU_OOB_BOOT_SLUMBER_CLEAR);
339 break;
340 case GMU_OOB_DCVS_SET:
341 gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET,
342 1 << GMU_OOB_DCVS_CLEAR);
343 break;
344 }
345 }
346
347 /* Enable CPU control of SPTP power power collapse */
a6xx_sptprac_enable(struct a6xx_gmu * gmu)348 static int a6xx_sptprac_enable(struct a6xx_gmu *gmu)
349 {
350 int ret;
351 u32 val;
352
353 if (!gmu->legacy)
354 return 0;
355
356 gmu_write(gmu, REG_A6XX_GMU_GX_SPTPRAC_POWER_CONTROL, 0x778000);
357
358 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS, val,
359 (val & 0x38) == 0x28, 1, 100);
360
361 if (ret) {
362 DRM_DEV_ERROR(gmu->dev, "Unable to power on SPTPRAC: 0x%x\n",
363 gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS));
364 }
365
366 return 0;
367 }
368
369 /* Disable CPU control of SPTP power power collapse */
a6xx_sptprac_disable(struct a6xx_gmu * gmu)370 static void a6xx_sptprac_disable(struct a6xx_gmu *gmu)
371 {
372 u32 val;
373 int ret;
374
375 if (!gmu->legacy)
376 return;
377
378 /* Make sure retention is on */
379 gmu_rmw(gmu, REG_A6XX_GPU_CC_GX_GDSCR, 0, (1 << 11));
380
381 gmu_write(gmu, REG_A6XX_GMU_GX_SPTPRAC_POWER_CONTROL, 0x778001);
382
383 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS, val,
384 (val & 0x04), 100, 10000);
385
386 if (ret)
387 DRM_DEV_ERROR(gmu->dev, "failed to power off SPTPRAC: 0x%x\n",
388 gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS));
389 }
390
391 /* Let the GMU know we are starting a boot sequence */
a6xx_gmu_gfx_rail_on(struct a6xx_gmu * gmu)392 static int a6xx_gmu_gfx_rail_on(struct a6xx_gmu *gmu)
393 {
394 u32 vote;
395
396 /* Let the GMU know we are getting ready for boot */
397 gmu_write(gmu, REG_A6XX_GMU_BOOT_SLUMBER_OPTION, 0);
398
399 /* Choose the "default" power level as the highest available */
400 vote = gmu->gx_arc_votes[gmu->nr_gpu_freqs - 1];
401
402 gmu_write(gmu, REG_A6XX_GMU_GX_VOTE_IDX, vote & 0xff);
403 gmu_write(gmu, REG_A6XX_GMU_MX_VOTE_IDX, (vote >> 8) & 0xff);
404
405 /* Let the GMU know the boot sequence has started */
406 return a6xx_gmu_set_oob(gmu, GMU_OOB_BOOT_SLUMBER);
407 }
408
409 /* Let the GMU know that we are about to go into slumber */
a6xx_gmu_notify_slumber(struct a6xx_gmu * gmu)410 static int a6xx_gmu_notify_slumber(struct a6xx_gmu *gmu)
411 {
412 int ret;
413
414 /* Disable the power counter so the GMU isn't busy */
415 gmu_write(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 0);
416
417 /* Disable SPTP_PC if the CPU is responsible for it */
418 if (gmu->idle_level < GMU_IDLE_STATE_SPTP)
419 a6xx_sptprac_disable(gmu);
420
421 if (!gmu->legacy) {
422 ret = a6xx_hfi_send_prep_slumber(gmu);
423 goto out;
424 }
425
426 /* Tell the GMU to get ready to slumber */
427 gmu_write(gmu, REG_A6XX_GMU_BOOT_SLUMBER_OPTION, 1);
428
429 ret = a6xx_gmu_set_oob(gmu, GMU_OOB_BOOT_SLUMBER);
430 a6xx_gmu_clear_oob(gmu, GMU_OOB_BOOT_SLUMBER);
431
432 if (!ret) {
433 /* Check to see if the GMU really did slumber */
434 if (gmu_read(gmu, REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE)
435 != 0x0f) {
436 DRM_DEV_ERROR(gmu->dev, "The GMU did not go into slumber\n");
437 ret = -ETIMEDOUT;
438 }
439 }
440
441 out:
442 /* Put fence into allow mode */
443 gmu_write(gmu, REG_A6XX_GMU_AO_AHB_FENCE_CTRL, 0);
444 return ret;
445 }
446
a6xx_rpmh_start(struct a6xx_gmu * gmu)447 static int a6xx_rpmh_start(struct a6xx_gmu *gmu)
448 {
449 int ret;
450 u32 val;
451
452 gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 1 << 1);
453 /* Wait for the register to finish posting */
454 wmb();
455
456 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_RSCC_CONTROL_ACK, val,
457 val & (1 << 1), 100, 10000);
458 if (ret) {
459 DRM_DEV_ERROR(gmu->dev, "Unable to power on the GPU RSC\n");
460 return ret;
461 }
462
463 ret = gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_SEQ_BUSY_DRV0, val,
464 !val, 100, 10000);
465
466 if (ret) {
467 DRM_DEV_ERROR(gmu->dev, "GPU RSC sequence stuck while waking up the GPU\n");
468 return ret;
469 }
470
471 gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 0);
472
473 /* Set up CX GMU counter 0 to count busy ticks */
474 gmu_write(gmu, REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_MASK, 0xff000000);
475 gmu_rmw(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_0, 0xff, 0x20);
476
477 /* Enable the power counter */
478 gmu_write(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 1);
479 return 0;
480 }
481
a6xx_rpmh_stop(struct a6xx_gmu * gmu)482 static void a6xx_rpmh_stop(struct a6xx_gmu *gmu)
483 {
484 int ret;
485 u32 val;
486
487 gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 1);
488
489 ret = gmu_poll_timeout_rscc(gmu, REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0,
490 val, val & (1 << 16), 100, 10000);
491 if (ret)
492 DRM_DEV_ERROR(gmu->dev, "Unable to power off the GPU RSC\n");
493
494 gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 0);
495 }
496
pdc_write(void __iomem * ptr,u32 offset,u32 value)497 static inline void pdc_write(void __iomem *ptr, u32 offset, u32 value)
498 {
499 return msm_writel(value, ptr + (offset << 2));
500 }
501
502 static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev,
503 const char *name);
504
a6xx_gmu_rpmh_init(struct a6xx_gmu * gmu)505 static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu)
506 {
507 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
508 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
509 struct platform_device *pdev = to_platform_device(gmu->dev);
510 void __iomem *pdcptr = a6xx_gmu_get_mmio(pdev, "gmu_pdc");
511 void __iomem *seqptr = a6xx_gmu_get_mmio(pdev, "gmu_pdc_seq");
512 uint32_t pdc_address_offset;
513
514 if (!pdcptr || !seqptr)
515 goto err;
516
517 if (adreno_is_a618(adreno_gpu) || adreno_is_a640(adreno_gpu))
518 pdc_address_offset = 0x30090;
519 else if (adreno_is_a650(adreno_gpu))
520 pdc_address_offset = 0x300a0;
521 else
522 pdc_address_offset = 0x30080;
523
524 /* Disable SDE clock gating */
525 gmu_write_rscc(gmu, REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0, BIT(24));
526
527 /* Setup RSC PDC handshake for sleep and wakeup */
528 gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_SLAVE_ID_DRV0, 1);
529 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA, 0);
530 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR, 0);
531 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA + 2, 0);
532 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR + 2, 0);
533 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA + 4, 0x80000000);
534 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR + 4, 0);
535 gmu_write_rscc(gmu, REG_A6XX_RSCC_OVERRIDE_START_ADDR, 0);
536 gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_SEQ_START_ADDR, 0x4520);
537 gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_MATCH_VALUE_LO, 0x4510);
538 gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_MATCH_VALUE_HI, 0x4514);
539
540 /* Load RSC sequencer uCode for sleep and wakeup */
541 if (adreno_is_a650(adreno_gpu)) {
542 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0, 0xeaaae5a0);
543 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 1, 0xe1a1ebab);
544 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 2, 0xa2e0a581);
545 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 3, 0xecac82e2);
546 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 4, 0x0020edad);
547 } else {
548 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0, 0xa7a506a0);
549 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 1, 0xa1e6a6e7);
550 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 2, 0xa2e081e1);
551 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 3, 0xe9a982e2);
552 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 4, 0x0020e8a8);
553 }
554
555 /* Load PDC sequencer uCode for power up and power down sequence */
556 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0, 0xfebea1e1);
557 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 1, 0xa5a4a3a2);
558 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 2, 0x8382a6e0);
559 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 3, 0xbce3e284);
560 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 4, 0x002081fc);
561
562 /* Set TCS commands used by PDC sequence for low power modes */
563 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD_ENABLE_BANK, 7);
564 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK, 0);
565 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CONTROL, 0);
566 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID, 0x10108);
567 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR, 0x30010);
568 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA, 1);
569 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID + 4, 0x10108);
570 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 4, 0x30000);
571 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA + 4, 0x0);
572
573 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID + 8, 0x10108);
574 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 8, pdc_address_offset);
575 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA + 8, 0x0);
576
577 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD_ENABLE_BANK, 7);
578 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK, 0);
579 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CONTROL, 0);
580 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID, 0x10108);
581 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR, 0x30010);
582 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA, 2);
583
584 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID + 4, 0x10108);
585 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 4, 0x30000);
586 if (adreno_is_a618(adreno_gpu) || adreno_is_a650(adreno_gpu))
587 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 4, 0x2);
588 else
589 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 4, 0x3);
590 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID + 8, 0x10108);
591 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 8, pdc_address_offset);
592 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 8, 0x3);
593
594 /* Setup GPU PDC */
595 pdc_write(pdcptr, REG_A6XX_PDC_GPU_SEQ_START_ADDR, 0);
596 pdc_write(pdcptr, REG_A6XX_PDC_GPU_ENABLE_PDC, 0x80000001);
597
598 /* ensure no writes happen before the uCode is fully written */
599 wmb();
600
601 err:
602 if (!IS_ERR_OR_NULL(pdcptr))
603 iounmap(pdcptr);
604 if (!IS_ERR_OR_NULL(seqptr))
605 iounmap(seqptr);
606 }
607
608 /*
609 * The lowest 16 bits of this value are the number of XO clock cycles for main
610 * hysteresis which is set at 0x1680 cycles (300 us). The higher 16 bits are
611 * for the shorter hysteresis that happens after main - this is 0xa (.5 us)
612 */
613
614 #define GMU_PWR_COL_HYST 0x000a1680
615
616 /* Set up the idle state for the GMU */
a6xx_gmu_power_config(struct a6xx_gmu * gmu)617 static void a6xx_gmu_power_config(struct a6xx_gmu *gmu)
618 {
619 /* Disable GMU WB/RB buffer */
620 gmu_write(gmu, REG_A6XX_GMU_SYS_BUS_CONFIG, 0x1);
621 gmu_write(gmu, REG_A6XX_GMU_ICACHE_CONFIG, 0x1);
622 gmu_write(gmu, REG_A6XX_GMU_DCACHE_CONFIG, 0x1);
623
624 gmu_write(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0x9c40400);
625
626 switch (gmu->idle_level) {
627 case GMU_IDLE_STATE_IFPC:
628 gmu_write(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_HYST,
629 GMU_PWR_COL_HYST);
630 gmu_rmw(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0,
631 A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_IFPC_ENABLE |
632 A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_HM_POWER_COLLAPSE_ENABLE);
633 fallthrough;
634 case GMU_IDLE_STATE_SPTP:
635 gmu_write(gmu, REG_A6XX_GMU_PWR_COL_SPTPRAC_HYST,
636 GMU_PWR_COL_HYST);
637 gmu_rmw(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0,
638 A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_IFPC_ENABLE |
639 A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_SPTPRAC_POWER_CONTROL_ENABLE);
640 }
641
642 /* Enable RPMh GPU client */
643 gmu_rmw(gmu, REG_A6XX_GMU_RPMH_CTRL, 0,
644 A6XX_GMU_RPMH_CTRL_RPMH_INTERFACE_ENABLE |
645 A6XX_GMU_RPMH_CTRL_LLC_VOTE_ENABLE |
646 A6XX_GMU_RPMH_CTRL_DDR_VOTE_ENABLE |
647 A6XX_GMU_RPMH_CTRL_MX_VOTE_ENABLE |
648 A6XX_GMU_RPMH_CTRL_CX_VOTE_ENABLE |
649 A6XX_GMU_RPMH_CTRL_GFX_VOTE_ENABLE);
650 }
651
652 struct block_header {
653 u32 addr;
654 u32 size;
655 u32 type;
656 u32 value;
657 u32 data[];
658 };
659
660 /* this should be a general kernel helper */
in_range(u32 addr,u32 start,u32 size)661 static int in_range(u32 addr, u32 start, u32 size)
662 {
663 return addr >= start && addr < start + size;
664 }
665
fw_block_mem(struct a6xx_gmu_bo * bo,const struct block_header * blk)666 static bool fw_block_mem(struct a6xx_gmu_bo *bo, const struct block_header *blk)
667 {
668 if (!in_range(blk->addr, bo->iova, bo->size))
669 return false;
670
671 memcpy(bo->virt + blk->addr - bo->iova, blk->data, blk->size);
672 return true;
673 }
674
a6xx_gmu_fw_load(struct a6xx_gmu * gmu)675 static int a6xx_gmu_fw_load(struct a6xx_gmu *gmu)
676 {
677 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
678 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
679 const struct firmware *fw_image = adreno_gpu->fw[ADRENO_FW_GMU];
680 const struct block_header *blk;
681 u32 reg_offset;
682
683 u32 itcm_base = 0x00000000;
684 u32 dtcm_base = 0x00040000;
685
686 if (adreno_is_a650(adreno_gpu))
687 dtcm_base = 0x10004000;
688
689 if (gmu->legacy) {
690 /* Sanity check the size of the firmware that was loaded */
691 if (fw_image->size > 0x8000) {
692 DRM_DEV_ERROR(gmu->dev,
693 "GMU firmware is bigger than the available region\n");
694 return -EINVAL;
695 }
696
697 gmu_write_bulk(gmu, REG_A6XX_GMU_CM3_ITCM_START,
698 (u32*) fw_image->data, fw_image->size);
699 return 0;
700 }
701
702
703 for (blk = (const struct block_header *) fw_image->data;
704 (const u8*) blk < fw_image->data + fw_image->size;
705 blk = (const struct block_header *) &blk->data[blk->size >> 2]) {
706 if (blk->size == 0)
707 continue;
708
709 if (in_range(blk->addr, itcm_base, SZ_16K)) {
710 reg_offset = (blk->addr - itcm_base) >> 2;
711 gmu_write_bulk(gmu,
712 REG_A6XX_GMU_CM3_ITCM_START + reg_offset,
713 blk->data, blk->size);
714 } else if (in_range(blk->addr, dtcm_base, SZ_16K)) {
715 reg_offset = (blk->addr - dtcm_base) >> 2;
716 gmu_write_bulk(gmu,
717 REG_A6XX_GMU_CM3_DTCM_START + reg_offset,
718 blk->data, blk->size);
719 } else if (!fw_block_mem(&gmu->icache, blk) &&
720 !fw_block_mem(&gmu->dcache, blk) &&
721 !fw_block_mem(&gmu->dummy, blk)) {
722 DRM_DEV_ERROR(gmu->dev,
723 "failed to match fw block (addr=%.8x size=%d data[0]=%.8x)\n",
724 blk->addr, blk->size, blk->data[0]);
725 }
726 }
727
728 return 0;
729 }
730
a6xx_gmu_fw_start(struct a6xx_gmu * gmu,unsigned int state)731 static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state)
732 {
733 static bool rpmh_init;
734 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
735 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
736 int ret;
737 u32 chipid;
738
739 if (adreno_is_a650(adreno_gpu))
740 gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_CX_FAL_INTF, 1);
741
742 if (state == GMU_WARM_BOOT) {
743 ret = a6xx_rpmh_start(gmu);
744 if (ret)
745 return ret;
746 } else {
747 if (WARN(!adreno_gpu->fw[ADRENO_FW_GMU],
748 "GMU firmware is not loaded\n"))
749 return -ENOENT;
750
751 /* Turn on register retention */
752 gmu_write(gmu, REG_A6XX_GMU_GENERAL_7, 1);
753
754 /* We only need to load the RPMh microcode once */
755 if (!rpmh_init) {
756 a6xx_gmu_rpmh_init(gmu);
757 rpmh_init = true;
758 } else {
759 ret = a6xx_rpmh_start(gmu);
760 if (ret)
761 return ret;
762 }
763
764 ret = a6xx_gmu_fw_load(gmu);
765 if (ret)
766 return ret;
767 }
768
769 gmu_write(gmu, REG_A6XX_GMU_CM3_FW_INIT_RESULT, 0);
770 gmu_write(gmu, REG_A6XX_GMU_CM3_BOOT_CONFIG, 0x02);
771
772 /* Write the iova of the HFI table */
773 gmu_write(gmu, REG_A6XX_GMU_HFI_QTBL_ADDR, gmu->hfi.iova);
774 gmu_write(gmu, REG_A6XX_GMU_HFI_QTBL_INFO, 1);
775
776 gmu_write(gmu, REG_A6XX_GMU_AHB_FENCE_RANGE_0,
777 (1 << 31) | (0xa << 18) | (0xa0));
778
779 chipid = adreno_gpu->rev.core << 24;
780 chipid |= adreno_gpu->rev.major << 16;
781 chipid |= adreno_gpu->rev.minor << 12;
782 chipid |= adreno_gpu->rev.patchid << 8;
783
784 gmu_write(gmu, REG_A6XX_GMU_HFI_SFR_ADDR, chipid);
785
786 gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_MSG,
787 gmu->log.iova | (gmu->log.size / SZ_4K - 1));
788
789 /* Set up the lowest idle level on the GMU */
790 a6xx_gmu_power_config(gmu);
791
792 ret = a6xx_gmu_start(gmu);
793 if (ret)
794 return ret;
795
796 if (gmu->legacy) {
797 ret = a6xx_gmu_gfx_rail_on(gmu);
798 if (ret)
799 return ret;
800 }
801
802 /* Enable SPTP_PC if the CPU is responsible for it */
803 if (gmu->idle_level < GMU_IDLE_STATE_SPTP) {
804 ret = a6xx_sptprac_enable(gmu);
805 if (ret)
806 return ret;
807 }
808
809 ret = a6xx_gmu_hfi_start(gmu);
810 if (ret)
811 return ret;
812
813 /* FIXME: Do we need this wmb() here? */
814 wmb();
815
816 return 0;
817 }
818
819 #define A6XX_HFI_IRQ_MASK \
820 (A6XX_GMU_GMU2HOST_INTR_INFO_CM3_FAULT)
821
822 #define A6XX_GMU_IRQ_MASK \
823 (A6XX_GMU_AO_HOST_INTERRUPT_STATUS_WDOG_BITE | \
824 A6XX_GMU_AO_HOST_INTERRUPT_STATUS_HOST_AHB_BUS_ERROR | \
825 A6XX_GMU_AO_HOST_INTERRUPT_STATUS_FENCE_ERR)
826
a6xx_gmu_irq_disable(struct a6xx_gmu * gmu)827 static void a6xx_gmu_irq_disable(struct a6xx_gmu *gmu)
828 {
829 disable_irq(gmu->gmu_irq);
830 disable_irq(gmu->hfi_irq);
831
832 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_MASK, ~0);
833 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_MASK, ~0);
834 }
835
a6xx_gmu_rpmh_off(struct a6xx_gmu * gmu)836 static void a6xx_gmu_rpmh_off(struct a6xx_gmu *gmu)
837 {
838 u32 val;
839
840 /* Make sure there are no outstanding RPMh votes */
841 gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS0_DRV0_STATUS, val,
842 (val & 1), 100, 10000);
843 gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS1_DRV0_STATUS, val,
844 (val & 1), 100, 10000);
845 gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS2_DRV0_STATUS, val,
846 (val & 1), 100, 10000);
847 gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS3_DRV0_STATUS, val,
848 (val & 1), 100, 1000);
849 }
850
851 /* Force the GMU off in case it isn't responsive */
a6xx_gmu_force_off(struct a6xx_gmu * gmu)852 static void a6xx_gmu_force_off(struct a6xx_gmu *gmu)
853 {
854 /* Flush all the queues */
855 a6xx_hfi_stop(gmu);
856
857 /* Stop the interrupts */
858 a6xx_gmu_irq_disable(gmu);
859
860 /* Force off SPTP in case the GMU is managing it */
861 a6xx_sptprac_disable(gmu);
862
863 /* Make sure there are no outstanding RPMh votes */
864 a6xx_gmu_rpmh_off(gmu);
865 }
866
a6xx_gmu_set_initial_freq(struct msm_gpu * gpu,struct a6xx_gmu * gmu)867 static void a6xx_gmu_set_initial_freq(struct msm_gpu *gpu, struct a6xx_gmu *gmu)
868 {
869 struct dev_pm_opp *gpu_opp;
870 unsigned long gpu_freq = gmu->gpu_freqs[gmu->current_perf_index];
871
872 gpu_opp = dev_pm_opp_find_freq_exact(&gpu->pdev->dev, gpu_freq, true);
873 if (IS_ERR_OR_NULL(gpu_opp))
874 return;
875
876 gmu->freq = 0; /* so a6xx_gmu_set_freq() doesn't exit early */
877 a6xx_gmu_set_freq(gpu, gpu_opp);
878 dev_pm_opp_put(gpu_opp);
879 }
880
a6xx_gmu_set_initial_bw(struct msm_gpu * gpu,struct a6xx_gmu * gmu)881 static void a6xx_gmu_set_initial_bw(struct msm_gpu *gpu, struct a6xx_gmu *gmu)
882 {
883 struct dev_pm_opp *gpu_opp;
884 unsigned long gpu_freq = gmu->gpu_freqs[gmu->current_perf_index];
885
886 gpu_opp = dev_pm_opp_find_freq_exact(&gpu->pdev->dev, gpu_freq, true);
887 if (IS_ERR_OR_NULL(gpu_opp))
888 return;
889
890 dev_pm_opp_set_bw(&gpu->pdev->dev, gpu_opp);
891 dev_pm_opp_put(gpu_opp);
892 }
893
a6xx_gmu_resume(struct a6xx_gpu * a6xx_gpu)894 int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu)
895 {
896 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
897 struct msm_gpu *gpu = &adreno_gpu->base;
898 struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
899 int status, ret;
900
901 if (WARN(!gmu->initialized, "The GMU is not set up yet\n"))
902 return 0;
903
904 gmu->hung = false;
905
906 /* Turn on the resources */
907 pm_runtime_get_sync(gmu->dev);
908
909 /*
910 * "enable" the GX power domain which won't actually do anything but it
911 * will make sure that the refcounting is correct in case we need to
912 * bring down the GX after a GMU failure
913 */
914 if (!IS_ERR_OR_NULL(gmu->gxpd))
915 pm_runtime_get_sync(gmu->gxpd);
916
917 /* Use a known rate to bring up the GMU */
918 clk_set_rate(gmu->core_clk, 200000000);
919 ret = clk_bulk_prepare_enable(gmu->nr_clocks, gmu->clocks);
920 if (ret) {
921 pm_runtime_put(gmu->gxpd);
922 pm_runtime_put(gmu->dev);
923 return ret;
924 }
925
926 /* Set the bus quota to a reasonable value for boot */
927 a6xx_gmu_set_initial_bw(gpu, gmu);
928
929 /* Enable the GMU interrupt */
930 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_CLR, ~0);
931 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_MASK, ~A6XX_GMU_IRQ_MASK);
932 enable_irq(gmu->gmu_irq);
933
934 /* Check to see if we are doing a cold or warm boot */
935 status = gmu_read(gmu, REG_A6XX_GMU_GENERAL_7) == 1 ?
936 GMU_WARM_BOOT : GMU_COLD_BOOT;
937
938 /*
939 * Warm boot path does not work on newer GPUs
940 * Presumably this is because icache/dcache regions must be restored
941 */
942 if (!gmu->legacy)
943 status = GMU_COLD_BOOT;
944
945 ret = a6xx_gmu_fw_start(gmu, status);
946 if (ret)
947 goto out;
948
949 ret = a6xx_hfi_start(gmu, status);
950 if (ret)
951 goto out;
952
953 /*
954 * Turn on the GMU firmware fault interrupt after we know the boot
955 * sequence is successful
956 */
957 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, ~0);
958 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_MASK, ~A6XX_HFI_IRQ_MASK);
959 enable_irq(gmu->hfi_irq);
960
961 /* Set the GPU to the current freq */
962 a6xx_gmu_set_initial_freq(gpu, gmu);
963
964 out:
965 /* On failure, shut down the GMU to leave it in a good state */
966 if (ret) {
967 disable_irq(gmu->gmu_irq);
968 a6xx_rpmh_stop(gmu);
969 pm_runtime_put(gmu->gxpd);
970 pm_runtime_put(gmu->dev);
971 }
972
973 return ret;
974 }
975
a6xx_gmu_isidle(struct a6xx_gmu * gmu)976 bool a6xx_gmu_isidle(struct a6xx_gmu *gmu)
977 {
978 u32 reg;
979
980 if (!gmu->initialized)
981 return true;
982
983 reg = gmu_read(gmu, REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS);
984
985 if (reg & A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS_GPUBUSYIGNAHB)
986 return false;
987
988 return true;
989 }
990
991 #define GBIF_CLIENT_HALT_MASK BIT(0)
992 #define GBIF_ARB_HALT_MASK BIT(1)
993
a6xx_bus_clear_pending_transactions(struct adreno_gpu * adreno_gpu)994 static void a6xx_bus_clear_pending_transactions(struct adreno_gpu *adreno_gpu)
995 {
996 struct msm_gpu *gpu = &adreno_gpu->base;
997
998 if (!a6xx_has_gbif(adreno_gpu)) {
999 gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, 0xf);
1000 spin_until((gpu_read(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL1) &
1001 0xf) == 0xf);
1002 gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, 0);
1003
1004 return;
1005 }
1006
1007 /* Halt new client requests on GBIF */
1008 gpu_write(gpu, REG_A6XX_GBIF_HALT, GBIF_CLIENT_HALT_MASK);
1009 spin_until((gpu_read(gpu, REG_A6XX_GBIF_HALT_ACK) &
1010 (GBIF_CLIENT_HALT_MASK)) == GBIF_CLIENT_HALT_MASK);
1011
1012 /* Halt all AXI requests on GBIF */
1013 gpu_write(gpu, REG_A6XX_GBIF_HALT, GBIF_ARB_HALT_MASK);
1014 spin_until((gpu_read(gpu, REG_A6XX_GBIF_HALT_ACK) &
1015 (GBIF_ARB_HALT_MASK)) == GBIF_ARB_HALT_MASK);
1016
1017 /* The GBIF halt needs to be explicitly cleared */
1018 gpu_write(gpu, REG_A6XX_GBIF_HALT, 0x0);
1019 }
1020
1021 /* Gracefully try to shut down the GMU and by extension the GPU */
a6xx_gmu_shutdown(struct a6xx_gmu * gmu)1022 static void a6xx_gmu_shutdown(struct a6xx_gmu *gmu)
1023 {
1024 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
1025 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
1026 u32 val;
1027
1028 /*
1029 * The GMU may still be in slumber unless the GPU started so check and
1030 * skip putting it back into slumber if so
1031 */
1032 val = gmu_read(gmu, REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE);
1033
1034 if (val != 0xf) {
1035 int ret = a6xx_gmu_wait_for_idle(gmu);
1036
1037 /* If the GMU isn't responding assume it is hung */
1038 if (ret) {
1039 a6xx_gmu_force_off(gmu);
1040 return;
1041 }
1042
1043 a6xx_bus_clear_pending_transactions(adreno_gpu);
1044
1045 /* tell the GMU we want to slumber */
1046 a6xx_gmu_notify_slumber(gmu);
1047
1048 ret = gmu_poll_timeout(gmu,
1049 REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS, val,
1050 !(val & A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS_GPUBUSYIGNAHB),
1051 100, 10000);
1052
1053 /*
1054 * Let the user know we failed to slumber but don't worry too
1055 * much because we are powering down anyway
1056 */
1057
1058 if (ret)
1059 DRM_DEV_ERROR(gmu->dev,
1060 "Unable to slumber GMU: status = 0%x/0%x\n",
1061 gmu_read(gmu,
1062 REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS),
1063 gmu_read(gmu,
1064 REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS2));
1065 }
1066
1067 /* Turn off HFI */
1068 a6xx_hfi_stop(gmu);
1069
1070 /* Stop the interrupts and mask the hardware */
1071 a6xx_gmu_irq_disable(gmu);
1072
1073 /* Tell RPMh to power off the GPU */
1074 a6xx_rpmh_stop(gmu);
1075 }
1076
1077
a6xx_gmu_stop(struct a6xx_gpu * a6xx_gpu)1078 int a6xx_gmu_stop(struct a6xx_gpu *a6xx_gpu)
1079 {
1080 struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
1081 struct msm_gpu *gpu = &a6xx_gpu->base.base;
1082
1083 if (!pm_runtime_active(gmu->dev))
1084 return 0;
1085
1086 /*
1087 * Force the GMU off if we detected a hang, otherwise try to shut it
1088 * down gracefully
1089 */
1090 if (gmu->hung)
1091 a6xx_gmu_force_off(gmu);
1092 else
1093 a6xx_gmu_shutdown(gmu);
1094
1095 /* Remove the bus vote */
1096 dev_pm_opp_set_bw(&gpu->pdev->dev, NULL);
1097
1098 /*
1099 * Make sure the GX domain is off before turning off the GMU (CX)
1100 * domain. Usually the GMU does this but only if the shutdown sequence
1101 * was successful
1102 */
1103 if (!IS_ERR_OR_NULL(gmu->gxpd))
1104 pm_runtime_put_sync(gmu->gxpd);
1105
1106 clk_bulk_disable_unprepare(gmu->nr_clocks, gmu->clocks);
1107
1108 pm_runtime_put_sync(gmu->dev);
1109
1110 return 0;
1111 }
1112
a6xx_gmu_memory_free(struct a6xx_gmu * gmu)1113 static void a6xx_gmu_memory_free(struct a6xx_gmu *gmu)
1114 {
1115 msm_gem_kernel_put(gmu->hfi.obj, gmu->aspace, false);
1116 msm_gem_kernel_put(gmu->debug.obj, gmu->aspace, false);
1117 msm_gem_kernel_put(gmu->icache.obj, gmu->aspace, false);
1118 msm_gem_kernel_put(gmu->dcache.obj, gmu->aspace, false);
1119 msm_gem_kernel_put(gmu->dummy.obj, gmu->aspace, false);
1120 msm_gem_kernel_put(gmu->log.obj, gmu->aspace, false);
1121
1122 gmu->aspace->mmu->funcs->detach(gmu->aspace->mmu);
1123 msm_gem_address_space_put(gmu->aspace);
1124 }
1125
a6xx_gmu_memory_alloc(struct a6xx_gmu * gmu,struct a6xx_gmu_bo * bo,size_t size,u64 iova)1126 static int a6xx_gmu_memory_alloc(struct a6xx_gmu *gmu, struct a6xx_gmu_bo *bo,
1127 size_t size, u64 iova)
1128 {
1129 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
1130 struct drm_device *dev = a6xx_gpu->base.base.dev;
1131 uint32_t flags = MSM_BO_WC;
1132 u64 range_start, range_end;
1133 int ret;
1134
1135 size = PAGE_ALIGN(size);
1136 if (!iova) {
1137 /* no fixed address - use GMU's uncached range */
1138 range_start = 0x60000000 + PAGE_SIZE; /* skip dummy page */
1139 range_end = 0x80000000;
1140 } else {
1141 /* range for fixed address */
1142 range_start = iova;
1143 range_end = iova + size;
1144 /* use IOMMU_PRIV for icache/dcache */
1145 flags |= MSM_BO_MAP_PRIV;
1146 }
1147
1148 bo->obj = msm_gem_new(dev, size, flags);
1149 if (IS_ERR(bo->obj))
1150 return PTR_ERR(bo->obj);
1151
1152 ret = msm_gem_get_and_pin_iova_range(bo->obj, gmu->aspace, &bo->iova,
1153 range_start >> PAGE_SHIFT, range_end >> PAGE_SHIFT);
1154 if (ret) {
1155 drm_gem_object_put(bo->obj);
1156 return ret;
1157 }
1158
1159 bo->virt = msm_gem_get_vaddr(bo->obj);
1160 bo->size = size;
1161
1162 return 0;
1163 }
1164
a6xx_gmu_memory_probe(struct a6xx_gmu * gmu)1165 static int a6xx_gmu_memory_probe(struct a6xx_gmu *gmu)
1166 {
1167 struct iommu_domain *domain;
1168 struct msm_mmu *mmu;
1169
1170 domain = iommu_domain_alloc(&platform_bus_type);
1171 if (!domain)
1172 return -ENODEV;
1173
1174 mmu = msm_iommu_new(gmu->dev, domain);
1175 gmu->aspace = msm_gem_address_space_create(mmu, "gmu", 0x0, 0x80000000);
1176 if (IS_ERR(gmu->aspace)) {
1177 iommu_domain_free(domain);
1178 return PTR_ERR(gmu->aspace);
1179 }
1180
1181 return 0;
1182 }
1183
1184 /* Return the 'arc-level' for the given frequency */
a6xx_gmu_get_arc_level(struct device * dev,unsigned long freq)1185 static unsigned int a6xx_gmu_get_arc_level(struct device *dev,
1186 unsigned long freq)
1187 {
1188 struct dev_pm_opp *opp;
1189 unsigned int val;
1190
1191 if (!freq)
1192 return 0;
1193
1194 opp = dev_pm_opp_find_freq_exact(dev, freq, true);
1195 if (IS_ERR(opp))
1196 return 0;
1197
1198 val = dev_pm_opp_get_level(opp);
1199
1200 dev_pm_opp_put(opp);
1201
1202 return val;
1203 }
1204
a6xx_gmu_rpmh_arc_votes_init(struct device * dev,u32 * votes,unsigned long * freqs,int freqs_count,const char * id)1205 static int a6xx_gmu_rpmh_arc_votes_init(struct device *dev, u32 *votes,
1206 unsigned long *freqs, int freqs_count, const char *id)
1207 {
1208 int i, j;
1209 const u16 *pri, *sec;
1210 size_t pri_count, sec_count;
1211
1212 pri = cmd_db_read_aux_data(id, &pri_count);
1213 if (IS_ERR(pri))
1214 return PTR_ERR(pri);
1215 /*
1216 * The data comes back as an array of unsigned shorts so adjust the
1217 * count accordingly
1218 */
1219 pri_count >>= 1;
1220 if (!pri_count)
1221 return -EINVAL;
1222
1223 sec = cmd_db_read_aux_data("mx.lvl", &sec_count);
1224 if (IS_ERR(sec))
1225 return PTR_ERR(sec);
1226
1227 sec_count >>= 1;
1228 if (!sec_count)
1229 return -EINVAL;
1230
1231 /* Construct a vote for each frequency */
1232 for (i = 0; i < freqs_count; i++) {
1233 u8 pindex = 0, sindex = 0;
1234 unsigned int level = a6xx_gmu_get_arc_level(dev, freqs[i]);
1235
1236 /* Get the primary index that matches the arc level */
1237 for (j = 0; j < pri_count; j++) {
1238 if (pri[j] >= level) {
1239 pindex = j;
1240 break;
1241 }
1242 }
1243
1244 if (j == pri_count) {
1245 DRM_DEV_ERROR(dev,
1246 "Level %u not found in the RPMh list\n",
1247 level);
1248 DRM_DEV_ERROR(dev, "Available levels:\n");
1249 for (j = 0; j < pri_count; j++)
1250 DRM_DEV_ERROR(dev, " %u\n", pri[j]);
1251
1252 return -EINVAL;
1253 }
1254
1255 /*
1256 * Look for a level in in the secondary list that matches. If
1257 * nothing fits, use the maximum non zero vote
1258 */
1259
1260 for (j = 0; j < sec_count; j++) {
1261 if (sec[j] >= level) {
1262 sindex = j;
1263 break;
1264 } else if (sec[j]) {
1265 sindex = j;
1266 }
1267 }
1268
1269 /* Construct the vote */
1270 votes[i] = ((pri[pindex] & 0xffff) << 16) |
1271 (sindex << 8) | pindex;
1272 }
1273
1274 return 0;
1275 }
1276
1277 /*
1278 * The GMU votes with the RPMh for itself and on behalf of the GPU but we need
1279 * to construct the list of votes on the CPU and send it over. Query the RPMh
1280 * voltage levels and build the votes
1281 */
1282
a6xx_gmu_rpmh_votes_init(struct a6xx_gmu * gmu)1283 static int a6xx_gmu_rpmh_votes_init(struct a6xx_gmu *gmu)
1284 {
1285 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
1286 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
1287 struct msm_gpu *gpu = &adreno_gpu->base;
1288 int ret;
1289
1290 /* Build the GX votes */
1291 ret = a6xx_gmu_rpmh_arc_votes_init(&gpu->pdev->dev, gmu->gx_arc_votes,
1292 gmu->gpu_freqs, gmu->nr_gpu_freqs, "gfx.lvl");
1293
1294 /* Build the CX votes */
1295 ret |= a6xx_gmu_rpmh_arc_votes_init(gmu->dev, gmu->cx_arc_votes,
1296 gmu->gmu_freqs, gmu->nr_gmu_freqs, "cx.lvl");
1297
1298 return ret;
1299 }
1300
a6xx_gmu_build_freq_table(struct device * dev,unsigned long * freqs,u32 size)1301 static int a6xx_gmu_build_freq_table(struct device *dev, unsigned long *freqs,
1302 u32 size)
1303 {
1304 int count = dev_pm_opp_get_opp_count(dev);
1305 struct dev_pm_opp *opp;
1306 int i, index = 0;
1307 unsigned long freq = 1;
1308
1309 /*
1310 * The OPP table doesn't contain the "off" frequency level so we need to
1311 * add 1 to the table size to account for it
1312 */
1313
1314 if (WARN(count + 1 > size,
1315 "The GMU frequency table is being truncated\n"))
1316 count = size - 1;
1317
1318 /* Set the "off" frequency */
1319 freqs[index++] = 0;
1320
1321 for (i = 0; i < count; i++) {
1322 opp = dev_pm_opp_find_freq_ceil(dev, &freq);
1323 if (IS_ERR(opp))
1324 break;
1325
1326 dev_pm_opp_put(opp);
1327 freqs[index++] = freq++;
1328 }
1329
1330 return index;
1331 }
1332
a6xx_gmu_pwrlevels_probe(struct a6xx_gmu * gmu)1333 static int a6xx_gmu_pwrlevels_probe(struct a6xx_gmu *gmu)
1334 {
1335 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
1336 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
1337 struct msm_gpu *gpu = &adreno_gpu->base;
1338
1339 int ret = 0;
1340
1341 /*
1342 * The GMU handles its own frequency switching so build a list of
1343 * available frequencies to send during initialization
1344 */
1345 ret = dev_pm_opp_of_add_table(gmu->dev);
1346 if (ret) {
1347 DRM_DEV_ERROR(gmu->dev, "Unable to set the OPP table for the GMU\n");
1348 return ret;
1349 }
1350
1351 gmu->nr_gmu_freqs = a6xx_gmu_build_freq_table(gmu->dev,
1352 gmu->gmu_freqs, ARRAY_SIZE(gmu->gmu_freqs));
1353
1354 /*
1355 * The GMU also handles GPU frequency switching so build a list
1356 * from the GPU OPP table
1357 */
1358 gmu->nr_gpu_freqs = a6xx_gmu_build_freq_table(&gpu->pdev->dev,
1359 gmu->gpu_freqs, ARRAY_SIZE(gmu->gpu_freqs));
1360
1361 gmu->current_perf_index = gmu->nr_gpu_freqs - 1;
1362
1363 /* Build the list of RPMh votes that we'll send to the GMU */
1364 return a6xx_gmu_rpmh_votes_init(gmu);
1365 }
1366
a6xx_gmu_clocks_probe(struct a6xx_gmu * gmu)1367 static int a6xx_gmu_clocks_probe(struct a6xx_gmu *gmu)
1368 {
1369 int ret = devm_clk_bulk_get_all(gmu->dev, &gmu->clocks);
1370
1371 if (ret < 1)
1372 return ret;
1373
1374 gmu->nr_clocks = ret;
1375
1376 gmu->core_clk = msm_clk_bulk_get_clock(gmu->clocks,
1377 gmu->nr_clocks, "gmu");
1378
1379 return 0;
1380 }
1381
a6xx_gmu_get_mmio(struct platform_device * pdev,const char * name)1382 static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev,
1383 const char *name)
1384 {
1385 void __iomem *ret;
1386 struct resource *res = platform_get_resource_byname(pdev,
1387 IORESOURCE_MEM, name);
1388
1389 if (!res) {
1390 DRM_DEV_ERROR(&pdev->dev, "Unable to find the %s registers\n", name);
1391 return ERR_PTR(-EINVAL);
1392 }
1393
1394 ret = ioremap(res->start, resource_size(res));
1395 if (!ret) {
1396 DRM_DEV_ERROR(&pdev->dev, "Unable to map the %s registers\n", name);
1397 return ERR_PTR(-EINVAL);
1398 }
1399
1400 return ret;
1401 }
1402
a6xx_gmu_get_irq(struct a6xx_gmu * gmu,struct platform_device * pdev,const char * name,irq_handler_t handler)1403 static int a6xx_gmu_get_irq(struct a6xx_gmu *gmu, struct platform_device *pdev,
1404 const char *name, irq_handler_t handler)
1405 {
1406 int irq, ret;
1407
1408 irq = platform_get_irq_byname(pdev, name);
1409
1410 ret = request_irq(irq, handler, IRQF_TRIGGER_HIGH, name, gmu);
1411 if (ret) {
1412 DRM_DEV_ERROR(&pdev->dev, "Unable to get interrupt %s %d\n",
1413 name, ret);
1414 return ret;
1415 }
1416
1417 disable_irq(irq);
1418
1419 return irq;
1420 }
1421
a6xx_gmu_remove(struct a6xx_gpu * a6xx_gpu)1422 void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu)
1423 {
1424 struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
1425 struct platform_device *pdev = to_platform_device(gmu->dev);
1426
1427 if (!gmu->initialized)
1428 return;
1429
1430 pm_runtime_force_suspend(gmu->dev);
1431
1432 if (!IS_ERR_OR_NULL(gmu->gxpd)) {
1433 pm_runtime_disable(gmu->gxpd);
1434 dev_pm_domain_detach(gmu->gxpd, false);
1435 }
1436
1437 iounmap(gmu->mmio);
1438 if (platform_get_resource_byname(pdev, IORESOURCE_MEM, "rscc"))
1439 iounmap(gmu->rscc);
1440 gmu->mmio = NULL;
1441 gmu->rscc = NULL;
1442
1443 a6xx_gmu_memory_free(gmu);
1444
1445 free_irq(gmu->gmu_irq, gmu);
1446 free_irq(gmu->hfi_irq, gmu);
1447
1448 /* Drop reference taken in of_find_device_by_node */
1449 put_device(gmu->dev);
1450
1451 gmu->initialized = false;
1452 }
1453
a6xx_gmu_init(struct a6xx_gpu * a6xx_gpu,struct device_node * node)1454 int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node)
1455 {
1456 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
1457 struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
1458 struct platform_device *pdev = of_find_device_by_node(node);
1459 int ret;
1460
1461 if (!pdev)
1462 return -ENODEV;
1463
1464 gmu->dev = &pdev->dev;
1465
1466 of_dma_configure(gmu->dev, node, true);
1467
1468 /* Fow now, don't do anything fancy until we get our feet under us */
1469 gmu->idle_level = GMU_IDLE_STATE_ACTIVE;
1470
1471 pm_runtime_enable(gmu->dev);
1472
1473 /* Get the list of clocks */
1474 ret = a6xx_gmu_clocks_probe(gmu);
1475 if (ret)
1476 goto err_put_device;
1477
1478 ret = a6xx_gmu_memory_probe(gmu);
1479 if (ret)
1480 goto err_put_device;
1481
1482 /* Allocate memory for the GMU dummy page */
1483 ret = a6xx_gmu_memory_alloc(gmu, &gmu->dummy, SZ_4K, 0x60000000);
1484 if (ret)
1485 goto err_memory;
1486
1487 if (adreno_is_a650(adreno_gpu)) {
1488 ret = a6xx_gmu_memory_alloc(gmu, &gmu->icache,
1489 SZ_16M - SZ_16K, 0x04000);
1490 if (ret)
1491 goto err_memory;
1492 } else if (adreno_is_a640(adreno_gpu)) {
1493 ret = a6xx_gmu_memory_alloc(gmu, &gmu->icache,
1494 SZ_256K - SZ_16K, 0x04000);
1495 if (ret)
1496 goto err_memory;
1497
1498 ret = a6xx_gmu_memory_alloc(gmu, &gmu->dcache,
1499 SZ_256K - SZ_16K, 0x44000);
1500 if (ret)
1501 goto err_memory;
1502 } else {
1503 /* HFI v1, has sptprac */
1504 gmu->legacy = true;
1505
1506 /* Allocate memory for the GMU debug region */
1507 ret = a6xx_gmu_memory_alloc(gmu, &gmu->debug, SZ_16K, 0);
1508 if (ret)
1509 goto err_memory;
1510 }
1511
1512 /* Allocate memory for for the HFI queues */
1513 ret = a6xx_gmu_memory_alloc(gmu, &gmu->hfi, SZ_16K, 0);
1514 if (ret)
1515 goto err_memory;
1516
1517 /* Allocate memory for the GMU log region */
1518 ret = a6xx_gmu_memory_alloc(gmu, &gmu->log, SZ_4K, 0);
1519 if (ret)
1520 goto err_memory;
1521
1522 /* Map the GMU registers */
1523 gmu->mmio = a6xx_gmu_get_mmio(pdev, "gmu");
1524 if (IS_ERR(gmu->mmio)) {
1525 ret = PTR_ERR(gmu->mmio);
1526 goto err_memory;
1527 }
1528
1529 if (adreno_is_a650(adreno_gpu)) {
1530 gmu->rscc = a6xx_gmu_get_mmio(pdev, "rscc");
1531 if (IS_ERR(gmu->rscc))
1532 goto err_mmio;
1533 } else {
1534 gmu->rscc = gmu->mmio + 0x23000;
1535 }
1536
1537 /* Get the HFI and GMU interrupts */
1538 gmu->hfi_irq = a6xx_gmu_get_irq(gmu, pdev, "hfi", a6xx_hfi_irq);
1539 gmu->gmu_irq = a6xx_gmu_get_irq(gmu, pdev, "gmu", a6xx_gmu_irq);
1540
1541 if (gmu->hfi_irq < 0 || gmu->gmu_irq < 0)
1542 goto err_mmio;
1543
1544 /*
1545 * Get a link to the GX power domain to reset the GPU in case of GMU
1546 * crash
1547 */
1548 gmu->gxpd = dev_pm_domain_attach_by_name(gmu->dev, "gx");
1549
1550 /* Get the power levels for the GMU and GPU */
1551 a6xx_gmu_pwrlevels_probe(gmu);
1552
1553 /* Set up the HFI queues */
1554 a6xx_hfi_init(gmu);
1555
1556 gmu->initialized = true;
1557
1558 return 0;
1559
1560 err_mmio:
1561 iounmap(gmu->mmio);
1562 if (platform_get_resource_byname(pdev, IORESOURCE_MEM, "rscc"))
1563 iounmap(gmu->rscc);
1564 free_irq(gmu->gmu_irq, gmu);
1565 free_irq(gmu->hfi_irq, gmu);
1566
1567 ret = -ENODEV;
1568
1569 err_memory:
1570 a6xx_gmu_memory_free(gmu);
1571 err_put_device:
1572 /* Drop reference taken in of_find_device_by_node */
1573 put_device(gmu->dev);
1574
1575 return ret;
1576 }
1577