1 // SPDX-License-Identifier: BSD-3-Clause-Clear
2 /*
3 * Copyright (c) 2018-2020 The Linux Foundation. All rights reserved.
4 */
5
6 #include <linux/types.h>
7 #include <linux/bitops.h>
8 #include <linux/bitfield.h>
9
10 #include "hw.h"
11 #include "core.h"
12 #include "ce.h"
13
14 /* Map from pdev index to hw mac index */
ath11k_hw_ipq8074_mac_from_pdev_id(int pdev_idx)15 static u8 ath11k_hw_ipq8074_mac_from_pdev_id(int pdev_idx)
16 {
17 switch (pdev_idx) {
18 case 0:
19 return 0;
20 case 1:
21 return 2;
22 case 2:
23 return 1;
24 default:
25 return ATH11K_INVALID_HW_MAC_ID;
26 }
27 }
28
ath11k_hw_ipq6018_mac_from_pdev_id(int pdev_idx)29 static u8 ath11k_hw_ipq6018_mac_from_pdev_id(int pdev_idx)
30 {
31 return pdev_idx;
32 }
33
ath11k_init_wmi_config_qca6390(struct ath11k_base * ab,struct target_resource_config * config)34 static void ath11k_init_wmi_config_qca6390(struct ath11k_base *ab,
35 struct target_resource_config *config)
36 {
37 config->num_vdevs = 4;
38 config->num_peers = 16;
39 config->num_tids = 32;
40
41 config->num_offload_peers = 3;
42 config->num_offload_reorder_buffs = 3;
43 config->num_peer_keys = TARGET_NUM_PEER_KEYS;
44 config->ast_skid_limit = TARGET_AST_SKID_LIMIT;
45 config->tx_chain_mask = (1 << ab->target_caps.num_rf_chains) - 1;
46 config->rx_chain_mask = (1 << ab->target_caps.num_rf_chains) - 1;
47 config->rx_timeout_pri[0] = TARGET_RX_TIMEOUT_LO_PRI;
48 config->rx_timeout_pri[1] = TARGET_RX_TIMEOUT_LO_PRI;
49 config->rx_timeout_pri[2] = TARGET_RX_TIMEOUT_LO_PRI;
50 config->rx_timeout_pri[3] = TARGET_RX_TIMEOUT_HI_PRI;
51 config->rx_decap_mode = TARGET_DECAP_MODE_NATIVE_WIFI;
52 config->scan_max_pending_req = TARGET_SCAN_MAX_PENDING_REQS;
53 config->bmiss_offload_max_vdev = TARGET_BMISS_OFFLOAD_MAX_VDEV;
54 config->roam_offload_max_vdev = TARGET_ROAM_OFFLOAD_MAX_VDEV;
55 config->roam_offload_max_ap_profiles = TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES;
56 config->num_mcast_groups = 0;
57 config->num_mcast_table_elems = 0;
58 config->mcast2ucast_mode = 0;
59 config->tx_dbg_log_size = TARGET_TX_DBG_LOG_SIZE;
60 config->num_wds_entries = 0;
61 config->dma_burst_size = 0;
62 config->rx_skip_defrag_timeout_dup_detection_check = 0;
63 config->vow_config = TARGET_VOW_CONFIG;
64 config->gtk_offload_max_vdev = 2;
65 config->num_msdu_desc = 0x400;
66 config->beacon_tx_offload_max_vdev = 2;
67 config->rx_batchmode = TARGET_RX_BATCHMODE;
68
69 config->peer_map_unmap_v2_support = 0;
70 config->use_pdev_id = 1;
71 config->max_frag_entries = 0xa;
72 config->num_tdls_vdevs = 0x1;
73 config->num_tdls_conn_table_entries = 8;
74 config->beacon_tx_offload_max_vdev = 0x2;
75 config->num_multicast_filter_entries = 0x20;
76 config->num_wow_filters = 0x16;
77 config->num_keep_alive_pattern = 0;
78 }
79
ath11k_init_wmi_config_ipq8074(struct ath11k_base * ab,struct target_resource_config * config)80 static void ath11k_init_wmi_config_ipq8074(struct ath11k_base *ab,
81 struct target_resource_config *config)
82 {
83 config->num_vdevs = ab->num_radios * TARGET_NUM_VDEVS;
84
85 if (ab->num_radios == 2) {
86 config->num_peers = TARGET_NUM_PEERS(DBS);
87 config->num_tids = TARGET_NUM_TIDS(DBS);
88 } else if (ab->num_radios == 3) {
89 config->num_peers = TARGET_NUM_PEERS(DBS_SBS);
90 config->num_tids = TARGET_NUM_TIDS(DBS_SBS);
91 } else {
92 /* Control should not reach here */
93 config->num_peers = TARGET_NUM_PEERS(SINGLE);
94 config->num_tids = TARGET_NUM_TIDS(SINGLE);
95 }
96 config->num_offload_peers = TARGET_NUM_OFFLD_PEERS;
97 config->num_offload_reorder_buffs = TARGET_NUM_OFFLD_REORDER_BUFFS;
98 config->num_peer_keys = TARGET_NUM_PEER_KEYS;
99 config->ast_skid_limit = TARGET_AST_SKID_LIMIT;
100 config->tx_chain_mask = (1 << ab->target_caps.num_rf_chains) - 1;
101 config->rx_chain_mask = (1 << ab->target_caps.num_rf_chains) - 1;
102 config->rx_timeout_pri[0] = TARGET_RX_TIMEOUT_LO_PRI;
103 config->rx_timeout_pri[1] = TARGET_RX_TIMEOUT_LO_PRI;
104 config->rx_timeout_pri[2] = TARGET_RX_TIMEOUT_LO_PRI;
105 config->rx_timeout_pri[3] = TARGET_RX_TIMEOUT_HI_PRI;
106
107 if (test_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags))
108 config->rx_decap_mode = TARGET_DECAP_MODE_RAW;
109 else
110 config->rx_decap_mode = TARGET_DECAP_MODE_NATIVE_WIFI;
111
112 config->scan_max_pending_req = TARGET_SCAN_MAX_PENDING_REQS;
113 config->bmiss_offload_max_vdev = TARGET_BMISS_OFFLOAD_MAX_VDEV;
114 config->roam_offload_max_vdev = TARGET_ROAM_OFFLOAD_MAX_VDEV;
115 config->roam_offload_max_ap_profiles = TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES;
116 config->num_mcast_groups = TARGET_NUM_MCAST_GROUPS;
117 config->num_mcast_table_elems = TARGET_NUM_MCAST_TABLE_ELEMS;
118 config->mcast2ucast_mode = TARGET_MCAST2UCAST_MODE;
119 config->tx_dbg_log_size = TARGET_TX_DBG_LOG_SIZE;
120 config->num_wds_entries = TARGET_NUM_WDS_ENTRIES;
121 config->dma_burst_size = TARGET_DMA_BURST_SIZE;
122 config->rx_skip_defrag_timeout_dup_detection_check =
123 TARGET_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK;
124 config->vow_config = TARGET_VOW_CONFIG;
125 config->gtk_offload_max_vdev = TARGET_GTK_OFFLOAD_MAX_VDEV;
126 config->num_msdu_desc = TARGET_NUM_MSDU_DESC;
127 config->beacon_tx_offload_max_vdev = ab->num_radios * TARGET_MAX_BCN_OFFLD;
128 config->rx_batchmode = TARGET_RX_BATCHMODE;
129 config->peer_map_unmap_v2_support = 1;
130 config->twt_ap_pdev_count = ab->num_radios;
131 config->twt_ap_sta_count = 1000;
132 }
133
ath11k_hw_mac_id_to_pdev_id_ipq8074(struct ath11k_hw_params * hw,int mac_id)134 static int ath11k_hw_mac_id_to_pdev_id_ipq8074(struct ath11k_hw_params *hw,
135 int mac_id)
136 {
137 return mac_id;
138 }
139
ath11k_hw_mac_id_to_srng_id_ipq8074(struct ath11k_hw_params * hw,int mac_id)140 static int ath11k_hw_mac_id_to_srng_id_ipq8074(struct ath11k_hw_params *hw,
141 int mac_id)
142 {
143 return 0;
144 }
145
ath11k_hw_mac_id_to_pdev_id_qca6390(struct ath11k_hw_params * hw,int mac_id)146 static int ath11k_hw_mac_id_to_pdev_id_qca6390(struct ath11k_hw_params *hw,
147 int mac_id)
148 {
149 return 0;
150 }
151
ath11k_hw_mac_id_to_srng_id_qca6390(struct ath11k_hw_params * hw,int mac_id)152 static int ath11k_hw_mac_id_to_srng_id_qca6390(struct ath11k_hw_params *hw,
153 int mac_id)
154 {
155 return mac_id;
156 }
157
158 const struct ath11k_hw_ops ipq8074_ops = {
159 .get_hw_mac_from_pdev_id = ath11k_hw_ipq8074_mac_from_pdev_id,
160 .wmi_init_config = ath11k_init_wmi_config_ipq8074,
161 .mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_ipq8074,
162 .mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_ipq8074,
163 };
164
165 const struct ath11k_hw_ops ipq6018_ops = {
166 .get_hw_mac_from_pdev_id = ath11k_hw_ipq6018_mac_from_pdev_id,
167 .wmi_init_config = ath11k_init_wmi_config_ipq8074,
168 .mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_ipq8074,
169 .mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_ipq8074,
170 };
171
172 const struct ath11k_hw_ops qca6390_ops = {
173 .get_hw_mac_from_pdev_id = ath11k_hw_ipq8074_mac_from_pdev_id,
174 .wmi_init_config = ath11k_init_wmi_config_qca6390,
175 .mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_qca6390,
176 .mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_qca6390,
177 };
178
179 #define ATH11K_TX_RING_MASK_0 0x1
180 #define ATH11K_TX_RING_MASK_1 0x2
181 #define ATH11K_TX_RING_MASK_2 0x4
182
183 #define ATH11K_RX_RING_MASK_0 0x1
184 #define ATH11K_RX_RING_MASK_1 0x2
185 #define ATH11K_RX_RING_MASK_2 0x4
186 #define ATH11K_RX_RING_MASK_3 0x8
187
188 #define ATH11K_RX_ERR_RING_MASK_0 0x1
189
190 #define ATH11K_RX_WBM_REL_RING_MASK_0 0x1
191
192 #define ATH11K_REO_STATUS_RING_MASK_0 0x1
193
194 #define ATH11K_RXDMA2HOST_RING_MASK_0 0x1
195 #define ATH11K_RXDMA2HOST_RING_MASK_1 0x2
196 #define ATH11K_RXDMA2HOST_RING_MASK_2 0x4
197
198 #define ATH11K_HOST2RXDMA_RING_MASK_0 0x1
199 #define ATH11K_HOST2RXDMA_RING_MASK_1 0x2
200 #define ATH11K_HOST2RXDMA_RING_MASK_2 0x4
201
202 #define ATH11K_RX_MON_STATUS_RING_MASK_0 0x1
203 #define ATH11K_RX_MON_STATUS_RING_MASK_1 0x2
204 #define ATH11K_RX_MON_STATUS_RING_MASK_2 0x4
205
206 const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_ipq8074 = {
207 .tx = {
208 ATH11K_TX_RING_MASK_0,
209 ATH11K_TX_RING_MASK_1,
210 ATH11K_TX_RING_MASK_2,
211 },
212 .rx_mon_status = {
213 0, 0, 0, 0,
214 ATH11K_RX_MON_STATUS_RING_MASK_0,
215 ATH11K_RX_MON_STATUS_RING_MASK_1,
216 ATH11K_RX_MON_STATUS_RING_MASK_2,
217 },
218 .rx = {
219 0, 0, 0, 0, 0, 0, 0,
220 ATH11K_RX_RING_MASK_0,
221 ATH11K_RX_RING_MASK_1,
222 ATH11K_RX_RING_MASK_2,
223 ATH11K_RX_RING_MASK_3,
224 },
225 .rx_err = {
226 ATH11K_RX_ERR_RING_MASK_0,
227 },
228 .rx_wbm_rel = {
229 ATH11K_RX_WBM_REL_RING_MASK_0,
230 },
231 .reo_status = {
232 ATH11K_REO_STATUS_RING_MASK_0,
233 },
234 .rxdma2host = {
235 ATH11K_RXDMA2HOST_RING_MASK_0,
236 ATH11K_RXDMA2HOST_RING_MASK_1,
237 ATH11K_RXDMA2HOST_RING_MASK_2,
238 },
239 .host2rxdma = {
240 ATH11K_HOST2RXDMA_RING_MASK_0,
241 ATH11K_HOST2RXDMA_RING_MASK_1,
242 ATH11K_HOST2RXDMA_RING_MASK_2,
243 },
244 };
245
246 const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_qca6390 = {
247 .tx = {
248 ATH11K_TX_RING_MASK_0,
249 },
250 .rx_mon_status = {
251 0, 0, 0, 0,
252 ATH11K_RX_MON_STATUS_RING_MASK_0,
253 ATH11K_RX_MON_STATUS_RING_MASK_1,
254 ATH11K_RX_MON_STATUS_RING_MASK_2,
255 },
256 .rx = {
257 0, 0, 0, 0, 0, 0, 0,
258 ATH11K_RX_RING_MASK_0,
259 ATH11K_RX_RING_MASK_1,
260 ATH11K_RX_RING_MASK_2,
261 ATH11K_RX_RING_MASK_3,
262 },
263 .rx_err = {
264 ATH11K_RX_ERR_RING_MASK_0,
265 },
266 .rx_wbm_rel = {
267 ATH11K_RX_WBM_REL_RING_MASK_0,
268 },
269 .reo_status = {
270 ATH11K_REO_STATUS_RING_MASK_0,
271 },
272 .rxdma2host = {
273 ATH11K_RXDMA2HOST_RING_MASK_0,
274 ATH11K_RXDMA2HOST_RING_MASK_1,
275 ATH11K_RXDMA2HOST_RING_MASK_2,
276 },
277 .host2rxdma = {
278 },
279 };
280
281 /* Target firmware's Copy Engine configuration. */
282 const struct ce_pipe_config ath11k_target_ce_config_wlan_ipq8074[] = {
283 /* CE0: host->target HTC control and raw streams */
284 {
285 .pipenum = __cpu_to_le32(0),
286 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
287 .nentries = __cpu_to_le32(32),
288 .nbytes_max = __cpu_to_le32(2048),
289 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
290 .reserved = __cpu_to_le32(0),
291 },
292
293 /* CE1: target->host HTT + HTC control */
294 {
295 .pipenum = __cpu_to_le32(1),
296 .pipedir = __cpu_to_le32(PIPEDIR_IN),
297 .nentries = __cpu_to_le32(32),
298 .nbytes_max = __cpu_to_le32(2048),
299 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
300 .reserved = __cpu_to_le32(0),
301 },
302
303 /* CE2: target->host WMI */
304 {
305 .pipenum = __cpu_to_le32(2),
306 .pipedir = __cpu_to_le32(PIPEDIR_IN),
307 .nentries = __cpu_to_le32(32),
308 .nbytes_max = __cpu_to_le32(2048),
309 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
310 .reserved = __cpu_to_le32(0),
311 },
312
313 /* CE3: host->target WMI */
314 {
315 .pipenum = __cpu_to_le32(3),
316 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
317 .nentries = __cpu_to_le32(32),
318 .nbytes_max = __cpu_to_le32(2048),
319 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
320 .reserved = __cpu_to_le32(0),
321 },
322
323 /* CE4: host->target HTT */
324 {
325 .pipenum = __cpu_to_le32(4),
326 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
327 .nentries = __cpu_to_le32(256),
328 .nbytes_max = __cpu_to_le32(256),
329 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR),
330 .reserved = __cpu_to_le32(0),
331 },
332
333 /* CE5: target->host Pktlog */
334 {
335 .pipenum = __cpu_to_le32(5),
336 .pipedir = __cpu_to_le32(PIPEDIR_IN),
337 .nentries = __cpu_to_le32(32),
338 .nbytes_max = __cpu_to_le32(2048),
339 .flags = __cpu_to_le32(0),
340 .reserved = __cpu_to_le32(0),
341 },
342
343 /* CE6: Reserved for target autonomous hif_memcpy */
344 {
345 .pipenum = __cpu_to_le32(6),
346 .pipedir = __cpu_to_le32(PIPEDIR_INOUT),
347 .nentries = __cpu_to_le32(32),
348 .nbytes_max = __cpu_to_le32(65535),
349 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
350 .reserved = __cpu_to_le32(0),
351 },
352
353 /* CE7 used only by Host */
354 {
355 .pipenum = __cpu_to_le32(7),
356 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
357 .nentries = __cpu_to_le32(32),
358 .nbytes_max = __cpu_to_le32(2048),
359 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
360 .reserved = __cpu_to_le32(0),
361 },
362
363 /* CE8 target->host used only by IPA */
364 {
365 .pipenum = __cpu_to_le32(8),
366 .pipedir = __cpu_to_le32(PIPEDIR_INOUT),
367 .nentries = __cpu_to_le32(32),
368 .nbytes_max = __cpu_to_le32(65535),
369 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
370 .reserved = __cpu_to_le32(0),
371 },
372
373 /* CE9 host->target HTT */
374 {
375 .pipenum = __cpu_to_le32(9),
376 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
377 .nentries = __cpu_to_le32(32),
378 .nbytes_max = __cpu_to_le32(2048),
379 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
380 .reserved = __cpu_to_le32(0),
381 },
382
383 /* CE10 target->host HTT */
384 {
385 .pipenum = __cpu_to_le32(10),
386 .pipedir = __cpu_to_le32(PIPEDIR_INOUT_H2H),
387 .nentries = __cpu_to_le32(0),
388 .nbytes_max = __cpu_to_le32(0),
389 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
390 .reserved = __cpu_to_le32(0),
391 },
392
393 /* CE11 Not used */
394 };
395
396 /* Map from service/endpoint to Copy Engine.
397 * This table is derived from the CE_PCI TABLE, above.
398 * It is passed to the Target at startup for use by firmware.
399 */
400 const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_ipq8074[] = {
401 {
402 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO),
403 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
404 .pipenum = __cpu_to_le32(3),
405 },
406 {
407 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO),
408 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
409 .pipenum = __cpu_to_le32(2),
410 },
411 {
412 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK),
413 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
414 .pipenum = __cpu_to_le32(3),
415 },
416 {
417 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK),
418 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
419 .pipenum = __cpu_to_le32(2),
420 },
421 {
422 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE),
423 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
424 .pipenum = __cpu_to_le32(3),
425 },
426 {
427 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE),
428 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
429 .pipenum = __cpu_to_le32(2),
430 },
431 {
432 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI),
433 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
434 .pipenum = __cpu_to_le32(3),
435 },
436 {
437 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI),
438 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
439 .pipenum = __cpu_to_le32(2),
440 },
441 {
442 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL),
443 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
444 .pipenum = __cpu_to_le32(3),
445 },
446 {
447 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL),
448 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
449 .pipenum = __cpu_to_le32(2),
450 },
451 {
452 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC1),
453 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
454 .pipenum = __cpu_to_le32(7),
455 },
456 {
457 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC1),
458 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
459 .pipenum = __cpu_to_le32(2),
460 },
461 {
462 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC2),
463 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
464 .pipenum = __cpu_to_le32(9),
465 },
466 {
467 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC2),
468 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
469 .pipenum = __cpu_to_le32(2),
470 },
471 {
472 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL),
473 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
474 .pipenum = __cpu_to_le32(0),
475 },
476 {
477 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL),
478 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
479 .pipenum = __cpu_to_le32(1),
480 },
481 { /* not used */
482 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS),
483 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
484 .pipenum = __cpu_to_le32(0),
485 },
486 { /* not used */
487 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS),
488 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
489 .pipenum = __cpu_to_le32(1),
490 },
491 {
492 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG),
493 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
494 .pipenum = __cpu_to_le32(4),
495 },
496 {
497 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG),
498 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
499 .pipenum = __cpu_to_le32(1),
500 },
501 {
502 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_PKT_LOG),
503 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
504 .pipenum = __cpu_to_le32(5),
505 },
506
507 /* (Additions here) */
508
509 { /* terminator entry */ }
510 };
511
512 const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_ipq6018[] = {
513 {
514 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO),
515 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
516 .pipenum = __cpu_to_le32(3),
517 },
518 {
519 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO),
520 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
521 .pipenum = __cpu_to_le32(2),
522 },
523 {
524 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK),
525 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
526 .pipenum = __cpu_to_le32(3),
527 },
528 {
529 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK),
530 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
531 .pipenum = __cpu_to_le32(2),
532 },
533 {
534 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE),
535 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
536 .pipenum = __cpu_to_le32(3),
537 },
538 {
539 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE),
540 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
541 .pipenum = __cpu_to_le32(2),
542 },
543 {
544 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI),
545 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
546 .pipenum = __cpu_to_le32(3),
547 },
548 {
549 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI),
550 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
551 .pipenum = __cpu_to_le32(2),
552 },
553 {
554 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL),
555 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
556 .pipenum = __cpu_to_le32(3),
557 },
558 {
559 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL),
560 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
561 .pipenum = __cpu_to_le32(2),
562 },
563 {
564 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC1),
565 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
566 .pipenum = __cpu_to_le32(7),
567 },
568 {
569 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC1),
570 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
571 .pipenum = __cpu_to_le32(2),
572 },
573 {
574 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL),
575 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
576 .pipenum = __cpu_to_le32(0),
577 },
578 {
579 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL),
580 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
581 .pipenum = __cpu_to_le32(1),
582 },
583 { /* not used */
584 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS),
585 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
586 .pipenum = __cpu_to_le32(0),
587 },
588 { /* not used */
589 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS),
590 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
591 .pipenum = __cpu_to_le32(1),
592 },
593 {
594 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG),
595 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
596 .pipenum = __cpu_to_le32(4),
597 },
598 {
599 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG),
600 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
601 .pipenum = __cpu_to_le32(1),
602 },
603 {
604 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_PKT_LOG),
605 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
606 .pipenum = __cpu_to_le32(5),
607 },
608
609 /* (Additions here) */
610
611 { /* terminator entry */ }
612 };
613
614 /* Target firmware's Copy Engine configuration. */
615 const struct ce_pipe_config ath11k_target_ce_config_wlan_qca6390[] = {
616 /* CE0: host->target HTC control and raw streams */
617 {
618 .pipenum = __cpu_to_le32(0),
619 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
620 .nentries = __cpu_to_le32(32),
621 .nbytes_max = __cpu_to_le32(2048),
622 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
623 .reserved = __cpu_to_le32(0),
624 },
625
626 /* CE1: target->host HTT + HTC control */
627 {
628 .pipenum = __cpu_to_le32(1),
629 .pipedir = __cpu_to_le32(PIPEDIR_IN),
630 .nentries = __cpu_to_le32(32),
631 .nbytes_max = __cpu_to_le32(2048),
632 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
633 .reserved = __cpu_to_le32(0),
634 },
635
636 /* CE2: target->host WMI */
637 {
638 .pipenum = __cpu_to_le32(2),
639 .pipedir = __cpu_to_le32(PIPEDIR_IN),
640 .nentries = __cpu_to_le32(32),
641 .nbytes_max = __cpu_to_le32(2048),
642 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
643 .reserved = __cpu_to_le32(0),
644 },
645
646 /* CE3: host->target WMI */
647 {
648 .pipenum = __cpu_to_le32(3),
649 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
650 .nentries = __cpu_to_le32(32),
651 .nbytes_max = __cpu_to_le32(2048),
652 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
653 .reserved = __cpu_to_le32(0),
654 },
655
656 /* CE4: host->target HTT */
657 {
658 .pipenum = __cpu_to_le32(4),
659 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
660 .nentries = __cpu_to_le32(256),
661 .nbytes_max = __cpu_to_le32(256),
662 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR),
663 .reserved = __cpu_to_le32(0),
664 },
665
666 /* CE5: target->host Pktlog */
667 {
668 .pipenum = __cpu_to_le32(5),
669 .pipedir = __cpu_to_le32(PIPEDIR_IN),
670 .nentries = __cpu_to_le32(32),
671 .nbytes_max = __cpu_to_le32(2048),
672 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
673 .reserved = __cpu_to_le32(0),
674 },
675
676 /* CE6: Reserved for target autonomous hif_memcpy */
677 {
678 .pipenum = __cpu_to_le32(6),
679 .pipedir = __cpu_to_le32(PIPEDIR_INOUT),
680 .nentries = __cpu_to_le32(32),
681 .nbytes_max = __cpu_to_le32(16384),
682 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
683 .reserved = __cpu_to_le32(0),
684 },
685
686 /* CE7 used only by Host */
687 {
688 .pipenum = __cpu_to_le32(7),
689 .pipedir = __cpu_to_le32(PIPEDIR_INOUT_H2H),
690 .nentries = __cpu_to_le32(0),
691 .nbytes_max = __cpu_to_le32(0),
692 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR),
693 .reserved = __cpu_to_le32(0),
694 },
695
696 /* CE8 target->host used only by IPA */
697 {
698 .pipenum = __cpu_to_le32(8),
699 .pipedir = __cpu_to_le32(PIPEDIR_INOUT),
700 .nentries = __cpu_to_le32(32),
701 .nbytes_max = __cpu_to_le32(16384),
702 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
703 .reserved = __cpu_to_le32(0),
704 },
705 /* CE 9, 10, 11 are used by MHI driver */
706 };
707
708 /* Map from service/endpoint to Copy Engine.
709 * This table is derived from the CE_PCI TABLE, above.
710 * It is passed to the Target at startup for use by firmware.
711 */
712 const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_qca6390[] = {
713 {
714 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO),
715 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
716 __cpu_to_le32(3),
717 },
718 {
719 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO),
720 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
721 __cpu_to_le32(2),
722 },
723 {
724 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK),
725 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
726 __cpu_to_le32(3),
727 },
728 {
729 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK),
730 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
731 __cpu_to_le32(2),
732 },
733 {
734 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE),
735 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
736 __cpu_to_le32(3),
737 },
738 {
739 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE),
740 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
741 __cpu_to_le32(2),
742 },
743 {
744 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI),
745 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
746 __cpu_to_le32(3),
747 },
748 {
749 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI),
750 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
751 __cpu_to_le32(2),
752 },
753 {
754 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL),
755 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
756 __cpu_to_le32(3),
757 },
758 {
759 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL),
760 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
761 __cpu_to_le32(2),
762 },
763 {
764 __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL),
765 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
766 __cpu_to_le32(0),
767 },
768 {
769 __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL),
770 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
771 __cpu_to_le32(2),
772 },
773 {
774 __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG),
775 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
776 __cpu_to_le32(4),
777 },
778 {
779 __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG),
780 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
781 __cpu_to_le32(1),
782 },
783
784 /* (Additions here) */
785
786 { /* must be last */
787 __cpu_to_le32(0),
788 __cpu_to_le32(0),
789 __cpu_to_le32(0),
790 },
791 };
792
793 const struct ath11k_hw_regs ipq8074_regs = {
794 /* SW2TCL(x) R0 ring configuration address */
795 .hal_tcl1_ring_base_lsb = 0x00000510,
796 .hal_tcl1_ring_base_msb = 0x00000514,
797 .hal_tcl1_ring_id = 0x00000518,
798 .hal_tcl1_ring_misc = 0x00000520,
799 .hal_tcl1_ring_tp_addr_lsb = 0x0000052c,
800 .hal_tcl1_ring_tp_addr_msb = 0x00000530,
801 .hal_tcl1_ring_consumer_int_setup_ix0 = 0x00000540,
802 .hal_tcl1_ring_consumer_int_setup_ix1 = 0x00000544,
803 .hal_tcl1_ring_msi1_base_lsb = 0x00000558,
804 .hal_tcl1_ring_msi1_base_msb = 0x0000055c,
805 .hal_tcl1_ring_msi1_data = 0x00000560,
806 .hal_tcl2_ring_base_lsb = 0x00000568,
807 .hal_tcl_ring_base_lsb = 0x00000618,
808
809 /* TCL STATUS ring address */
810 .hal_tcl_status_ring_base_lsb = 0x00000720,
811
812 /* REO2SW(x) R0 ring configuration address */
813 .hal_reo1_ring_base_lsb = 0x0000029c,
814 .hal_reo1_ring_base_msb = 0x000002a0,
815 .hal_reo1_ring_id = 0x000002a4,
816 .hal_reo1_ring_misc = 0x000002ac,
817 .hal_reo1_ring_hp_addr_lsb = 0x000002b0,
818 .hal_reo1_ring_hp_addr_msb = 0x000002b4,
819 .hal_reo1_ring_producer_int_setup = 0x000002c0,
820 .hal_reo1_ring_msi1_base_lsb = 0x000002e4,
821 .hal_reo1_ring_msi1_base_msb = 0x000002e8,
822 .hal_reo1_ring_msi1_data = 0x000002ec,
823 .hal_reo2_ring_base_lsb = 0x000002f4,
824 .hal_reo1_aging_thresh_ix_0 = 0x00000564,
825 .hal_reo1_aging_thresh_ix_1 = 0x00000568,
826 .hal_reo1_aging_thresh_ix_2 = 0x0000056c,
827 .hal_reo1_aging_thresh_ix_3 = 0x00000570,
828
829 /* REO2SW(x) R2 ring pointers (head/tail) address */
830 .hal_reo1_ring_hp = 0x00003038,
831 .hal_reo1_ring_tp = 0x0000303c,
832 .hal_reo2_ring_hp = 0x00003040,
833
834 /* REO2TCL R0 ring configuration address */
835 .hal_reo_tcl_ring_base_lsb = 0x000003fc,
836 .hal_reo_tcl_ring_hp = 0x00003058,
837
838 /* REO status address */
839 .hal_reo_status_ring_base_lsb = 0x00000504,
840 .hal_reo_status_hp = 0x00003070,
841
842 };
843
844 const struct ath11k_hw_regs qca6390_regs = {
845 /* SW2TCL(x) R0 ring configuration address */
846 .hal_tcl1_ring_base_lsb = 0x00000684,
847 .hal_tcl1_ring_base_msb = 0x00000688,
848 .hal_tcl1_ring_id = 0x0000068c,
849 .hal_tcl1_ring_misc = 0x00000694,
850 .hal_tcl1_ring_tp_addr_lsb = 0x000006a0,
851 .hal_tcl1_ring_tp_addr_msb = 0x000006a4,
852 .hal_tcl1_ring_consumer_int_setup_ix0 = 0x000006b4,
853 .hal_tcl1_ring_consumer_int_setup_ix1 = 0x000006b8,
854 .hal_tcl1_ring_msi1_base_lsb = 0x000006cc,
855 .hal_tcl1_ring_msi1_base_msb = 0x000006d0,
856 .hal_tcl1_ring_msi1_data = 0x000006d4,
857 .hal_tcl2_ring_base_lsb = 0x000006dc,
858 .hal_tcl_ring_base_lsb = 0x0000078c,
859
860 /* TCL STATUS ring address */
861 .hal_tcl_status_ring_base_lsb = 0x00000894,
862
863 /* REO2SW(x) R0 ring configuration address */
864 .hal_reo1_ring_base_lsb = 0x00000244,
865 .hal_reo1_ring_base_msb = 0x00000248,
866 .hal_reo1_ring_id = 0x0000024c,
867 .hal_reo1_ring_misc = 0x00000254,
868 .hal_reo1_ring_hp_addr_lsb = 0x00000258,
869 .hal_reo1_ring_hp_addr_msb = 0x0000025c,
870 .hal_reo1_ring_producer_int_setup = 0x00000268,
871 .hal_reo1_ring_msi1_base_lsb = 0x0000028c,
872 .hal_reo1_ring_msi1_base_msb = 0x00000290,
873 .hal_reo1_ring_msi1_data = 0x00000294,
874 .hal_reo2_ring_base_lsb = 0x0000029c,
875 .hal_reo1_aging_thresh_ix_0 = 0x0000050c,
876 .hal_reo1_aging_thresh_ix_1 = 0x00000510,
877 .hal_reo1_aging_thresh_ix_2 = 0x00000514,
878 .hal_reo1_aging_thresh_ix_3 = 0x00000518,
879
880 /* REO2SW(x) R2 ring pointers (head/tail) address */
881 .hal_reo1_ring_hp = 0x00003030,
882 .hal_reo1_ring_tp = 0x00003034,
883 .hal_reo2_ring_hp = 0x00003038,
884
885 /* REO2TCL R0 ring configuration address */
886 .hal_reo_tcl_ring_base_lsb = 0x000003a4,
887 .hal_reo_tcl_ring_hp = 0x00003050,
888
889 /* REO status address */
890 .hal_reo_status_ring_base_lsb = 0x000004ac,
891 .hal_reo_status_hp = 0x00003068,
892 };
893