1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * QLogic qlcnic NIC Driver
4 * Copyright (c) 2009-2013 QLogic Corporation
5 */
6
7 #include <linux/types.h>
8
9 #include "qlcnic_sriov.h"
10 #include "qlcnic.h"
11 #include "qlcnic_83xx_hw.h"
12
13 #define QLC_BC_COMMAND 0
14 #define QLC_BC_RESPONSE 1
15
16 #define QLC_MBOX_RESP_TIMEOUT (10 * HZ)
17 #define QLC_MBOX_CH_FREE_TIMEOUT (10 * HZ)
18
19 #define QLC_BC_MSG 0
20 #define QLC_BC_CFREE 1
21 #define QLC_BC_FLR 2
22 #define QLC_BC_HDR_SZ 16
23 #define QLC_BC_PAYLOAD_SZ (1024 - QLC_BC_HDR_SZ)
24
25 #define QLC_DEFAULT_RCV_DESCRIPTORS_SRIOV_VF 2048
26 #define QLC_DEFAULT_JUMBO_RCV_DESCRIPTORS_SRIOV_VF 512
27
28 #define QLC_83XX_VF_RESET_FAIL_THRESH 8
29 #define QLC_BC_CMD_MAX_RETRY_CNT 5
30
31 static void qlcnic_sriov_handle_async_issue_cmd(struct work_struct *work);
32 static void qlcnic_sriov_vf_free_mac_list(struct qlcnic_adapter *);
33 static int qlcnic_sriov_alloc_bc_mbx_args(struct qlcnic_cmd_args *, u32);
34 static void qlcnic_sriov_vf_poll_dev_state(struct work_struct *);
35 static void qlcnic_sriov_vf_cancel_fw_work(struct qlcnic_adapter *);
36 static void qlcnic_sriov_cleanup_transaction(struct qlcnic_bc_trans *);
37 static int qlcnic_sriov_issue_cmd(struct qlcnic_adapter *,
38 struct qlcnic_cmd_args *);
39 static int qlcnic_sriov_channel_cfg_cmd(struct qlcnic_adapter *, u8);
40 static void qlcnic_sriov_process_bc_cmd(struct work_struct *);
41 static int qlcnic_sriov_vf_shutdown(struct pci_dev *);
42 static int qlcnic_sriov_vf_resume(struct qlcnic_adapter *);
43 static int qlcnic_sriov_async_issue_cmd(struct qlcnic_adapter *,
44 struct qlcnic_cmd_args *);
45
46 static struct qlcnic_hardware_ops qlcnic_sriov_vf_hw_ops = {
47 .read_crb = qlcnic_83xx_read_crb,
48 .write_crb = qlcnic_83xx_write_crb,
49 .read_reg = qlcnic_83xx_rd_reg_indirect,
50 .write_reg = qlcnic_83xx_wrt_reg_indirect,
51 .get_mac_address = qlcnic_83xx_get_mac_address,
52 .setup_intr = qlcnic_83xx_setup_intr,
53 .alloc_mbx_args = qlcnic_83xx_alloc_mbx_args,
54 .mbx_cmd = qlcnic_sriov_issue_cmd,
55 .get_func_no = qlcnic_83xx_get_func_no,
56 .api_lock = qlcnic_83xx_cam_lock,
57 .api_unlock = qlcnic_83xx_cam_unlock,
58 .process_lb_rcv_ring_diag = qlcnic_83xx_process_rcv_ring_diag,
59 .create_rx_ctx = qlcnic_83xx_create_rx_ctx,
60 .create_tx_ctx = qlcnic_83xx_create_tx_ctx,
61 .del_rx_ctx = qlcnic_83xx_del_rx_ctx,
62 .del_tx_ctx = qlcnic_83xx_del_tx_ctx,
63 .setup_link_event = qlcnic_83xx_setup_link_event,
64 .get_nic_info = qlcnic_83xx_get_nic_info,
65 .get_pci_info = qlcnic_83xx_get_pci_info,
66 .set_nic_info = qlcnic_83xx_set_nic_info,
67 .change_macvlan = qlcnic_83xx_sre_macaddr_change,
68 .napi_enable = qlcnic_83xx_napi_enable,
69 .napi_disable = qlcnic_83xx_napi_disable,
70 .config_intr_coal = qlcnic_83xx_config_intr_coal,
71 .config_rss = qlcnic_83xx_config_rss,
72 .config_hw_lro = qlcnic_83xx_config_hw_lro,
73 .config_promisc_mode = qlcnic_83xx_nic_set_promisc,
74 .change_l2_filter = qlcnic_83xx_change_l2_filter,
75 .get_board_info = qlcnic_83xx_get_port_info,
76 .free_mac_list = qlcnic_sriov_vf_free_mac_list,
77 .enable_sds_intr = qlcnic_83xx_enable_sds_intr,
78 .disable_sds_intr = qlcnic_83xx_disable_sds_intr,
79 .encap_rx_offload = qlcnic_83xx_encap_rx_offload,
80 .encap_tx_offload = qlcnic_83xx_encap_tx_offload,
81 };
82
83 static struct qlcnic_nic_template qlcnic_sriov_vf_ops = {
84 .config_bridged_mode = qlcnic_config_bridged_mode,
85 .config_led = qlcnic_config_led,
86 .cancel_idc_work = qlcnic_sriov_vf_cancel_fw_work,
87 .napi_add = qlcnic_83xx_napi_add,
88 .napi_del = qlcnic_83xx_napi_del,
89 .shutdown = qlcnic_sriov_vf_shutdown,
90 .resume = qlcnic_sriov_vf_resume,
91 .config_ipaddr = qlcnic_83xx_config_ipaddr,
92 .clear_legacy_intr = qlcnic_83xx_clear_legacy_intr,
93 };
94
95 static const struct qlcnic_mailbox_metadata qlcnic_sriov_bc_mbx_tbl[] = {
96 {QLCNIC_BC_CMD_CHANNEL_INIT, 2, 2},
97 {QLCNIC_BC_CMD_CHANNEL_TERM, 2, 2},
98 {QLCNIC_BC_CMD_GET_ACL, 3, 14},
99 {QLCNIC_BC_CMD_CFG_GUEST_VLAN, 2, 2},
100 };
101
qlcnic_sriov_bc_msg_check(u32 val)102 static inline bool qlcnic_sriov_bc_msg_check(u32 val)
103 {
104 return (val & (1 << QLC_BC_MSG)) ? true : false;
105 }
106
qlcnic_sriov_channel_free_check(u32 val)107 static inline bool qlcnic_sriov_channel_free_check(u32 val)
108 {
109 return (val & (1 << QLC_BC_CFREE)) ? true : false;
110 }
111
qlcnic_sriov_flr_check(u32 val)112 static inline bool qlcnic_sriov_flr_check(u32 val)
113 {
114 return (val & (1 << QLC_BC_FLR)) ? true : false;
115 }
116
qlcnic_sriov_target_func_id(u32 val)117 static inline u8 qlcnic_sriov_target_func_id(u32 val)
118 {
119 return (val >> 4) & 0xff;
120 }
121
qlcnic_sriov_virtid_fn(struct qlcnic_adapter * adapter,int vf_id)122 static int qlcnic_sriov_virtid_fn(struct qlcnic_adapter *adapter, int vf_id)
123 {
124 struct pci_dev *dev = adapter->pdev;
125 int pos;
126 u16 stride, offset;
127
128 if (qlcnic_sriov_vf_check(adapter))
129 return 0;
130
131 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_SRIOV);
132 if (!pos)
133 return 0;
134 pci_read_config_word(dev, pos + PCI_SRIOV_VF_OFFSET, &offset);
135 pci_read_config_word(dev, pos + PCI_SRIOV_VF_STRIDE, &stride);
136
137 return (dev->devfn + offset + stride * vf_id) & 0xff;
138 }
139
qlcnic_sriov_init(struct qlcnic_adapter * adapter,int num_vfs)140 int qlcnic_sriov_init(struct qlcnic_adapter *adapter, int num_vfs)
141 {
142 struct qlcnic_sriov *sriov;
143 struct qlcnic_back_channel *bc;
144 struct workqueue_struct *wq;
145 struct qlcnic_vport *vp;
146 struct qlcnic_vf_info *vf;
147 int err, i;
148
149 if (!qlcnic_sriov_enable_check(adapter))
150 return -EIO;
151
152 sriov = kzalloc(sizeof(struct qlcnic_sriov), GFP_KERNEL);
153 if (!sriov)
154 return -ENOMEM;
155
156 adapter->ahw->sriov = sriov;
157 sriov->num_vfs = num_vfs;
158 bc = &sriov->bc;
159 sriov->vf_info = kcalloc(num_vfs, sizeof(struct qlcnic_vf_info),
160 GFP_KERNEL);
161 if (!sriov->vf_info) {
162 err = -ENOMEM;
163 goto qlcnic_free_sriov;
164 }
165
166 wq = create_singlethread_workqueue("bc-trans");
167 if (wq == NULL) {
168 err = -ENOMEM;
169 dev_err(&adapter->pdev->dev,
170 "Cannot create bc-trans workqueue\n");
171 goto qlcnic_free_vf_info;
172 }
173
174 bc->bc_trans_wq = wq;
175
176 wq = create_singlethread_workqueue("async");
177 if (wq == NULL) {
178 err = -ENOMEM;
179 dev_err(&adapter->pdev->dev, "Cannot create async workqueue\n");
180 goto qlcnic_destroy_trans_wq;
181 }
182
183 bc->bc_async_wq = wq;
184 INIT_LIST_HEAD(&bc->async_cmd_list);
185 INIT_WORK(&bc->vf_async_work, qlcnic_sriov_handle_async_issue_cmd);
186 spin_lock_init(&bc->queue_lock);
187 bc->adapter = adapter;
188
189 for (i = 0; i < num_vfs; i++) {
190 vf = &sriov->vf_info[i];
191 vf->adapter = adapter;
192 vf->pci_func = qlcnic_sriov_virtid_fn(adapter, i);
193 mutex_init(&vf->send_cmd_lock);
194 spin_lock_init(&vf->vlan_list_lock);
195 INIT_LIST_HEAD(&vf->rcv_act.wait_list);
196 INIT_LIST_HEAD(&vf->rcv_pend.wait_list);
197 spin_lock_init(&vf->rcv_act.lock);
198 spin_lock_init(&vf->rcv_pend.lock);
199 init_completion(&vf->ch_free_cmpl);
200
201 INIT_WORK(&vf->trans_work, qlcnic_sriov_process_bc_cmd);
202
203 if (qlcnic_sriov_pf_check(adapter)) {
204 vp = kzalloc(sizeof(struct qlcnic_vport), GFP_KERNEL);
205 if (!vp) {
206 err = -ENOMEM;
207 goto qlcnic_destroy_async_wq;
208 }
209 sriov->vf_info[i].vp = vp;
210 vp->vlan_mode = QLC_GUEST_VLAN_MODE;
211 vp->max_tx_bw = MAX_BW;
212 vp->min_tx_bw = MIN_BW;
213 vp->spoofchk = false;
214 eth_random_addr(vp->mac);
215 dev_info(&adapter->pdev->dev,
216 "MAC Address %pM is configured for VF %d\n",
217 vp->mac, i);
218 }
219 }
220
221 return 0;
222
223 qlcnic_destroy_async_wq:
224 while (i--)
225 kfree(sriov->vf_info[i].vp);
226 destroy_workqueue(bc->bc_async_wq);
227
228 qlcnic_destroy_trans_wq:
229 destroy_workqueue(bc->bc_trans_wq);
230
231 qlcnic_free_vf_info:
232 kfree(sriov->vf_info);
233
234 qlcnic_free_sriov:
235 kfree(adapter->ahw->sriov);
236 return err;
237 }
238
qlcnic_sriov_cleanup_list(struct qlcnic_trans_list * t_list)239 void qlcnic_sriov_cleanup_list(struct qlcnic_trans_list *t_list)
240 {
241 struct qlcnic_bc_trans *trans;
242 struct qlcnic_cmd_args cmd;
243 unsigned long flags;
244
245 spin_lock_irqsave(&t_list->lock, flags);
246
247 while (!list_empty(&t_list->wait_list)) {
248 trans = list_first_entry(&t_list->wait_list,
249 struct qlcnic_bc_trans, list);
250 list_del(&trans->list);
251 t_list->count--;
252 cmd.req.arg = (u32 *)trans->req_pay;
253 cmd.rsp.arg = (u32 *)trans->rsp_pay;
254 qlcnic_free_mbx_args(&cmd);
255 qlcnic_sriov_cleanup_transaction(trans);
256 }
257
258 spin_unlock_irqrestore(&t_list->lock, flags);
259 }
260
__qlcnic_sriov_cleanup(struct qlcnic_adapter * adapter)261 void __qlcnic_sriov_cleanup(struct qlcnic_adapter *adapter)
262 {
263 struct qlcnic_sriov *sriov = adapter->ahw->sriov;
264 struct qlcnic_back_channel *bc = &sriov->bc;
265 struct qlcnic_vf_info *vf;
266 int i;
267
268 if (!qlcnic_sriov_enable_check(adapter))
269 return;
270
271 qlcnic_sriov_cleanup_async_list(bc);
272 destroy_workqueue(bc->bc_async_wq);
273
274 for (i = 0; i < sriov->num_vfs; i++) {
275 vf = &sriov->vf_info[i];
276 qlcnic_sriov_cleanup_list(&vf->rcv_pend);
277 cancel_work_sync(&vf->trans_work);
278 qlcnic_sriov_cleanup_list(&vf->rcv_act);
279 }
280
281 destroy_workqueue(bc->bc_trans_wq);
282
283 for (i = 0; i < sriov->num_vfs; i++)
284 kfree(sriov->vf_info[i].vp);
285
286 kfree(sriov->vf_info);
287 kfree(adapter->ahw->sriov);
288 }
289
qlcnic_sriov_vf_cleanup(struct qlcnic_adapter * adapter)290 static void qlcnic_sriov_vf_cleanup(struct qlcnic_adapter *adapter)
291 {
292 qlcnic_sriov_channel_cfg_cmd(adapter, QLCNIC_BC_CMD_CHANNEL_TERM);
293 qlcnic_sriov_cfg_bc_intr(adapter, 0);
294 __qlcnic_sriov_cleanup(adapter);
295 }
296
qlcnic_sriov_cleanup(struct qlcnic_adapter * adapter)297 void qlcnic_sriov_cleanup(struct qlcnic_adapter *adapter)
298 {
299 if (!test_bit(__QLCNIC_SRIOV_ENABLE, &adapter->state))
300 return;
301
302 qlcnic_sriov_free_vlans(adapter);
303
304 if (qlcnic_sriov_pf_check(adapter))
305 qlcnic_sriov_pf_cleanup(adapter);
306
307 if (qlcnic_sriov_vf_check(adapter))
308 qlcnic_sriov_vf_cleanup(adapter);
309 }
310
qlcnic_sriov_post_bc_msg(struct qlcnic_adapter * adapter,u32 * hdr,u32 * pay,u8 pci_func,u8 size)311 static int qlcnic_sriov_post_bc_msg(struct qlcnic_adapter *adapter, u32 *hdr,
312 u32 *pay, u8 pci_func, u8 size)
313 {
314 struct qlcnic_hardware_context *ahw = adapter->ahw;
315 struct qlcnic_mailbox *mbx = ahw->mailbox;
316 struct qlcnic_cmd_args cmd;
317 unsigned long timeout;
318 int err;
319
320 memset(&cmd, 0, sizeof(struct qlcnic_cmd_args));
321 cmd.hdr = hdr;
322 cmd.pay = pay;
323 cmd.pay_size = size;
324 cmd.func_num = pci_func;
325 cmd.op_type = QLC_83XX_MBX_POST_BC_OP;
326 cmd.cmd_op = ((struct qlcnic_bc_hdr *)hdr)->cmd_op;
327
328 err = mbx->ops->enqueue_cmd(adapter, &cmd, &timeout);
329 if (err) {
330 dev_err(&adapter->pdev->dev,
331 "%s: Mailbox not available, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n",
332 __func__, cmd.cmd_op, cmd.type, ahw->pci_func,
333 ahw->op_mode);
334 return err;
335 }
336
337 if (!wait_for_completion_timeout(&cmd.completion, timeout)) {
338 dev_err(&adapter->pdev->dev,
339 "%s: Mailbox command timed out, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n",
340 __func__, cmd.cmd_op, cmd.type, ahw->pci_func,
341 ahw->op_mode);
342 flush_workqueue(mbx->work_q);
343 }
344
345 return cmd.rsp_opcode;
346 }
347
qlcnic_sriov_vf_cfg_buff_desc(struct qlcnic_adapter * adapter)348 static void qlcnic_sriov_vf_cfg_buff_desc(struct qlcnic_adapter *adapter)
349 {
350 adapter->num_rxd = QLC_DEFAULT_RCV_DESCRIPTORS_SRIOV_VF;
351 adapter->max_rxd = MAX_RCV_DESCRIPTORS_10G;
352 adapter->num_jumbo_rxd = QLC_DEFAULT_JUMBO_RCV_DESCRIPTORS_SRIOV_VF;
353 adapter->max_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_10G;
354 adapter->num_txd = MAX_CMD_DESCRIPTORS;
355 adapter->max_rds_rings = MAX_RDS_RINGS;
356 }
357
qlcnic_sriov_get_vf_vport_info(struct qlcnic_adapter * adapter,struct qlcnic_info * npar_info,u16 vport_id)358 int qlcnic_sriov_get_vf_vport_info(struct qlcnic_adapter *adapter,
359 struct qlcnic_info *npar_info, u16 vport_id)
360 {
361 struct device *dev = &adapter->pdev->dev;
362 struct qlcnic_cmd_args cmd;
363 int err;
364 u32 status;
365
366 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_NIC_INFO);
367 if (err)
368 return err;
369
370 cmd.req.arg[1] = vport_id << 16 | 0x1;
371 err = qlcnic_issue_cmd(adapter, &cmd);
372 if (err) {
373 dev_err(&adapter->pdev->dev,
374 "Failed to get vport info, err=%d\n", err);
375 qlcnic_free_mbx_args(&cmd);
376 return err;
377 }
378
379 status = cmd.rsp.arg[2] & 0xffff;
380 if (status & BIT_0)
381 npar_info->min_tx_bw = MSW(cmd.rsp.arg[2]);
382 if (status & BIT_1)
383 npar_info->max_tx_bw = LSW(cmd.rsp.arg[3]);
384 if (status & BIT_2)
385 npar_info->max_tx_ques = MSW(cmd.rsp.arg[3]);
386 if (status & BIT_3)
387 npar_info->max_tx_mac_filters = LSW(cmd.rsp.arg[4]);
388 if (status & BIT_4)
389 npar_info->max_rx_mcast_mac_filters = MSW(cmd.rsp.arg[4]);
390 if (status & BIT_5)
391 npar_info->max_rx_ucast_mac_filters = LSW(cmd.rsp.arg[5]);
392 if (status & BIT_6)
393 npar_info->max_rx_ip_addr = MSW(cmd.rsp.arg[5]);
394 if (status & BIT_7)
395 npar_info->max_rx_lro_flow = LSW(cmd.rsp.arg[6]);
396 if (status & BIT_8)
397 npar_info->max_rx_status_rings = MSW(cmd.rsp.arg[6]);
398 if (status & BIT_9)
399 npar_info->max_rx_buf_rings = LSW(cmd.rsp.arg[7]);
400
401 npar_info->max_rx_ques = MSW(cmd.rsp.arg[7]);
402 npar_info->max_tx_vlan_keys = LSW(cmd.rsp.arg[8]);
403 npar_info->max_local_ipv6_addrs = MSW(cmd.rsp.arg[8]);
404 npar_info->max_remote_ipv6_addrs = LSW(cmd.rsp.arg[9]);
405
406 dev_info(dev, "\n\tmin_tx_bw: %d, max_tx_bw: %d max_tx_ques: %d,\n"
407 "\tmax_tx_mac_filters: %d max_rx_mcast_mac_filters: %d,\n"
408 "\tmax_rx_ucast_mac_filters: 0x%x, max_rx_ip_addr: %d,\n"
409 "\tmax_rx_lro_flow: %d max_rx_status_rings: %d,\n"
410 "\tmax_rx_buf_rings: %d, max_rx_ques: %d, max_tx_vlan_keys %d\n"
411 "\tlocal_ipv6_addr: %d, remote_ipv6_addr: %d\n",
412 npar_info->min_tx_bw, npar_info->max_tx_bw,
413 npar_info->max_tx_ques, npar_info->max_tx_mac_filters,
414 npar_info->max_rx_mcast_mac_filters,
415 npar_info->max_rx_ucast_mac_filters, npar_info->max_rx_ip_addr,
416 npar_info->max_rx_lro_flow, npar_info->max_rx_status_rings,
417 npar_info->max_rx_buf_rings, npar_info->max_rx_ques,
418 npar_info->max_tx_vlan_keys, npar_info->max_local_ipv6_addrs,
419 npar_info->max_remote_ipv6_addrs);
420
421 qlcnic_free_mbx_args(&cmd);
422 return err;
423 }
424
qlcnic_sriov_set_pvid_mode(struct qlcnic_adapter * adapter,struct qlcnic_cmd_args * cmd)425 static int qlcnic_sriov_set_pvid_mode(struct qlcnic_adapter *adapter,
426 struct qlcnic_cmd_args *cmd)
427 {
428 adapter->rx_pvid = MSW(cmd->rsp.arg[1]) & 0xffff;
429 adapter->flags &= ~QLCNIC_TAGGING_ENABLED;
430 return 0;
431 }
432
qlcnic_sriov_set_guest_vlan_mode(struct qlcnic_adapter * adapter,struct qlcnic_cmd_args * cmd)433 static int qlcnic_sriov_set_guest_vlan_mode(struct qlcnic_adapter *adapter,
434 struct qlcnic_cmd_args *cmd)
435 {
436 struct qlcnic_sriov *sriov = adapter->ahw->sriov;
437 int i, num_vlans, ret;
438 u16 *vlans;
439
440 if (sriov->allowed_vlans)
441 return 0;
442
443 sriov->any_vlan = cmd->rsp.arg[2] & 0xf;
444 sriov->num_allowed_vlans = cmd->rsp.arg[2] >> 16;
445 dev_info(&adapter->pdev->dev, "Number of allowed Guest VLANs = %d\n",
446 sriov->num_allowed_vlans);
447
448 ret = qlcnic_sriov_alloc_vlans(adapter);
449 if (ret)
450 return ret;
451
452 if (!sriov->any_vlan)
453 return 0;
454
455 num_vlans = sriov->num_allowed_vlans;
456 sriov->allowed_vlans = kcalloc(num_vlans, sizeof(u16), GFP_KERNEL);
457 if (!sriov->allowed_vlans)
458 return -ENOMEM;
459
460 vlans = (u16 *)&cmd->rsp.arg[3];
461 for (i = 0; i < num_vlans; i++)
462 sriov->allowed_vlans[i] = vlans[i];
463
464 return 0;
465 }
466
qlcnic_sriov_get_vf_acl(struct qlcnic_adapter * adapter)467 static int qlcnic_sriov_get_vf_acl(struct qlcnic_adapter *adapter)
468 {
469 struct qlcnic_sriov *sriov = adapter->ahw->sriov;
470 struct qlcnic_cmd_args cmd;
471 int ret = 0;
472
473 memset(&cmd, 0, sizeof(cmd));
474 ret = qlcnic_sriov_alloc_bc_mbx_args(&cmd, QLCNIC_BC_CMD_GET_ACL);
475 if (ret)
476 return ret;
477
478 ret = qlcnic_issue_cmd(adapter, &cmd);
479 if (ret) {
480 dev_err(&adapter->pdev->dev, "Failed to get ACL, err=%d\n",
481 ret);
482 } else {
483 sriov->vlan_mode = cmd.rsp.arg[1] & 0x3;
484 switch (sriov->vlan_mode) {
485 case QLC_GUEST_VLAN_MODE:
486 ret = qlcnic_sriov_set_guest_vlan_mode(adapter, &cmd);
487 break;
488 case QLC_PVID_MODE:
489 ret = qlcnic_sriov_set_pvid_mode(adapter, &cmd);
490 break;
491 }
492 }
493
494 qlcnic_free_mbx_args(&cmd);
495 return ret;
496 }
497
qlcnic_sriov_vf_init_driver(struct qlcnic_adapter * adapter)498 static int qlcnic_sriov_vf_init_driver(struct qlcnic_adapter *adapter)
499 {
500 struct qlcnic_hardware_context *ahw = adapter->ahw;
501 struct qlcnic_info nic_info;
502 int err;
503
504 err = qlcnic_sriov_get_vf_vport_info(adapter, &nic_info, 0);
505 if (err)
506 return err;
507
508 ahw->max_mc_count = nic_info.max_rx_mcast_mac_filters;
509
510 err = qlcnic_get_nic_info(adapter, &nic_info, ahw->pci_func);
511 if (err)
512 return -EIO;
513
514 if (qlcnic_83xx_get_port_info(adapter))
515 return -EIO;
516
517 qlcnic_sriov_vf_cfg_buff_desc(adapter);
518 adapter->flags |= QLCNIC_ADAPTER_INITIALIZED;
519 dev_info(&adapter->pdev->dev, "HAL Version: %d\n",
520 adapter->ahw->fw_hal_version);
521
522 ahw->physical_port = (u8) nic_info.phys_port;
523 ahw->switch_mode = nic_info.switch_mode;
524 ahw->max_mtu = nic_info.max_mtu;
525 ahw->op_mode = nic_info.op_mode;
526 ahw->capabilities = nic_info.capabilities;
527 return 0;
528 }
529
qlcnic_sriov_setup_vf(struct qlcnic_adapter * adapter,int pci_using_dac)530 static int qlcnic_sriov_setup_vf(struct qlcnic_adapter *adapter,
531 int pci_using_dac)
532 {
533 int err;
534
535 adapter->flags |= QLCNIC_VLAN_FILTERING;
536 adapter->ahw->total_nic_func = 1;
537 INIT_LIST_HEAD(&adapter->vf_mc_list);
538 if (!qlcnic_use_msi_x && !!qlcnic_use_msi)
539 dev_warn(&adapter->pdev->dev,
540 "Device does not support MSI interrupts\n");
541
542 /* compute and set default and max tx/sds rings */
543 qlcnic_set_tx_ring_count(adapter, QLCNIC_SINGLE_RING);
544 qlcnic_set_sds_ring_count(adapter, QLCNIC_SINGLE_RING);
545
546 err = qlcnic_setup_intr(adapter);
547 if (err) {
548 dev_err(&adapter->pdev->dev, "Failed to setup interrupt\n");
549 goto err_out_disable_msi;
550 }
551
552 err = qlcnic_83xx_setup_mbx_intr(adapter);
553 if (err)
554 goto err_out_disable_msi;
555
556 err = qlcnic_sriov_init(adapter, 1);
557 if (err)
558 goto err_out_disable_mbx_intr;
559
560 err = qlcnic_sriov_cfg_bc_intr(adapter, 1);
561 if (err)
562 goto err_out_cleanup_sriov;
563
564 err = qlcnic_sriov_channel_cfg_cmd(adapter, QLCNIC_BC_CMD_CHANNEL_INIT);
565 if (err)
566 goto err_out_disable_bc_intr;
567
568 err = qlcnic_sriov_vf_init_driver(adapter);
569 if (err)
570 goto err_out_send_channel_term;
571
572 err = qlcnic_sriov_get_vf_acl(adapter);
573 if (err)
574 goto err_out_send_channel_term;
575
576 err = qlcnic_setup_netdev(adapter, adapter->netdev, pci_using_dac);
577 if (err)
578 goto err_out_send_channel_term;
579
580 pci_set_drvdata(adapter->pdev, adapter);
581 dev_info(&adapter->pdev->dev, "%s: XGbE port initialized\n",
582 adapter->netdev->name);
583
584 qlcnic_schedule_work(adapter, qlcnic_sriov_vf_poll_dev_state,
585 adapter->ahw->idc.delay);
586 return 0;
587
588 err_out_send_channel_term:
589 qlcnic_sriov_channel_cfg_cmd(adapter, QLCNIC_BC_CMD_CHANNEL_TERM);
590
591 err_out_disable_bc_intr:
592 qlcnic_sriov_cfg_bc_intr(adapter, 0);
593
594 err_out_cleanup_sriov:
595 __qlcnic_sriov_cleanup(adapter);
596
597 err_out_disable_mbx_intr:
598 qlcnic_83xx_free_mbx_intr(adapter);
599
600 err_out_disable_msi:
601 qlcnic_teardown_intr(adapter);
602 return err;
603 }
604
qlcnic_sriov_check_dev_ready(struct qlcnic_adapter * adapter)605 static int qlcnic_sriov_check_dev_ready(struct qlcnic_adapter *adapter)
606 {
607 u32 state;
608
609 do {
610 msleep(20);
611 if (++adapter->fw_fail_cnt > QLC_BC_CMD_MAX_RETRY_CNT)
612 return -EIO;
613 state = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_STATE);
614 } while (state != QLC_83XX_IDC_DEV_READY);
615
616 return 0;
617 }
618
qlcnic_sriov_vf_init(struct qlcnic_adapter * adapter,int pci_using_dac)619 int qlcnic_sriov_vf_init(struct qlcnic_adapter *adapter, int pci_using_dac)
620 {
621 struct qlcnic_hardware_context *ahw = adapter->ahw;
622 int err;
623
624 set_bit(QLC_83XX_MODULE_LOADED, &ahw->idc.status);
625 ahw->idc.delay = QLC_83XX_IDC_FW_POLL_DELAY;
626 ahw->reset_context = 0;
627 adapter->fw_fail_cnt = 0;
628 ahw->msix_supported = 1;
629 adapter->need_fw_reset = 0;
630 adapter->flags |= QLCNIC_TX_INTR_SHARED;
631
632 err = qlcnic_sriov_check_dev_ready(adapter);
633 if (err)
634 return err;
635
636 err = qlcnic_sriov_setup_vf(adapter, pci_using_dac);
637 if (err)
638 return err;
639
640 if (qlcnic_read_mac_addr(adapter))
641 dev_warn(&adapter->pdev->dev, "failed to read mac addr\n");
642
643 INIT_DELAYED_WORK(&adapter->idc_aen_work, qlcnic_83xx_idc_aen_work);
644
645 clear_bit(__QLCNIC_RESETTING, &adapter->state);
646 return 0;
647 }
648
qlcnic_sriov_vf_set_ops(struct qlcnic_adapter * adapter)649 void qlcnic_sriov_vf_set_ops(struct qlcnic_adapter *adapter)
650 {
651 struct qlcnic_hardware_context *ahw = adapter->ahw;
652
653 ahw->op_mode = QLCNIC_SRIOV_VF_FUNC;
654 dev_info(&adapter->pdev->dev,
655 "HAL Version: %d Non Privileged SRIOV function\n",
656 ahw->fw_hal_version);
657 adapter->nic_ops = &qlcnic_sriov_vf_ops;
658 set_bit(__QLCNIC_SRIOV_ENABLE, &adapter->state);
659 return;
660 }
661
qlcnic_sriov_vf_register_map(struct qlcnic_hardware_context * ahw)662 void qlcnic_sriov_vf_register_map(struct qlcnic_hardware_context *ahw)
663 {
664 ahw->hw_ops = &qlcnic_sriov_vf_hw_ops;
665 ahw->reg_tbl = (u32 *)qlcnic_83xx_reg_tbl;
666 ahw->ext_reg_tbl = (u32 *)qlcnic_83xx_ext_reg_tbl;
667 }
668
qlcnic_sriov_get_bc_paysize(u32 real_pay_size,u8 curr_frag)669 static u32 qlcnic_sriov_get_bc_paysize(u32 real_pay_size, u8 curr_frag)
670 {
671 u32 pay_size;
672
673 pay_size = real_pay_size / ((curr_frag + 1) * QLC_BC_PAYLOAD_SZ);
674
675 if (pay_size)
676 pay_size = QLC_BC_PAYLOAD_SZ;
677 else
678 pay_size = real_pay_size % QLC_BC_PAYLOAD_SZ;
679
680 return pay_size;
681 }
682
qlcnic_sriov_func_to_index(struct qlcnic_adapter * adapter,u8 pci_func)683 int qlcnic_sriov_func_to_index(struct qlcnic_adapter *adapter, u8 pci_func)
684 {
685 struct qlcnic_vf_info *vf_info = adapter->ahw->sriov->vf_info;
686 u8 i;
687
688 if (qlcnic_sriov_vf_check(adapter))
689 return 0;
690
691 for (i = 0; i < adapter->ahw->sriov->num_vfs; i++) {
692 if (vf_info[i].pci_func == pci_func)
693 return i;
694 }
695
696 return -EINVAL;
697 }
698
qlcnic_sriov_alloc_bc_trans(struct qlcnic_bc_trans ** trans)699 static inline int qlcnic_sriov_alloc_bc_trans(struct qlcnic_bc_trans **trans)
700 {
701 *trans = kzalloc(sizeof(struct qlcnic_bc_trans), GFP_ATOMIC);
702 if (!*trans)
703 return -ENOMEM;
704
705 init_completion(&(*trans)->resp_cmpl);
706 return 0;
707 }
708
qlcnic_sriov_alloc_bc_msg(struct qlcnic_bc_hdr ** hdr,u32 size)709 static inline int qlcnic_sriov_alloc_bc_msg(struct qlcnic_bc_hdr **hdr,
710 u32 size)
711 {
712 *hdr = kcalloc(size, sizeof(struct qlcnic_bc_hdr), GFP_ATOMIC);
713 if (!*hdr)
714 return -ENOMEM;
715
716 return 0;
717 }
718
qlcnic_sriov_alloc_bc_mbx_args(struct qlcnic_cmd_args * mbx,u32 type)719 static int qlcnic_sriov_alloc_bc_mbx_args(struct qlcnic_cmd_args *mbx, u32 type)
720 {
721 const struct qlcnic_mailbox_metadata *mbx_tbl;
722 int i, size;
723
724 mbx_tbl = qlcnic_sriov_bc_mbx_tbl;
725 size = ARRAY_SIZE(qlcnic_sriov_bc_mbx_tbl);
726
727 for (i = 0; i < size; i++) {
728 if (type == mbx_tbl[i].cmd) {
729 mbx->op_type = QLC_BC_CMD;
730 mbx->req.num = mbx_tbl[i].in_args;
731 mbx->rsp.num = mbx_tbl[i].out_args;
732 mbx->req.arg = kcalloc(mbx->req.num, sizeof(u32),
733 GFP_ATOMIC);
734 if (!mbx->req.arg)
735 return -ENOMEM;
736 mbx->rsp.arg = kcalloc(mbx->rsp.num, sizeof(u32),
737 GFP_ATOMIC);
738 if (!mbx->rsp.arg) {
739 kfree(mbx->req.arg);
740 mbx->req.arg = NULL;
741 return -ENOMEM;
742 }
743 mbx->req.arg[0] = (type | (mbx->req.num << 16) |
744 (3 << 29));
745 mbx->rsp.arg[0] = (type & 0xffff) | mbx->rsp.num << 16;
746 return 0;
747 }
748 }
749 return -EINVAL;
750 }
751
qlcnic_sriov_prepare_bc_hdr(struct qlcnic_bc_trans * trans,struct qlcnic_cmd_args * cmd,u16 seq,u8 msg_type)752 static int qlcnic_sriov_prepare_bc_hdr(struct qlcnic_bc_trans *trans,
753 struct qlcnic_cmd_args *cmd,
754 u16 seq, u8 msg_type)
755 {
756 struct qlcnic_bc_hdr *hdr;
757 int i;
758 u32 num_regs, bc_pay_sz;
759 u16 remainder;
760 u8 cmd_op, num_frags, t_num_frags;
761
762 bc_pay_sz = QLC_BC_PAYLOAD_SZ;
763 if (msg_type == QLC_BC_COMMAND) {
764 trans->req_pay = (struct qlcnic_bc_payload *)cmd->req.arg;
765 trans->rsp_pay = (struct qlcnic_bc_payload *)cmd->rsp.arg;
766 num_regs = cmd->req.num;
767 trans->req_pay_size = (num_regs * 4);
768 num_regs = cmd->rsp.num;
769 trans->rsp_pay_size = (num_regs * 4);
770 cmd_op = cmd->req.arg[0] & 0xff;
771 remainder = (trans->req_pay_size) % (bc_pay_sz);
772 num_frags = (trans->req_pay_size) / (bc_pay_sz);
773 if (remainder)
774 num_frags++;
775 t_num_frags = num_frags;
776 if (qlcnic_sriov_alloc_bc_msg(&trans->req_hdr, num_frags))
777 return -ENOMEM;
778 remainder = (trans->rsp_pay_size) % (bc_pay_sz);
779 num_frags = (trans->rsp_pay_size) / (bc_pay_sz);
780 if (remainder)
781 num_frags++;
782 if (qlcnic_sriov_alloc_bc_msg(&trans->rsp_hdr, num_frags))
783 return -ENOMEM;
784 num_frags = t_num_frags;
785 hdr = trans->req_hdr;
786 } else {
787 cmd->req.arg = (u32 *)trans->req_pay;
788 cmd->rsp.arg = (u32 *)trans->rsp_pay;
789 cmd_op = cmd->req.arg[0] & 0xff;
790 cmd->cmd_op = cmd_op;
791 remainder = (trans->rsp_pay_size) % (bc_pay_sz);
792 num_frags = (trans->rsp_pay_size) / (bc_pay_sz);
793 if (remainder)
794 num_frags++;
795 cmd->req.num = trans->req_pay_size / 4;
796 cmd->rsp.num = trans->rsp_pay_size / 4;
797 hdr = trans->rsp_hdr;
798 cmd->op_type = trans->req_hdr->op_type;
799 }
800
801 trans->trans_id = seq;
802 trans->cmd_id = cmd_op;
803 for (i = 0; i < num_frags; i++) {
804 hdr[i].version = 2;
805 hdr[i].msg_type = msg_type;
806 hdr[i].op_type = cmd->op_type;
807 hdr[i].num_cmds = 1;
808 hdr[i].num_frags = num_frags;
809 hdr[i].frag_num = i + 1;
810 hdr[i].cmd_op = cmd_op;
811 hdr[i].seq_id = seq;
812 }
813 return 0;
814 }
815
qlcnic_sriov_cleanup_transaction(struct qlcnic_bc_trans * trans)816 static void qlcnic_sriov_cleanup_transaction(struct qlcnic_bc_trans *trans)
817 {
818 if (!trans)
819 return;
820 kfree(trans->req_hdr);
821 kfree(trans->rsp_hdr);
822 kfree(trans);
823 }
824
qlcnic_sriov_clear_trans(struct qlcnic_vf_info * vf,struct qlcnic_bc_trans * trans,u8 type)825 static int qlcnic_sriov_clear_trans(struct qlcnic_vf_info *vf,
826 struct qlcnic_bc_trans *trans, u8 type)
827 {
828 struct qlcnic_trans_list *t_list;
829 unsigned long flags;
830 int ret = 0;
831
832 if (type == QLC_BC_RESPONSE) {
833 t_list = &vf->rcv_act;
834 spin_lock_irqsave(&t_list->lock, flags);
835 t_list->count--;
836 list_del(&trans->list);
837 if (t_list->count > 0)
838 ret = 1;
839 spin_unlock_irqrestore(&t_list->lock, flags);
840 }
841 if (type == QLC_BC_COMMAND) {
842 while (test_and_set_bit(QLC_BC_VF_SEND, &vf->state))
843 msleep(100);
844 vf->send_cmd = NULL;
845 clear_bit(QLC_BC_VF_SEND, &vf->state);
846 }
847 return ret;
848 }
849
qlcnic_sriov_schedule_bc_cmd(struct qlcnic_sriov * sriov,struct qlcnic_vf_info * vf,work_func_t func)850 static void qlcnic_sriov_schedule_bc_cmd(struct qlcnic_sriov *sriov,
851 struct qlcnic_vf_info *vf,
852 work_func_t func)
853 {
854 if (test_bit(QLC_BC_VF_FLR, &vf->state) ||
855 vf->adapter->need_fw_reset)
856 return;
857
858 queue_work(sriov->bc.bc_trans_wq, &vf->trans_work);
859 }
860
qlcnic_sriov_wait_for_resp(struct qlcnic_bc_trans * trans)861 static inline void qlcnic_sriov_wait_for_resp(struct qlcnic_bc_trans *trans)
862 {
863 struct completion *cmpl = &trans->resp_cmpl;
864
865 if (wait_for_completion_timeout(cmpl, QLC_MBOX_RESP_TIMEOUT))
866 trans->trans_state = QLC_END;
867 else
868 trans->trans_state = QLC_ABORT;
869
870 return;
871 }
872
qlcnic_sriov_handle_multi_frags(struct qlcnic_bc_trans * trans,u8 type)873 static void qlcnic_sriov_handle_multi_frags(struct qlcnic_bc_trans *trans,
874 u8 type)
875 {
876 if (type == QLC_BC_RESPONSE) {
877 trans->curr_rsp_frag++;
878 if (trans->curr_rsp_frag < trans->rsp_hdr->num_frags)
879 trans->trans_state = QLC_INIT;
880 else
881 trans->trans_state = QLC_END;
882 } else {
883 trans->curr_req_frag++;
884 if (trans->curr_req_frag < trans->req_hdr->num_frags)
885 trans->trans_state = QLC_INIT;
886 else
887 trans->trans_state = QLC_WAIT_FOR_RESP;
888 }
889 }
890
qlcnic_sriov_wait_for_channel_free(struct qlcnic_bc_trans * trans,u8 type)891 static void qlcnic_sriov_wait_for_channel_free(struct qlcnic_bc_trans *trans,
892 u8 type)
893 {
894 struct qlcnic_vf_info *vf = trans->vf;
895 struct completion *cmpl = &vf->ch_free_cmpl;
896
897 if (!wait_for_completion_timeout(cmpl, QLC_MBOX_CH_FREE_TIMEOUT)) {
898 trans->trans_state = QLC_ABORT;
899 return;
900 }
901
902 clear_bit(QLC_BC_VF_CHANNEL, &vf->state);
903 qlcnic_sriov_handle_multi_frags(trans, type);
904 }
905
qlcnic_sriov_pull_bc_msg(struct qlcnic_adapter * adapter,u32 * hdr,u32 * pay,u32 size)906 static void qlcnic_sriov_pull_bc_msg(struct qlcnic_adapter *adapter,
907 u32 *hdr, u32 *pay, u32 size)
908 {
909 struct qlcnic_hardware_context *ahw = adapter->ahw;
910 u8 i, max = 2, hdr_size, j;
911
912 hdr_size = (sizeof(struct qlcnic_bc_hdr) / sizeof(u32));
913 max = (size / sizeof(u32)) + hdr_size;
914
915 for (i = 2, j = 0; j < hdr_size; i++, j++)
916 *(hdr++) = readl(QLCNIC_MBX_FW(ahw, i));
917 for (; j < max; i++, j++)
918 *(pay++) = readl(QLCNIC_MBX_FW(ahw, i));
919 }
920
__qlcnic_sriov_issue_bc_post(struct qlcnic_vf_info * vf)921 static int __qlcnic_sriov_issue_bc_post(struct qlcnic_vf_info *vf)
922 {
923 int ret = -EBUSY;
924 u32 timeout = 10000;
925
926 do {
927 if (!test_and_set_bit(QLC_BC_VF_CHANNEL, &vf->state)) {
928 ret = 0;
929 break;
930 }
931 mdelay(1);
932 } while (--timeout);
933
934 return ret;
935 }
936
qlcnic_sriov_issue_bc_post(struct qlcnic_bc_trans * trans,u8 type)937 static int qlcnic_sriov_issue_bc_post(struct qlcnic_bc_trans *trans, u8 type)
938 {
939 struct qlcnic_vf_info *vf = trans->vf;
940 u32 pay_size;
941 u32 *hdr, *pay;
942 int ret;
943 u8 pci_func = trans->func_id;
944
945 if (__qlcnic_sriov_issue_bc_post(vf))
946 return -EBUSY;
947
948 if (type == QLC_BC_COMMAND) {
949 hdr = (u32 *)(trans->req_hdr + trans->curr_req_frag);
950 pay = (u32 *)(trans->req_pay + trans->curr_req_frag);
951 pay_size = qlcnic_sriov_get_bc_paysize(trans->req_pay_size,
952 trans->curr_req_frag);
953 pay_size = (pay_size / sizeof(u32));
954 } else {
955 hdr = (u32 *)(trans->rsp_hdr + trans->curr_rsp_frag);
956 pay = (u32 *)(trans->rsp_pay + trans->curr_rsp_frag);
957 pay_size = qlcnic_sriov_get_bc_paysize(trans->rsp_pay_size,
958 trans->curr_rsp_frag);
959 pay_size = (pay_size / sizeof(u32));
960 }
961
962 ret = qlcnic_sriov_post_bc_msg(vf->adapter, hdr, pay,
963 pci_func, pay_size);
964 return ret;
965 }
966
__qlcnic_sriov_send_bc_msg(struct qlcnic_bc_trans * trans,struct qlcnic_vf_info * vf,u8 type)967 static int __qlcnic_sriov_send_bc_msg(struct qlcnic_bc_trans *trans,
968 struct qlcnic_vf_info *vf, u8 type)
969 {
970 bool flag = true;
971 int err = -EIO;
972
973 while (flag) {
974 if (test_bit(QLC_BC_VF_FLR, &vf->state) ||
975 vf->adapter->need_fw_reset)
976 trans->trans_state = QLC_ABORT;
977
978 switch (trans->trans_state) {
979 case QLC_INIT:
980 trans->trans_state = QLC_WAIT_FOR_CHANNEL_FREE;
981 if (qlcnic_sriov_issue_bc_post(trans, type))
982 trans->trans_state = QLC_ABORT;
983 break;
984 case QLC_WAIT_FOR_CHANNEL_FREE:
985 qlcnic_sriov_wait_for_channel_free(trans, type);
986 break;
987 case QLC_WAIT_FOR_RESP:
988 qlcnic_sriov_wait_for_resp(trans);
989 break;
990 case QLC_END:
991 err = 0;
992 flag = false;
993 break;
994 case QLC_ABORT:
995 err = -EIO;
996 flag = false;
997 clear_bit(QLC_BC_VF_CHANNEL, &vf->state);
998 break;
999 default:
1000 err = -EIO;
1001 flag = false;
1002 }
1003 }
1004 return err;
1005 }
1006
qlcnic_sriov_send_bc_cmd(struct qlcnic_adapter * adapter,struct qlcnic_bc_trans * trans,int pci_func)1007 static int qlcnic_sriov_send_bc_cmd(struct qlcnic_adapter *adapter,
1008 struct qlcnic_bc_trans *trans, int pci_func)
1009 {
1010 struct qlcnic_vf_info *vf;
1011 int err, index = qlcnic_sriov_func_to_index(adapter, pci_func);
1012
1013 if (index < 0)
1014 return -EIO;
1015
1016 vf = &adapter->ahw->sriov->vf_info[index];
1017 trans->vf = vf;
1018 trans->func_id = pci_func;
1019
1020 if (!test_bit(QLC_BC_VF_STATE, &vf->state)) {
1021 if (qlcnic_sriov_pf_check(adapter))
1022 return -EIO;
1023 if (qlcnic_sriov_vf_check(adapter) &&
1024 trans->cmd_id != QLCNIC_BC_CMD_CHANNEL_INIT)
1025 return -EIO;
1026 }
1027
1028 mutex_lock(&vf->send_cmd_lock);
1029 vf->send_cmd = trans;
1030 err = __qlcnic_sriov_send_bc_msg(trans, vf, QLC_BC_COMMAND);
1031 qlcnic_sriov_clear_trans(vf, trans, QLC_BC_COMMAND);
1032 mutex_unlock(&vf->send_cmd_lock);
1033 return err;
1034 }
1035
__qlcnic_sriov_process_bc_cmd(struct qlcnic_adapter * adapter,struct qlcnic_bc_trans * trans,struct qlcnic_cmd_args * cmd)1036 static void __qlcnic_sriov_process_bc_cmd(struct qlcnic_adapter *adapter,
1037 struct qlcnic_bc_trans *trans,
1038 struct qlcnic_cmd_args *cmd)
1039 {
1040 #ifdef CONFIG_QLCNIC_SRIOV
1041 if (qlcnic_sriov_pf_check(adapter)) {
1042 qlcnic_sriov_pf_process_bc_cmd(adapter, trans, cmd);
1043 return;
1044 }
1045 #endif
1046 cmd->rsp.arg[0] |= (0x9 << 25);
1047 return;
1048 }
1049
qlcnic_sriov_process_bc_cmd(struct work_struct * work)1050 static void qlcnic_sriov_process_bc_cmd(struct work_struct *work)
1051 {
1052 struct qlcnic_vf_info *vf = container_of(work, struct qlcnic_vf_info,
1053 trans_work);
1054 struct qlcnic_bc_trans *trans = NULL;
1055 struct qlcnic_adapter *adapter = vf->adapter;
1056 struct qlcnic_cmd_args cmd;
1057 u8 req;
1058
1059 if (adapter->need_fw_reset)
1060 return;
1061
1062 if (test_bit(QLC_BC_VF_FLR, &vf->state))
1063 return;
1064
1065 memset(&cmd, 0, sizeof(struct qlcnic_cmd_args));
1066 trans = list_first_entry(&vf->rcv_act.wait_list,
1067 struct qlcnic_bc_trans, list);
1068 adapter = vf->adapter;
1069
1070 if (qlcnic_sriov_prepare_bc_hdr(trans, &cmd, trans->req_hdr->seq_id,
1071 QLC_BC_RESPONSE))
1072 goto cleanup_trans;
1073
1074 __qlcnic_sriov_process_bc_cmd(adapter, trans, &cmd);
1075 trans->trans_state = QLC_INIT;
1076 __qlcnic_sriov_send_bc_msg(trans, vf, QLC_BC_RESPONSE);
1077
1078 cleanup_trans:
1079 qlcnic_free_mbx_args(&cmd);
1080 req = qlcnic_sriov_clear_trans(vf, trans, QLC_BC_RESPONSE);
1081 qlcnic_sriov_cleanup_transaction(trans);
1082 if (req)
1083 qlcnic_sriov_schedule_bc_cmd(adapter->ahw->sriov, vf,
1084 qlcnic_sriov_process_bc_cmd);
1085 }
1086
qlcnic_sriov_handle_bc_resp(struct qlcnic_bc_hdr * hdr,struct qlcnic_vf_info * vf)1087 static void qlcnic_sriov_handle_bc_resp(struct qlcnic_bc_hdr *hdr,
1088 struct qlcnic_vf_info *vf)
1089 {
1090 struct qlcnic_bc_trans *trans;
1091 u32 pay_size;
1092
1093 if (test_and_set_bit(QLC_BC_VF_SEND, &vf->state))
1094 return;
1095
1096 trans = vf->send_cmd;
1097
1098 if (trans == NULL)
1099 goto clear_send;
1100
1101 if (trans->trans_id != hdr->seq_id)
1102 goto clear_send;
1103
1104 pay_size = qlcnic_sriov_get_bc_paysize(trans->rsp_pay_size,
1105 trans->curr_rsp_frag);
1106 qlcnic_sriov_pull_bc_msg(vf->adapter,
1107 (u32 *)(trans->rsp_hdr + trans->curr_rsp_frag),
1108 (u32 *)(trans->rsp_pay + trans->curr_rsp_frag),
1109 pay_size);
1110 if (++trans->curr_rsp_frag < trans->rsp_hdr->num_frags)
1111 goto clear_send;
1112
1113 complete(&trans->resp_cmpl);
1114
1115 clear_send:
1116 clear_bit(QLC_BC_VF_SEND, &vf->state);
1117 }
1118
__qlcnic_sriov_add_act_list(struct qlcnic_sriov * sriov,struct qlcnic_vf_info * vf,struct qlcnic_bc_trans * trans)1119 int __qlcnic_sriov_add_act_list(struct qlcnic_sriov *sriov,
1120 struct qlcnic_vf_info *vf,
1121 struct qlcnic_bc_trans *trans)
1122 {
1123 struct qlcnic_trans_list *t_list = &vf->rcv_act;
1124
1125 t_list->count++;
1126 list_add_tail(&trans->list, &t_list->wait_list);
1127 if (t_list->count == 1)
1128 qlcnic_sriov_schedule_bc_cmd(sriov, vf,
1129 qlcnic_sriov_process_bc_cmd);
1130 return 0;
1131 }
1132
qlcnic_sriov_add_act_list(struct qlcnic_sriov * sriov,struct qlcnic_vf_info * vf,struct qlcnic_bc_trans * trans)1133 static int qlcnic_sriov_add_act_list(struct qlcnic_sriov *sriov,
1134 struct qlcnic_vf_info *vf,
1135 struct qlcnic_bc_trans *trans)
1136 {
1137 struct qlcnic_trans_list *t_list = &vf->rcv_act;
1138
1139 spin_lock(&t_list->lock);
1140
1141 __qlcnic_sriov_add_act_list(sriov, vf, trans);
1142
1143 spin_unlock(&t_list->lock);
1144 return 0;
1145 }
1146
qlcnic_sriov_handle_pending_trans(struct qlcnic_sriov * sriov,struct qlcnic_vf_info * vf,struct qlcnic_bc_hdr * hdr)1147 static void qlcnic_sriov_handle_pending_trans(struct qlcnic_sriov *sriov,
1148 struct qlcnic_vf_info *vf,
1149 struct qlcnic_bc_hdr *hdr)
1150 {
1151 struct qlcnic_bc_trans *trans = NULL;
1152 struct list_head *node;
1153 u32 pay_size, curr_frag;
1154 u8 found = 0, active = 0;
1155
1156 spin_lock(&vf->rcv_pend.lock);
1157 if (vf->rcv_pend.count > 0) {
1158 list_for_each(node, &vf->rcv_pend.wait_list) {
1159 trans = list_entry(node, struct qlcnic_bc_trans, list);
1160 if (trans->trans_id == hdr->seq_id) {
1161 found = 1;
1162 break;
1163 }
1164 }
1165 }
1166
1167 if (found) {
1168 curr_frag = trans->curr_req_frag;
1169 pay_size = qlcnic_sriov_get_bc_paysize(trans->req_pay_size,
1170 curr_frag);
1171 qlcnic_sriov_pull_bc_msg(vf->adapter,
1172 (u32 *)(trans->req_hdr + curr_frag),
1173 (u32 *)(trans->req_pay + curr_frag),
1174 pay_size);
1175 trans->curr_req_frag++;
1176 if (trans->curr_req_frag >= hdr->num_frags) {
1177 vf->rcv_pend.count--;
1178 list_del(&trans->list);
1179 active = 1;
1180 }
1181 }
1182 spin_unlock(&vf->rcv_pend.lock);
1183
1184 if (active)
1185 if (qlcnic_sriov_add_act_list(sriov, vf, trans))
1186 qlcnic_sriov_cleanup_transaction(trans);
1187
1188 return;
1189 }
1190
qlcnic_sriov_handle_bc_cmd(struct qlcnic_sriov * sriov,struct qlcnic_bc_hdr * hdr,struct qlcnic_vf_info * vf)1191 static void qlcnic_sriov_handle_bc_cmd(struct qlcnic_sriov *sriov,
1192 struct qlcnic_bc_hdr *hdr,
1193 struct qlcnic_vf_info *vf)
1194 {
1195 struct qlcnic_bc_trans *trans;
1196 struct qlcnic_adapter *adapter = vf->adapter;
1197 struct qlcnic_cmd_args cmd;
1198 u32 pay_size;
1199 int err;
1200 u8 cmd_op;
1201
1202 if (adapter->need_fw_reset)
1203 return;
1204
1205 if (!test_bit(QLC_BC_VF_STATE, &vf->state) &&
1206 hdr->op_type != QLC_BC_CMD &&
1207 hdr->cmd_op != QLCNIC_BC_CMD_CHANNEL_INIT)
1208 return;
1209
1210 if (hdr->frag_num > 1) {
1211 qlcnic_sriov_handle_pending_trans(sriov, vf, hdr);
1212 return;
1213 }
1214
1215 memset(&cmd, 0, sizeof(struct qlcnic_cmd_args));
1216 cmd_op = hdr->cmd_op;
1217 if (qlcnic_sriov_alloc_bc_trans(&trans))
1218 return;
1219
1220 if (hdr->op_type == QLC_BC_CMD)
1221 err = qlcnic_sriov_alloc_bc_mbx_args(&cmd, cmd_op);
1222 else
1223 err = qlcnic_alloc_mbx_args(&cmd, adapter, cmd_op);
1224
1225 if (err) {
1226 qlcnic_sriov_cleanup_transaction(trans);
1227 return;
1228 }
1229
1230 cmd.op_type = hdr->op_type;
1231 if (qlcnic_sriov_prepare_bc_hdr(trans, &cmd, hdr->seq_id,
1232 QLC_BC_COMMAND)) {
1233 qlcnic_free_mbx_args(&cmd);
1234 qlcnic_sriov_cleanup_transaction(trans);
1235 return;
1236 }
1237
1238 pay_size = qlcnic_sriov_get_bc_paysize(trans->req_pay_size,
1239 trans->curr_req_frag);
1240 qlcnic_sriov_pull_bc_msg(vf->adapter,
1241 (u32 *)(trans->req_hdr + trans->curr_req_frag),
1242 (u32 *)(trans->req_pay + trans->curr_req_frag),
1243 pay_size);
1244 trans->func_id = vf->pci_func;
1245 trans->vf = vf;
1246 trans->trans_id = hdr->seq_id;
1247 trans->curr_req_frag++;
1248
1249 if (qlcnic_sriov_soft_flr_check(adapter, trans, vf))
1250 return;
1251
1252 if (trans->curr_req_frag == trans->req_hdr->num_frags) {
1253 if (qlcnic_sriov_add_act_list(sriov, vf, trans)) {
1254 qlcnic_free_mbx_args(&cmd);
1255 qlcnic_sriov_cleanup_transaction(trans);
1256 }
1257 } else {
1258 spin_lock(&vf->rcv_pend.lock);
1259 list_add_tail(&trans->list, &vf->rcv_pend.wait_list);
1260 vf->rcv_pend.count++;
1261 spin_unlock(&vf->rcv_pend.lock);
1262 }
1263 }
1264
qlcnic_sriov_handle_msg_event(struct qlcnic_sriov * sriov,struct qlcnic_vf_info * vf)1265 static void qlcnic_sriov_handle_msg_event(struct qlcnic_sriov *sriov,
1266 struct qlcnic_vf_info *vf)
1267 {
1268 struct qlcnic_bc_hdr hdr;
1269 u32 *ptr = (u32 *)&hdr;
1270 u8 msg_type, i;
1271
1272 for (i = 2; i < 6; i++)
1273 ptr[i - 2] = readl(QLCNIC_MBX_FW(vf->adapter->ahw, i));
1274 msg_type = hdr.msg_type;
1275
1276 switch (msg_type) {
1277 case QLC_BC_COMMAND:
1278 qlcnic_sriov_handle_bc_cmd(sriov, &hdr, vf);
1279 break;
1280 case QLC_BC_RESPONSE:
1281 qlcnic_sriov_handle_bc_resp(&hdr, vf);
1282 break;
1283 }
1284 }
1285
qlcnic_sriov_handle_flr_event(struct qlcnic_sriov * sriov,struct qlcnic_vf_info * vf)1286 static void qlcnic_sriov_handle_flr_event(struct qlcnic_sriov *sriov,
1287 struct qlcnic_vf_info *vf)
1288 {
1289 struct qlcnic_adapter *adapter = vf->adapter;
1290
1291 if (qlcnic_sriov_pf_check(adapter))
1292 qlcnic_sriov_pf_handle_flr(sriov, vf);
1293 else
1294 dev_err(&adapter->pdev->dev,
1295 "Invalid event to VF. VF should not get FLR event\n");
1296 }
1297
qlcnic_sriov_handle_bc_event(struct qlcnic_adapter * adapter,u32 event)1298 void qlcnic_sriov_handle_bc_event(struct qlcnic_adapter *adapter, u32 event)
1299 {
1300 struct qlcnic_vf_info *vf;
1301 struct qlcnic_sriov *sriov;
1302 int index;
1303 u8 pci_func;
1304
1305 sriov = adapter->ahw->sriov;
1306 pci_func = qlcnic_sriov_target_func_id(event);
1307 index = qlcnic_sriov_func_to_index(adapter, pci_func);
1308
1309 if (index < 0)
1310 return;
1311
1312 vf = &sriov->vf_info[index];
1313 vf->pci_func = pci_func;
1314
1315 if (qlcnic_sriov_channel_free_check(event))
1316 complete(&vf->ch_free_cmpl);
1317
1318 if (qlcnic_sriov_flr_check(event)) {
1319 qlcnic_sriov_handle_flr_event(sriov, vf);
1320 return;
1321 }
1322
1323 if (qlcnic_sriov_bc_msg_check(event))
1324 qlcnic_sriov_handle_msg_event(sriov, vf);
1325 }
1326
qlcnic_sriov_cfg_bc_intr(struct qlcnic_adapter * adapter,u8 enable)1327 int qlcnic_sriov_cfg_bc_intr(struct qlcnic_adapter *adapter, u8 enable)
1328 {
1329 struct qlcnic_cmd_args cmd;
1330 int err;
1331
1332 if (!test_bit(__QLCNIC_SRIOV_ENABLE, &adapter->state))
1333 return 0;
1334
1335 if (qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_BC_EVENT_SETUP))
1336 return -ENOMEM;
1337
1338 if (enable)
1339 cmd.req.arg[1] = (1 << 4) | (1 << 5) | (1 << 6) | (1 << 7);
1340
1341 err = qlcnic_83xx_issue_cmd(adapter, &cmd);
1342
1343 if (err != QLCNIC_RCODE_SUCCESS) {
1344 dev_err(&adapter->pdev->dev,
1345 "Failed to %s bc events, err=%d\n",
1346 (enable ? "enable" : "disable"), err);
1347 }
1348
1349 qlcnic_free_mbx_args(&cmd);
1350 return err;
1351 }
1352
qlcnic_sriov_retry_bc_cmd(struct qlcnic_adapter * adapter,struct qlcnic_bc_trans * trans)1353 static int qlcnic_sriov_retry_bc_cmd(struct qlcnic_adapter *adapter,
1354 struct qlcnic_bc_trans *trans)
1355 {
1356 u8 max = QLC_BC_CMD_MAX_RETRY_CNT;
1357 u32 state;
1358
1359 state = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_STATE);
1360 if (state == QLC_83XX_IDC_DEV_READY) {
1361 msleep(20);
1362 clear_bit(QLC_BC_VF_CHANNEL, &trans->vf->state);
1363 trans->trans_state = QLC_INIT;
1364 if (++adapter->fw_fail_cnt > max)
1365 return -EIO;
1366 else
1367 return 0;
1368 }
1369
1370 return -EIO;
1371 }
1372
__qlcnic_sriov_issue_cmd(struct qlcnic_adapter * adapter,struct qlcnic_cmd_args * cmd)1373 static int __qlcnic_sriov_issue_cmd(struct qlcnic_adapter *adapter,
1374 struct qlcnic_cmd_args *cmd)
1375 {
1376 struct qlcnic_hardware_context *ahw = adapter->ahw;
1377 struct qlcnic_mailbox *mbx = ahw->mailbox;
1378 struct device *dev = &adapter->pdev->dev;
1379 struct qlcnic_bc_trans *trans;
1380 int err;
1381 u32 rsp_data, opcode, mbx_err_code, rsp;
1382 u16 seq = ++adapter->ahw->sriov->bc.trans_counter;
1383 u8 func = ahw->pci_func;
1384
1385 rsp = qlcnic_sriov_alloc_bc_trans(&trans);
1386 if (rsp)
1387 goto free_cmd;
1388
1389 rsp = qlcnic_sriov_prepare_bc_hdr(trans, cmd, seq, QLC_BC_COMMAND);
1390 if (rsp)
1391 goto cleanup_transaction;
1392
1393 retry:
1394 if (!test_bit(QLC_83XX_MBX_READY, &mbx->status)) {
1395 rsp = -EIO;
1396 QLCDB(adapter, DRV, "MBX not Ready!(cmd 0x%x) for VF 0x%x\n",
1397 QLCNIC_MBX_RSP(cmd->req.arg[0]), func);
1398 goto err_out;
1399 }
1400
1401 err = qlcnic_sriov_send_bc_cmd(adapter, trans, func);
1402 if (err) {
1403 dev_err(dev, "MBX command 0x%x timed out for VF %d\n",
1404 (cmd->req.arg[0] & 0xffff), func);
1405 rsp = QLCNIC_RCODE_TIMEOUT;
1406
1407 /* After adapter reset PF driver may take some time to
1408 * respond to VF's request. Retry request till maximum retries.
1409 */
1410 if ((trans->req_hdr->cmd_op == QLCNIC_BC_CMD_CHANNEL_INIT) &&
1411 !qlcnic_sriov_retry_bc_cmd(adapter, trans))
1412 goto retry;
1413
1414 goto err_out;
1415 }
1416
1417 rsp_data = cmd->rsp.arg[0];
1418 mbx_err_code = QLCNIC_MBX_STATUS(rsp_data);
1419 opcode = QLCNIC_MBX_RSP(cmd->req.arg[0]);
1420
1421 if ((mbx_err_code == QLCNIC_MBX_RSP_OK) ||
1422 (mbx_err_code == QLCNIC_MBX_PORT_RSP_OK)) {
1423 rsp = QLCNIC_RCODE_SUCCESS;
1424 } else {
1425 if (cmd->type == QLC_83XX_MBX_CMD_NO_WAIT) {
1426 rsp = QLCNIC_RCODE_SUCCESS;
1427 } else {
1428 rsp = mbx_err_code;
1429 if (!rsp)
1430 rsp = 1;
1431
1432 dev_err(dev,
1433 "MBX command 0x%x failed with err:0x%x for VF %d\n",
1434 opcode, mbx_err_code, func);
1435 }
1436 }
1437
1438 err_out:
1439 if (rsp == QLCNIC_RCODE_TIMEOUT) {
1440 ahw->reset_context = 1;
1441 adapter->need_fw_reset = 1;
1442 clear_bit(QLC_83XX_MBX_READY, &mbx->status);
1443 }
1444
1445 cleanup_transaction:
1446 qlcnic_sriov_cleanup_transaction(trans);
1447
1448 free_cmd:
1449 if (cmd->type == QLC_83XX_MBX_CMD_NO_WAIT) {
1450 qlcnic_free_mbx_args(cmd);
1451 kfree(cmd);
1452 }
1453
1454 return rsp;
1455 }
1456
1457
qlcnic_sriov_issue_cmd(struct qlcnic_adapter * adapter,struct qlcnic_cmd_args * cmd)1458 static int qlcnic_sriov_issue_cmd(struct qlcnic_adapter *adapter,
1459 struct qlcnic_cmd_args *cmd)
1460 {
1461 if (cmd->type == QLC_83XX_MBX_CMD_NO_WAIT)
1462 return qlcnic_sriov_async_issue_cmd(adapter, cmd);
1463 else
1464 return __qlcnic_sriov_issue_cmd(adapter, cmd);
1465 }
1466
qlcnic_sriov_channel_cfg_cmd(struct qlcnic_adapter * adapter,u8 cmd_op)1467 static int qlcnic_sriov_channel_cfg_cmd(struct qlcnic_adapter *adapter, u8 cmd_op)
1468 {
1469 struct qlcnic_cmd_args cmd;
1470 struct qlcnic_vf_info *vf = &adapter->ahw->sriov->vf_info[0];
1471 int ret;
1472
1473 memset(&cmd, 0, sizeof(cmd));
1474 if (qlcnic_sriov_alloc_bc_mbx_args(&cmd, cmd_op))
1475 return -ENOMEM;
1476
1477 ret = qlcnic_issue_cmd(adapter, &cmd);
1478 if (ret) {
1479 dev_err(&adapter->pdev->dev,
1480 "Failed bc channel %s %d\n", cmd_op ? "term" : "init",
1481 ret);
1482 goto out;
1483 }
1484
1485 cmd_op = (cmd.rsp.arg[0] & 0xff);
1486 if (cmd.rsp.arg[0] >> 25 == 2)
1487 return 2;
1488 if (cmd_op == QLCNIC_BC_CMD_CHANNEL_INIT)
1489 set_bit(QLC_BC_VF_STATE, &vf->state);
1490 else
1491 clear_bit(QLC_BC_VF_STATE, &vf->state);
1492
1493 out:
1494 qlcnic_free_mbx_args(&cmd);
1495 return ret;
1496 }
1497
qlcnic_vf_add_mc_list(struct net_device * netdev,const u8 * mac,enum qlcnic_mac_type mac_type)1498 static void qlcnic_vf_add_mc_list(struct net_device *netdev, const u8 *mac,
1499 enum qlcnic_mac_type mac_type)
1500 {
1501 struct qlcnic_adapter *adapter = netdev_priv(netdev);
1502 struct qlcnic_sriov *sriov = adapter->ahw->sriov;
1503 struct qlcnic_vf_info *vf;
1504 u16 vlan_id;
1505 int i;
1506
1507 vf = &adapter->ahw->sriov->vf_info[0];
1508
1509 if (!qlcnic_sriov_check_any_vlan(vf)) {
1510 qlcnic_nic_add_mac(adapter, mac, 0, mac_type);
1511 } else {
1512 spin_lock(&vf->vlan_list_lock);
1513 for (i = 0; i < sriov->num_allowed_vlans; i++) {
1514 vlan_id = vf->sriov_vlans[i];
1515 if (vlan_id)
1516 qlcnic_nic_add_mac(adapter, mac, vlan_id,
1517 mac_type);
1518 }
1519 spin_unlock(&vf->vlan_list_lock);
1520 if (qlcnic_84xx_check(adapter))
1521 qlcnic_nic_add_mac(adapter, mac, 0, mac_type);
1522 }
1523 }
1524
qlcnic_sriov_cleanup_async_list(struct qlcnic_back_channel * bc)1525 void qlcnic_sriov_cleanup_async_list(struct qlcnic_back_channel *bc)
1526 {
1527 struct list_head *head = &bc->async_cmd_list;
1528 struct qlcnic_async_cmd *entry;
1529
1530 flush_workqueue(bc->bc_async_wq);
1531 cancel_work_sync(&bc->vf_async_work);
1532
1533 spin_lock(&bc->queue_lock);
1534 while (!list_empty(head)) {
1535 entry = list_entry(head->next, struct qlcnic_async_cmd,
1536 list);
1537 list_del(&entry->list);
1538 kfree(entry->cmd);
1539 kfree(entry);
1540 }
1541 spin_unlock(&bc->queue_lock);
1542 }
1543
qlcnic_sriov_vf_set_multi(struct net_device * netdev)1544 void qlcnic_sriov_vf_set_multi(struct net_device *netdev)
1545 {
1546 struct qlcnic_adapter *adapter = netdev_priv(netdev);
1547 struct qlcnic_hardware_context *ahw = adapter->ahw;
1548 static const u8 bcast_addr[ETH_ALEN] = {
1549 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
1550 };
1551 struct netdev_hw_addr *ha;
1552 u32 mode = VPORT_MISS_MODE_DROP;
1553
1554 if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state))
1555 return;
1556
1557 if (netdev->flags & IFF_PROMISC) {
1558 if (!(adapter->flags & QLCNIC_PROMISC_DISABLED))
1559 mode = VPORT_MISS_MODE_ACCEPT_ALL;
1560 } else if ((netdev->flags & IFF_ALLMULTI) ||
1561 (netdev_mc_count(netdev) > ahw->max_mc_count)) {
1562 mode = VPORT_MISS_MODE_ACCEPT_MULTI;
1563 } else {
1564 qlcnic_vf_add_mc_list(netdev, bcast_addr, QLCNIC_BROADCAST_MAC);
1565 if (!netdev_mc_empty(netdev)) {
1566 qlcnic_flush_mcast_mac(adapter);
1567 netdev_for_each_mc_addr(ha, netdev)
1568 qlcnic_vf_add_mc_list(netdev, ha->addr,
1569 QLCNIC_MULTICAST_MAC);
1570 }
1571 }
1572
1573 /* configure unicast MAC address, if there is not sufficient space
1574 * to store all the unicast addresses then enable promiscuous mode
1575 */
1576 if (netdev_uc_count(netdev) > ahw->max_uc_count) {
1577 mode = VPORT_MISS_MODE_ACCEPT_ALL;
1578 } else if (!netdev_uc_empty(netdev)) {
1579 netdev_for_each_uc_addr(ha, netdev)
1580 qlcnic_vf_add_mc_list(netdev, ha->addr,
1581 QLCNIC_UNICAST_MAC);
1582 }
1583
1584 if (adapter->pdev->is_virtfn) {
1585 if (mode == VPORT_MISS_MODE_ACCEPT_ALL &&
1586 !adapter->fdb_mac_learn) {
1587 qlcnic_alloc_lb_filters_mem(adapter);
1588 adapter->drv_mac_learn = true;
1589 adapter->rx_mac_learn = true;
1590 } else {
1591 adapter->drv_mac_learn = false;
1592 adapter->rx_mac_learn = false;
1593 }
1594 }
1595
1596 qlcnic_nic_set_promisc(adapter, mode);
1597 }
1598
qlcnic_sriov_handle_async_issue_cmd(struct work_struct * work)1599 static void qlcnic_sriov_handle_async_issue_cmd(struct work_struct *work)
1600 {
1601 struct qlcnic_async_cmd *entry, *tmp;
1602 struct qlcnic_back_channel *bc;
1603 struct qlcnic_cmd_args *cmd;
1604 struct list_head *head;
1605 LIST_HEAD(del_list);
1606
1607 bc = container_of(work, struct qlcnic_back_channel, vf_async_work);
1608 head = &bc->async_cmd_list;
1609
1610 spin_lock(&bc->queue_lock);
1611 list_splice_init(head, &del_list);
1612 spin_unlock(&bc->queue_lock);
1613
1614 list_for_each_entry_safe(entry, tmp, &del_list, list) {
1615 list_del(&entry->list);
1616 cmd = entry->cmd;
1617 __qlcnic_sriov_issue_cmd(bc->adapter, cmd);
1618 kfree(entry);
1619 }
1620
1621 if (!list_empty(head))
1622 queue_work(bc->bc_async_wq, &bc->vf_async_work);
1623
1624 return;
1625 }
1626
1627 static struct qlcnic_async_cmd *
qlcnic_sriov_alloc_async_cmd(struct qlcnic_back_channel * bc,struct qlcnic_cmd_args * cmd)1628 qlcnic_sriov_alloc_async_cmd(struct qlcnic_back_channel *bc,
1629 struct qlcnic_cmd_args *cmd)
1630 {
1631 struct qlcnic_async_cmd *entry = NULL;
1632
1633 entry = kzalloc(sizeof(*entry), GFP_ATOMIC);
1634 if (!entry)
1635 return NULL;
1636
1637 entry->cmd = cmd;
1638
1639 spin_lock(&bc->queue_lock);
1640 list_add_tail(&entry->list, &bc->async_cmd_list);
1641 spin_unlock(&bc->queue_lock);
1642
1643 return entry;
1644 }
1645
qlcnic_sriov_schedule_async_cmd(struct qlcnic_back_channel * bc,struct qlcnic_cmd_args * cmd)1646 static void qlcnic_sriov_schedule_async_cmd(struct qlcnic_back_channel *bc,
1647 struct qlcnic_cmd_args *cmd)
1648 {
1649 struct qlcnic_async_cmd *entry = NULL;
1650
1651 entry = qlcnic_sriov_alloc_async_cmd(bc, cmd);
1652 if (!entry) {
1653 qlcnic_free_mbx_args(cmd);
1654 kfree(cmd);
1655 return;
1656 }
1657
1658 queue_work(bc->bc_async_wq, &bc->vf_async_work);
1659 }
1660
qlcnic_sriov_async_issue_cmd(struct qlcnic_adapter * adapter,struct qlcnic_cmd_args * cmd)1661 static int qlcnic_sriov_async_issue_cmd(struct qlcnic_adapter *adapter,
1662 struct qlcnic_cmd_args *cmd)
1663 {
1664
1665 struct qlcnic_back_channel *bc = &adapter->ahw->sriov->bc;
1666
1667 if (adapter->need_fw_reset)
1668 return -EIO;
1669
1670 qlcnic_sriov_schedule_async_cmd(bc, cmd);
1671
1672 return 0;
1673 }
1674
qlcnic_sriov_vf_reinit_driver(struct qlcnic_adapter * adapter)1675 static int qlcnic_sriov_vf_reinit_driver(struct qlcnic_adapter *adapter)
1676 {
1677 int err;
1678
1679 adapter->need_fw_reset = 0;
1680 qlcnic_83xx_reinit_mbx_work(adapter->ahw->mailbox);
1681 qlcnic_83xx_enable_mbx_interrupt(adapter);
1682
1683 err = qlcnic_sriov_cfg_bc_intr(adapter, 1);
1684 if (err)
1685 return err;
1686
1687 err = qlcnic_sriov_channel_cfg_cmd(adapter, QLCNIC_BC_CMD_CHANNEL_INIT);
1688 if (err)
1689 goto err_out_cleanup_bc_intr;
1690
1691 err = qlcnic_sriov_vf_init_driver(adapter);
1692 if (err)
1693 goto err_out_term_channel;
1694
1695 return 0;
1696
1697 err_out_term_channel:
1698 qlcnic_sriov_channel_cfg_cmd(adapter, QLCNIC_BC_CMD_CHANNEL_TERM);
1699
1700 err_out_cleanup_bc_intr:
1701 qlcnic_sriov_cfg_bc_intr(adapter, 0);
1702 return err;
1703 }
1704
qlcnic_sriov_vf_attach(struct qlcnic_adapter * adapter)1705 static void qlcnic_sriov_vf_attach(struct qlcnic_adapter *adapter)
1706 {
1707 struct net_device *netdev = adapter->netdev;
1708
1709 if (netif_running(netdev)) {
1710 if (!qlcnic_up(adapter, netdev))
1711 qlcnic_restore_indev_addr(netdev, NETDEV_UP);
1712 }
1713
1714 netif_device_attach(netdev);
1715 }
1716
qlcnic_sriov_vf_detach(struct qlcnic_adapter * adapter)1717 static void qlcnic_sriov_vf_detach(struct qlcnic_adapter *adapter)
1718 {
1719 struct qlcnic_hardware_context *ahw = adapter->ahw;
1720 struct qlcnic_intrpt_config *intr_tbl = ahw->intr_tbl;
1721 struct net_device *netdev = adapter->netdev;
1722 u8 i, max_ints = ahw->num_msix - 1;
1723
1724 netif_device_detach(netdev);
1725 qlcnic_83xx_detach_mailbox_work(adapter);
1726 qlcnic_83xx_disable_mbx_intr(adapter);
1727
1728 if (netif_running(netdev))
1729 qlcnic_down(adapter, netdev);
1730
1731 for (i = 0; i < max_ints; i++) {
1732 intr_tbl[i].id = i;
1733 intr_tbl[i].enabled = 0;
1734 intr_tbl[i].src = 0;
1735 }
1736 ahw->reset_context = 0;
1737 }
1738
qlcnic_sriov_vf_handle_dev_ready(struct qlcnic_adapter * adapter)1739 static int qlcnic_sriov_vf_handle_dev_ready(struct qlcnic_adapter *adapter)
1740 {
1741 struct qlcnic_hardware_context *ahw = adapter->ahw;
1742 struct device *dev = &adapter->pdev->dev;
1743 struct qlc_83xx_idc *idc = &ahw->idc;
1744 u8 func = ahw->pci_func;
1745 u32 state;
1746
1747 if ((idc->prev_state == QLC_83XX_IDC_DEV_NEED_RESET) ||
1748 (idc->prev_state == QLC_83XX_IDC_DEV_INIT)) {
1749 if (!qlcnic_sriov_vf_reinit_driver(adapter)) {
1750 qlcnic_sriov_vf_attach(adapter);
1751 adapter->fw_fail_cnt = 0;
1752 dev_info(dev,
1753 "%s: Reinitialization of VF 0x%x done after FW reset\n",
1754 __func__, func);
1755 } else {
1756 dev_err(dev,
1757 "%s: Reinitialization of VF 0x%x failed after FW reset\n",
1758 __func__, func);
1759 state = QLCRDX(ahw, QLC_83XX_IDC_DEV_STATE);
1760 dev_info(dev, "Current state 0x%x after FW reset\n",
1761 state);
1762 }
1763 }
1764
1765 return 0;
1766 }
1767
qlcnic_sriov_vf_handle_context_reset(struct qlcnic_adapter * adapter)1768 static int qlcnic_sriov_vf_handle_context_reset(struct qlcnic_adapter *adapter)
1769 {
1770 struct qlcnic_hardware_context *ahw = adapter->ahw;
1771 struct qlcnic_mailbox *mbx = ahw->mailbox;
1772 struct device *dev = &adapter->pdev->dev;
1773 struct qlc_83xx_idc *idc = &ahw->idc;
1774 u8 func = ahw->pci_func;
1775 u32 state;
1776
1777 adapter->reset_ctx_cnt++;
1778
1779 /* Skip the context reset and check if FW is hung */
1780 if (adapter->reset_ctx_cnt < 3) {
1781 adapter->need_fw_reset = 1;
1782 clear_bit(QLC_83XX_MBX_READY, &mbx->status);
1783 dev_info(dev,
1784 "Resetting context, wait here to check if FW is in failed state\n");
1785 return 0;
1786 }
1787
1788 /* Check if number of resets exceed the threshold.
1789 * If it exceeds the threshold just fail the VF.
1790 */
1791 if (adapter->reset_ctx_cnt > QLC_83XX_VF_RESET_FAIL_THRESH) {
1792 clear_bit(QLC_83XX_MODULE_LOADED, &idc->status);
1793 adapter->tx_timeo_cnt = 0;
1794 adapter->fw_fail_cnt = 0;
1795 adapter->reset_ctx_cnt = 0;
1796 qlcnic_sriov_vf_detach(adapter);
1797 dev_err(dev,
1798 "Device context resets have exceeded the threshold, device interface will be shutdown\n");
1799 return -EIO;
1800 }
1801
1802 dev_info(dev, "Resetting context of VF 0x%x\n", func);
1803 dev_info(dev, "%s: Context reset count %d for VF 0x%x\n",
1804 __func__, adapter->reset_ctx_cnt, func);
1805 set_bit(__QLCNIC_RESETTING, &adapter->state);
1806 adapter->need_fw_reset = 1;
1807 clear_bit(QLC_83XX_MBX_READY, &mbx->status);
1808 qlcnic_sriov_vf_detach(adapter);
1809 adapter->need_fw_reset = 0;
1810
1811 if (!qlcnic_sriov_vf_reinit_driver(adapter)) {
1812 qlcnic_sriov_vf_attach(adapter);
1813 adapter->tx_timeo_cnt = 0;
1814 adapter->reset_ctx_cnt = 0;
1815 adapter->fw_fail_cnt = 0;
1816 dev_info(dev, "Done resetting context for VF 0x%x\n", func);
1817 } else {
1818 dev_err(dev, "%s: Reinitialization of VF 0x%x failed\n",
1819 __func__, func);
1820 state = QLCRDX(ahw, QLC_83XX_IDC_DEV_STATE);
1821 dev_info(dev, "%s: Current state 0x%x\n", __func__, state);
1822 }
1823
1824 return 0;
1825 }
1826
qlcnic_sriov_vf_idc_ready_state(struct qlcnic_adapter * adapter)1827 static int qlcnic_sriov_vf_idc_ready_state(struct qlcnic_adapter *adapter)
1828 {
1829 struct qlcnic_hardware_context *ahw = adapter->ahw;
1830 int ret = 0;
1831
1832 if (ahw->idc.prev_state != QLC_83XX_IDC_DEV_READY)
1833 ret = qlcnic_sriov_vf_handle_dev_ready(adapter);
1834 else if (ahw->reset_context)
1835 ret = qlcnic_sriov_vf_handle_context_reset(adapter);
1836
1837 clear_bit(__QLCNIC_RESETTING, &adapter->state);
1838 return ret;
1839 }
1840
qlcnic_sriov_vf_idc_failed_state(struct qlcnic_adapter * adapter)1841 static int qlcnic_sriov_vf_idc_failed_state(struct qlcnic_adapter *adapter)
1842 {
1843 struct qlc_83xx_idc *idc = &adapter->ahw->idc;
1844
1845 dev_err(&adapter->pdev->dev, "Device is in failed state\n");
1846 if (idc->prev_state == QLC_83XX_IDC_DEV_READY)
1847 qlcnic_sriov_vf_detach(adapter);
1848
1849 clear_bit(QLC_83XX_MODULE_LOADED, &idc->status);
1850 clear_bit(__QLCNIC_RESETTING, &adapter->state);
1851 return -EIO;
1852 }
1853
1854 static int
qlcnic_sriov_vf_idc_need_quiescent_state(struct qlcnic_adapter * adapter)1855 qlcnic_sriov_vf_idc_need_quiescent_state(struct qlcnic_adapter *adapter)
1856 {
1857 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
1858 struct qlc_83xx_idc *idc = &adapter->ahw->idc;
1859
1860 dev_info(&adapter->pdev->dev, "Device is in quiescent state\n");
1861 if (idc->prev_state == QLC_83XX_IDC_DEV_READY) {
1862 set_bit(__QLCNIC_RESETTING, &adapter->state);
1863 adapter->tx_timeo_cnt = 0;
1864 adapter->reset_ctx_cnt = 0;
1865 clear_bit(QLC_83XX_MBX_READY, &mbx->status);
1866 qlcnic_sriov_vf_detach(adapter);
1867 }
1868
1869 return 0;
1870 }
1871
qlcnic_sriov_vf_idc_init_reset_state(struct qlcnic_adapter * adapter)1872 static int qlcnic_sriov_vf_idc_init_reset_state(struct qlcnic_adapter *adapter)
1873 {
1874 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
1875 struct qlc_83xx_idc *idc = &adapter->ahw->idc;
1876 u8 func = adapter->ahw->pci_func;
1877
1878 if (idc->prev_state == QLC_83XX_IDC_DEV_READY) {
1879 dev_err(&adapter->pdev->dev,
1880 "Firmware hang detected by VF 0x%x\n", func);
1881 set_bit(__QLCNIC_RESETTING, &adapter->state);
1882 adapter->tx_timeo_cnt = 0;
1883 adapter->reset_ctx_cnt = 0;
1884 clear_bit(QLC_83XX_MBX_READY, &mbx->status);
1885 qlcnic_sriov_vf_detach(adapter);
1886 }
1887 return 0;
1888 }
1889
qlcnic_sriov_vf_idc_unknown_state(struct qlcnic_adapter * adapter)1890 static int qlcnic_sriov_vf_idc_unknown_state(struct qlcnic_adapter *adapter)
1891 {
1892 dev_err(&adapter->pdev->dev, "%s: Device in unknown state\n", __func__);
1893 return 0;
1894 }
1895
qlcnic_sriov_vf_periodic_tasks(struct qlcnic_adapter * adapter)1896 static void qlcnic_sriov_vf_periodic_tasks(struct qlcnic_adapter *adapter)
1897 {
1898 if (adapter->fhash.fnum)
1899 qlcnic_prune_lb_filters(adapter);
1900 }
1901
qlcnic_sriov_vf_poll_dev_state(struct work_struct * work)1902 static void qlcnic_sriov_vf_poll_dev_state(struct work_struct *work)
1903 {
1904 struct qlcnic_adapter *adapter;
1905 struct qlc_83xx_idc *idc;
1906 int ret = 0;
1907
1908 adapter = container_of(work, struct qlcnic_adapter, fw_work.work);
1909 idc = &adapter->ahw->idc;
1910 idc->curr_state = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_STATE);
1911
1912 switch (idc->curr_state) {
1913 case QLC_83XX_IDC_DEV_READY:
1914 ret = qlcnic_sriov_vf_idc_ready_state(adapter);
1915 break;
1916 case QLC_83XX_IDC_DEV_NEED_RESET:
1917 case QLC_83XX_IDC_DEV_INIT:
1918 ret = qlcnic_sriov_vf_idc_init_reset_state(adapter);
1919 break;
1920 case QLC_83XX_IDC_DEV_NEED_QUISCENT:
1921 ret = qlcnic_sriov_vf_idc_need_quiescent_state(adapter);
1922 break;
1923 case QLC_83XX_IDC_DEV_FAILED:
1924 ret = qlcnic_sriov_vf_idc_failed_state(adapter);
1925 break;
1926 case QLC_83XX_IDC_DEV_QUISCENT:
1927 break;
1928 default:
1929 ret = qlcnic_sriov_vf_idc_unknown_state(adapter);
1930 }
1931
1932 idc->prev_state = idc->curr_state;
1933 qlcnic_sriov_vf_periodic_tasks(adapter);
1934
1935 if (!ret && test_bit(QLC_83XX_MODULE_LOADED, &idc->status))
1936 qlcnic_schedule_work(adapter, qlcnic_sriov_vf_poll_dev_state,
1937 idc->delay);
1938 }
1939
qlcnic_sriov_vf_cancel_fw_work(struct qlcnic_adapter * adapter)1940 static void qlcnic_sriov_vf_cancel_fw_work(struct qlcnic_adapter *adapter)
1941 {
1942 while (test_and_set_bit(__QLCNIC_RESETTING, &adapter->state))
1943 msleep(20);
1944
1945 clear_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status);
1946 clear_bit(__QLCNIC_RESETTING, &adapter->state);
1947 cancel_delayed_work_sync(&adapter->fw_work);
1948 }
1949
qlcnic_sriov_check_vlan_id(struct qlcnic_sriov * sriov,struct qlcnic_vf_info * vf,u16 vlan_id)1950 static int qlcnic_sriov_check_vlan_id(struct qlcnic_sriov *sriov,
1951 struct qlcnic_vf_info *vf, u16 vlan_id)
1952 {
1953 int i, err = -EINVAL;
1954
1955 if (!vf->sriov_vlans)
1956 return err;
1957
1958 spin_lock_bh(&vf->vlan_list_lock);
1959
1960 for (i = 0; i < sriov->num_allowed_vlans; i++) {
1961 if (vf->sriov_vlans[i] == vlan_id) {
1962 err = 0;
1963 break;
1964 }
1965 }
1966
1967 spin_unlock_bh(&vf->vlan_list_lock);
1968 return err;
1969 }
1970
qlcnic_sriov_validate_num_vlans(struct qlcnic_sriov * sriov,struct qlcnic_vf_info * vf)1971 static int qlcnic_sriov_validate_num_vlans(struct qlcnic_sriov *sriov,
1972 struct qlcnic_vf_info *vf)
1973 {
1974 int err = 0;
1975
1976 spin_lock_bh(&vf->vlan_list_lock);
1977
1978 if (vf->num_vlan >= sriov->num_allowed_vlans)
1979 err = -EINVAL;
1980
1981 spin_unlock_bh(&vf->vlan_list_lock);
1982 return err;
1983 }
1984
qlcnic_sriov_validate_vlan_cfg(struct qlcnic_adapter * adapter,u16 vid,u8 enable)1985 static int qlcnic_sriov_validate_vlan_cfg(struct qlcnic_adapter *adapter,
1986 u16 vid, u8 enable)
1987 {
1988 struct qlcnic_sriov *sriov = adapter->ahw->sriov;
1989 struct qlcnic_vf_info *vf;
1990 bool vlan_exist;
1991 u8 allowed = 0;
1992 int i;
1993
1994 vf = &adapter->ahw->sriov->vf_info[0];
1995 vlan_exist = qlcnic_sriov_check_any_vlan(vf);
1996 if (sriov->vlan_mode != QLC_GUEST_VLAN_MODE)
1997 return -EINVAL;
1998
1999 if (enable) {
2000 if (qlcnic_83xx_vf_check(adapter) && vlan_exist)
2001 return -EINVAL;
2002
2003 if (qlcnic_sriov_validate_num_vlans(sriov, vf))
2004 return -EINVAL;
2005
2006 if (sriov->any_vlan) {
2007 for (i = 0; i < sriov->num_allowed_vlans; i++) {
2008 if (sriov->allowed_vlans[i] == vid)
2009 allowed = 1;
2010 }
2011
2012 if (!allowed)
2013 return -EINVAL;
2014 }
2015 } else {
2016 if (!vlan_exist || qlcnic_sriov_check_vlan_id(sriov, vf, vid))
2017 return -EINVAL;
2018 }
2019
2020 return 0;
2021 }
2022
qlcnic_sriov_vlan_operation(struct qlcnic_vf_info * vf,u16 vlan_id,enum qlcnic_vlan_operations opcode)2023 static void qlcnic_sriov_vlan_operation(struct qlcnic_vf_info *vf, u16 vlan_id,
2024 enum qlcnic_vlan_operations opcode)
2025 {
2026 struct qlcnic_adapter *adapter = vf->adapter;
2027 struct qlcnic_sriov *sriov;
2028
2029 sriov = adapter->ahw->sriov;
2030
2031 if (!vf->sriov_vlans)
2032 return;
2033
2034 spin_lock_bh(&vf->vlan_list_lock);
2035
2036 switch (opcode) {
2037 case QLC_VLAN_ADD:
2038 qlcnic_sriov_add_vlan_id(sriov, vf, vlan_id);
2039 break;
2040 case QLC_VLAN_DELETE:
2041 qlcnic_sriov_del_vlan_id(sriov, vf, vlan_id);
2042 break;
2043 default:
2044 netdev_err(adapter->netdev, "Invalid VLAN operation\n");
2045 }
2046
2047 spin_unlock_bh(&vf->vlan_list_lock);
2048 return;
2049 }
2050
qlcnic_sriov_cfg_vf_guest_vlan(struct qlcnic_adapter * adapter,u16 vid,u8 enable)2051 int qlcnic_sriov_cfg_vf_guest_vlan(struct qlcnic_adapter *adapter,
2052 u16 vid, u8 enable)
2053 {
2054 struct qlcnic_sriov *sriov = adapter->ahw->sriov;
2055 struct net_device *netdev = adapter->netdev;
2056 struct qlcnic_vf_info *vf;
2057 struct qlcnic_cmd_args cmd;
2058 int ret;
2059
2060 memset(&cmd, 0, sizeof(cmd));
2061 if (vid == 0)
2062 return 0;
2063
2064 vf = &adapter->ahw->sriov->vf_info[0];
2065 ret = qlcnic_sriov_validate_vlan_cfg(adapter, vid, enable);
2066 if (ret)
2067 return ret;
2068
2069 ret = qlcnic_sriov_alloc_bc_mbx_args(&cmd,
2070 QLCNIC_BC_CMD_CFG_GUEST_VLAN);
2071 if (ret)
2072 return ret;
2073
2074 cmd.req.arg[1] = (enable & 1) | vid << 16;
2075
2076 qlcnic_sriov_cleanup_async_list(&sriov->bc);
2077 ret = qlcnic_issue_cmd(adapter, &cmd);
2078 if (ret) {
2079 dev_err(&adapter->pdev->dev,
2080 "Failed to configure guest VLAN, err=%d\n", ret);
2081 } else {
2082 netif_addr_lock_bh(netdev);
2083 qlcnic_free_mac_list(adapter);
2084 netif_addr_unlock_bh(netdev);
2085
2086 if (enable)
2087 qlcnic_sriov_vlan_operation(vf, vid, QLC_VLAN_ADD);
2088 else
2089 qlcnic_sriov_vlan_operation(vf, vid, QLC_VLAN_DELETE);
2090
2091 netif_addr_lock_bh(netdev);
2092 qlcnic_set_multi(netdev);
2093 netif_addr_unlock_bh(netdev);
2094 }
2095
2096 qlcnic_free_mbx_args(&cmd);
2097 return ret;
2098 }
2099
qlcnic_sriov_vf_free_mac_list(struct qlcnic_adapter * adapter)2100 static void qlcnic_sriov_vf_free_mac_list(struct qlcnic_adapter *adapter)
2101 {
2102 struct list_head *head = &adapter->mac_list;
2103 struct qlcnic_mac_vlan_list *cur;
2104
2105 while (!list_empty(head)) {
2106 cur = list_entry(head->next, struct qlcnic_mac_vlan_list, list);
2107 qlcnic_sre_macaddr_change(adapter, cur->mac_addr, cur->vlan_id,
2108 QLCNIC_MAC_DEL);
2109 list_del(&cur->list);
2110 kfree(cur);
2111 }
2112 }
2113
2114
qlcnic_sriov_vf_shutdown(struct pci_dev * pdev)2115 static int qlcnic_sriov_vf_shutdown(struct pci_dev *pdev)
2116 {
2117 struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
2118 struct net_device *netdev = adapter->netdev;
2119 int retval;
2120
2121 netif_device_detach(netdev);
2122 qlcnic_cancel_idc_work(adapter);
2123
2124 if (netif_running(netdev))
2125 qlcnic_down(adapter, netdev);
2126
2127 qlcnic_sriov_channel_cfg_cmd(adapter, QLCNIC_BC_CMD_CHANNEL_TERM);
2128 qlcnic_sriov_cfg_bc_intr(adapter, 0);
2129 qlcnic_83xx_disable_mbx_intr(adapter);
2130 cancel_delayed_work_sync(&adapter->idc_aen_work);
2131
2132 retval = pci_save_state(pdev);
2133 if (retval)
2134 return retval;
2135
2136 return 0;
2137 }
2138
qlcnic_sriov_vf_resume(struct qlcnic_adapter * adapter)2139 static int qlcnic_sriov_vf_resume(struct qlcnic_adapter *adapter)
2140 {
2141 struct qlc_83xx_idc *idc = &adapter->ahw->idc;
2142 struct net_device *netdev = adapter->netdev;
2143 int err;
2144
2145 set_bit(QLC_83XX_MODULE_LOADED, &idc->status);
2146 qlcnic_83xx_enable_mbx_interrupt(adapter);
2147 err = qlcnic_sriov_cfg_bc_intr(adapter, 1);
2148 if (err)
2149 return err;
2150
2151 err = qlcnic_sriov_channel_cfg_cmd(adapter, QLCNIC_BC_CMD_CHANNEL_INIT);
2152 if (!err) {
2153 if (netif_running(netdev)) {
2154 err = qlcnic_up(adapter, netdev);
2155 if (!err)
2156 qlcnic_restore_indev_addr(netdev, NETDEV_UP);
2157 }
2158 }
2159
2160 netif_device_attach(netdev);
2161 qlcnic_schedule_work(adapter, qlcnic_sriov_vf_poll_dev_state,
2162 idc->delay);
2163 return err;
2164 }
2165
qlcnic_sriov_alloc_vlans(struct qlcnic_adapter * adapter)2166 int qlcnic_sriov_alloc_vlans(struct qlcnic_adapter *adapter)
2167 {
2168 struct qlcnic_sriov *sriov = adapter->ahw->sriov;
2169 struct qlcnic_vf_info *vf;
2170 int i;
2171
2172 for (i = 0; i < sriov->num_vfs; i++) {
2173 vf = &sriov->vf_info[i];
2174 vf->sriov_vlans = kcalloc(sriov->num_allowed_vlans,
2175 sizeof(*vf->sriov_vlans), GFP_KERNEL);
2176 if (!vf->sriov_vlans)
2177 return -ENOMEM;
2178 }
2179
2180 return 0;
2181 }
2182
qlcnic_sriov_free_vlans(struct qlcnic_adapter * adapter)2183 void qlcnic_sriov_free_vlans(struct qlcnic_adapter *adapter)
2184 {
2185 struct qlcnic_sriov *sriov = adapter->ahw->sriov;
2186 struct qlcnic_vf_info *vf;
2187 int i;
2188
2189 for (i = 0; i < sriov->num_vfs; i++) {
2190 vf = &sriov->vf_info[i];
2191 kfree(vf->sriov_vlans);
2192 vf->sriov_vlans = NULL;
2193 }
2194 }
2195
qlcnic_sriov_add_vlan_id(struct qlcnic_sriov * sriov,struct qlcnic_vf_info * vf,u16 vlan_id)2196 void qlcnic_sriov_add_vlan_id(struct qlcnic_sriov *sriov,
2197 struct qlcnic_vf_info *vf, u16 vlan_id)
2198 {
2199 int i;
2200
2201 for (i = 0; i < sriov->num_allowed_vlans; i++) {
2202 if (!vf->sriov_vlans[i]) {
2203 vf->sriov_vlans[i] = vlan_id;
2204 vf->num_vlan++;
2205 return;
2206 }
2207 }
2208 }
2209
qlcnic_sriov_del_vlan_id(struct qlcnic_sriov * sriov,struct qlcnic_vf_info * vf,u16 vlan_id)2210 void qlcnic_sriov_del_vlan_id(struct qlcnic_sriov *sriov,
2211 struct qlcnic_vf_info *vf, u16 vlan_id)
2212 {
2213 int i;
2214
2215 for (i = 0; i < sriov->num_allowed_vlans; i++) {
2216 if (vf->sriov_vlans[i] == vlan_id) {
2217 vf->sriov_vlans[i] = 0;
2218 vf->num_vlan--;
2219 return;
2220 }
2221 }
2222 }
2223
qlcnic_sriov_check_any_vlan(struct qlcnic_vf_info * vf)2224 bool qlcnic_sriov_check_any_vlan(struct qlcnic_vf_info *vf)
2225 {
2226 bool err = false;
2227
2228 spin_lock_bh(&vf->vlan_list_lock);
2229
2230 if (vf->num_vlan)
2231 err = true;
2232
2233 spin_unlock_bh(&vf->vlan_list_lock);
2234 return err;
2235 }
2236