1 /*
2 * Copyright 2007-11 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26
27 #include <linux/backlight.h>
28 #include <linux/dmi.h>
29 #include <linux/pci.h>
30
31 #include <drm/drm_crtc_helper.h>
32 #include <drm/drm_file.h>
33 #include <drm/radeon_drm.h>
34
35 #include "atom.h"
36 #include "radeon.h"
37 #include "radeon_asic.h"
38 #include "radeon_audio.h"
39
40 extern int atom_debug;
41
42 static u8
radeon_atom_get_backlight_level_from_reg(struct radeon_device * rdev)43 radeon_atom_get_backlight_level_from_reg(struct radeon_device *rdev)
44 {
45 u8 backlight_level;
46 u32 bios_2_scratch;
47
48 if (rdev->family >= CHIP_R600)
49 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
50 else
51 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
52
53 backlight_level = ((bios_2_scratch & ATOM_S2_CURRENT_BL_LEVEL_MASK) >>
54 ATOM_S2_CURRENT_BL_LEVEL_SHIFT);
55
56 return backlight_level;
57 }
58
59 static void
radeon_atom_set_backlight_level_to_reg(struct radeon_device * rdev,u8 backlight_level)60 radeon_atom_set_backlight_level_to_reg(struct radeon_device *rdev,
61 u8 backlight_level)
62 {
63 u32 bios_2_scratch;
64
65 if (rdev->family >= CHIP_R600)
66 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
67 else
68 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
69
70 bios_2_scratch &= ~ATOM_S2_CURRENT_BL_LEVEL_MASK;
71 bios_2_scratch |= ((backlight_level << ATOM_S2_CURRENT_BL_LEVEL_SHIFT) &
72 ATOM_S2_CURRENT_BL_LEVEL_MASK);
73
74 if (rdev->family >= CHIP_R600)
75 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
76 else
77 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
78 }
79
80 u8
atombios_get_backlight_level(struct radeon_encoder * radeon_encoder)81 atombios_get_backlight_level(struct radeon_encoder *radeon_encoder)
82 {
83 struct drm_device *dev = radeon_encoder->base.dev;
84 struct radeon_device *rdev = dev->dev_private;
85
86 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
87 return 0;
88
89 return radeon_atom_get_backlight_level_from_reg(rdev);
90 }
91
92 void
atombios_set_backlight_level(struct radeon_encoder * radeon_encoder,u8 level)93 atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level)
94 {
95 struct drm_encoder *encoder = &radeon_encoder->base;
96 struct drm_device *dev = radeon_encoder->base.dev;
97 struct radeon_device *rdev = dev->dev_private;
98 struct radeon_encoder_atom_dig *dig;
99 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
100 int index;
101
102 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
103 return;
104
105 if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) &&
106 radeon_encoder->enc_priv) {
107 dig = radeon_encoder->enc_priv;
108 dig->backlight_level = level;
109 radeon_atom_set_backlight_level_to_reg(rdev, dig->backlight_level);
110
111 switch (radeon_encoder->encoder_id) {
112 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
113 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
114 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
115 if (dig->backlight_level == 0) {
116 args.ucAction = ATOM_LCD_BLOFF;
117 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
118 } else {
119 args.ucAction = ATOM_LCD_BL_BRIGHTNESS_CONTROL;
120 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
121 args.ucAction = ATOM_LCD_BLON;
122 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
123 }
124 break;
125 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
126 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
127 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
128 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
129 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
130 if (dig->backlight_level == 0)
131 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
132 else {
133 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL, 0, 0);
134 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
135 }
136 break;
137 default:
138 break;
139 }
140 }
141 }
142
143 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
144
radeon_atom_bl_level(struct backlight_device * bd)145 static u8 radeon_atom_bl_level(struct backlight_device *bd)
146 {
147 u8 level;
148
149 /* Convert brightness to hardware level */
150 if (bd->props.brightness < 0)
151 level = 0;
152 else if (bd->props.brightness > RADEON_MAX_BL_LEVEL)
153 level = RADEON_MAX_BL_LEVEL;
154 else
155 level = bd->props.brightness;
156
157 return level;
158 }
159
radeon_atom_backlight_update_status(struct backlight_device * bd)160 static int radeon_atom_backlight_update_status(struct backlight_device *bd)
161 {
162 struct radeon_backlight_privdata *pdata = bl_get_data(bd);
163 struct radeon_encoder *radeon_encoder = pdata->encoder;
164
165 atombios_set_backlight_level(radeon_encoder, radeon_atom_bl_level(bd));
166
167 return 0;
168 }
169
radeon_atom_backlight_get_brightness(struct backlight_device * bd)170 static int radeon_atom_backlight_get_brightness(struct backlight_device *bd)
171 {
172 struct radeon_backlight_privdata *pdata = bl_get_data(bd);
173 struct radeon_encoder *radeon_encoder = pdata->encoder;
174 struct drm_device *dev = radeon_encoder->base.dev;
175 struct radeon_device *rdev = dev->dev_private;
176
177 return radeon_atom_get_backlight_level_from_reg(rdev);
178 }
179
180 static const struct backlight_ops radeon_atom_backlight_ops = {
181 .get_brightness = radeon_atom_backlight_get_brightness,
182 .update_status = radeon_atom_backlight_update_status,
183 };
184
radeon_atom_backlight_init(struct radeon_encoder * radeon_encoder,struct drm_connector * drm_connector)185 void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder,
186 struct drm_connector *drm_connector)
187 {
188 struct drm_device *dev = radeon_encoder->base.dev;
189 struct radeon_device *rdev = dev->dev_private;
190 struct backlight_device *bd;
191 struct backlight_properties props;
192 struct radeon_backlight_privdata *pdata;
193 struct radeon_encoder_atom_dig *dig;
194 char bl_name[16];
195
196 /* Mac laptops with multiple GPUs use the gmux driver for backlight
197 * so don't register a backlight device
198 */
199 if ((rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) &&
200 (rdev->pdev->device == 0x6741) &&
201 !dmi_match(DMI_PRODUCT_NAME, "iMac12,1"))
202 return;
203
204 if (!radeon_encoder->enc_priv)
205 return;
206
207 if (!rdev->is_atom_bios)
208 return;
209
210 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
211 return;
212
213 pdata = kmalloc(sizeof(struct radeon_backlight_privdata), GFP_KERNEL);
214 if (!pdata) {
215 DRM_ERROR("Memory allocation failed\n");
216 goto error;
217 }
218
219 memset(&props, 0, sizeof(props));
220 props.max_brightness = RADEON_MAX_BL_LEVEL;
221 props.type = BACKLIGHT_RAW;
222 snprintf(bl_name, sizeof(bl_name),
223 "radeon_bl%d", dev->primary->index);
224 bd = backlight_device_register(bl_name, drm_connector->kdev,
225 pdata, &radeon_atom_backlight_ops, &props);
226 if (IS_ERR(bd)) {
227 DRM_ERROR("Backlight registration failed\n");
228 goto error;
229 }
230
231 pdata->encoder = radeon_encoder;
232
233 dig = radeon_encoder->enc_priv;
234 dig->bl_dev = bd;
235
236 bd->props.brightness = radeon_atom_backlight_get_brightness(bd);
237 /* Set a reasonable default here if the level is 0 otherwise
238 * fbdev will attempt to turn the backlight on after console
239 * unblanking and it will try and restore 0 which turns the backlight
240 * off again.
241 */
242 if (bd->props.brightness == 0)
243 bd->props.brightness = RADEON_MAX_BL_LEVEL;
244 bd->props.power = FB_BLANK_UNBLANK;
245 backlight_update_status(bd);
246
247 DRM_INFO("radeon atom DIG backlight initialized\n");
248 rdev->mode_info.bl_encoder = radeon_encoder;
249
250 return;
251
252 error:
253 kfree(pdata);
254 return;
255 }
256
radeon_atom_backlight_exit(struct radeon_encoder * radeon_encoder)257 static void radeon_atom_backlight_exit(struct radeon_encoder *radeon_encoder)
258 {
259 struct drm_device *dev = radeon_encoder->base.dev;
260 struct radeon_device *rdev = dev->dev_private;
261 struct backlight_device *bd = NULL;
262 struct radeon_encoder_atom_dig *dig;
263
264 if (!radeon_encoder->enc_priv)
265 return;
266
267 if (!rdev->is_atom_bios)
268 return;
269
270 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
271 return;
272
273 dig = radeon_encoder->enc_priv;
274 bd = dig->bl_dev;
275 dig->bl_dev = NULL;
276
277 if (bd) {
278 struct radeon_legacy_backlight_privdata *pdata;
279
280 pdata = bl_get_data(bd);
281 backlight_device_unregister(bd);
282 kfree(pdata);
283
284 DRM_INFO("radeon atom LVDS backlight unloaded\n");
285 }
286 }
287
288 #else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */
289
radeon_atom_backlight_init(struct radeon_encoder * encoder)290 void radeon_atom_backlight_init(struct radeon_encoder *encoder)
291 {
292 }
293
radeon_atom_backlight_exit(struct radeon_encoder * encoder)294 static void radeon_atom_backlight_exit(struct radeon_encoder *encoder)
295 {
296 }
297
298 #endif
299
300 /* evil but including atombios.h is much worse */
301 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
302 struct drm_display_mode *mode);
303
radeon_atom_mode_fixup(struct drm_encoder * encoder,const struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)304 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
305 const struct drm_display_mode *mode,
306 struct drm_display_mode *adjusted_mode)
307 {
308 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
309 struct drm_device *dev = encoder->dev;
310 struct radeon_device *rdev = dev->dev_private;
311
312 /* set the active encoder to connector routing */
313 radeon_encoder_set_active_device(encoder);
314 drm_mode_set_crtcinfo(adjusted_mode, 0);
315
316 /* hw bug */
317 if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
318 && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
319 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
320
321 /* vertical FP must be at least 1 */
322 if (mode->crtc_vsync_start == mode->crtc_vdisplay)
323 adjusted_mode->crtc_vsync_start++;
324
325 /* get the native mode for scaling */
326 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) {
327 radeon_panel_mode_fixup(encoder, adjusted_mode);
328 } else if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
329 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
330 if (tv_dac) {
331 if (tv_dac->tv_std == TV_STD_NTSC ||
332 tv_dac->tv_std == TV_STD_NTSC_J ||
333 tv_dac->tv_std == TV_STD_PAL_M)
334 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
335 else
336 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
337 }
338 } else if (radeon_encoder->rmx_type != RMX_OFF) {
339 radeon_panel_mode_fixup(encoder, adjusted_mode);
340 }
341
342 if (ASIC_IS_DCE3(rdev) &&
343 ((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
344 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE))) {
345 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
346 radeon_dp_set_link_config(connector, adjusted_mode);
347 }
348
349 return true;
350 }
351
352 static void
atombios_dac_setup(struct drm_encoder * encoder,int action)353 atombios_dac_setup(struct drm_encoder *encoder, int action)
354 {
355 struct drm_device *dev = encoder->dev;
356 struct radeon_device *rdev = dev->dev_private;
357 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
358 DAC_ENCODER_CONTROL_PS_ALLOCATION args;
359 int index = 0;
360 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
361
362 memset(&args, 0, sizeof(args));
363
364 switch (radeon_encoder->encoder_id) {
365 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
366 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
367 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
368 break;
369 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
370 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
371 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
372 break;
373 }
374
375 args.ucAction = action;
376
377 if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
378 args.ucDacStandard = ATOM_DAC1_PS2;
379 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
380 args.ucDacStandard = ATOM_DAC1_CV;
381 else {
382 switch (dac_info->tv_std) {
383 case TV_STD_PAL:
384 case TV_STD_PAL_M:
385 case TV_STD_SCART_PAL:
386 case TV_STD_SECAM:
387 case TV_STD_PAL_CN:
388 args.ucDacStandard = ATOM_DAC1_PAL;
389 break;
390 case TV_STD_NTSC:
391 case TV_STD_NTSC_J:
392 case TV_STD_PAL_60:
393 default:
394 args.ucDacStandard = ATOM_DAC1_NTSC;
395 break;
396 }
397 }
398 args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
399
400 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
401
402 }
403
404 static void
atombios_tv_setup(struct drm_encoder * encoder,int action)405 atombios_tv_setup(struct drm_encoder *encoder, int action)
406 {
407 struct drm_device *dev = encoder->dev;
408 struct radeon_device *rdev = dev->dev_private;
409 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
410 TV_ENCODER_CONTROL_PS_ALLOCATION args;
411 int index = 0;
412 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
413
414 memset(&args, 0, sizeof(args));
415
416 index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
417
418 args.sTVEncoder.ucAction = action;
419
420 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
421 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
422 else {
423 switch (dac_info->tv_std) {
424 case TV_STD_NTSC:
425 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
426 break;
427 case TV_STD_PAL:
428 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
429 break;
430 case TV_STD_PAL_M:
431 args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
432 break;
433 case TV_STD_PAL_60:
434 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
435 break;
436 case TV_STD_NTSC_J:
437 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
438 break;
439 case TV_STD_SCART_PAL:
440 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
441 break;
442 case TV_STD_SECAM:
443 args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
444 break;
445 case TV_STD_PAL_CN:
446 args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
447 break;
448 default:
449 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
450 break;
451 }
452 }
453
454 args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
455
456 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
457
458 }
459
radeon_atom_get_bpc(struct drm_encoder * encoder)460 static u8 radeon_atom_get_bpc(struct drm_encoder *encoder)
461 {
462 int bpc = 8;
463
464 if (encoder->crtc) {
465 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
466 bpc = radeon_crtc->bpc;
467 }
468
469 switch (bpc) {
470 case 0:
471 return PANEL_BPC_UNDEFINE;
472 case 6:
473 return PANEL_6BIT_PER_COLOR;
474 case 8:
475 default:
476 return PANEL_8BIT_PER_COLOR;
477 case 10:
478 return PANEL_10BIT_PER_COLOR;
479 case 12:
480 return PANEL_12BIT_PER_COLOR;
481 case 16:
482 return PANEL_16BIT_PER_COLOR;
483 }
484 }
485
486 union dvo_encoder_control {
487 ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds;
488 DVO_ENCODER_CONTROL_PS_ALLOCATION dvo;
489 DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3;
490 DVO_ENCODER_CONTROL_PS_ALLOCATION_V1_4 dvo_v4;
491 };
492
493 void
atombios_dvo_setup(struct drm_encoder * encoder,int action)494 atombios_dvo_setup(struct drm_encoder *encoder, int action)
495 {
496 struct drm_device *dev = encoder->dev;
497 struct radeon_device *rdev = dev->dev_private;
498 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
499 union dvo_encoder_control args;
500 int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
501 uint8_t frev, crev;
502
503 memset(&args, 0, sizeof(args));
504
505 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
506 return;
507
508 /* some R4xx chips have the wrong frev */
509 if (rdev->family <= CHIP_RV410)
510 frev = 1;
511
512 switch (frev) {
513 case 1:
514 switch (crev) {
515 case 1:
516 /* R4xx, R5xx */
517 args.ext_tmds.sXTmdsEncoder.ucEnable = action;
518
519 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
520 args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL;
521
522 args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB;
523 break;
524 case 2:
525 /* RS600/690/740 */
526 args.dvo.sDVOEncoder.ucAction = action;
527 args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
528 /* DFP1, CRT1, TV1 depending on the type of port */
529 args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX;
530
531 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
532 args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL;
533 break;
534 case 3:
535 /* R6xx */
536 args.dvo_v3.ucAction = action;
537 args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
538 args.dvo_v3.ucDVOConfig = 0; /* XXX */
539 break;
540 case 4:
541 /* DCE8 */
542 args.dvo_v4.ucAction = action;
543 args.dvo_v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
544 args.dvo_v4.ucDVOConfig = 0; /* XXX */
545 args.dvo_v4.ucBitPerColor = radeon_atom_get_bpc(encoder);
546 break;
547 default:
548 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
549 break;
550 }
551 break;
552 default:
553 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
554 break;
555 }
556
557 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
558 }
559
560 union lvds_encoder_control {
561 LVDS_ENCODER_CONTROL_PS_ALLOCATION v1;
562 LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
563 };
564
565 void
atombios_digital_setup(struct drm_encoder * encoder,int action)566 atombios_digital_setup(struct drm_encoder *encoder, int action)
567 {
568 struct drm_device *dev = encoder->dev;
569 struct radeon_device *rdev = dev->dev_private;
570 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
571 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
572 union lvds_encoder_control args;
573 int index = 0;
574 int hdmi_detected = 0;
575 uint8_t frev, crev;
576
577 if (!dig)
578 return;
579
580 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
581 hdmi_detected = 1;
582
583 memset(&args, 0, sizeof(args));
584
585 switch (radeon_encoder->encoder_id) {
586 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
587 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
588 break;
589 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
590 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
591 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
592 break;
593 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
594 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
595 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
596 else
597 index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
598 break;
599 }
600
601 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
602 return;
603
604 switch (frev) {
605 case 1:
606 case 2:
607 switch (crev) {
608 case 1:
609 args.v1.ucMisc = 0;
610 args.v1.ucAction = action;
611 if (hdmi_detected)
612 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
613 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
614 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
615 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
616 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
617 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
618 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
619 } else {
620 if (dig->linkb)
621 args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
622 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
623 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
624 /*if (pScrn->rgbBits == 8) */
625 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
626 }
627 break;
628 case 2:
629 case 3:
630 args.v2.ucMisc = 0;
631 args.v2.ucAction = action;
632 if (crev == 3) {
633 if (dig->coherent_mode)
634 args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
635 }
636 if (hdmi_detected)
637 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
638 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
639 args.v2.ucTruncate = 0;
640 args.v2.ucSpatial = 0;
641 args.v2.ucTemporal = 0;
642 args.v2.ucFRC = 0;
643 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
644 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
645 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
646 if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) {
647 args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
648 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
649 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
650 }
651 if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) {
652 args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
653 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
654 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
655 if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
656 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
657 }
658 } else {
659 if (dig->linkb)
660 args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
661 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
662 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
663 }
664 break;
665 default:
666 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
667 break;
668 }
669 break;
670 default:
671 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
672 break;
673 }
674
675 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
676 }
677
678 int
atombios_get_encoder_mode(struct drm_encoder * encoder)679 atombios_get_encoder_mode(struct drm_encoder *encoder)
680 {
681 struct drm_device *dev = encoder->dev;
682 struct radeon_device *rdev = dev->dev_private;
683 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
684 struct drm_connector *connector;
685 struct radeon_connector *radeon_connector;
686 struct radeon_connector_atom_dig *dig_connector;
687 struct radeon_encoder_atom_dig *dig_enc;
688
689 if (radeon_encoder_is_digital(encoder)) {
690 dig_enc = radeon_encoder->enc_priv;
691 if (dig_enc->active_mst_links)
692 return ATOM_ENCODER_MODE_DP_MST;
693 }
694 if (radeon_encoder->is_mst_encoder || radeon_encoder->offset)
695 return ATOM_ENCODER_MODE_DP_MST;
696 /* dp bridges are always DP */
697 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)
698 return ATOM_ENCODER_MODE_DP;
699
700 /* DVO is always DVO */
701 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DVO1) ||
702 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1))
703 return ATOM_ENCODER_MODE_DVO;
704
705 connector = radeon_get_connector_for_encoder(encoder);
706 /* if we don't have an active device yet, just use one of
707 * the connectors tied to the encoder.
708 */
709 if (!connector)
710 connector = radeon_get_connector_for_encoder_init(encoder);
711 radeon_connector = to_radeon_connector(connector);
712
713 switch (connector->connector_type) {
714 case DRM_MODE_CONNECTOR_DVII:
715 case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
716 if (radeon_audio != 0) {
717 if (radeon_connector->use_digital &&
718 (radeon_connector->audio == RADEON_AUDIO_ENABLE))
719 return ATOM_ENCODER_MODE_HDMI;
720 else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
721 (radeon_connector->audio == RADEON_AUDIO_AUTO))
722 return ATOM_ENCODER_MODE_HDMI;
723 else if (radeon_connector->use_digital)
724 return ATOM_ENCODER_MODE_DVI;
725 else
726 return ATOM_ENCODER_MODE_CRT;
727 } else if (radeon_connector->use_digital) {
728 return ATOM_ENCODER_MODE_DVI;
729 } else {
730 return ATOM_ENCODER_MODE_CRT;
731 }
732 break;
733 case DRM_MODE_CONNECTOR_DVID:
734 case DRM_MODE_CONNECTOR_HDMIA:
735 default:
736 if (radeon_audio != 0) {
737 if (radeon_connector->audio == RADEON_AUDIO_ENABLE)
738 return ATOM_ENCODER_MODE_HDMI;
739 else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
740 (radeon_connector->audio == RADEON_AUDIO_AUTO))
741 return ATOM_ENCODER_MODE_HDMI;
742 else
743 return ATOM_ENCODER_MODE_DVI;
744 } else {
745 return ATOM_ENCODER_MODE_DVI;
746 }
747 break;
748 case DRM_MODE_CONNECTOR_LVDS:
749 return ATOM_ENCODER_MODE_LVDS;
750 break;
751 case DRM_MODE_CONNECTOR_DisplayPort:
752 dig_connector = radeon_connector->con_priv;
753 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
754 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
755 if (radeon_audio != 0 &&
756 drm_detect_monitor_audio(radeon_connector_edid(connector)) &&
757 ASIC_IS_DCE4(rdev) && !ASIC_IS_DCE5(rdev))
758 return ATOM_ENCODER_MODE_DP_AUDIO;
759 return ATOM_ENCODER_MODE_DP;
760 } else if (radeon_audio != 0) {
761 if (radeon_connector->audio == RADEON_AUDIO_ENABLE)
762 return ATOM_ENCODER_MODE_HDMI;
763 else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
764 (radeon_connector->audio == RADEON_AUDIO_AUTO))
765 return ATOM_ENCODER_MODE_HDMI;
766 else
767 return ATOM_ENCODER_MODE_DVI;
768 } else {
769 return ATOM_ENCODER_MODE_DVI;
770 }
771 break;
772 case DRM_MODE_CONNECTOR_eDP:
773 if (radeon_audio != 0 &&
774 drm_detect_monitor_audio(radeon_connector_edid(connector)) &&
775 ASIC_IS_DCE4(rdev) && !ASIC_IS_DCE5(rdev))
776 return ATOM_ENCODER_MODE_DP_AUDIO;
777 return ATOM_ENCODER_MODE_DP;
778 case DRM_MODE_CONNECTOR_DVIA:
779 case DRM_MODE_CONNECTOR_VGA:
780 return ATOM_ENCODER_MODE_CRT;
781 break;
782 case DRM_MODE_CONNECTOR_Composite:
783 case DRM_MODE_CONNECTOR_SVIDEO:
784 case DRM_MODE_CONNECTOR_9PinDIN:
785 /* fix me */
786 return ATOM_ENCODER_MODE_TV;
787 /*return ATOM_ENCODER_MODE_CV;*/
788 break;
789 }
790 }
791
792 /*
793 * DIG Encoder/Transmitter Setup
794 *
795 * DCE 3.0/3.1
796 * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
797 * Supports up to 3 digital outputs
798 * - 2 DIG encoder blocks.
799 * DIG1 can drive UNIPHY link A or link B
800 * DIG2 can drive UNIPHY link B or LVTMA
801 *
802 * DCE 3.2
803 * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
804 * Supports up to 5 digital outputs
805 * - 2 DIG encoder blocks.
806 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
807 *
808 * DCE 4.0/5.0/6.0
809 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
810 * Supports up to 6 digital outputs
811 * - 6 DIG encoder blocks.
812 * - DIG to PHY mapping is hardcoded
813 * DIG1 drives UNIPHY0 link A, A+B
814 * DIG2 drives UNIPHY0 link B
815 * DIG3 drives UNIPHY1 link A, A+B
816 * DIG4 drives UNIPHY1 link B
817 * DIG5 drives UNIPHY2 link A, A+B
818 * DIG6 drives UNIPHY2 link B
819 *
820 * DCE 4.1
821 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
822 * Supports up to 6 digital outputs
823 * - 2 DIG encoder blocks.
824 * llano
825 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
826 * ontario
827 * DIG1 drives UNIPHY0/1/2 link A
828 * DIG2 drives UNIPHY0/1/2 link B
829 *
830 * Routing
831 * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
832 * Examples:
833 * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI
834 * crtc1 -> dig1 -> UNIPHY0 link B -> DP
835 * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS
836 * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI
837 */
838
839 union dig_encoder_control {
840 DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
841 DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
842 DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
843 DIG_ENCODER_CONTROL_PARAMETERS_V4 v4;
844 };
845
846 void
atombios_dig_encoder_setup2(struct drm_encoder * encoder,int action,int panel_mode,int enc_override)847 atombios_dig_encoder_setup2(struct drm_encoder *encoder, int action, int panel_mode, int enc_override)
848 {
849 struct drm_device *dev = encoder->dev;
850 struct radeon_device *rdev = dev->dev_private;
851 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
852 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
853 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
854 union dig_encoder_control args;
855 int index = 0;
856 uint8_t frev, crev;
857 int dp_clock = 0;
858 int dp_lane_count = 0;
859 int hpd_id = RADEON_HPD_NONE;
860
861 if (connector) {
862 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
863 struct radeon_connector_atom_dig *dig_connector =
864 radeon_connector->con_priv;
865
866 dp_clock = dig_connector->dp_clock;
867 dp_lane_count = dig_connector->dp_lane_count;
868 hpd_id = radeon_connector->hpd.hpd;
869 }
870
871 /* no dig encoder assigned */
872 if (dig->dig_encoder == -1)
873 return;
874
875 memset(&args, 0, sizeof(args));
876
877 if (ASIC_IS_DCE4(rdev))
878 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
879 else {
880 if (dig->dig_encoder)
881 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
882 else
883 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
884 }
885
886 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
887 return;
888
889 switch (frev) {
890 case 1:
891 switch (crev) {
892 case 1:
893 args.v1.ucAction = action;
894 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
895 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
896 args.v3.ucPanelMode = panel_mode;
897 else
898 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
899
900 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
901 args.v1.ucLaneNum = dp_lane_count;
902 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
903 args.v1.ucLaneNum = 8;
904 else
905 args.v1.ucLaneNum = 4;
906
907 switch (radeon_encoder->encoder_id) {
908 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
909 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
910 break;
911 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
912 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
913 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
914 break;
915 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
916 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
917 break;
918 }
919 if (dig->linkb)
920 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
921 else
922 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
923
924 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000))
925 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
926
927 break;
928 case 2:
929 case 3:
930 args.v3.ucAction = action;
931 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
932 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
933 args.v3.ucPanelMode = panel_mode;
934 else
935 args.v3.ucEncoderMode = atombios_get_encoder_mode(encoder);
936
937 if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode))
938 args.v3.ucLaneNum = dp_lane_count;
939 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
940 args.v3.ucLaneNum = 8;
941 else
942 args.v3.ucLaneNum = 4;
943
944 if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode) && (dp_clock == 270000))
945 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
946 if (enc_override != -1)
947 args.v3.acConfig.ucDigSel = enc_override;
948 else
949 args.v3.acConfig.ucDigSel = dig->dig_encoder;
950 args.v3.ucBitPerColor = radeon_atom_get_bpc(encoder);
951 break;
952 case 4:
953 args.v4.ucAction = action;
954 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
955 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
956 args.v4.ucPanelMode = panel_mode;
957 else
958 args.v4.ucEncoderMode = atombios_get_encoder_mode(encoder);
959
960 if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode))
961 args.v4.ucLaneNum = dp_lane_count;
962 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
963 args.v4.ucLaneNum = 8;
964 else
965 args.v4.ucLaneNum = 4;
966
967 if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) {
968 if (dp_clock == 540000)
969 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ;
970 else if (dp_clock == 324000)
971 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ;
972 else if (dp_clock == 270000)
973 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ;
974 else
975 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ;
976 }
977
978 if (enc_override != -1)
979 args.v4.acConfig.ucDigSel = enc_override;
980 else
981 args.v4.acConfig.ucDigSel = dig->dig_encoder;
982 args.v4.ucBitPerColor = radeon_atom_get_bpc(encoder);
983 if (hpd_id == RADEON_HPD_NONE)
984 args.v4.ucHPD_ID = 0;
985 else
986 args.v4.ucHPD_ID = hpd_id + 1;
987 break;
988 default:
989 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
990 break;
991 }
992 break;
993 default:
994 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
995 break;
996 }
997
998 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
999
1000 }
1001
1002 void
atombios_dig_encoder_setup(struct drm_encoder * encoder,int action,int panel_mode)1003 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode)
1004 {
1005 atombios_dig_encoder_setup2(encoder, action, panel_mode, -1);
1006 }
1007
1008 union dig_transmitter_control {
1009 DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
1010 DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
1011 DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
1012 DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4;
1013 DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 v5;
1014 };
1015
1016 void
atombios_dig_transmitter_setup2(struct drm_encoder * encoder,int action,uint8_t lane_num,uint8_t lane_set,int fe)1017 atombios_dig_transmitter_setup2(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set, int fe)
1018 {
1019 struct drm_device *dev = encoder->dev;
1020 struct radeon_device *rdev = dev->dev_private;
1021 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1022 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1023 struct drm_connector *connector;
1024 union dig_transmitter_control args;
1025 int index = 0;
1026 uint8_t frev, crev;
1027 bool is_dp = false;
1028 int pll_id = 0;
1029 int dp_clock = 0;
1030 int dp_lane_count = 0;
1031 int connector_object_id = 0;
1032 int igp_lane_info = 0;
1033 int dig_encoder = dig->dig_encoder;
1034 int hpd_id = RADEON_HPD_NONE;
1035
1036 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1037 connector = radeon_get_connector_for_encoder_init(encoder);
1038 /* just needed to avoid bailing in the encoder check. the encoder
1039 * isn't used for init
1040 */
1041 dig_encoder = 0;
1042 } else
1043 connector = radeon_get_connector_for_encoder(encoder);
1044
1045 if (connector) {
1046 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1047 struct radeon_connector_atom_dig *dig_connector =
1048 radeon_connector->con_priv;
1049
1050 hpd_id = radeon_connector->hpd.hpd;
1051 dp_clock = dig_connector->dp_clock;
1052 dp_lane_count = dig_connector->dp_lane_count;
1053 connector_object_id =
1054 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1055 igp_lane_info = dig_connector->igp_lane_info;
1056 }
1057
1058 if (encoder->crtc) {
1059 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1060 pll_id = radeon_crtc->pll_id;
1061 }
1062
1063 /* no dig encoder assigned */
1064 if (dig_encoder == -1)
1065 return;
1066
1067 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)))
1068 is_dp = true;
1069
1070 memset(&args, 0, sizeof(args));
1071
1072 switch (radeon_encoder->encoder_id) {
1073 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1074 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1075 break;
1076 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1077 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1078 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1079 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1080 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1081 break;
1082 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1083 index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl);
1084 break;
1085 }
1086
1087 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1088 return;
1089
1090 switch (frev) {
1091 case 1:
1092 switch (crev) {
1093 case 1:
1094 args.v1.ucAction = action;
1095 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1096 args.v1.usInitInfo = cpu_to_le16(connector_object_id);
1097 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1098 args.v1.asMode.ucLaneSel = lane_num;
1099 args.v1.asMode.ucLaneSet = lane_set;
1100 } else {
1101 if (is_dp)
1102 args.v1.usPixelClock = cpu_to_le16(dp_clock / 10);
1103 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1104 args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1105 else
1106 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1107 }
1108
1109 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
1110
1111 if (dig_encoder)
1112 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
1113 else
1114 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
1115
1116 if ((rdev->flags & RADEON_IS_IGP) &&
1117 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
1118 if (is_dp ||
1119 !radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) {
1120 if (igp_lane_info & 0x1)
1121 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
1122 else if (igp_lane_info & 0x2)
1123 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
1124 else if (igp_lane_info & 0x4)
1125 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
1126 else if (igp_lane_info & 0x8)
1127 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
1128 } else {
1129 if (igp_lane_info & 0x3)
1130 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
1131 else if (igp_lane_info & 0xc)
1132 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
1133 }
1134 }
1135
1136 if (dig->linkb)
1137 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
1138 else
1139 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
1140
1141 if (is_dp)
1142 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1143 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1144 if (dig->coherent_mode)
1145 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1146 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1147 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
1148 }
1149 break;
1150 case 2:
1151 args.v2.ucAction = action;
1152 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1153 args.v2.usInitInfo = cpu_to_le16(connector_object_id);
1154 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1155 args.v2.asMode.ucLaneSel = lane_num;
1156 args.v2.asMode.ucLaneSet = lane_set;
1157 } else {
1158 if (is_dp)
1159 args.v2.usPixelClock = cpu_to_le16(dp_clock / 10);
1160 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1161 args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1162 else
1163 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1164 }
1165
1166 args.v2.acConfig.ucEncoderSel = dig_encoder;
1167 if (dig->linkb)
1168 args.v2.acConfig.ucLinkSel = 1;
1169
1170 switch (radeon_encoder->encoder_id) {
1171 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1172 args.v2.acConfig.ucTransmitterSel = 0;
1173 break;
1174 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1175 args.v2.acConfig.ucTransmitterSel = 1;
1176 break;
1177 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1178 args.v2.acConfig.ucTransmitterSel = 2;
1179 break;
1180 }
1181
1182 if (is_dp) {
1183 args.v2.acConfig.fCoherentMode = 1;
1184 args.v2.acConfig.fDPConnector = 1;
1185 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1186 if (dig->coherent_mode)
1187 args.v2.acConfig.fCoherentMode = 1;
1188 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1189 args.v2.acConfig.fDualLinkConnector = 1;
1190 }
1191 break;
1192 case 3:
1193 args.v3.ucAction = action;
1194 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1195 args.v3.usInitInfo = cpu_to_le16(connector_object_id);
1196 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1197 args.v3.asMode.ucLaneSel = lane_num;
1198 args.v3.asMode.ucLaneSet = lane_set;
1199 } else {
1200 if (is_dp)
1201 args.v3.usPixelClock = cpu_to_le16(dp_clock / 10);
1202 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1203 args.v3.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1204 else
1205 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1206 }
1207
1208 if (is_dp)
1209 args.v3.ucLaneNum = dp_lane_count;
1210 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1211 args.v3.ucLaneNum = 8;
1212 else
1213 args.v3.ucLaneNum = 4;
1214
1215 if (dig->linkb)
1216 args.v3.acConfig.ucLinkSel = 1;
1217 if (dig_encoder & 1)
1218 args.v3.acConfig.ucEncoderSel = 1;
1219
1220 /* Select the PLL for the PHY
1221 * DP PHY should be clocked from external src if there is
1222 * one.
1223 */
1224 /* On DCE4, if there is an external clock, it generates the DP ref clock */
1225 if (is_dp && rdev->clock.dp_extclk)
1226 args.v3.acConfig.ucRefClkSource = 2; /* external src */
1227 else
1228 args.v3.acConfig.ucRefClkSource = pll_id;
1229
1230 switch (radeon_encoder->encoder_id) {
1231 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1232 args.v3.acConfig.ucTransmitterSel = 0;
1233 break;
1234 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1235 args.v3.acConfig.ucTransmitterSel = 1;
1236 break;
1237 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1238 args.v3.acConfig.ucTransmitterSel = 2;
1239 break;
1240 }
1241
1242 if (is_dp)
1243 args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
1244 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1245 if (dig->coherent_mode)
1246 args.v3.acConfig.fCoherentMode = 1;
1247 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1248 args.v3.acConfig.fDualLinkConnector = 1;
1249 }
1250 break;
1251 case 4:
1252 args.v4.ucAction = action;
1253 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1254 args.v4.usInitInfo = cpu_to_le16(connector_object_id);
1255 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1256 args.v4.asMode.ucLaneSel = lane_num;
1257 args.v4.asMode.ucLaneSet = lane_set;
1258 } else {
1259 if (is_dp)
1260 args.v4.usPixelClock = cpu_to_le16(dp_clock / 10);
1261 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1262 args.v4.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1263 else
1264 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1265 }
1266
1267 if (is_dp)
1268 args.v4.ucLaneNum = dp_lane_count;
1269 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1270 args.v4.ucLaneNum = 8;
1271 else
1272 args.v4.ucLaneNum = 4;
1273
1274 if (dig->linkb)
1275 args.v4.acConfig.ucLinkSel = 1;
1276 if (dig_encoder & 1)
1277 args.v4.acConfig.ucEncoderSel = 1;
1278
1279 /* Select the PLL for the PHY
1280 * DP PHY should be clocked from external src if there is
1281 * one.
1282 */
1283 /* On DCE5 DCPLL usually generates the DP ref clock */
1284 if (is_dp) {
1285 if (rdev->clock.dp_extclk)
1286 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK;
1287 else
1288 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL;
1289 } else
1290 args.v4.acConfig.ucRefClkSource = pll_id;
1291
1292 switch (radeon_encoder->encoder_id) {
1293 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1294 args.v4.acConfig.ucTransmitterSel = 0;
1295 break;
1296 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1297 args.v4.acConfig.ucTransmitterSel = 1;
1298 break;
1299 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1300 args.v4.acConfig.ucTransmitterSel = 2;
1301 break;
1302 }
1303
1304 if (is_dp)
1305 args.v4.acConfig.fCoherentMode = 1; /* DP requires coherent */
1306 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1307 if (dig->coherent_mode)
1308 args.v4.acConfig.fCoherentMode = 1;
1309 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1310 args.v4.acConfig.fDualLinkConnector = 1;
1311 }
1312 break;
1313 case 5:
1314 args.v5.ucAction = action;
1315 if (is_dp)
1316 args.v5.usSymClock = cpu_to_le16(dp_clock / 10);
1317 else
1318 args.v5.usSymClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1319
1320 switch (radeon_encoder->encoder_id) {
1321 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1322 if (dig->linkb)
1323 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYB;
1324 else
1325 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYA;
1326 break;
1327 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1328 if (dig->linkb)
1329 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYD;
1330 else
1331 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYC;
1332 break;
1333 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1334 if (dig->linkb)
1335 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYF;
1336 else
1337 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYE;
1338 break;
1339 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1340 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYG;
1341 break;
1342 }
1343 if (is_dp)
1344 args.v5.ucLaneNum = dp_lane_count;
1345 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1346 args.v5.ucLaneNum = 8;
1347 else
1348 args.v5.ucLaneNum = 4;
1349 args.v5.ucConnObjId = connector_object_id;
1350 args.v5.ucDigMode = atombios_get_encoder_mode(encoder);
1351
1352 if (is_dp && rdev->clock.dp_extclk)
1353 args.v5.asConfig.ucPhyClkSrcId = ENCODER_REFCLK_SRC_EXTCLK;
1354 else
1355 args.v5.asConfig.ucPhyClkSrcId = pll_id;
1356
1357 if (is_dp)
1358 args.v5.asConfig.ucCoherentMode = 1; /* DP requires coherent */
1359 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1360 if (dig->coherent_mode)
1361 args.v5.asConfig.ucCoherentMode = 1;
1362 }
1363 if (hpd_id == RADEON_HPD_NONE)
1364 args.v5.asConfig.ucHPDSel = 0;
1365 else
1366 args.v5.asConfig.ucHPDSel = hpd_id + 1;
1367 args.v5.ucDigEncoderSel = (fe != -1) ? (1 << fe) : (1 << dig_encoder);
1368 args.v5.ucDPLaneSet = lane_set;
1369 break;
1370 default:
1371 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1372 break;
1373 }
1374 break;
1375 default:
1376 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1377 break;
1378 }
1379
1380 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1381 }
1382
1383 void
atombios_dig_transmitter_setup(struct drm_encoder * encoder,int action,uint8_t lane_num,uint8_t lane_set)1384 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
1385 {
1386 atombios_dig_transmitter_setup2(encoder, action, lane_num, lane_set, -1);
1387 }
1388
1389 bool
atombios_set_edp_panel_power(struct drm_connector * connector,int action)1390 atombios_set_edp_panel_power(struct drm_connector *connector, int action)
1391 {
1392 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1393 struct drm_device *dev = radeon_connector->base.dev;
1394 struct radeon_device *rdev = dev->dev_private;
1395 union dig_transmitter_control args;
1396 int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1397 uint8_t frev, crev;
1398
1399 if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
1400 goto done;
1401
1402 if (!ASIC_IS_DCE4(rdev))
1403 goto done;
1404
1405 if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) &&
1406 (action != ATOM_TRANSMITTER_ACTION_POWER_OFF))
1407 goto done;
1408
1409 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1410 goto done;
1411
1412 memset(&args, 0, sizeof(args));
1413
1414 args.v1.ucAction = action;
1415
1416 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1417
1418 /* wait for the panel to power up */
1419 if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) {
1420 int i;
1421
1422 for (i = 0; i < 300; i++) {
1423 if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd))
1424 return true;
1425 mdelay(1);
1426 }
1427 return false;
1428 }
1429 done:
1430 return true;
1431 }
1432
1433 union external_encoder_control {
1434 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1;
1435 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3;
1436 };
1437
1438 static void
atombios_external_encoder_setup(struct drm_encoder * encoder,struct drm_encoder * ext_encoder,int action)1439 atombios_external_encoder_setup(struct drm_encoder *encoder,
1440 struct drm_encoder *ext_encoder,
1441 int action)
1442 {
1443 struct drm_device *dev = encoder->dev;
1444 struct radeon_device *rdev = dev->dev_private;
1445 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1446 struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder);
1447 union external_encoder_control args;
1448 struct drm_connector *connector;
1449 int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl);
1450 u8 frev, crev;
1451 int dp_clock = 0;
1452 int dp_lane_count = 0;
1453 int connector_object_id = 0;
1454 u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1455
1456 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1457 connector = radeon_get_connector_for_encoder_init(encoder);
1458 else
1459 connector = radeon_get_connector_for_encoder(encoder);
1460
1461 if (connector) {
1462 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1463 struct radeon_connector_atom_dig *dig_connector =
1464 radeon_connector->con_priv;
1465
1466 dp_clock = dig_connector->dp_clock;
1467 dp_lane_count = dig_connector->dp_lane_count;
1468 connector_object_id =
1469 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1470 }
1471
1472 memset(&args, 0, sizeof(args));
1473
1474 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1475 return;
1476
1477 switch (frev) {
1478 case 1:
1479 /* no params on frev 1 */
1480 break;
1481 case 2:
1482 switch (crev) {
1483 case 1:
1484 case 2:
1485 args.v1.sDigEncoder.ucAction = action;
1486 args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1487 args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1488
1489 if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)) {
1490 if (dp_clock == 270000)
1491 args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
1492 args.v1.sDigEncoder.ucLaneNum = dp_lane_count;
1493 } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1494 args.v1.sDigEncoder.ucLaneNum = 8;
1495 else
1496 args.v1.sDigEncoder.ucLaneNum = 4;
1497 break;
1498 case 3:
1499 args.v3.sExtEncoder.ucAction = action;
1500 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1501 args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id);
1502 else
1503 args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1504 args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1505
1506 if (ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)) {
1507 if (dp_clock == 270000)
1508 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
1509 else if (dp_clock == 540000)
1510 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ;
1511 args.v3.sExtEncoder.ucLaneNum = dp_lane_count;
1512 } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1513 args.v3.sExtEncoder.ucLaneNum = 8;
1514 else
1515 args.v3.sExtEncoder.ucLaneNum = 4;
1516 switch (ext_enum) {
1517 case GRAPH_OBJECT_ENUM_ID1:
1518 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1;
1519 break;
1520 case GRAPH_OBJECT_ENUM_ID2:
1521 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2;
1522 break;
1523 case GRAPH_OBJECT_ENUM_ID3:
1524 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3;
1525 break;
1526 }
1527 args.v3.sExtEncoder.ucBitPerColor = radeon_atom_get_bpc(encoder);
1528 break;
1529 default:
1530 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1531 return;
1532 }
1533 break;
1534 default:
1535 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1536 return;
1537 }
1538 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1539 }
1540
1541 static void
atombios_yuv_setup(struct drm_encoder * encoder,bool enable)1542 atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
1543 {
1544 struct drm_device *dev = encoder->dev;
1545 struct radeon_device *rdev = dev->dev_private;
1546 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1547 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1548 ENABLE_YUV_PS_ALLOCATION args;
1549 int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
1550 uint32_t temp, reg;
1551
1552 memset(&args, 0, sizeof(args));
1553
1554 if (rdev->family >= CHIP_R600)
1555 reg = R600_BIOS_3_SCRATCH;
1556 else
1557 reg = RADEON_BIOS_3_SCRATCH;
1558
1559 /* XXX: fix up scratch reg handling */
1560 temp = RREG32(reg);
1561 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1562 WREG32(reg, (ATOM_S3_TV1_ACTIVE |
1563 (radeon_crtc->crtc_id << 18)));
1564 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1565 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
1566 else
1567 WREG32(reg, 0);
1568
1569 if (enable)
1570 args.ucEnable = ATOM_ENABLE;
1571 args.ucCRTC = radeon_crtc->crtc_id;
1572
1573 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1574
1575 WREG32(reg, temp);
1576 }
1577
1578 static void
radeon_atom_encoder_dpms_avivo(struct drm_encoder * encoder,int mode)1579 radeon_atom_encoder_dpms_avivo(struct drm_encoder *encoder, int mode)
1580 {
1581 struct drm_device *dev = encoder->dev;
1582 struct radeon_device *rdev = dev->dev_private;
1583 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1584 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
1585 int index = 0;
1586
1587 memset(&args, 0, sizeof(args));
1588
1589 switch (radeon_encoder->encoder_id) {
1590 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1591 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1592 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
1593 break;
1594 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1595 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1596 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1597 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1598 break;
1599 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1600 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1601 break;
1602 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1603 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1604 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1605 else
1606 index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
1607 break;
1608 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1609 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1610 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1611 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1612 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1613 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1614 else
1615 index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
1616 break;
1617 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1618 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1619 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1620 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1621 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1622 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1623 else
1624 index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
1625 break;
1626 default:
1627 return;
1628 }
1629
1630 switch (mode) {
1631 case DRM_MODE_DPMS_ON:
1632 args.ucAction = ATOM_ENABLE;
1633 /* workaround for DVOOutputControl on some RS690 systems */
1634 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DDI) {
1635 u32 reg = RREG32(RADEON_BIOS_3_SCRATCH);
1636 WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE);
1637 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1638 WREG32(RADEON_BIOS_3_SCRATCH, reg);
1639 } else
1640 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1641 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1642 if (rdev->mode_info.bl_encoder) {
1643 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1644
1645 atombios_set_backlight_level(radeon_encoder, dig->backlight_level);
1646 } else {
1647 args.ucAction = ATOM_LCD_BLON;
1648 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1649 }
1650 }
1651 break;
1652 case DRM_MODE_DPMS_STANDBY:
1653 case DRM_MODE_DPMS_SUSPEND:
1654 case DRM_MODE_DPMS_OFF:
1655 args.ucAction = ATOM_DISABLE;
1656 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1657 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1658 args.ucAction = ATOM_LCD_BLOFF;
1659 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1660 }
1661 break;
1662 }
1663 }
1664
1665 static void
radeon_atom_encoder_dpms_dig(struct drm_encoder * encoder,int mode)1666 radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode)
1667 {
1668 struct drm_device *dev = encoder->dev;
1669 struct radeon_device *rdev = dev->dev_private;
1670 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1671 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1672 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1673 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1674 struct radeon_connector *radeon_connector = NULL;
1675 struct radeon_connector_atom_dig *radeon_dig_connector = NULL;
1676 bool travis_quirk = false;
1677
1678 if (connector) {
1679 radeon_connector = to_radeon_connector(connector);
1680 radeon_dig_connector = radeon_connector->con_priv;
1681 if ((radeon_connector_encoder_get_dp_bridge_encoder_id(connector) ==
1682 ENCODER_OBJECT_ID_TRAVIS) &&
1683 (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) &&
1684 !ASIC_IS_DCE5(rdev))
1685 travis_quirk = true;
1686 }
1687
1688 switch (mode) {
1689 case DRM_MODE_DPMS_ON:
1690 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
1691 if (!connector)
1692 dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
1693 else
1694 dig->panel_mode = radeon_dp_get_panel_mode(encoder, connector);
1695
1696 /* setup and enable the encoder */
1697 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1698 atombios_dig_encoder_setup(encoder,
1699 ATOM_ENCODER_CMD_SETUP_PANEL_MODE,
1700 dig->panel_mode);
1701 if (ext_encoder) {
1702 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))
1703 atombios_external_encoder_setup(encoder, ext_encoder,
1704 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP);
1705 }
1706 } else if (ASIC_IS_DCE4(rdev)) {
1707 /* setup and enable the encoder */
1708 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1709 } else {
1710 /* setup and enable the encoder and transmitter */
1711 atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0);
1712 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1713 }
1714 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1715 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1716 atombios_set_edp_panel_power(connector,
1717 ATOM_TRANSMITTER_ACTION_POWER_ON);
1718 radeon_dig_connector->edp_on = true;
1719 }
1720 }
1721 /* enable the transmitter */
1722 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1723 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1724 /* DP_SET_POWER_D0 is set in radeon_dp_link_train */
1725 radeon_dp_link_train(encoder, connector);
1726 if (ASIC_IS_DCE4(rdev))
1727 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0);
1728 }
1729 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1730 if (rdev->mode_info.bl_encoder)
1731 atombios_set_backlight_level(radeon_encoder, dig->backlight_level);
1732 else
1733 atombios_dig_transmitter_setup(encoder,
1734 ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
1735 }
1736 if (ext_encoder)
1737 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
1738 break;
1739 case DRM_MODE_DPMS_STANDBY:
1740 case DRM_MODE_DPMS_SUSPEND:
1741 case DRM_MODE_DPMS_OFF:
1742
1743 /* don't power off encoders with active MST links */
1744 if (dig->active_mst_links)
1745 return;
1746
1747 if (ASIC_IS_DCE4(rdev)) {
1748 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector)
1749 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
1750 }
1751 if (ext_encoder)
1752 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE);
1753 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1754 atombios_dig_transmitter_setup(encoder,
1755 ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
1756
1757 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) &&
1758 connector && !travis_quirk)
1759 radeon_dp_set_rx_power_state(connector, DP_SET_POWER_D3);
1760 if (ASIC_IS_DCE4(rdev)) {
1761 /* disable the transmitter */
1762 atombios_dig_transmitter_setup(encoder,
1763 ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1764 } else {
1765 /* disable the encoder and transmitter */
1766 atombios_dig_transmitter_setup(encoder,
1767 ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1768 atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
1769 }
1770 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1771 if (travis_quirk)
1772 radeon_dp_set_rx_power_state(connector, DP_SET_POWER_D3);
1773 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1774 atombios_set_edp_panel_power(connector,
1775 ATOM_TRANSMITTER_ACTION_POWER_OFF);
1776 radeon_dig_connector->edp_on = false;
1777 }
1778 }
1779 break;
1780 }
1781 }
1782
1783 static void
radeon_atom_encoder_dpms(struct drm_encoder * encoder,int mode)1784 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1785 {
1786 struct drm_device *dev = encoder->dev;
1787 struct radeon_device *rdev = dev->dev_private;
1788 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1789 int encoder_mode = atombios_get_encoder_mode(encoder);
1790
1791 DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
1792 radeon_encoder->encoder_id, mode, radeon_encoder->devices,
1793 radeon_encoder->active_device);
1794
1795 if ((radeon_audio != 0) &&
1796 ((encoder_mode == ATOM_ENCODER_MODE_HDMI) ||
1797 ENCODER_MODE_IS_DP(encoder_mode)))
1798 radeon_audio_dpms(encoder, mode);
1799
1800 switch (radeon_encoder->encoder_id) {
1801 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1802 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1803 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1804 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1805 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1806 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1807 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1808 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1809 radeon_atom_encoder_dpms_avivo(encoder, mode);
1810 break;
1811 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1812 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1813 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1814 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1815 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1816 radeon_atom_encoder_dpms_dig(encoder, mode);
1817 break;
1818 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1819 if (ASIC_IS_DCE5(rdev)) {
1820 switch (mode) {
1821 case DRM_MODE_DPMS_ON:
1822 atombios_dvo_setup(encoder, ATOM_ENABLE);
1823 break;
1824 case DRM_MODE_DPMS_STANDBY:
1825 case DRM_MODE_DPMS_SUSPEND:
1826 case DRM_MODE_DPMS_OFF:
1827 atombios_dvo_setup(encoder, ATOM_DISABLE);
1828 break;
1829 }
1830 } else if (ASIC_IS_DCE3(rdev))
1831 radeon_atom_encoder_dpms_dig(encoder, mode);
1832 else
1833 radeon_atom_encoder_dpms_avivo(encoder, mode);
1834 break;
1835 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1836 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1837 if (ASIC_IS_DCE5(rdev)) {
1838 switch (mode) {
1839 case DRM_MODE_DPMS_ON:
1840 atombios_dac_setup(encoder, ATOM_ENABLE);
1841 break;
1842 case DRM_MODE_DPMS_STANDBY:
1843 case DRM_MODE_DPMS_SUSPEND:
1844 case DRM_MODE_DPMS_OFF:
1845 atombios_dac_setup(encoder, ATOM_DISABLE);
1846 break;
1847 }
1848 } else
1849 radeon_atom_encoder_dpms_avivo(encoder, mode);
1850 break;
1851 default:
1852 return;
1853 }
1854
1855 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1856
1857 }
1858
1859 union crtc_source_param {
1860 SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1861 SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1862 };
1863
1864 static void
atombios_set_encoder_crtc_source(struct drm_encoder * encoder)1865 atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1866 {
1867 struct drm_device *dev = encoder->dev;
1868 struct radeon_device *rdev = dev->dev_private;
1869 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1870 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1871 union crtc_source_param args;
1872 int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1873 uint8_t frev, crev;
1874 struct radeon_encoder_atom_dig *dig;
1875
1876 memset(&args, 0, sizeof(args));
1877
1878 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1879 return;
1880
1881 switch (frev) {
1882 case 1:
1883 switch (crev) {
1884 case 1:
1885 default:
1886 if (ASIC_IS_AVIVO(rdev))
1887 args.v1.ucCRTC = radeon_crtc->crtc_id;
1888 else {
1889 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1)
1890 args.v1.ucCRTC = radeon_crtc->crtc_id;
1891 else
1892 args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1893 }
1894 switch (radeon_encoder->encoder_id) {
1895 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1896 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1897 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1898 break;
1899 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1900 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1901 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1902 args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1903 else
1904 args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1905 break;
1906 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1907 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1908 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1909 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1910 break;
1911 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1912 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1913 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1914 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1915 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1916 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1917 else
1918 args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1919 break;
1920 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1921 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1922 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1923 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1924 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1925 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1926 else
1927 args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1928 break;
1929 }
1930 break;
1931 case 2:
1932 args.v2.ucCRTC = radeon_crtc->crtc_id;
1933 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) {
1934 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1935
1936 if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)
1937 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
1938 else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA)
1939 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT;
1940 else
1941 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1942 } else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1943 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
1944 } else {
1945 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1946 }
1947 switch (radeon_encoder->encoder_id) {
1948 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1949 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1950 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1951 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1952 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1953 dig = radeon_encoder->enc_priv;
1954 switch (dig->dig_encoder) {
1955 case 0:
1956 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1957 break;
1958 case 1:
1959 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1960 break;
1961 case 2:
1962 args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
1963 break;
1964 case 3:
1965 args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
1966 break;
1967 case 4:
1968 args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
1969 break;
1970 case 5:
1971 args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
1972 break;
1973 case 6:
1974 args.v2.ucEncoderID = ASIC_INT_DIG7_ENCODER_ID;
1975 break;
1976 }
1977 break;
1978 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1979 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1980 break;
1981 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1982 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1983 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1984 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1985 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1986 else
1987 args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1988 break;
1989 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1990 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1991 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1992 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1993 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1994 else
1995 args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1996 break;
1997 }
1998 break;
1999 }
2000 break;
2001 default:
2002 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
2003 return;
2004 }
2005
2006 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2007
2008 /* update scratch regs with new routing */
2009 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
2010 }
2011
2012 void
atombios_set_mst_encoder_crtc_source(struct drm_encoder * encoder,int fe)2013 atombios_set_mst_encoder_crtc_source(struct drm_encoder *encoder, int fe)
2014 {
2015 struct drm_device *dev = encoder->dev;
2016 struct radeon_device *rdev = dev->dev_private;
2017 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
2018 int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
2019 uint8_t frev, crev;
2020 union crtc_source_param args;
2021
2022 memset(&args, 0, sizeof(args));
2023
2024 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2025 return;
2026
2027 if (frev != 1 && crev != 2)
2028 DRM_ERROR("Unknown table for MST %d, %d\n", frev, crev);
2029
2030 args.v2.ucCRTC = radeon_crtc->crtc_id;
2031 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_DP_MST;
2032
2033 switch (fe) {
2034 case 0:
2035 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
2036 break;
2037 case 1:
2038 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
2039 break;
2040 case 2:
2041 args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
2042 break;
2043 case 3:
2044 args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
2045 break;
2046 case 4:
2047 args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
2048 break;
2049 case 5:
2050 args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
2051 break;
2052 case 6:
2053 args.v2.ucEncoderID = ASIC_INT_DIG7_ENCODER_ID;
2054 break;
2055 }
2056 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2057 }
2058
2059 static void
atombios_apply_encoder_quirks(struct drm_encoder * encoder,struct drm_display_mode * mode)2060 atombios_apply_encoder_quirks(struct drm_encoder *encoder,
2061 struct drm_display_mode *mode)
2062 {
2063 struct drm_device *dev = encoder->dev;
2064 struct radeon_device *rdev = dev->dev_private;
2065 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2066 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
2067
2068 /* Funky macbooks */
2069 if ((dev->pdev->device == 0x71C5) &&
2070 (dev->pdev->subsystem_vendor == 0x106b) &&
2071 (dev->pdev->subsystem_device == 0x0080)) {
2072 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2073 uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
2074
2075 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
2076 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
2077
2078 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
2079 }
2080 }
2081
2082 /* set scaler clears this on some chips */
2083 if (ASIC_IS_AVIVO(rdev) &&
2084 (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) {
2085 if (ASIC_IS_DCE8(rdev)) {
2086 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2087 WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset,
2088 CIK_INTERLEAVE_EN);
2089 else
2090 WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
2091 } else if (ASIC_IS_DCE4(rdev)) {
2092 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2093 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
2094 EVERGREEN_INTERLEAVE_EN);
2095 else
2096 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
2097 } else {
2098 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2099 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
2100 AVIVO_D1MODE_INTERLEAVE_EN);
2101 else
2102 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
2103 }
2104 }
2105 }
2106
radeon_atom_release_dig_encoder(struct radeon_device * rdev,int enc_idx)2107 void radeon_atom_release_dig_encoder(struct radeon_device *rdev, int enc_idx)
2108 {
2109 if (enc_idx < 0)
2110 return;
2111 rdev->mode_info.active_encoders &= ~(1 << enc_idx);
2112 }
2113
radeon_atom_pick_dig_encoder(struct drm_encoder * encoder,int fe_idx)2114 int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder, int fe_idx)
2115 {
2116 struct drm_device *dev = encoder->dev;
2117 struct radeon_device *rdev = dev->dev_private;
2118 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
2119 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2120 struct drm_encoder *test_encoder;
2121 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
2122 uint32_t dig_enc_in_use = 0;
2123 int enc_idx = -1;
2124
2125 if (fe_idx >= 0) {
2126 enc_idx = fe_idx;
2127 goto assigned;
2128 }
2129 if (ASIC_IS_DCE6(rdev)) {
2130 /* DCE6 */
2131 switch (radeon_encoder->encoder_id) {
2132 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2133 if (dig->linkb)
2134 enc_idx = 1;
2135 else
2136 enc_idx = 0;
2137 break;
2138 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2139 if (dig->linkb)
2140 enc_idx = 3;
2141 else
2142 enc_idx = 2;
2143 break;
2144 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2145 if (dig->linkb)
2146 enc_idx = 5;
2147 else
2148 enc_idx = 4;
2149 break;
2150 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2151 enc_idx = 6;
2152 break;
2153 }
2154 goto assigned;
2155 } else if (ASIC_IS_DCE4(rdev)) {
2156 /* DCE4/5 */
2157 if (ASIC_IS_DCE41(rdev) && !ASIC_IS_DCE61(rdev)) {
2158 /* ontario follows DCE4 */
2159 if (rdev->family == CHIP_PALM) {
2160 if (dig->linkb)
2161 enc_idx = 1;
2162 else
2163 enc_idx = 0;
2164 } else
2165 /* llano follows DCE3.2 */
2166 enc_idx = radeon_crtc->crtc_id;
2167 } else {
2168 switch (radeon_encoder->encoder_id) {
2169 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2170 if (dig->linkb)
2171 enc_idx = 1;
2172 else
2173 enc_idx = 0;
2174 break;
2175 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2176 if (dig->linkb)
2177 enc_idx = 3;
2178 else
2179 enc_idx = 2;
2180 break;
2181 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2182 if (dig->linkb)
2183 enc_idx = 5;
2184 else
2185 enc_idx = 4;
2186 break;
2187 }
2188 }
2189 goto assigned;
2190 }
2191
2192 /*
2193 * On DCE32 any encoder can drive any block so usually just use crtc id,
2194 * but Apple thinks different at least on iMac10,1 and iMac11,2, so there use linkb,
2195 * otherwise the internal eDP panel will stay dark.
2196 */
2197 if (ASIC_IS_DCE32(rdev)) {
2198 if (dmi_match(DMI_PRODUCT_NAME, "iMac10,1") ||
2199 dmi_match(DMI_PRODUCT_NAME, "iMac11,2"))
2200 enc_idx = (dig->linkb) ? 1 : 0;
2201 else
2202 enc_idx = radeon_crtc->crtc_id;
2203
2204 goto assigned;
2205 }
2206
2207 /* on DCE3 - LVTMA can only be driven by DIGB */
2208 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
2209 struct radeon_encoder *radeon_test_encoder;
2210
2211 if (encoder == test_encoder)
2212 continue;
2213
2214 if (!radeon_encoder_is_digital(test_encoder))
2215 continue;
2216
2217 radeon_test_encoder = to_radeon_encoder(test_encoder);
2218 dig = radeon_test_encoder->enc_priv;
2219
2220 if (dig->dig_encoder >= 0)
2221 dig_enc_in_use |= (1 << dig->dig_encoder);
2222 }
2223
2224 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
2225 if (dig_enc_in_use & 0x2)
2226 DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
2227 return 1;
2228 }
2229 if (!(dig_enc_in_use & 1))
2230 return 0;
2231 return 1;
2232
2233 assigned:
2234 if (enc_idx == -1) {
2235 DRM_ERROR("Got encoder index incorrect - returning 0\n");
2236 return 0;
2237 }
2238 if (rdev->mode_info.active_encoders & (1 << enc_idx))
2239 DRM_ERROR("chosen encoder in use %d\n", enc_idx);
2240
2241 rdev->mode_info.active_encoders |= (1 << enc_idx);
2242 return enc_idx;
2243 }
2244
2245 /* This only needs to be called once at startup */
2246 void
radeon_atom_encoder_init(struct radeon_device * rdev)2247 radeon_atom_encoder_init(struct radeon_device *rdev)
2248 {
2249 struct drm_device *dev = rdev->ddev;
2250 struct drm_encoder *encoder;
2251
2252 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2253 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2254 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2255
2256 switch (radeon_encoder->encoder_id) {
2257 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2258 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2259 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2260 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2261 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2262 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
2263 break;
2264 default:
2265 break;
2266 }
2267
2268 if (ext_encoder && (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)))
2269 atombios_external_encoder_setup(encoder, ext_encoder,
2270 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT);
2271 }
2272 }
2273
2274 static void
radeon_atom_encoder_mode_set(struct drm_encoder * encoder,struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)2275 radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
2276 struct drm_display_mode *mode,
2277 struct drm_display_mode *adjusted_mode)
2278 {
2279 struct drm_device *dev = encoder->dev;
2280 struct radeon_device *rdev = dev->dev_private;
2281 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2282 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
2283 int encoder_mode;
2284
2285 radeon_encoder->pixel_clock = adjusted_mode->clock;
2286
2287 /* need to call this here rather than in prepare() since we need some crtc info */
2288 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2289
2290 if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) {
2291 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
2292 atombios_yuv_setup(encoder, true);
2293 else
2294 atombios_yuv_setup(encoder, false);
2295 }
2296
2297 switch (radeon_encoder->encoder_id) {
2298 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2299 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2300 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2301 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2302 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
2303 break;
2304 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2305 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2306 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2307 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2308 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2309 /* handled in dpms */
2310 break;
2311 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2312 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2313 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2314 atombios_dvo_setup(encoder, ATOM_ENABLE);
2315 break;
2316 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2317 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2318 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2319 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2320 atombios_dac_setup(encoder, ATOM_ENABLE);
2321 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) {
2322 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2323 atombios_tv_setup(encoder, ATOM_ENABLE);
2324 else
2325 atombios_tv_setup(encoder, ATOM_DISABLE);
2326 }
2327 break;
2328 }
2329
2330 atombios_apply_encoder_quirks(encoder, adjusted_mode);
2331
2332 encoder_mode = atombios_get_encoder_mode(encoder);
2333 if (connector && (radeon_audio != 0) &&
2334 ((encoder_mode == ATOM_ENCODER_MODE_HDMI) ||
2335 ENCODER_MODE_IS_DP(encoder_mode)))
2336 radeon_audio_mode_set(encoder, adjusted_mode);
2337 }
2338
2339 static bool
atombios_dac_load_detect(struct drm_encoder * encoder,struct drm_connector * connector)2340 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2341 {
2342 struct drm_device *dev = encoder->dev;
2343 struct radeon_device *rdev = dev->dev_private;
2344 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2345 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2346
2347 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
2348 ATOM_DEVICE_CV_SUPPORT |
2349 ATOM_DEVICE_CRT_SUPPORT)) {
2350 DAC_LOAD_DETECTION_PS_ALLOCATION args;
2351 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
2352 uint8_t frev, crev;
2353
2354 memset(&args, 0, sizeof(args));
2355
2356 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2357 return false;
2358
2359 args.sDacload.ucMisc = 0;
2360
2361 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
2362 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
2363 args.sDacload.ucDacType = ATOM_DAC_A;
2364 else
2365 args.sDacload.ucDacType = ATOM_DAC_B;
2366
2367 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
2368 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
2369 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
2370 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
2371 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2372 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
2373 if (crev >= 3)
2374 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
2375 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2376 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
2377 if (crev >= 3)
2378 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
2379 }
2380
2381 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2382
2383 return true;
2384 } else
2385 return false;
2386 }
2387
2388 static enum drm_connector_status
radeon_atom_dac_detect(struct drm_encoder * encoder,struct drm_connector * connector)2389 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2390 {
2391 struct drm_device *dev = encoder->dev;
2392 struct radeon_device *rdev = dev->dev_private;
2393 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2394 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2395 uint32_t bios_0_scratch;
2396
2397 if (!atombios_dac_load_detect(encoder, connector)) {
2398 DRM_DEBUG_KMS("detect returned false \n");
2399 return connector_status_unknown;
2400 }
2401
2402 if (rdev->family >= CHIP_R600)
2403 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2404 else
2405 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2406
2407 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2408 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2409 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2410 return connector_status_connected;
2411 }
2412 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2413 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2414 return connector_status_connected;
2415 }
2416 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2417 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2418 return connector_status_connected;
2419 }
2420 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2421 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2422 return connector_status_connected; /* CTV */
2423 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2424 return connector_status_connected; /* STV */
2425 }
2426 return connector_status_disconnected;
2427 }
2428
2429 static enum drm_connector_status
radeon_atom_dig_detect(struct drm_encoder * encoder,struct drm_connector * connector)2430 radeon_atom_dig_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2431 {
2432 struct drm_device *dev = encoder->dev;
2433 struct radeon_device *rdev = dev->dev_private;
2434 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2435 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2436 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2437 u32 bios_0_scratch;
2438
2439 if (!ASIC_IS_DCE4(rdev))
2440 return connector_status_unknown;
2441
2442 if (!ext_encoder)
2443 return connector_status_unknown;
2444
2445 if ((radeon_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0)
2446 return connector_status_unknown;
2447
2448 /* load detect on the dp bridge */
2449 atombios_external_encoder_setup(encoder, ext_encoder,
2450 EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION);
2451
2452 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2453
2454 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2455 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2456 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2457 return connector_status_connected;
2458 }
2459 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2460 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2461 return connector_status_connected;
2462 }
2463 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2464 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2465 return connector_status_connected;
2466 }
2467 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2468 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2469 return connector_status_connected; /* CTV */
2470 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2471 return connector_status_connected; /* STV */
2472 }
2473 return connector_status_disconnected;
2474 }
2475
2476 void
radeon_atom_ext_encoder_setup_ddc(struct drm_encoder * encoder)2477 radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder)
2478 {
2479 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2480
2481 if (ext_encoder)
2482 /* ddc_setup on the dp bridge */
2483 atombios_external_encoder_setup(encoder, ext_encoder,
2484 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP);
2485
2486 }
2487
radeon_atom_encoder_prepare(struct drm_encoder * encoder)2488 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
2489 {
2490 struct radeon_device *rdev = encoder->dev->dev_private;
2491 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2492 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
2493
2494 if ((radeon_encoder->active_device &
2495 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
2496 (radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
2497 ENCODER_OBJECT_ID_NONE)) {
2498 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
2499 if (dig) {
2500 if (dig->dig_encoder >= 0)
2501 radeon_atom_release_dig_encoder(rdev, dig->dig_encoder);
2502 dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder, -1);
2503 if (radeon_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) {
2504 if (rdev->family >= CHIP_R600)
2505 dig->afmt = rdev->mode_info.afmt[dig->dig_encoder];
2506 else
2507 /* RS600/690/740 have only 1 afmt block */
2508 dig->afmt = rdev->mode_info.afmt[0];
2509 }
2510 }
2511 }
2512
2513 radeon_atom_output_lock(encoder, true);
2514
2515 if (connector) {
2516 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2517
2518 /* select the clock/data port if it uses a router */
2519 if (radeon_connector->router.cd_valid)
2520 radeon_router_select_cd_port(radeon_connector);
2521
2522 /* turn eDP panel on for mode set */
2523 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
2524 atombios_set_edp_panel_power(connector,
2525 ATOM_TRANSMITTER_ACTION_POWER_ON);
2526 }
2527
2528 /* this is needed for the pll/ss setup to work correctly in some cases */
2529 atombios_set_encoder_crtc_source(encoder);
2530 /* set up the FMT blocks */
2531 if (ASIC_IS_DCE8(rdev))
2532 dce8_program_fmt(encoder);
2533 else if (ASIC_IS_DCE4(rdev))
2534 dce4_program_fmt(encoder);
2535 else if (ASIC_IS_DCE3(rdev))
2536 dce3_program_fmt(encoder);
2537 else if (ASIC_IS_AVIVO(rdev))
2538 avivo_program_fmt(encoder);
2539 }
2540
radeon_atom_encoder_commit(struct drm_encoder * encoder)2541 static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
2542 {
2543 /* need to call this here as we need the crtc set up */
2544 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
2545 radeon_atom_output_lock(encoder, false);
2546 }
2547
radeon_atom_encoder_disable(struct drm_encoder * encoder)2548 static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
2549 {
2550 struct drm_device *dev = encoder->dev;
2551 struct radeon_device *rdev = dev->dev_private;
2552 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2553 struct radeon_encoder_atom_dig *dig;
2554
2555 /* check for pre-DCE3 cards with shared encoders;
2556 * can't really use the links individually, so don't disable
2557 * the encoder if it's in use by another connector
2558 */
2559 if (!ASIC_IS_DCE3(rdev)) {
2560 struct drm_encoder *other_encoder;
2561 struct radeon_encoder *other_radeon_encoder;
2562
2563 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
2564 other_radeon_encoder = to_radeon_encoder(other_encoder);
2565 if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) &&
2566 drm_helper_encoder_in_use(other_encoder))
2567 goto disable_done;
2568 }
2569 }
2570
2571 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2572
2573 switch (radeon_encoder->encoder_id) {
2574 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2575 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2576 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2577 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2578 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE);
2579 break;
2580 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2581 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2582 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2583 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2584 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2585 /* handled in dpms */
2586 break;
2587 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2588 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2589 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2590 atombios_dvo_setup(encoder, ATOM_DISABLE);
2591 break;
2592 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2593 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2594 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2595 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2596 atombios_dac_setup(encoder, ATOM_DISABLE);
2597 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2598 atombios_tv_setup(encoder, ATOM_DISABLE);
2599 break;
2600 }
2601
2602 disable_done:
2603 if (radeon_encoder_is_digital(encoder)) {
2604 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
2605 if (rdev->asic->display.hdmi_enable)
2606 radeon_hdmi_enable(rdev, encoder, false);
2607 }
2608 if (atombios_get_encoder_mode(encoder) != ATOM_ENCODER_MODE_DP_MST) {
2609 dig = radeon_encoder->enc_priv;
2610 radeon_atom_release_dig_encoder(rdev, dig->dig_encoder);
2611 dig->dig_encoder = -1;
2612 radeon_encoder->active_device = 0;
2613 }
2614 } else
2615 radeon_encoder->active_device = 0;
2616 }
2617
2618 /* these are handled by the primary encoders */
radeon_atom_ext_prepare(struct drm_encoder * encoder)2619 static void radeon_atom_ext_prepare(struct drm_encoder *encoder)
2620 {
2621
2622 }
2623
radeon_atom_ext_commit(struct drm_encoder * encoder)2624 static void radeon_atom_ext_commit(struct drm_encoder *encoder)
2625 {
2626
2627 }
2628
2629 static void
radeon_atom_ext_mode_set(struct drm_encoder * encoder,struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)2630 radeon_atom_ext_mode_set(struct drm_encoder *encoder,
2631 struct drm_display_mode *mode,
2632 struct drm_display_mode *adjusted_mode)
2633 {
2634
2635 }
2636
radeon_atom_ext_disable(struct drm_encoder * encoder)2637 static void radeon_atom_ext_disable(struct drm_encoder *encoder)
2638 {
2639
2640 }
2641
2642 static void
radeon_atom_ext_dpms(struct drm_encoder * encoder,int mode)2643 radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode)
2644 {
2645
2646 }
2647
2648 static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = {
2649 .dpms = radeon_atom_ext_dpms,
2650 .prepare = radeon_atom_ext_prepare,
2651 .mode_set = radeon_atom_ext_mode_set,
2652 .commit = radeon_atom_ext_commit,
2653 .disable = radeon_atom_ext_disable,
2654 /* no detect for TMDS/LVDS yet */
2655 };
2656
2657 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
2658 .dpms = radeon_atom_encoder_dpms,
2659 .mode_fixup = radeon_atom_mode_fixup,
2660 .prepare = radeon_atom_encoder_prepare,
2661 .mode_set = radeon_atom_encoder_mode_set,
2662 .commit = radeon_atom_encoder_commit,
2663 .disable = radeon_atom_encoder_disable,
2664 .detect = radeon_atom_dig_detect,
2665 };
2666
2667 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
2668 .dpms = radeon_atom_encoder_dpms,
2669 .mode_fixup = radeon_atom_mode_fixup,
2670 .prepare = radeon_atom_encoder_prepare,
2671 .mode_set = radeon_atom_encoder_mode_set,
2672 .commit = radeon_atom_encoder_commit,
2673 .detect = radeon_atom_dac_detect,
2674 };
2675
radeon_enc_destroy(struct drm_encoder * encoder)2676 void radeon_enc_destroy(struct drm_encoder *encoder)
2677 {
2678 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2679 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2680 radeon_atom_backlight_exit(radeon_encoder);
2681 kfree(radeon_encoder->enc_priv);
2682 drm_encoder_cleanup(encoder);
2683 kfree(radeon_encoder);
2684 }
2685
2686 static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
2687 .destroy = radeon_enc_destroy,
2688 };
2689
2690 static struct radeon_encoder_atom_dac *
radeon_atombios_set_dac_info(struct radeon_encoder * radeon_encoder)2691 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
2692 {
2693 struct drm_device *dev = radeon_encoder->base.dev;
2694 struct radeon_device *rdev = dev->dev_private;
2695 struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
2696
2697 if (!dac)
2698 return NULL;
2699
2700 dac->tv_std = radeon_atombios_get_tv_info(rdev);
2701 return dac;
2702 }
2703
2704 static struct radeon_encoder_atom_dig *
radeon_atombios_set_dig_info(struct radeon_encoder * radeon_encoder)2705 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
2706 {
2707 int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
2708 struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
2709
2710 if (!dig)
2711 return NULL;
2712
2713 /* coherent mode by default */
2714 dig->coherent_mode = true;
2715 dig->dig_encoder = -1;
2716
2717 if (encoder_enum == 2)
2718 dig->linkb = true;
2719 else
2720 dig->linkb = false;
2721
2722 return dig;
2723 }
2724
2725 void
radeon_add_atom_encoder(struct drm_device * dev,uint32_t encoder_enum,uint32_t supported_device,u16 caps)2726 radeon_add_atom_encoder(struct drm_device *dev,
2727 uint32_t encoder_enum,
2728 uint32_t supported_device,
2729 u16 caps)
2730 {
2731 struct radeon_device *rdev = dev->dev_private;
2732 struct drm_encoder *encoder;
2733 struct radeon_encoder *radeon_encoder;
2734
2735 /* see if we already added it */
2736 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2737 radeon_encoder = to_radeon_encoder(encoder);
2738 if (radeon_encoder->encoder_enum == encoder_enum) {
2739 radeon_encoder->devices |= supported_device;
2740 return;
2741 }
2742
2743 }
2744
2745 /* add a new one */
2746 radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
2747 if (!radeon_encoder)
2748 return;
2749
2750 encoder = &radeon_encoder->base;
2751 switch (rdev->num_crtc) {
2752 case 1:
2753 encoder->possible_crtcs = 0x1;
2754 break;
2755 case 2:
2756 default:
2757 encoder->possible_crtcs = 0x3;
2758 break;
2759 case 4:
2760 encoder->possible_crtcs = 0xf;
2761 break;
2762 case 6:
2763 encoder->possible_crtcs = 0x3f;
2764 break;
2765 }
2766
2767 radeon_encoder->enc_priv = NULL;
2768
2769 radeon_encoder->encoder_enum = encoder_enum;
2770 radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
2771 radeon_encoder->devices = supported_device;
2772 radeon_encoder->rmx_type = RMX_OFF;
2773 radeon_encoder->underscan_type = UNDERSCAN_OFF;
2774 radeon_encoder->is_ext_encoder = false;
2775 radeon_encoder->caps = caps;
2776
2777 switch (radeon_encoder->encoder_id) {
2778 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2779 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2780 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2781 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2782 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2783 radeon_encoder->rmx_type = RMX_FULL;
2784 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2785 DRM_MODE_ENCODER_LVDS, NULL);
2786 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2787 } else {
2788 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2789 DRM_MODE_ENCODER_TMDS, NULL);
2790 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2791 }
2792 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2793 break;
2794 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2795 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2796 DRM_MODE_ENCODER_DAC, NULL);
2797 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2798 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2799 break;
2800 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2801 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2802 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2803 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2804 DRM_MODE_ENCODER_TVDAC, NULL);
2805 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2806 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2807 break;
2808 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2809 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2810 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2811 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2812 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2813 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2814 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2815 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2816 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2817 radeon_encoder->rmx_type = RMX_FULL;
2818 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2819 DRM_MODE_ENCODER_LVDS, NULL);
2820 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2821 } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
2822 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2823 DRM_MODE_ENCODER_DAC, NULL);
2824 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2825 } else {
2826 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2827 DRM_MODE_ENCODER_TMDS, NULL);
2828 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2829 }
2830 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2831 break;
2832 case ENCODER_OBJECT_ID_SI170B:
2833 case ENCODER_OBJECT_ID_CH7303:
2834 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
2835 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
2836 case ENCODER_OBJECT_ID_TITFP513:
2837 case ENCODER_OBJECT_ID_VT1623:
2838 case ENCODER_OBJECT_ID_HDMI_SI1930:
2839 case ENCODER_OBJECT_ID_TRAVIS:
2840 case ENCODER_OBJECT_ID_NUTMEG:
2841 /* these are handled by the primary encoders */
2842 radeon_encoder->is_ext_encoder = true;
2843 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2844 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2845 DRM_MODE_ENCODER_LVDS, NULL);
2846 else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
2847 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2848 DRM_MODE_ENCODER_DAC, NULL);
2849 else
2850 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2851 DRM_MODE_ENCODER_TMDS, NULL);
2852 drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs);
2853 break;
2854 }
2855 }
2856