1 /*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26
27 #include <linux/pci.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/gcd.h>
30
31 #include <asm/div64.h>
32
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/drm_device.h>
35 #include <drm/drm_drv.h>
36 #include <drm/drm_edid.h>
37 #include <drm/drm_fb_helper.h>
38 #include <drm/drm_fourcc.h>
39 #include <drm/drm_gem_framebuffer_helper.h>
40 #include <drm/drm_plane_helper.h>
41 #include <drm/drm_probe_helper.h>
42 #include <drm/drm_vblank.h>
43 #include <drm/radeon_drm.h>
44
45 #include "atom.h"
46 #include "radeon.h"
47
48 u32 radeon_get_vblank_counter_kms(struct drm_crtc *crtc);
49 int radeon_enable_vblank_kms(struct drm_crtc *crtc);
50 void radeon_disable_vblank_kms(struct drm_crtc *crtc);
51
avivo_crtc_load_lut(struct drm_crtc * crtc)52 static void avivo_crtc_load_lut(struct drm_crtc *crtc)
53 {
54 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
55 struct drm_device *dev = crtc->dev;
56 struct radeon_device *rdev = dev->dev_private;
57 u16 *r, *g, *b;
58 int i;
59
60 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
61 WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
62
63 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
64 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
65 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
66
67 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
68 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
69 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
70
71 WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id);
72 WREG32(AVIVO_DC_LUT_RW_MODE, 0);
73 WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);
74
75 WREG8(AVIVO_DC_LUT_RW_INDEX, 0);
76 r = crtc->gamma_store;
77 g = r + crtc->gamma_size;
78 b = g + crtc->gamma_size;
79 for (i = 0; i < 256; i++) {
80 WREG32(AVIVO_DC_LUT_30_COLOR,
81 ((*r++ & 0xffc0) << 14) |
82 ((*g++ & 0xffc0) << 4) |
83 (*b++ >> 6));
84 }
85
86 /* Only change bit 0 of LUT_SEL, other bits are set elsewhere */
87 WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id, ~1);
88 }
89
dce4_crtc_load_lut(struct drm_crtc * crtc)90 static void dce4_crtc_load_lut(struct drm_crtc *crtc)
91 {
92 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
93 struct drm_device *dev = crtc->dev;
94 struct radeon_device *rdev = dev->dev_private;
95 u16 *r, *g, *b;
96 int i;
97
98 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
99 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
100
101 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
102 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
103 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
104
105 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
106 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
107 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
108
109 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
110 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
111
112 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
113 r = crtc->gamma_store;
114 g = r + crtc->gamma_size;
115 b = g + crtc->gamma_size;
116 for (i = 0; i < 256; i++) {
117 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
118 ((*r++ & 0xffc0) << 14) |
119 ((*g++ & 0xffc0) << 4) |
120 (*b++ >> 6));
121 }
122 }
123
dce5_crtc_load_lut(struct drm_crtc * crtc)124 static void dce5_crtc_load_lut(struct drm_crtc *crtc)
125 {
126 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
127 struct drm_device *dev = crtc->dev;
128 struct radeon_device *rdev = dev->dev_private;
129 u16 *r, *g, *b;
130 int i;
131
132 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
133
134 msleep(10);
135
136 WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
137 (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) |
138 NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS)));
139 WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset,
140 NI_GRPH_PRESCALE_BYPASS);
141 WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset,
142 NI_OVL_PRESCALE_BYPASS);
143 WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset,
144 (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) |
145 NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT)));
146
147 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
148
149 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
150 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
151 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
152
153 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
154 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
155 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
156
157 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
158 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
159
160 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
161 r = crtc->gamma_store;
162 g = r + crtc->gamma_size;
163 b = g + crtc->gamma_size;
164 for (i = 0; i < 256; i++) {
165 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
166 ((*r++ & 0xffc0) << 14) |
167 ((*g++ & 0xffc0) << 4) |
168 (*b++ >> 6));
169 }
170
171 WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset,
172 (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
173 NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
174 NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
175 NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS)));
176 WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset,
177 (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) |
178 NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS)));
179 WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset,
180 (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) |
181 NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS)));
182 WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
183 (NI_OUTPUT_CSC_GRPH_MODE(radeon_crtc->output_csc) |
184 NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS)));
185 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
186 WREG32(0x6940 + radeon_crtc->crtc_offset, 0);
187 if (ASIC_IS_DCE8(rdev)) {
188 /* XXX this only needs to be programmed once per crtc at startup,
189 * not sure where the best place for it is
190 */
191 WREG32(CIK_ALPHA_CONTROL + radeon_crtc->crtc_offset,
192 CIK_CURSOR_ALPHA_BLND_ENA);
193 }
194 }
195
legacy_crtc_load_lut(struct drm_crtc * crtc)196 static void legacy_crtc_load_lut(struct drm_crtc *crtc)
197 {
198 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
199 struct drm_device *dev = crtc->dev;
200 struct radeon_device *rdev = dev->dev_private;
201 u16 *r, *g, *b;
202 int i;
203 uint32_t dac2_cntl;
204
205 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
206 if (radeon_crtc->crtc_id == 0)
207 dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL;
208 else
209 dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL;
210 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
211
212 WREG8(RADEON_PALETTE_INDEX, 0);
213 r = crtc->gamma_store;
214 g = r + crtc->gamma_size;
215 b = g + crtc->gamma_size;
216 for (i = 0; i < 256; i++) {
217 WREG32(RADEON_PALETTE_30_DATA,
218 ((*r++ & 0xffc0) << 14) |
219 ((*g++ & 0xffc0) << 4) |
220 (*b++ >> 6));
221 }
222 }
223
radeon_crtc_load_lut(struct drm_crtc * crtc)224 void radeon_crtc_load_lut(struct drm_crtc *crtc)
225 {
226 struct drm_device *dev = crtc->dev;
227 struct radeon_device *rdev = dev->dev_private;
228
229 if (!crtc->enabled)
230 return;
231
232 if (ASIC_IS_DCE5(rdev))
233 dce5_crtc_load_lut(crtc);
234 else if (ASIC_IS_DCE4(rdev))
235 dce4_crtc_load_lut(crtc);
236 else if (ASIC_IS_AVIVO(rdev))
237 avivo_crtc_load_lut(crtc);
238 else
239 legacy_crtc_load_lut(crtc);
240 }
241
radeon_crtc_gamma_set(struct drm_crtc * crtc,u16 * red,u16 * green,u16 * blue,uint32_t size,struct drm_modeset_acquire_ctx * ctx)242 static int radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
243 u16 *blue, uint32_t size,
244 struct drm_modeset_acquire_ctx *ctx)
245 {
246 radeon_crtc_load_lut(crtc);
247
248 return 0;
249 }
250
radeon_crtc_destroy(struct drm_crtc * crtc)251 static void radeon_crtc_destroy(struct drm_crtc *crtc)
252 {
253 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
254
255 drm_crtc_cleanup(crtc);
256 destroy_workqueue(radeon_crtc->flip_queue);
257 kfree(radeon_crtc);
258 }
259
260 /**
261 * radeon_unpin_work_func - unpin old buffer object
262 *
263 * @__work - kernel work item
264 *
265 * Unpin the old frame buffer object outside of the interrupt handler
266 */
radeon_unpin_work_func(struct work_struct * __work)267 static void radeon_unpin_work_func(struct work_struct *__work)
268 {
269 struct radeon_flip_work *work =
270 container_of(__work, struct radeon_flip_work, unpin_work);
271 int r;
272
273 /* unpin of the old buffer */
274 r = radeon_bo_reserve(work->old_rbo, false);
275 if (likely(r == 0)) {
276 r = radeon_bo_unpin(work->old_rbo);
277 if (unlikely(r != 0)) {
278 DRM_ERROR("failed to unpin buffer after flip\n");
279 }
280 radeon_bo_unreserve(work->old_rbo);
281 } else
282 DRM_ERROR("failed to reserve buffer after flip\n");
283
284 drm_gem_object_put(&work->old_rbo->tbo.base);
285 kfree(work);
286 }
287
radeon_crtc_handle_vblank(struct radeon_device * rdev,int crtc_id)288 void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id)
289 {
290 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
291 unsigned long flags;
292 u32 update_pending;
293 int vpos, hpos;
294
295 /* can happen during initialization */
296 if (radeon_crtc == NULL)
297 return;
298
299 /* Skip the pageflip completion check below (based on polling) on
300 * asics which reliably support hw pageflip completion irqs. pflip
301 * irqs are a reliable and race-free method of handling pageflip
302 * completion detection. A use_pflipirq module parameter < 2 allows
303 * to override this in case of asics with faulty pflip irqs.
304 * A module parameter of 0 would only use this polling based path,
305 * a parameter of 1 would use pflip irq only as a backup to this
306 * path, as in Linux 3.16.
307 */
308 if ((radeon_use_pflipirq == 2) && ASIC_IS_DCE4(rdev))
309 return;
310
311 spin_lock_irqsave(&rdev->ddev->event_lock, flags);
312 if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) {
313 DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != "
314 "RADEON_FLIP_SUBMITTED(%d)\n",
315 radeon_crtc->flip_status,
316 RADEON_FLIP_SUBMITTED);
317 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
318 return;
319 }
320
321 update_pending = radeon_page_flip_pending(rdev, crtc_id);
322
323 /* Has the pageflip already completed in crtc, or is it certain
324 * to complete in this vblank? GET_DISTANCE_TO_VBLANKSTART provides
325 * distance to start of "fudged earlier" vblank in vpos, distance to
326 * start of real vblank in hpos. vpos >= 0 && hpos < 0 means we are in
327 * the last few scanlines before start of real vblank, where the vblank
328 * irq can fire, so we have sampled update_pending a bit too early and
329 * know the flip will complete at leading edge of the upcoming real
330 * vblank. On pre-AVIVO hardware, flips also complete inside the real
331 * vblank, not only at leading edge, so if update_pending for hpos >= 0
332 * == inside real vblank, the flip will complete almost immediately.
333 * Note that this method of completion handling is still not 100% race
334 * free, as we could execute before the radeon_flip_work_func managed
335 * to run and set the RADEON_FLIP_SUBMITTED status, thereby we no-op,
336 * but the flip still gets programmed into hw and completed during
337 * vblank, leading to a delayed emission of the flip completion event.
338 * This applies at least to pre-AVIVO hardware, where flips are always
339 * completing inside vblank, not only at leading edge of vblank.
340 */
341 if (update_pending &&
342 (DRM_SCANOUTPOS_VALID &
343 radeon_get_crtc_scanoutpos(rdev->ddev, crtc_id,
344 GET_DISTANCE_TO_VBLANKSTART,
345 &vpos, &hpos, NULL, NULL,
346 &rdev->mode_info.crtcs[crtc_id]->base.hwmode)) &&
347 ((vpos >= 0 && hpos < 0) || (hpos >= 0 && !ASIC_IS_AVIVO(rdev)))) {
348 /* crtc didn't flip in this target vblank interval,
349 * but flip is pending in crtc. Based on the current
350 * scanout position we know that the current frame is
351 * (nearly) complete and the flip will (likely)
352 * complete before the start of the next frame.
353 */
354 update_pending = 0;
355 }
356 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
357 if (!update_pending)
358 radeon_crtc_handle_flip(rdev, crtc_id);
359 }
360
361 /**
362 * radeon_crtc_handle_flip - page flip completed
363 *
364 * @rdev: radeon device pointer
365 * @crtc_id: crtc number this event is for
366 *
367 * Called when we are sure that a page flip for this crtc is completed.
368 */
radeon_crtc_handle_flip(struct radeon_device * rdev,int crtc_id)369 void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id)
370 {
371 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
372 struct radeon_flip_work *work;
373 unsigned long flags;
374
375 /* this can happen at init */
376 if (radeon_crtc == NULL)
377 return;
378
379 spin_lock_irqsave(&rdev->ddev->event_lock, flags);
380 work = radeon_crtc->flip_work;
381 if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) {
382 DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != "
383 "RADEON_FLIP_SUBMITTED(%d)\n",
384 radeon_crtc->flip_status,
385 RADEON_FLIP_SUBMITTED);
386 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
387 return;
388 }
389
390 /* Pageflip completed. Clean up. */
391 radeon_crtc->flip_status = RADEON_FLIP_NONE;
392 radeon_crtc->flip_work = NULL;
393
394 /* wakeup userspace */
395 if (work->event)
396 drm_crtc_send_vblank_event(&radeon_crtc->base, work->event);
397
398 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
399
400 drm_crtc_vblank_put(&radeon_crtc->base);
401 radeon_irq_kms_pflip_irq_put(rdev, work->crtc_id);
402 queue_work(radeon_crtc->flip_queue, &work->unpin_work);
403 }
404
405 /**
406 * radeon_flip_work_func - page flip framebuffer
407 *
408 * @work - kernel work item
409 *
410 * Wait for the buffer object to become idle and do the actual page flip
411 */
radeon_flip_work_func(struct work_struct * __work)412 static void radeon_flip_work_func(struct work_struct *__work)
413 {
414 struct radeon_flip_work *work =
415 container_of(__work, struct radeon_flip_work, flip_work);
416 struct radeon_device *rdev = work->rdev;
417 struct drm_device *dev = rdev->ddev;
418 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[work->crtc_id];
419
420 struct drm_crtc *crtc = &radeon_crtc->base;
421 unsigned long flags;
422 int r;
423 int vpos, hpos;
424
425 down_read(&rdev->exclusive_lock);
426 if (work->fence) {
427 struct radeon_fence *fence;
428
429 fence = to_radeon_fence(work->fence);
430 if (fence && fence->rdev == rdev) {
431 r = radeon_fence_wait(fence, false);
432 if (r == -EDEADLK) {
433 up_read(&rdev->exclusive_lock);
434 do {
435 r = radeon_gpu_reset(rdev);
436 } while (r == -EAGAIN);
437 down_read(&rdev->exclusive_lock);
438 }
439 } else
440 r = dma_fence_wait(work->fence, false);
441
442 if (r)
443 DRM_ERROR("failed to wait on page flip fence (%d)!\n", r);
444
445 /* We continue with the page flip even if we failed to wait on
446 * the fence, otherwise the DRM core and userspace will be
447 * confused about which BO the CRTC is scanning out
448 */
449
450 dma_fence_put(work->fence);
451 work->fence = NULL;
452 }
453
454 /* Wait until we're out of the vertical blank period before the one
455 * targeted by the flip. Always wait on pre DCE4 to avoid races with
456 * flip completion handling from vblank irq, as these old asics don't
457 * have reliable pageflip completion interrupts.
458 */
459 while (radeon_crtc->enabled &&
460 (radeon_get_crtc_scanoutpos(dev, work->crtc_id, 0,
461 &vpos, &hpos, NULL, NULL,
462 &crtc->hwmode)
463 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
464 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
465 (!ASIC_IS_AVIVO(rdev) ||
466 ((int) (work->target_vblank -
467 crtc->funcs->get_vblank_counter(crtc)) > 0)))
468 usleep_range(1000, 2000);
469
470 /* We borrow the event spin lock for protecting flip_status */
471 spin_lock_irqsave(&crtc->dev->event_lock, flags);
472
473 /* set the proper interrupt */
474 radeon_irq_kms_pflip_irq_get(rdev, radeon_crtc->crtc_id);
475
476 /* do the flip (mmio) */
477 radeon_page_flip(rdev, radeon_crtc->crtc_id, work->base, work->async);
478
479 radeon_crtc->flip_status = RADEON_FLIP_SUBMITTED;
480 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
481 up_read(&rdev->exclusive_lock);
482 }
483
radeon_crtc_page_flip_target(struct drm_crtc * crtc,struct drm_framebuffer * fb,struct drm_pending_vblank_event * event,uint32_t page_flip_flags,uint32_t target,struct drm_modeset_acquire_ctx * ctx)484 static int radeon_crtc_page_flip_target(struct drm_crtc *crtc,
485 struct drm_framebuffer *fb,
486 struct drm_pending_vblank_event *event,
487 uint32_t page_flip_flags,
488 uint32_t target,
489 struct drm_modeset_acquire_ctx *ctx)
490 {
491 struct drm_device *dev = crtc->dev;
492 struct radeon_device *rdev = dev->dev_private;
493 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
494 struct drm_gem_object *obj;
495 struct radeon_flip_work *work;
496 struct radeon_bo *new_rbo;
497 uint32_t tiling_flags, pitch_pixels;
498 uint64_t base;
499 unsigned long flags;
500 int r;
501
502 work = kzalloc(sizeof *work, GFP_KERNEL);
503 if (work == NULL)
504 return -ENOMEM;
505
506 INIT_WORK(&work->flip_work, radeon_flip_work_func);
507 INIT_WORK(&work->unpin_work, radeon_unpin_work_func);
508
509 work->rdev = rdev;
510 work->crtc_id = radeon_crtc->crtc_id;
511 work->event = event;
512 work->async = (page_flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0;
513
514 /* schedule unpin of the old buffer */
515 obj = crtc->primary->fb->obj[0];
516
517 /* take a reference to the old object */
518 drm_gem_object_get(obj);
519 work->old_rbo = gem_to_radeon_bo(obj);
520
521 obj = fb->obj[0];
522 new_rbo = gem_to_radeon_bo(obj);
523
524 /* pin the new buffer */
525 DRM_DEBUG_DRIVER("flip-ioctl() cur_rbo = %p, new_rbo = %p\n",
526 work->old_rbo, new_rbo);
527
528 r = radeon_bo_reserve(new_rbo, false);
529 if (unlikely(r != 0)) {
530 DRM_ERROR("failed to reserve new rbo buffer before flip\n");
531 goto cleanup;
532 }
533 /* Only 27 bit offset for legacy CRTC */
534 r = radeon_bo_pin_restricted(new_rbo, RADEON_GEM_DOMAIN_VRAM,
535 ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, &base);
536 if (unlikely(r != 0)) {
537 radeon_bo_unreserve(new_rbo);
538 r = -EINVAL;
539 DRM_ERROR("failed to pin new rbo buffer before flip\n");
540 goto cleanup;
541 }
542 work->fence = dma_fence_get(dma_resv_get_excl(new_rbo->tbo.base.resv));
543 radeon_bo_get_tiling_flags(new_rbo, &tiling_flags, NULL);
544 radeon_bo_unreserve(new_rbo);
545
546 if (!ASIC_IS_AVIVO(rdev)) {
547 /* crtc offset is from display base addr not FB location */
548 base -= radeon_crtc->legacy_display_base_addr;
549 pitch_pixels = fb->pitches[0] / fb->format->cpp[0];
550
551 if (tiling_flags & RADEON_TILING_MACRO) {
552 if (ASIC_IS_R300(rdev)) {
553 base &= ~0x7ff;
554 } else {
555 int byteshift = fb->format->cpp[0] * 8 >> 4;
556 int tile_addr = (((crtc->y >> 3) * pitch_pixels + crtc->x) >> (8 - byteshift)) << 11;
557 base += tile_addr + ((crtc->x << byteshift) % 256) + ((crtc->y % 8) << 8);
558 }
559 } else {
560 int offset = crtc->y * pitch_pixels + crtc->x;
561 switch (fb->format->cpp[0] * 8) {
562 case 8:
563 default:
564 offset *= 1;
565 break;
566 case 15:
567 case 16:
568 offset *= 2;
569 break;
570 case 24:
571 offset *= 3;
572 break;
573 case 32:
574 offset *= 4;
575 break;
576 }
577 base += offset;
578 }
579 base &= ~7;
580 }
581 work->base = base;
582 work->target_vblank = target - (uint32_t)drm_crtc_vblank_count(crtc) +
583 crtc->funcs->get_vblank_counter(crtc);
584
585 /* We borrow the event spin lock for protecting flip_work */
586 spin_lock_irqsave(&crtc->dev->event_lock, flags);
587
588 if (radeon_crtc->flip_status != RADEON_FLIP_NONE) {
589 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
590 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
591 r = -EBUSY;
592 goto pflip_cleanup;
593 }
594 radeon_crtc->flip_status = RADEON_FLIP_PENDING;
595 radeon_crtc->flip_work = work;
596
597 /* update crtc fb */
598 crtc->primary->fb = fb;
599
600 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
601
602 queue_work(radeon_crtc->flip_queue, &work->flip_work);
603 return 0;
604
605 pflip_cleanup:
606 if (unlikely(radeon_bo_reserve(new_rbo, false) != 0)) {
607 DRM_ERROR("failed to reserve new rbo in error path\n");
608 goto cleanup;
609 }
610 if (unlikely(radeon_bo_unpin(new_rbo) != 0)) {
611 DRM_ERROR("failed to unpin new rbo in error path\n");
612 }
613 radeon_bo_unreserve(new_rbo);
614
615 cleanup:
616 drm_gem_object_put(&work->old_rbo->tbo.base);
617 dma_fence_put(work->fence);
618 kfree(work);
619 return r;
620 }
621
622 static int
radeon_crtc_set_config(struct drm_mode_set * set,struct drm_modeset_acquire_ctx * ctx)623 radeon_crtc_set_config(struct drm_mode_set *set,
624 struct drm_modeset_acquire_ctx *ctx)
625 {
626 struct drm_device *dev;
627 struct radeon_device *rdev;
628 struct drm_crtc *crtc;
629 bool active = false;
630 int ret;
631
632 if (!set || !set->crtc)
633 return -EINVAL;
634
635 dev = set->crtc->dev;
636
637 ret = pm_runtime_get_sync(dev->dev);
638 if (ret < 0) {
639 pm_runtime_put_autosuspend(dev->dev);
640 return ret;
641 }
642
643 ret = drm_crtc_helper_set_config(set, ctx);
644
645 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
646 if (crtc->enabled)
647 active = true;
648
649 pm_runtime_mark_last_busy(dev->dev);
650
651 rdev = dev->dev_private;
652 /* if we have active crtcs and we don't have a power ref,
653 take the current one */
654 if (active && !rdev->have_disp_power_ref) {
655 rdev->have_disp_power_ref = true;
656 return ret;
657 }
658 /* if we have no active crtcs, then drop the power ref
659 we got before */
660 if (!active && rdev->have_disp_power_ref) {
661 pm_runtime_put_autosuspend(dev->dev);
662 rdev->have_disp_power_ref = false;
663 }
664
665 /* drop the power reference we got coming in here */
666 pm_runtime_put_autosuspend(dev->dev);
667 return ret;
668 }
669
670 static const struct drm_crtc_funcs radeon_crtc_funcs = {
671 .cursor_set2 = radeon_crtc_cursor_set2,
672 .cursor_move = radeon_crtc_cursor_move,
673 .gamma_set = radeon_crtc_gamma_set,
674 .set_config = radeon_crtc_set_config,
675 .destroy = radeon_crtc_destroy,
676 .page_flip_target = radeon_crtc_page_flip_target,
677 .get_vblank_counter = radeon_get_vblank_counter_kms,
678 .enable_vblank = radeon_enable_vblank_kms,
679 .disable_vblank = radeon_disable_vblank_kms,
680 .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
681 };
682
radeon_crtc_init(struct drm_device * dev,int index)683 static void radeon_crtc_init(struct drm_device *dev, int index)
684 {
685 struct radeon_device *rdev = dev->dev_private;
686 struct radeon_crtc *radeon_crtc;
687
688 radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
689 if (radeon_crtc == NULL)
690 return;
691
692 radeon_crtc->flip_queue = alloc_workqueue("radeon-crtc", WQ_HIGHPRI, 0);
693 if (!radeon_crtc->flip_queue) {
694 kfree(radeon_crtc);
695 return;
696 }
697
698 drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs);
699
700 drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256);
701 radeon_crtc->crtc_id = index;
702 rdev->mode_info.crtcs[index] = radeon_crtc;
703
704 if (rdev->family >= CHIP_BONAIRE) {
705 radeon_crtc->max_cursor_width = CIK_CURSOR_WIDTH;
706 radeon_crtc->max_cursor_height = CIK_CURSOR_HEIGHT;
707 } else {
708 radeon_crtc->max_cursor_width = CURSOR_WIDTH;
709 radeon_crtc->max_cursor_height = CURSOR_HEIGHT;
710 }
711 dev->mode_config.cursor_width = radeon_crtc->max_cursor_width;
712 dev->mode_config.cursor_height = radeon_crtc->max_cursor_height;
713
714 #if 0
715 radeon_crtc->mode_set.crtc = &radeon_crtc->base;
716 radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1);
717 radeon_crtc->mode_set.num_connectors = 0;
718 #endif
719
720 if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom))
721 radeon_atombios_init_crtc(dev, radeon_crtc);
722 else
723 radeon_legacy_init_crtc(dev, radeon_crtc);
724 }
725
726 static const char *encoder_names[38] = {
727 "NONE",
728 "INTERNAL_LVDS",
729 "INTERNAL_TMDS1",
730 "INTERNAL_TMDS2",
731 "INTERNAL_DAC1",
732 "INTERNAL_DAC2",
733 "INTERNAL_SDVOA",
734 "INTERNAL_SDVOB",
735 "SI170B",
736 "CH7303",
737 "CH7301",
738 "INTERNAL_DVO1",
739 "EXTERNAL_SDVOA",
740 "EXTERNAL_SDVOB",
741 "TITFP513",
742 "INTERNAL_LVTM1",
743 "VT1623",
744 "HDMI_SI1930",
745 "HDMI_INTERNAL",
746 "INTERNAL_KLDSCP_TMDS1",
747 "INTERNAL_KLDSCP_DVO1",
748 "INTERNAL_KLDSCP_DAC1",
749 "INTERNAL_KLDSCP_DAC2",
750 "SI178",
751 "MVPU_FPGA",
752 "INTERNAL_DDI",
753 "VT1625",
754 "HDMI_SI1932",
755 "DP_AN9801",
756 "DP_DP501",
757 "INTERNAL_UNIPHY",
758 "INTERNAL_KLDSCP_LVTMA",
759 "INTERNAL_UNIPHY1",
760 "INTERNAL_UNIPHY2",
761 "NUTMEG",
762 "TRAVIS",
763 "INTERNAL_VCE",
764 "INTERNAL_UNIPHY3",
765 };
766
767 static const char *hpd_names[6] = {
768 "HPD1",
769 "HPD2",
770 "HPD3",
771 "HPD4",
772 "HPD5",
773 "HPD6",
774 };
775
radeon_print_display_setup(struct drm_device * dev)776 static void radeon_print_display_setup(struct drm_device *dev)
777 {
778 struct drm_connector *connector;
779 struct radeon_connector *radeon_connector;
780 struct drm_encoder *encoder;
781 struct radeon_encoder *radeon_encoder;
782 uint32_t devices;
783 int i = 0;
784
785 DRM_INFO("Radeon Display Connectors\n");
786 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
787 radeon_connector = to_radeon_connector(connector);
788 DRM_INFO("Connector %d:\n", i);
789 DRM_INFO(" %s\n", connector->name);
790 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
791 DRM_INFO(" %s\n", hpd_names[radeon_connector->hpd.hpd]);
792 if (radeon_connector->ddc_bus) {
793 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
794 radeon_connector->ddc_bus->rec.mask_clk_reg,
795 radeon_connector->ddc_bus->rec.mask_data_reg,
796 radeon_connector->ddc_bus->rec.a_clk_reg,
797 radeon_connector->ddc_bus->rec.a_data_reg,
798 radeon_connector->ddc_bus->rec.en_clk_reg,
799 radeon_connector->ddc_bus->rec.en_data_reg,
800 radeon_connector->ddc_bus->rec.y_clk_reg,
801 radeon_connector->ddc_bus->rec.y_data_reg);
802 if (radeon_connector->router.ddc_valid)
803 DRM_INFO(" DDC Router 0x%x/0x%x\n",
804 radeon_connector->router.ddc_mux_control_pin,
805 radeon_connector->router.ddc_mux_state);
806 if (radeon_connector->router.cd_valid)
807 DRM_INFO(" Clock/Data Router 0x%x/0x%x\n",
808 radeon_connector->router.cd_mux_control_pin,
809 radeon_connector->router.cd_mux_state);
810 } else {
811 if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
812 connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
813 connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
814 connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
815 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
816 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
817 DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
818 }
819 DRM_INFO(" Encoders:\n");
820 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
821 radeon_encoder = to_radeon_encoder(encoder);
822 devices = radeon_encoder->devices & radeon_connector->devices;
823 if (devices) {
824 if (devices & ATOM_DEVICE_CRT1_SUPPORT)
825 DRM_INFO(" CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]);
826 if (devices & ATOM_DEVICE_CRT2_SUPPORT)
827 DRM_INFO(" CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]);
828 if (devices & ATOM_DEVICE_LCD1_SUPPORT)
829 DRM_INFO(" LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]);
830 if (devices & ATOM_DEVICE_DFP1_SUPPORT)
831 DRM_INFO(" DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]);
832 if (devices & ATOM_DEVICE_DFP2_SUPPORT)
833 DRM_INFO(" DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]);
834 if (devices & ATOM_DEVICE_DFP3_SUPPORT)
835 DRM_INFO(" DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]);
836 if (devices & ATOM_DEVICE_DFP4_SUPPORT)
837 DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]);
838 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
839 DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]);
840 if (devices & ATOM_DEVICE_DFP6_SUPPORT)
841 DRM_INFO(" DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]);
842 if (devices & ATOM_DEVICE_TV1_SUPPORT)
843 DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]);
844 if (devices & ATOM_DEVICE_CV_SUPPORT)
845 DRM_INFO(" CV: %s\n", encoder_names[radeon_encoder->encoder_id]);
846 }
847 }
848 i++;
849 }
850 }
851
radeon_setup_enc_conn(struct drm_device * dev)852 static bool radeon_setup_enc_conn(struct drm_device *dev)
853 {
854 struct radeon_device *rdev = dev->dev_private;
855 bool ret = false;
856
857 if (rdev->bios) {
858 if (rdev->is_atom_bios) {
859 ret = radeon_get_atom_connector_info_from_supported_devices_table(dev);
860 if (!ret)
861 ret = radeon_get_atom_connector_info_from_object_table(dev);
862 } else {
863 ret = radeon_get_legacy_connector_info_from_bios(dev);
864 if (!ret)
865 ret = radeon_get_legacy_connector_info_from_table(dev);
866 }
867 } else {
868 if (!ASIC_IS_AVIVO(rdev))
869 ret = radeon_get_legacy_connector_info_from_table(dev);
870 }
871 if (ret) {
872 radeon_setup_encoder_clones(dev);
873 radeon_print_display_setup(dev);
874 }
875
876 return ret;
877 }
878
879 /* avivo */
880
881 /**
882 * avivo_reduce_ratio - fractional number reduction
883 *
884 * @nom: nominator
885 * @den: denominator
886 * @nom_min: minimum value for nominator
887 * @den_min: minimum value for denominator
888 *
889 * Find the greatest common divisor and apply it on both nominator and
890 * denominator, but make nominator and denominator are at least as large
891 * as their minimum values.
892 */
avivo_reduce_ratio(unsigned * nom,unsigned * den,unsigned nom_min,unsigned den_min)893 static void avivo_reduce_ratio(unsigned *nom, unsigned *den,
894 unsigned nom_min, unsigned den_min)
895 {
896 unsigned tmp;
897
898 /* reduce the numbers to a simpler ratio */
899 tmp = gcd(*nom, *den);
900 *nom /= tmp;
901 *den /= tmp;
902
903 /* make sure nominator is large enough */
904 if (*nom < nom_min) {
905 tmp = DIV_ROUND_UP(nom_min, *nom);
906 *nom *= tmp;
907 *den *= tmp;
908 }
909
910 /* make sure the denominator is large enough */
911 if (*den < den_min) {
912 tmp = DIV_ROUND_UP(den_min, *den);
913 *nom *= tmp;
914 *den *= tmp;
915 }
916 }
917
918 /**
919 * avivo_get_fb_ref_div - feedback and ref divider calculation
920 *
921 * @nom: nominator
922 * @den: denominator
923 * @post_div: post divider
924 * @fb_div_max: feedback divider maximum
925 * @ref_div_max: reference divider maximum
926 * @fb_div: resulting feedback divider
927 * @ref_div: resulting reference divider
928 *
929 * Calculate feedback and reference divider for a given post divider. Makes
930 * sure we stay within the limits.
931 */
avivo_get_fb_ref_div(unsigned nom,unsigned den,unsigned post_div,unsigned fb_div_max,unsigned ref_div_max,unsigned * fb_div,unsigned * ref_div)932 static void avivo_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div,
933 unsigned fb_div_max, unsigned ref_div_max,
934 unsigned *fb_div, unsigned *ref_div)
935 {
936 /* limit reference * post divider to a maximum */
937 ref_div_max = max(min(100 / post_div, ref_div_max), 1u);
938
939 /* get matching reference and feedback divider */
940 *ref_div = min(max(den/post_div, 1u), ref_div_max);
941 *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den);
942
943 /* limit fb divider to its maximum */
944 if (*fb_div > fb_div_max) {
945 *ref_div = (*ref_div * fb_div_max)/(*fb_div);
946 *fb_div = fb_div_max;
947 }
948 }
949
950 /**
951 * radeon_compute_pll_avivo - compute PLL paramaters
952 *
953 * @pll: information about the PLL
954 * @dot_clock_p: resulting pixel clock
955 * fb_div_p: resulting feedback divider
956 * frac_fb_div_p: fractional part of the feedback divider
957 * ref_div_p: resulting reference divider
958 * post_div_p: resulting reference divider
959 *
960 * Try to calculate the PLL parameters to generate the given frequency:
961 * dot_clock = (ref_freq * feedback_div) / (ref_div * post_div)
962 */
radeon_compute_pll_avivo(struct radeon_pll * pll,u32 freq,u32 * dot_clock_p,u32 * fb_div_p,u32 * frac_fb_div_p,u32 * ref_div_p,u32 * post_div_p)963 void radeon_compute_pll_avivo(struct radeon_pll *pll,
964 u32 freq,
965 u32 *dot_clock_p,
966 u32 *fb_div_p,
967 u32 *frac_fb_div_p,
968 u32 *ref_div_p,
969 u32 *post_div_p)
970 {
971 unsigned target_clock = pll->flags & RADEON_PLL_USE_FRAC_FB_DIV ?
972 freq : freq / 10;
973
974 unsigned fb_div_min, fb_div_max, fb_div;
975 unsigned post_div_min, post_div_max, post_div;
976 unsigned ref_div_min, ref_div_max, ref_div;
977 unsigned post_div_best, diff_best;
978 unsigned nom, den;
979
980 /* determine allowed feedback divider range */
981 fb_div_min = pll->min_feedback_div;
982 fb_div_max = pll->max_feedback_div;
983
984 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
985 fb_div_min *= 10;
986 fb_div_max *= 10;
987 }
988
989 /* determine allowed ref divider range */
990 if (pll->flags & RADEON_PLL_USE_REF_DIV)
991 ref_div_min = pll->reference_div;
992 else
993 ref_div_min = pll->min_ref_div;
994
995 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV &&
996 pll->flags & RADEON_PLL_USE_REF_DIV)
997 ref_div_max = pll->reference_div;
998 else if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP)
999 /* fix for problems on RS880 */
1000 ref_div_max = min(pll->max_ref_div, 7u);
1001 else
1002 ref_div_max = pll->max_ref_div;
1003
1004 /* determine allowed post divider range */
1005 if (pll->flags & RADEON_PLL_USE_POST_DIV) {
1006 post_div_min = pll->post_div;
1007 post_div_max = pll->post_div;
1008 } else {
1009 unsigned vco_min, vco_max;
1010
1011 if (pll->flags & RADEON_PLL_IS_LCD) {
1012 vco_min = pll->lcd_pll_out_min;
1013 vco_max = pll->lcd_pll_out_max;
1014 } else {
1015 vco_min = pll->pll_out_min;
1016 vco_max = pll->pll_out_max;
1017 }
1018
1019 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
1020 vco_min *= 10;
1021 vco_max *= 10;
1022 }
1023
1024 post_div_min = vco_min / target_clock;
1025 if ((target_clock * post_div_min) < vco_min)
1026 ++post_div_min;
1027 if (post_div_min < pll->min_post_div)
1028 post_div_min = pll->min_post_div;
1029
1030 post_div_max = vco_max / target_clock;
1031 if ((target_clock * post_div_max) > vco_max)
1032 --post_div_max;
1033 if (post_div_max > pll->max_post_div)
1034 post_div_max = pll->max_post_div;
1035 }
1036
1037 /* represent the searched ratio as fractional number */
1038 nom = target_clock;
1039 den = pll->reference_freq;
1040
1041 /* reduce the numbers to a simpler ratio */
1042 avivo_reduce_ratio(&nom, &den, fb_div_min, post_div_min);
1043
1044 /* now search for a post divider */
1045 if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP)
1046 post_div_best = post_div_min;
1047 else
1048 post_div_best = post_div_max;
1049 diff_best = ~0;
1050
1051 for (post_div = post_div_min; post_div <= post_div_max; ++post_div) {
1052 unsigned diff;
1053 avivo_get_fb_ref_div(nom, den, post_div, fb_div_max,
1054 ref_div_max, &fb_div, &ref_div);
1055 diff = abs(target_clock - (pll->reference_freq * fb_div) /
1056 (ref_div * post_div));
1057
1058 if (diff < diff_best || (diff == diff_best &&
1059 !(pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP))) {
1060
1061 post_div_best = post_div;
1062 diff_best = diff;
1063 }
1064 }
1065 post_div = post_div_best;
1066
1067 /* get the feedback and reference divider for the optimal value */
1068 avivo_get_fb_ref_div(nom, den, post_div, fb_div_max, ref_div_max,
1069 &fb_div, &ref_div);
1070
1071 /* reduce the numbers to a simpler ratio once more */
1072 /* this also makes sure that the reference divider is large enough */
1073 avivo_reduce_ratio(&fb_div, &ref_div, fb_div_min, ref_div_min);
1074
1075 /* avoid high jitter with small fractional dividers */
1076 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV && (fb_div % 10)) {
1077 fb_div_min = max(fb_div_min, (9 - (fb_div % 10)) * 20 + 50);
1078 if (fb_div < fb_div_min) {
1079 unsigned tmp = DIV_ROUND_UP(fb_div_min, fb_div);
1080 fb_div *= tmp;
1081 ref_div *= tmp;
1082 }
1083 }
1084
1085 /* and finally save the result */
1086 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
1087 *fb_div_p = fb_div / 10;
1088 *frac_fb_div_p = fb_div % 10;
1089 } else {
1090 *fb_div_p = fb_div;
1091 *frac_fb_div_p = 0;
1092 }
1093
1094 *dot_clock_p = ((pll->reference_freq * *fb_div_p * 10) +
1095 (pll->reference_freq * *frac_fb_div_p)) /
1096 (ref_div * post_div * 10);
1097 *ref_div_p = ref_div;
1098 *post_div_p = post_div;
1099
1100 DRM_DEBUG_KMS("%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
1101 freq, *dot_clock_p * 10, *fb_div_p, *frac_fb_div_p,
1102 ref_div, post_div);
1103 }
1104
1105 /* pre-avivo */
radeon_div(uint64_t n,uint32_t d)1106 static inline uint32_t radeon_div(uint64_t n, uint32_t d)
1107 {
1108 uint64_t mod;
1109
1110 n += d / 2;
1111
1112 mod = do_div(n, d);
1113 return n;
1114 }
1115
radeon_compute_pll_legacy(struct radeon_pll * pll,uint64_t freq,uint32_t * dot_clock_p,uint32_t * fb_div_p,uint32_t * frac_fb_div_p,uint32_t * ref_div_p,uint32_t * post_div_p)1116 void radeon_compute_pll_legacy(struct radeon_pll *pll,
1117 uint64_t freq,
1118 uint32_t *dot_clock_p,
1119 uint32_t *fb_div_p,
1120 uint32_t *frac_fb_div_p,
1121 uint32_t *ref_div_p,
1122 uint32_t *post_div_p)
1123 {
1124 uint32_t min_ref_div = pll->min_ref_div;
1125 uint32_t max_ref_div = pll->max_ref_div;
1126 uint32_t min_post_div = pll->min_post_div;
1127 uint32_t max_post_div = pll->max_post_div;
1128 uint32_t min_fractional_feed_div = 0;
1129 uint32_t max_fractional_feed_div = 0;
1130 uint32_t best_vco = pll->best_vco;
1131 uint32_t best_post_div = 1;
1132 uint32_t best_ref_div = 1;
1133 uint32_t best_feedback_div = 1;
1134 uint32_t best_frac_feedback_div = 0;
1135 uint32_t best_freq = -1;
1136 uint32_t best_error = 0xffffffff;
1137 uint32_t best_vco_diff = 1;
1138 uint32_t post_div;
1139 u32 pll_out_min, pll_out_max;
1140
1141 DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
1142 freq = freq * 1000;
1143
1144 if (pll->flags & RADEON_PLL_IS_LCD) {
1145 pll_out_min = pll->lcd_pll_out_min;
1146 pll_out_max = pll->lcd_pll_out_max;
1147 } else {
1148 pll_out_min = pll->pll_out_min;
1149 pll_out_max = pll->pll_out_max;
1150 }
1151
1152 if (pll_out_min > 64800)
1153 pll_out_min = 64800;
1154
1155 if (pll->flags & RADEON_PLL_USE_REF_DIV)
1156 min_ref_div = max_ref_div = pll->reference_div;
1157 else {
1158 while (min_ref_div < max_ref_div-1) {
1159 uint32_t mid = (min_ref_div + max_ref_div) / 2;
1160 uint32_t pll_in = pll->reference_freq / mid;
1161 if (pll_in < pll->pll_in_min)
1162 max_ref_div = mid;
1163 else if (pll_in > pll->pll_in_max)
1164 min_ref_div = mid;
1165 else
1166 break;
1167 }
1168 }
1169
1170 if (pll->flags & RADEON_PLL_USE_POST_DIV)
1171 min_post_div = max_post_div = pll->post_div;
1172
1173 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
1174 min_fractional_feed_div = pll->min_frac_feedback_div;
1175 max_fractional_feed_div = pll->max_frac_feedback_div;
1176 }
1177
1178 for (post_div = max_post_div; post_div >= min_post_div; --post_div) {
1179 uint32_t ref_div;
1180
1181 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
1182 continue;
1183
1184 /* legacy radeons only have a few post_divs */
1185 if (pll->flags & RADEON_PLL_LEGACY) {
1186 if ((post_div == 5) ||
1187 (post_div == 7) ||
1188 (post_div == 9) ||
1189 (post_div == 10) ||
1190 (post_div == 11) ||
1191 (post_div == 13) ||
1192 (post_div == 14) ||
1193 (post_div == 15))
1194 continue;
1195 }
1196
1197 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
1198 uint32_t feedback_div, current_freq = 0, error, vco_diff;
1199 uint32_t pll_in = pll->reference_freq / ref_div;
1200 uint32_t min_feed_div = pll->min_feedback_div;
1201 uint32_t max_feed_div = pll->max_feedback_div + 1;
1202
1203 if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max)
1204 continue;
1205
1206 while (min_feed_div < max_feed_div) {
1207 uint32_t vco;
1208 uint32_t min_frac_feed_div = min_fractional_feed_div;
1209 uint32_t max_frac_feed_div = max_fractional_feed_div + 1;
1210 uint32_t frac_feedback_div;
1211 uint64_t tmp;
1212
1213 feedback_div = (min_feed_div + max_feed_div) / 2;
1214
1215 tmp = (uint64_t)pll->reference_freq * feedback_div;
1216 vco = radeon_div(tmp, ref_div);
1217
1218 if (vco < pll_out_min) {
1219 min_feed_div = feedback_div + 1;
1220 continue;
1221 } else if (vco > pll_out_max) {
1222 max_feed_div = feedback_div;
1223 continue;
1224 }
1225
1226 while (min_frac_feed_div < max_frac_feed_div) {
1227 frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2;
1228 tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div;
1229 tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
1230 current_freq = radeon_div(tmp, ref_div * post_div);
1231
1232 if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
1233 if (freq < current_freq)
1234 error = 0xffffffff;
1235 else
1236 error = freq - current_freq;
1237 } else
1238 error = abs(current_freq - freq);
1239 vco_diff = abs(vco - best_vco);
1240
1241 if ((best_vco == 0 && error < best_error) ||
1242 (best_vco != 0 &&
1243 ((best_error > 100 && error < best_error - 100) ||
1244 (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) {
1245 best_post_div = post_div;
1246 best_ref_div = ref_div;
1247 best_feedback_div = feedback_div;
1248 best_frac_feedback_div = frac_feedback_div;
1249 best_freq = current_freq;
1250 best_error = error;
1251 best_vco_diff = vco_diff;
1252 } else if (current_freq == freq) {
1253 if (best_freq == -1) {
1254 best_post_div = post_div;
1255 best_ref_div = ref_div;
1256 best_feedback_div = feedback_div;
1257 best_frac_feedback_div = frac_feedback_div;
1258 best_freq = current_freq;
1259 best_error = error;
1260 best_vco_diff = vco_diff;
1261 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
1262 ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
1263 ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
1264 ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
1265 ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
1266 ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
1267 best_post_div = post_div;
1268 best_ref_div = ref_div;
1269 best_feedback_div = feedback_div;
1270 best_frac_feedback_div = frac_feedback_div;
1271 best_freq = current_freq;
1272 best_error = error;
1273 best_vco_diff = vco_diff;
1274 }
1275 }
1276 if (current_freq < freq)
1277 min_frac_feed_div = frac_feedback_div + 1;
1278 else
1279 max_frac_feed_div = frac_feedback_div;
1280 }
1281 if (current_freq < freq)
1282 min_feed_div = feedback_div + 1;
1283 else
1284 max_feed_div = feedback_div;
1285 }
1286 }
1287 }
1288
1289 *dot_clock_p = best_freq / 10000;
1290 *fb_div_p = best_feedback_div;
1291 *frac_fb_div_p = best_frac_feedback_div;
1292 *ref_div_p = best_ref_div;
1293 *post_div_p = best_post_div;
1294 DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
1295 (long long)freq,
1296 best_freq / 1000, best_feedback_div, best_frac_feedback_div,
1297 best_ref_div, best_post_div);
1298
1299 }
1300
1301 static const struct drm_framebuffer_funcs radeon_fb_funcs = {
1302 .destroy = drm_gem_fb_destroy,
1303 .create_handle = drm_gem_fb_create_handle,
1304 };
1305
1306 int
radeon_framebuffer_init(struct drm_device * dev,struct drm_framebuffer * fb,const struct drm_mode_fb_cmd2 * mode_cmd,struct drm_gem_object * obj)1307 radeon_framebuffer_init(struct drm_device *dev,
1308 struct drm_framebuffer *fb,
1309 const struct drm_mode_fb_cmd2 *mode_cmd,
1310 struct drm_gem_object *obj)
1311 {
1312 int ret;
1313 fb->obj[0] = obj;
1314 drm_helper_mode_fill_fb_struct(dev, fb, mode_cmd);
1315 ret = drm_framebuffer_init(dev, fb, &radeon_fb_funcs);
1316 if (ret) {
1317 fb->obj[0] = NULL;
1318 return ret;
1319 }
1320 return 0;
1321 }
1322
1323 static struct drm_framebuffer *
radeon_user_framebuffer_create(struct drm_device * dev,struct drm_file * file_priv,const struct drm_mode_fb_cmd2 * mode_cmd)1324 radeon_user_framebuffer_create(struct drm_device *dev,
1325 struct drm_file *file_priv,
1326 const struct drm_mode_fb_cmd2 *mode_cmd)
1327 {
1328 struct drm_gem_object *obj;
1329 struct drm_framebuffer *fb;
1330 int ret;
1331
1332 obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[0]);
1333 if (obj == NULL) {
1334 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, "
1335 "can't create framebuffer\n", mode_cmd->handles[0]);
1336 return ERR_PTR(-ENOENT);
1337 }
1338
1339 /* Handle is imported dma-buf, so cannot be migrated to VRAM for scanout */
1340 if (obj->import_attach) {
1341 DRM_DEBUG_KMS("Cannot create framebuffer from imported dma_buf\n");
1342 drm_gem_object_put(obj);
1343 return ERR_PTR(-EINVAL);
1344 }
1345
1346 fb = kzalloc(sizeof(*fb), GFP_KERNEL);
1347 if (fb == NULL) {
1348 drm_gem_object_put(obj);
1349 return ERR_PTR(-ENOMEM);
1350 }
1351
1352 ret = radeon_framebuffer_init(dev, fb, mode_cmd, obj);
1353 if (ret) {
1354 kfree(fb);
1355 drm_gem_object_put(obj);
1356 return ERR_PTR(ret);
1357 }
1358
1359 return fb;
1360 }
1361
1362 static const struct drm_mode_config_funcs radeon_mode_funcs = {
1363 .fb_create = radeon_user_framebuffer_create,
1364 .output_poll_changed = drm_fb_helper_output_poll_changed,
1365 };
1366
1367 static const struct drm_prop_enum_list radeon_tmds_pll_enum_list[] =
1368 { { 0, "driver" },
1369 { 1, "bios" },
1370 };
1371
1372 static const struct drm_prop_enum_list radeon_tv_std_enum_list[] =
1373 { { TV_STD_NTSC, "ntsc" },
1374 { TV_STD_PAL, "pal" },
1375 { TV_STD_PAL_M, "pal-m" },
1376 { TV_STD_PAL_60, "pal-60" },
1377 { TV_STD_NTSC_J, "ntsc-j" },
1378 { TV_STD_SCART_PAL, "scart-pal" },
1379 { TV_STD_PAL_CN, "pal-cn" },
1380 { TV_STD_SECAM, "secam" },
1381 };
1382
1383 static const struct drm_prop_enum_list radeon_underscan_enum_list[] =
1384 { { UNDERSCAN_OFF, "off" },
1385 { UNDERSCAN_ON, "on" },
1386 { UNDERSCAN_AUTO, "auto" },
1387 };
1388
1389 static const struct drm_prop_enum_list radeon_audio_enum_list[] =
1390 { { RADEON_AUDIO_DISABLE, "off" },
1391 { RADEON_AUDIO_ENABLE, "on" },
1392 { RADEON_AUDIO_AUTO, "auto" },
1393 };
1394
1395 /* XXX support different dither options? spatial, temporal, both, etc. */
1396 static const struct drm_prop_enum_list radeon_dither_enum_list[] =
1397 { { RADEON_FMT_DITHER_DISABLE, "off" },
1398 { RADEON_FMT_DITHER_ENABLE, "on" },
1399 };
1400
1401 static const struct drm_prop_enum_list radeon_output_csc_enum_list[] =
1402 { { RADEON_OUTPUT_CSC_BYPASS, "bypass" },
1403 { RADEON_OUTPUT_CSC_TVRGB, "tvrgb" },
1404 { RADEON_OUTPUT_CSC_YCBCR601, "ycbcr601" },
1405 { RADEON_OUTPUT_CSC_YCBCR709, "ycbcr709" },
1406 };
1407
radeon_modeset_create_props(struct radeon_device * rdev)1408 static int radeon_modeset_create_props(struct radeon_device *rdev)
1409 {
1410 int sz;
1411
1412 if (rdev->is_atom_bios) {
1413 rdev->mode_info.coherent_mode_property =
1414 drm_property_create_range(rdev->ddev, 0 , "coherent", 0, 1);
1415 if (!rdev->mode_info.coherent_mode_property)
1416 return -ENOMEM;
1417 }
1418
1419 if (!ASIC_IS_AVIVO(rdev)) {
1420 sz = ARRAY_SIZE(radeon_tmds_pll_enum_list);
1421 rdev->mode_info.tmds_pll_property =
1422 drm_property_create_enum(rdev->ddev, 0,
1423 "tmds_pll",
1424 radeon_tmds_pll_enum_list, sz);
1425 }
1426
1427 rdev->mode_info.load_detect_property =
1428 drm_property_create_range(rdev->ddev, 0, "load detection", 0, 1);
1429 if (!rdev->mode_info.load_detect_property)
1430 return -ENOMEM;
1431
1432 drm_mode_create_scaling_mode_property(rdev->ddev);
1433
1434 sz = ARRAY_SIZE(radeon_tv_std_enum_list);
1435 rdev->mode_info.tv_std_property =
1436 drm_property_create_enum(rdev->ddev, 0,
1437 "tv standard",
1438 radeon_tv_std_enum_list, sz);
1439
1440 sz = ARRAY_SIZE(radeon_underscan_enum_list);
1441 rdev->mode_info.underscan_property =
1442 drm_property_create_enum(rdev->ddev, 0,
1443 "underscan",
1444 radeon_underscan_enum_list, sz);
1445
1446 rdev->mode_info.underscan_hborder_property =
1447 drm_property_create_range(rdev->ddev, 0,
1448 "underscan hborder", 0, 128);
1449 if (!rdev->mode_info.underscan_hborder_property)
1450 return -ENOMEM;
1451
1452 rdev->mode_info.underscan_vborder_property =
1453 drm_property_create_range(rdev->ddev, 0,
1454 "underscan vborder", 0, 128);
1455 if (!rdev->mode_info.underscan_vborder_property)
1456 return -ENOMEM;
1457
1458 sz = ARRAY_SIZE(radeon_audio_enum_list);
1459 rdev->mode_info.audio_property =
1460 drm_property_create_enum(rdev->ddev, 0,
1461 "audio",
1462 radeon_audio_enum_list, sz);
1463
1464 sz = ARRAY_SIZE(radeon_dither_enum_list);
1465 rdev->mode_info.dither_property =
1466 drm_property_create_enum(rdev->ddev, 0,
1467 "dither",
1468 radeon_dither_enum_list, sz);
1469
1470 sz = ARRAY_SIZE(radeon_output_csc_enum_list);
1471 rdev->mode_info.output_csc_property =
1472 drm_property_create_enum(rdev->ddev, 0,
1473 "output_csc",
1474 radeon_output_csc_enum_list, sz);
1475
1476 return 0;
1477 }
1478
radeon_update_display_priority(struct radeon_device * rdev)1479 void radeon_update_display_priority(struct radeon_device *rdev)
1480 {
1481 /* adjustment options for the display watermarks */
1482 if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) {
1483 /* set display priority to high for r3xx, rv515 chips
1484 * this avoids flickering due to underflow to the
1485 * display controllers during heavy acceleration.
1486 * Don't force high on rs4xx igp chips as it seems to
1487 * affect the sound card. See kernel bug 15982.
1488 */
1489 if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) &&
1490 !(rdev->flags & RADEON_IS_IGP))
1491 rdev->disp_priority = 2;
1492 else
1493 rdev->disp_priority = 0;
1494 } else
1495 rdev->disp_priority = radeon_disp_priority;
1496
1497 }
1498
1499 /*
1500 * Allocate hdmi structs and determine register offsets
1501 */
radeon_afmt_init(struct radeon_device * rdev)1502 static void radeon_afmt_init(struct radeon_device *rdev)
1503 {
1504 int i;
1505
1506 for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++)
1507 rdev->mode_info.afmt[i] = NULL;
1508
1509 if (ASIC_IS_NODCE(rdev)) {
1510 /* nothing to do */
1511 } else if (ASIC_IS_DCE4(rdev)) {
1512 static uint32_t eg_offsets[] = {
1513 EVERGREEN_CRTC0_REGISTER_OFFSET,
1514 EVERGREEN_CRTC1_REGISTER_OFFSET,
1515 EVERGREEN_CRTC2_REGISTER_OFFSET,
1516 EVERGREEN_CRTC3_REGISTER_OFFSET,
1517 EVERGREEN_CRTC4_REGISTER_OFFSET,
1518 EVERGREEN_CRTC5_REGISTER_OFFSET,
1519 0x13830 - 0x7030,
1520 };
1521 int num_afmt;
1522
1523 /* DCE8 has 7 audio blocks tied to DIG encoders */
1524 /* DCE6 has 6 audio blocks tied to DIG encoders */
1525 /* DCE4/5 has 6 audio blocks tied to DIG encoders */
1526 /* DCE4.1 has 2 audio blocks tied to DIG encoders */
1527 if (ASIC_IS_DCE8(rdev))
1528 num_afmt = 7;
1529 else if (ASIC_IS_DCE6(rdev))
1530 num_afmt = 6;
1531 else if (ASIC_IS_DCE5(rdev))
1532 num_afmt = 6;
1533 else if (ASIC_IS_DCE41(rdev))
1534 num_afmt = 2;
1535 else /* DCE4 */
1536 num_afmt = 6;
1537
1538 BUG_ON(num_afmt > ARRAY_SIZE(eg_offsets));
1539 for (i = 0; i < num_afmt; i++) {
1540 rdev->mode_info.afmt[i] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1541 if (rdev->mode_info.afmt[i]) {
1542 rdev->mode_info.afmt[i]->offset = eg_offsets[i];
1543 rdev->mode_info.afmt[i]->id = i;
1544 }
1545 }
1546 } else if (ASIC_IS_DCE3(rdev)) {
1547 /* DCE3.x has 2 audio blocks tied to DIG encoders */
1548 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1549 if (rdev->mode_info.afmt[0]) {
1550 rdev->mode_info.afmt[0]->offset = DCE3_HDMI_OFFSET0;
1551 rdev->mode_info.afmt[0]->id = 0;
1552 }
1553 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1554 if (rdev->mode_info.afmt[1]) {
1555 rdev->mode_info.afmt[1]->offset = DCE3_HDMI_OFFSET1;
1556 rdev->mode_info.afmt[1]->id = 1;
1557 }
1558 } else if (ASIC_IS_DCE2(rdev)) {
1559 /* DCE2 has at least 1 routable audio block */
1560 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1561 if (rdev->mode_info.afmt[0]) {
1562 rdev->mode_info.afmt[0]->offset = DCE2_HDMI_OFFSET0;
1563 rdev->mode_info.afmt[0]->id = 0;
1564 }
1565 /* r6xx has 2 routable audio blocks */
1566 if (rdev->family >= CHIP_R600) {
1567 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1568 if (rdev->mode_info.afmt[1]) {
1569 rdev->mode_info.afmt[1]->offset = DCE2_HDMI_OFFSET1;
1570 rdev->mode_info.afmt[1]->id = 1;
1571 }
1572 }
1573 }
1574 }
1575
radeon_afmt_fini(struct radeon_device * rdev)1576 static void radeon_afmt_fini(struct radeon_device *rdev)
1577 {
1578 int i;
1579
1580 for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) {
1581 kfree(rdev->mode_info.afmt[i]);
1582 rdev->mode_info.afmt[i] = NULL;
1583 }
1584 }
1585
radeon_modeset_init(struct radeon_device * rdev)1586 int radeon_modeset_init(struct radeon_device *rdev)
1587 {
1588 int i;
1589 int ret;
1590
1591 drm_mode_config_init(rdev->ddev);
1592 rdev->mode_info.mode_config_initialized = true;
1593
1594 rdev->ddev->mode_config.funcs = &radeon_mode_funcs;
1595
1596 if (radeon_use_pflipirq == 2 && rdev->family >= CHIP_R600)
1597 rdev->ddev->mode_config.async_page_flip = true;
1598
1599 if (ASIC_IS_DCE5(rdev)) {
1600 rdev->ddev->mode_config.max_width = 16384;
1601 rdev->ddev->mode_config.max_height = 16384;
1602 } else if (ASIC_IS_AVIVO(rdev)) {
1603 rdev->ddev->mode_config.max_width = 8192;
1604 rdev->ddev->mode_config.max_height = 8192;
1605 } else {
1606 rdev->ddev->mode_config.max_width = 4096;
1607 rdev->ddev->mode_config.max_height = 4096;
1608 }
1609
1610 rdev->ddev->mode_config.preferred_depth = 24;
1611 rdev->ddev->mode_config.prefer_shadow = 1;
1612
1613 rdev->ddev->mode_config.fb_base = rdev->mc.aper_base;
1614
1615 ret = radeon_modeset_create_props(rdev);
1616 if (ret) {
1617 return ret;
1618 }
1619
1620 /* init i2c buses */
1621 radeon_i2c_init(rdev);
1622
1623 /* check combios for a valid hardcoded EDID - Sun servers */
1624 if (!rdev->is_atom_bios) {
1625 /* check for hardcoded EDID in BIOS */
1626 radeon_combios_check_hardcoded_edid(rdev);
1627 }
1628
1629 /* allocate crtcs */
1630 for (i = 0; i < rdev->num_crtc; i++) {
1631 radeon_crtc_init(rdev->ddev, i);
1632 }
1633
1634 /* okay we should have all the bios connectors */
1635 ret = radeon_setup_enc_conn(rdev->ddev);
1636 if (!ret) {
1637 return ret;
1638 }
1639
1640 /* init dig PHYs, disp eng pll */
1641 if (rdev->is_atom_bios) {
1642 radeon_atom_encoder_init(rdev);
1643 radeon_atom_disp_eng_pll_init(rdev);
1644 }
1645
1646 /* initialize hpd */
1647 radeon_hpd_init(rdev);
1648
1649 /* setup afmt */
1650 radeon_afmt_init(rdev);
1651
1652 radeon_fbdev_init(rdev);
1653 drm_kms_helper_poll_init(rdev->ddev);
1654
1655 /* do pm late init */
1656 ret = radeon_pm_late_init(rdev);
1657
1658 return 0;
1659 }
1660
radeon_modeset_fini(struct radeon_device * rdev)1661 void radeon_modeset_fini(struct radeon_device *rdev)
1662 {
1663 if (rdev->mode_info.mode_config_initialized) {
1664 drm_kms_helper_poll_fini(rdev->ddev);
1665 radeon_hpd_fini(rdev);
1666 drm_helper_force_disable_all(rdev->ddev);
1667 radeon_fbdev_fini(rdev);
1668 radeon_afmt_fini(rdev);
1669 drm_mode_config_cleanup(rdev->ddev);
1670 rdev->mode_info.mode_config_initialized = false;
1671 }
1672
1673 kfree(rdev->mode_info.bios_hardcoded_edid);
1674
1675 /* free i2c buses */
1676 radeon_i2c_fini(rdev);
1677 }
1678
is_hdtv_mode(const struct drm_display_mode * mode)1679 static bool is_hdtv_mode(const struct drm_display_mode *mode)
1680 {
1681 /* try and guess if this is a tv or a monitor */
1682 if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
1683 (mode->vdisplay == 576) || /* 576p */
1684 (mode->vdisplay == 720) || /* 720p */
1685 (mode->vdisplay == 1080)) /* 1080p */
1686 return true;
1687 else
1688 return false;
1689 }
1690
radeon_crtc_scaling_mode_fixup(struct drm_crtc * crtc,const struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)1691 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
1692 const struct drm_display_mode *mode,
1693 struct drm_display_mode *adjusted_mode)
1694 {
1695 struct drm_device *dev = crtc->dev;
1696 struct radeon_device *rdev = dev->dev_private;
1697 struct drm_encoder *encoder;
1698 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1699 struct radeon_encoder *radeon_encoder;
1700 struct drm_connector *connector;
1701 bool first = true;
1702 u32 src_v = 1, dst_v = 1;
1703 u32 src_h = 1, dst_h = 1;
1704
1705 radeon_crtc->h_border = 0;
1706 radeon_crtc->v_border = 0;
1707
1708 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1709 if (encoder->crtc != crtc)
1710 continue;
1711 radeon_encoder = to_radeon_encoder(encoder);
1712 connector = radeon_get_connector_for_encoder(encoder);
1713
1714 if (first) {
1715 /* set scaling */
1716 if (radeon_encoder->rmx_type == RMX_OFF)
1717 radeon_crtc->rmx_type = RMX_OFF;
1718 else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay ||
1719 mode->vdisplay < radeon_encoder->native_mode.vdisplay)
1720 radeon_crtc->rmx_type = radeon_encoder->rmx_type;
1721 else
1722 radeon_crtc->rmx_type = RMX_OFF;
1723 /* copy native mode */
1724 memcpy(&radeon_crtc->native_mode,
1725 &radeon_encoder->native_mode,
1726 sizeof(struct drm_display_mode));
1727 src_v = crtc->mode.vdisplay;
1728 dst_v = radeon_crtc->native_mode.vdisplay;
1729 src_h = crtc->mode.hdisplay;
1730 dst_h = radeon_crtc->native_mode.hdisplay;
1731
1732 /* fix up for overscan on hdmi */
1733 if (ASIC_IS_AVIVO(rdev) &&
1734 (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
1735 ((radeon_encoder->underscan_type == UNDERSCAN_ON) ||
1736 ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) &&
1737 drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
1738 is_hdtv_mode(mode)))) {
1739 if (radeon_encoder->underscan_hborder != 0)
1740 radeon_crtc->h_border = radeon_encoder->underscan_hborder;
1741 else
1742 radeon_crtc->h_border = (mode->hdisplay >> 5) + 16;
1743 if (radeon_encoder->underscan_vborder != 0)
1744 radeon_crtc->v_border = radeon_encoder->underscan_vborder;
1745 else
1746 radeon_crtc->v_border = (mode->vdisplay >> 5) + 16;
1747 radeon_crtc->rmx_type = RMX_FULL;
1748 src_v = crtc->mode.vdisplay;
1749 dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2);
1750 src_h = crtc->mode.hdisplay;
1751 dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2);
1752 }
1753 first = false;
1754 } else {
1755 if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {
1756 /* WARNING: Right now this can't happen but
1757 * in the future we need to check that scaling
1758 * are consistent across different encoder
1759 * (ie all encoder can work with the same
1760 * scaling).
1761 */
1762 DRM_ERROR("Scaling not consistent across encoder.\n");
1763 return false;
1764 }
1765 }
1766 }
1767 if (radeon_crtc->rmx_type != RMX_OFF) {
1768 fixed20_12 a, b;
1769 a.full = dfixed_const(src_v);
1770 b.full = dfixed_const(dst_v);
1771 radeon_crtc->vsc.full = dfixed_div(a, b);
1772 a.full = dfixed_const(src_h);
1773 b.full = dfixed_const(dst_h);
1774 radeon_crtc->hsc.full = dfixed_div(a, b);
1775 } else {
1776 radeon_crtc->vsc.full = dfixed_const(1);
1777 radeon_crtc->hsc.full = dfixed_const(1);
1778 }
1779 return true;
1780 }
1781
1782 /*
1783 * Retrieve current video scanout position of crtc on a given gpu, and
1784 * an optional accurate timestamp of when query happened.
1785 *
1786 * \param dev Device to query.
1787 * \param crtc Crtc to query.
1788 * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0).
1789 * For driver internal use only also supports these flags:
1790 *
1791 * USE_REAL_VBLANKSTART to use the real start of vblank instead
1792 * of a fudged earlier start of vblank.
1793 *
1794 * GET_DISTANCE_TO_VBLANKSTART to return distance to the
1795 * fudged earlier start of vblank in *vpos and the distance
1796 * to true start of vblank in *hpos.
1797 *
1798 * \param *vpos Location where vertical scanout position should be stored.
1799 * \param *hpos Location where horizontal scanout position should go.
1800 * \param *stime Target location for timestamp taken immediately before
1801 * scanout position query. Can be NULL to skip timestamp.
1802 * \param *etime Target location for timestamp taken immediately after
1803 * scanout position query. Can be NULL to skip timestamp.
1804 *
1805 * Returns vpos as a positive number while in active scanout area.
1806 * Returns vpos as a negative number inside vblank, counting the number
1807 * of scanlines to go until end of vblank, e.g., -1 means "one scanline
1808 * until start of active scanout / end of vblank."
1809 *
1810 * \return Flags, or'ed together as follows:
1811 *
1812 * DRM_SCANOUTPOS_VALID = Query successful.
1813 * DRM_SCANOUTPOS_INVBL = Inside vblank.
1814 * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
1815 * this flag means that returned position may be offset by a constant but
1816 * unknown small number of scanlines wrt. real scanout position.
1817 *
1818 */
radeon_get_crtc_scanoutpos(struct drm_device * dev,unsigned int pipe,unsigned int flags,int * vpos,int * hpos,ktime_t * stime,ktime_t * etime,const struct drm_display_mode * mode)1819 int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
1820 unsigned int flags, int *vpos, int *hpos,
1821 ktime_t *stime, ktime_t *etime,
1822 const struct drm_display_mode *mode)
1823 {
1824 u32 stat_crtc = 0, vbl = 0, position = 0;
1825 int vbl_start, vbl_end, vtotal, ret = 0;
1826 bool in_vbl = true;
1827
1828 struct radeon_device *rdev = dev->dev_private;
1829
1830 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
1831
1832 /* Get optional system timestamp before query. */
1833 if (stime)
1834 *stime = ktime_get();
1835
1836 if (ASIC_IS_DCE4(rdev)) {
1837 if (pipe == 0) {
1838 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1839 EVERGREEN_CRTC0_REGISTER_OFFSET);
1840 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1841 EVERGREEN_CRTC0_REGISTER_OFFSET);
1842 ret |= DRM_SCANOUTPOS_VALID;
1843 }
1844 if (pipe == 1) {
1845 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1846 EVERGREEN_CRTC1_REGISTER_OFFSET);
1847 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1848 EVERGREEN_CRTC1_REGISTER_OFFSET);
1849 ret |= DRM_SCANOUTPOS_VALID;
1850 }
1851 if (pipe == 2) {
1852 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1853 EVERGREEN_CRTC2_REGISTER_OFFSET);
1854 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1855 EVERGREEN_CRTC2_REGISTER_OFFSET);
1856 ret |= DRM_SCANOUTPOS_VALID;
1857 }
1858 if (pipe == 3) {
1859 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1860 EVERGREEN_CRTC3_REGISTER_OFFSET);
1861 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1862 EVERGREEN_CRTC3_REGISTER_OFFSET);
1863 ret |= DRM_SCANOUTPOS_VALID;
1864 }
1865 if (pipe == 4) {
1866 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1867 EVERGREEN_CRTC4_REGISTER_OFFSET);
1868 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1869 EVERGREEN_CRTC4_REGISTER_OFFSET);
1870 ret |= DRM_SCANOUTPOS_VALID;
1871 }
1872 if (pipe == 5) {
1873 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1874 EVERGREEN_CRTC5_REGISTER_OFFSET);
1875 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1876 EVERGREEN_CRTC5_REGISTER_OFFSET);
1877 ret |= DRM_SCANOUTPOS_VALID;
1878 }
1879 } else if (ASIC_IS_AVIVO(rdev)) {
1880 if (pipe == 0) {
1881 vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END);
1882 position = RREG32(AVIVO_D1CRTC_STATUS_POSITION);
1883 ret |= DRM_SCANOUTPOS_VALID;
1884 }
1885 if (pipe == 1) {
1886 vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END);
1887 position = RREG32(AVIVO_D2CRTC_STATUS_POSITION);
1888 ret |= DRM_SCANOUTPOS_VALID;
1889 }
1890 } else {
1891 /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */
1892 if (pipe == 0) {
1893 /* Assume vbl_end == 0, get vbl_start from
1894 * upper 16 bits.
1895 */
1896 vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) &
1897 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1898 /* Only retrieve vpos from upper 16 bits, set hpos == 0. */
1899 position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1900 stat_crtc = RREG32(RADEON_CRTC_STATUS);
1901 if (!(stat_crtc & 1))
1902 in_vbl = false;
1903
1904 ret |= DRM_SCANOUTPOS_VALID;
1905 }
1906 if (pipe == 1) {
1907 vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) &
1908 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1909 position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1910 stat_crtc = RREG32(RADEON_CRTC2_STATUS);
1911 if (!(stat_crtc & 1))
1912 in_vbl = false;
1913
1914 ret |= DRM_SCANOUTPOS_VALID;
1915 }
1916 }
1917
1918 /* Get optional system timestamp after query. */
1919 if (etime)
1920 *etime = ktime_get();
1921
1922 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
1923
1924 /* Decode into vertical and horizontal scanout position. */
1925 *vpos = position & 0x1fff;
1926 *hpos = (position >> 16) & 0x1fff;
1927
1928 /* Valid vblank area boundaries from gpu retrieved? */
1929 if (vbl > 0) {
1930 /* Yes: Decode. */
1931 ret |= DRM_SCANOUTPOS_ACCURATE;
1932 vbl_start = vbl & 0x1fff;
1933 vbl_end = (vbl >> 16) & 0x1fff;
1934 }
1935 else {
1936 /* No: Fake something reasonable which gives at least ok results. */
1937 vbl_start = mode->crtc_vdisplay;
1938 vbl_end = 0;
1939 }
1940
1941 /* Called from driver internal vblank counter query code? */
1942 if (flags & GET_DISTANCE_TO_VBLANKSTART) {
1943 /* Caller wants distance from real vbl_start in *hpos */
1944 *hpos = *vpos - vbl_start;
1945 }
1946
1947 /* Fudge vblank to start a few scanlines earlier to handle the
1948 * problem that vblank irqs fire a few scanlines before start
1949 * of vblank. Some driver internal callers need the true vblank
1950 * start to be used and signal this via the USE_REAL_VBLANKSTART flag.
1951 *
1952 * The cause of the "early" vblank irq is that the irq is triggered
1953 * by the line buffer logic when the line buffer read position enters
1954 * the vblank, whereas our crtc scanout position naturally lags the
1955 * line buffer read position.
1956 */
1957 if (!(flags & USE_REAL_VBLANKSTART))
1958 vbl_start -= rdev->mode_info.crtcs[pipe]->lb_vblank_lead_lines;
1959
1960 /* Test scanout position against vblank region. */
1961 if ((*vpos < vbl_start) && (*vpos >= vbl_end))
1962 in_vbl = false;
1963
1964 /* In vblank? */
1965 if (in_vbl)
1966 ret |= DRM_SCANOUTPOS_IN_VBLANK;
1967
1968 /* Called from driver internal vblank counter query code? */
1969 if (flags & GET_DISTANCE_TO_VBLANKSTART) {
1970 /* Caller wants distance from fudged earlier vbl_start */
1971 *vpos -= vbl_start;
1972 return ret;
1973 }
1974
1975 /* Check if inside vblank area and apply corrective offsets:
1976 * vpos will then be >=0 in video scanout area, but negative
1977 * within vblank area, counting down the number of lines until
1978 * start of scanout.
1979 */
1980
1981 /* Inside "upper part" of vblank area? Apply corrective offset if so: */
1982 if (in_vbl && (*vpos >= vbl_start)) {
1983 vtotal = mode->crtc_vtotal;
1984 *vpos = *vpos - vtotal;
1985 }
1986
1987 /* Correct for shifted end of vbl at vbl_end. */
1988 *vpos = *vpos - vbl_end;
1989
1990 return ret;
1991 }
1992
1993 bool
radeon_get_crtc_scanout_position(struct drm_crtc * crtc,bool in_vblank_irq,int * vpos,int * hpos,ktime_t * stime,ktime_t * etime,const struct drm_display_mode * mode)1994 radeon_get_crtc_scanout_position(struct drm_crtc *crtc,
1995 bool in_vblank_irq, int *vpos, int *hpos,
1996 ktime_t *stime, ktime_t *etime,
1997 const struct drm_display_mode *mode)
1998 {
1999 struct drm_device *dev = crtc->dev;
2000 unsigned int pipe = crtc->index;
2001
2002 return radeon_get_crtc_scanoutpos(dev, pipe, 0, vpos, hpos,
2003 stime, etime, mode);
2004 }
2005