1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2009-2012 Realtek Corporation.*/
3
4 #include "wifi.h"
5 #include "core.h"
6 #include "pci.h"
7 #include "base.h"
8 #include "ps.h"
9 #include "efuse.h"
10 #include <linux/interrupt.h>
11 #include <linux/export.h>
12 #include <linux/module.h>
13
14 MODULE_AUTHOR("lizhaoming <chaoming_li@realsil.com.cn>");
15 MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>");
16 MODULE_AUTHOR("Larry Finger <Larry.FInger@lwfinger.net>");
17 MODULE_LICENSE("GPL");
18 MODULE_DESCRIPTION("PCI basic driver for rtlwifi");
19
20 static const u16 pcibridge_vendors[PCI_BRIDGE_VENDOR_MAX] = {
21 INTEL_VENDOR_ID,
22 ATI_VENDOR_ID,
23 AMD_VENDOR_ID,
24 SIS_VENDOR_ID
25 };
26
27 static const u8 ac_to_hwq[] = {
28 VO_QUEUE,
29 VI_QUEUE,
30 BE_QUEUE,
31 BK_QUEUE
32 };
33
_rtl_mac_to_hwqueue(struct ieee80211_hw * hw,struct sk_buff * skb)34 static u8 _rtl_mac_to_hwqueue(struct ieee80211_hw *hw, struct sk_buff *skb)
35 {
36 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
37 __le16 fc = rtl_get_fc(skb);
38 u8 queue_index = skb_get_queue_mapping(skb);
39 struct ieee80211_hdr *hdr;
40
41 if (unlikely(ieee80211_is_beacon(fc)))
42 return BEACON_QUEUE;
43 if (ieee80211_is_mgmt(fc) || ieee80211_is_ctl(fc))
44 return MGNT_QUEUE;
45 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
46 if (ieee80211_is_nullfunc(fc))
47 return HIGH_QUEUE;
48 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8822BE) {
49 hdr = rtl_get_hdr(skb);
50
51 if (is_multicast_ether_addr(hdr->addr1) ||
52 is_broadcast_ether_addr(hdr->addr1))
53 return HIGH_QUEUE;
54 }
55
56 return ac_to_hwq[queue_index];
57 }
58
59 /* Update PCI dependent default settings*/
_rtl_pci_update_default_setting(struct ieee80211_hw * hw)60 static void _rtl_pci_update_default_setting(struct ieee80211_hw *hw)
61 {
62 struct rtl_priv *rtlpriv = rtl_priv(hw);
63 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
64 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
65 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
66 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
67 u8 init_aspm;
68
69 ppsc->reg_rfps_level = 0;
70 ppsc->support_aspm = false;
71
72 /*Update PCI ASPM setting */
73 ppsc->const_amdpci_aspm = rtlpci->const_amdpci_aspm;
74 switch (rtlpci->const_pci_aspm) {
75 case 0:
76 /*No ASPM */
77 break;
78
79 case 1:
80 /*ASPM dynamically enabled/disable. */
81 ppsc->reg_rfps_level |= RT_RF_LPS_LEVEL_ASPM;
82 break;
83
84 case 2:
85 /*ASPM with Clock Req dynamically enabled/disable. */
86 ppsc->reg_rfps_level |= (RT_RF_LPS_LEVEL_ASPM |
87 RT_RF_OFF_LEVL_CLK_REQ);
88 break;
89
90 case 3:
91 /* Always enable ASPM and Clock Req
92 * from initialization to halt.
93 */
94 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM);
95 ppsc->reg_rfps_level |= (RT_RF_PS_LEVEL_ALWAYS_ASPM |
96 RT_RF_OFF_LEVL_CLK_REQ);
97 break;
98
99 case 4:
100 /* Always enable ASPM without Clock Req
101 * from initialization to halt.
102 */
103 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM |
104 RT_RF_OFF_LEVL_CLK_REQ);
105 ppsc->reg_rfps_level |= RT_RF_PS_LEVEL_ALWAYS_ASPM;
106 break;
107 }
108
109 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
110
111 /*Update Radio OFF setting */
112 switch (rtlpci->const_hwsw_rfoff_d3) {
113 case 1:
114 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
115 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
116 break;
117
118 case 2:
119 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
120 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
121 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
122 break;
123
124 case 3:
125 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_PCI_D3;
126 break;
127 }
128
129 /*Set HW definition to determine if it supports ASPM. */
130 switch (rtlpci->const_support_pciaspm) {
131 case 0:
132 /*Not support ASPM. */
133 ppsc->support_aspm = false;
134 break;
135 case 1:
136 /*Support ASPM. */
137 ppsc->support_aspm = true;
138 ppsc->support_backdoor = true;
139 break;
140 case 2:
141 /*ASPM value set by chipset. */
142 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL)
143 ppsc->support_aspm = true;
144 break;
145 default:
146 pr_err("switch case %#x not processed\n",
147 rtlpci->const_support_pciaspm);
148 break;
149 }
150
151 /* toshiba aspm issue, toshiba will set aspm selfly
152 * so we should not set aspm in driver
153 */
154 pci_read_config_byte(rtlpci->pdev, 0x80, &init_aspm);
155 if (rtlpriv->rtlhal.hw_type == HARDWARE_TYPE_RTL8192SE &&
156 init_aspm == 0x43)
157 ppsc->support_aspm = false;
158 }
159
_rtl_pci_platform_switch_device_pci_aspm(struct ieee80211_hw * hw,u8 value)160 static bool _rtl_pci_platform_switch_device_pci_aspm(
161 struct ieee80211_hw *hw,
162 u8 value)
163 {
164 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
165 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
166
167 value &= PCI_EXP_LNKCTL_ASPMC;
168
169 if (rtlhal->hw_type != HARDWARE_TYPE_RTL8192SE)
170 value |= PCI_EXP_LNKCTL_CCC;
171
172 pcie_capability_clear_and_set_word(rtlpci->pdev, PCI_EXP_LNKCTL,
173 PCI_EXP_LNKCTL_ASPMC | value,
174 value);
175
176 return false;
177 }
178
179 /* @value is PCI_EXP_LNKCTL_CLKREQ_EN or 0 to enable/disable clk request. */
_rtl_pci_switch_clk_req(struct ieee80211_hw * hw,u16 value)180 static void _rtl_pci_switch_clk_req(struct ieee80211_hw *hw, u16 value)
181 {
182 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
183 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
184
185 value &= PCI_EXP_LNKCTL_CLKREQ_EN;
186
187 pcie_capability_clear_and_set_word(rtlpci->pdev, PCI_EXP_LNKCTL,
188 PCI_EXP_LNKCTL_CLKREQ_EN,
189 value);
190
191 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
192 udelay(100);
193 }
194
195 /*Disable RTL8192SE ASPM & Disable Pci Bridge ASPM*/
rtl_pci_disable_aspm(struct ieee80211_hw * hw)196 static void rtl_pci_disable_aspm(struct ieee80211_hw *hw)
197 {
198 struct rtl_priv *rtlpriv = rtl_priv(hw);
199 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
200 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
201 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
202 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
203 /*Retrieve original configuration settings. */
204 u8 linkctrl_reg = pcipriv->ndis_adapter.linkctrl_reg;
205 u16 aspmlevel = 0;
206 u8 tmp_u1b = 0;
207
208 if (!ppsc->support_aspm)
209 return;
210
211 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
212 rtl_dbg(rtlpriv, COMP_POWER, DBG_TRACE,
213 "PCI(Bridge) UNKNOWN\n");
214
215 return;
216 }
217
218 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
219 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
220 _rtl_pci_switch_clk_req(hw, 0x0);
221 }
222
223 /*for promising device will in L0 state after an I/O. */
224 pci_read_config_byte(rtlpci->pdev, 0x80, &tmp_u1b);
225
226 /*Set corresponding value. */
227 aspmlevel |= BIT(0) | BIT(1);
228 linkctrl_reg &= ~aspmlevel;
229
230 _rtl_pci_platform_switch_device_pci_aspm(hw, linkctrl_reg);
231 }
232
233 /*Enable RTL8192SE ASPM & Enable Pci Bridge ASPM for
234 *power saving We should follow the sequence to enable
235 *RTL8192SE first then enable Pci Bridge ASPM
236 *or the system will show bluescreen.
237 */
rtl_pci_enable_aspm(struct ieee80211_hw * hw)238 static void rtl_pci_enable_aspm(struct ieee80211_hw *hw)
239 {
240 struct rtl_priv *rtlpriv = rtl_priv(hw);
241 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
242 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
243 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
244 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
245 u16 aspmlevel;
246 u8 u_device_aspmsetting;
247
248 if (!ppsc->support_aspm)
249 return;
250
251 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
252 rtl_dbg(rtlpriv, COMP_POWER, DBG_TRACE,
253 "PCI(Bridge) UNKNOWN\n");
254 return;
255 }
256
257 /*Get ASPM level (with/without Clock Req) */
258 aspmlevel = rtlpci->const_devicepci_aspm_setting;
259 u_device_aspmsetting = pcipriv->ndis_adapter.linkctrl_reg;
260
261 /*_rtl_pci_platform_switch_device_pci_aspm(dev,*/
262 /*(priv->ndis_adapter.linkctrl_reg | ASPMLevel)); */
263
264 u_device_aspmsetting |= aspmlevel;
265
266 _rtl_pci_platform_switch_device_pci_aspm(hw, u_device_aspmsetting);
267
268 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
269 _rtl_pci_switch_clk_req(hw, (ppsc->reg_rfps_level &
270 RT_RF_OFF_LEVL_CLK_REQ) ?
271 PCI_EXP_LNKCTL_CLKREQ_EN : 0);
272 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
273 }
274 udelay(100);
275 }
276
rtl_pci_get_amd_l1_patch(struct ieee80211_hw * hw)277 static bool rtl_pci_get_amd_l1_patch(struct ieee80211_hw *hw)
278 {
279 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
280
281 bool status = false;
282 u8 offset_e0;
283 unsigned int offset_e4;
284
285 pci_write_config_byte(rtlpci->pdev, 0xe0, 0xa0);
286
287 pci_read_config_byte(rtlpci->pdev, 0xe0, &offset_e0);
288
289 if (offset_e0 == 0xA0) {
290 pci_read_config_dword(rtlpci->pdev, 0xe4, &offset_e4);
291 if (offset_e4 & BIT(23))
292 status = true;
293 }
294
295 return status;
296 }
297
rtl_pci_check_buddy_priv(struct ieee80211_hw * hw,struct rtl_priv ** buddy_priv)298 static bool rtl_pci_check_buddy_priv(struct ieee80211_hw *hw,
299 struct rtl_priv **buddy_priv)
300 {
301 struct rtl_priv *rtlpriv = rtl_priv(hw);
302 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
303 bool find_buddy_priv = false;
304 struct rtl_priv *tpriv;
305 struct rtl_pci_priv *tpcipriv = NULL;
306
307 if (!list_empty(&rtlpriv->glb_var->glb_priv_list)) {
308 list_for_each_entry(tpriv, &rtlpriv->glb_var->glb_priv_list,
309 list) {
310 tpcipriv = (struct rtl_pci_priv *)tpriv->priv;
311 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
312 "pcipriv->ndis_adapter.funcnumber %x\n",
313 pcipriv->ndis_adapter.funcnumber);
314 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
315 "tpcipriv->ndis_adapter.funcnumber %x\n",
316 tpcipriv->ndis_adapter.funcnumber);
317
318 if (pcipriv->ndis_adapter.busnumber ==
319 tpcipriv->ndis_adapter.busnumber &&
320 pcipriv->ndis_adapter.devnumber ==
321 tpcipriv->ndis_adapter.devnumber &&
322 pcipriv->ndis_adapter.funcnumber !=
323 tpcipriv->ndis_adapter.funcnumber) {
324 find_buddy_priv = true;
325 break;
326 }
327 }
328 }
329
330 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
331 "find_buddy_priv %d\n", find_buddy_priv);
332
333 if (find_buddy_priv)
334 *buddy_priv = tpriv;
335
336 return find_buddy_priv;
337 }
338
rtl_pci_parse_configuration(struct pci_dev * pdev,struct ieee80211_hw * hw)339 static void rtl_pci_parse_configuration(struct pci_dev *pdev,
340 struct ieee80211_hw *hw)
341 {
342 struct rtl_priv *rtlpriv = rtl_priv(hw);
343 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
344
345 u8 tmp;
346 u16 linkctrl_reg;
347
348 /*Link Control Register */
349 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &linkctrl_reg);
350 pcipriv->ndis_adapter.linkctrl_reg = (u8)linkctrl_reg;
351
352 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "Link Control Register =%x\n",
353 pcipriv->ndis_adapter.linkctrl_reg);
354
355 pci_read_config_byte(pdev, 0x98, &tmp);
356 tmp |= BIT(4);
357 pci_write_config_byte(pdev, 0x98, tmp);
358
359 tmp = 0x17;
360 pci_write_config_byte(pdev, 0x70f, tmp);
361 }
362
rtl_pci_init_aspm(struct ieee80211_hw * hw)363 static void rtl_pci_init_aspm(struct ieee80211_hw *hw)
364 {
365 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
366
367 _rtl_pci_update_default_setting(hw);
368
369 if (ppsc->reg_rfps_level & RT_RF_PS_LEVEL_ALWAYS_ASPM) {
370 /*Always enable ASPM & Clock Req. */
371 rtl_pci_enable_aspm(hw);
372 RT_SET_PS_LEVEL(ppsc, RT_RF_PS_LEVEL_ALWAYS_ASPM);
373 }
374 }
375
_rtl_pci_io_handler_init(struct device * dev,struct ieee80211_hw * hw)376 static void _rtl_pci_io_handler_init(struct device *dev,
377 struct ieee80211_hw *hw)
378 {
379 struct rtl_priv *rtlpriv = rtl_priv(hw);
380
381 rtlpriv->io.dev = dev;
382
383 rtlpriv->io.write8_async = pci_write8_async;
384 rtlpriv->io.write16_async = pci_write16_async;
385 rtlpriv->io.write32_async = pci_write32_async;
386
387 rtlpriv->io.read8_sync = pci_read8_sync;
388 rtlpriv->io.read16_sync = pci_read16_sync;
389 rtlpriv->io.read32_sync = pci_read32_sync;
390 }
391
_rtl_update_earlymode_info(struct ieee80211_hw * hw,struct sk_buff * skb,struct rtl_tcb_desc * tcb_desc,u8 tid)392 static bool _rtl_update_earlymode_info(struct ieee80211_hw *hw,
393 struct sk_buff *skb,
394 struct rtl_tcb_desc *tcb_desc, u8 tid)
395 {
396 struct rtl_priv *rtlpriv = rtl_priv(hw);
397 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
398 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
399 struct sk_buff *next_skb;
400 u8 additionlen = FCS_LEN;
401
402 /* here open is 4, wep/tkip is 8, aes is 12*/
403 if (info->control.hw_key)
404 additionlen += info->control.hw_key->icv_len;
405
406 /* The most skb num is 6 */
407 tcb_desc->empkt_num = 0;
408 spin_lock_bh(&rtlpriv->locks.waitq_lock);
409 skb_queue_walk(&rtlpriv->mac80211.skb_waitq[tid], next_skb) {
410 struct ieee80211_tx_info *next_info;
411
412 next_info = IEEE80211_SKB_CB(next_skb);
413 if (next_info->flags & IEEE80211_TX_CTL_AMPDU) {
414 tcb_desc->empkt_len[tcb_desc->empkt_num] =
415 next_skb->len + additionlen;
416 tcb_desc->empkt_num++;
417 } else {
418 break;
419 }
420
421 if (skb_queue_is_last(&rtlpriv->mac80211.skb_waitq[tid],
422 next_skb))
423 break;
424
425 if (tcb_desc->empkt_num >= rtlhal->max_earlymode_num)
426 break;
427 }
428 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
429
430 return true;
431 }
432
433 /* just for early mode now */
_rtl_pci_tx_chk_waitq(struct ieee80211_hw * hw)434 static void _rtl_pci_tx_chk_waitq(struct ieee80211_hw *hw)
435 {
436 struct rtl_priv *rtlpriv = rtl_priv(hw);
437 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
438 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
439 struct sk_buff *skb = NULL;
440 struct ieee80211_tx_info *info = NULL;
441 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
442 int tid;
443
444 if (!rtlpriv->rtlhal.earlymode_enable)
445 return;
446
447 if (rtlpriv->dm.supp_phymode_switch &&
448 (rtlpriv->easy_concurrent_ctl.switch_in_process ||
449 (rtlpriv->buddy_priv &&
450 rtlpriv->buddy_priv->easy_concurrent_ctl.switch_in_process)))
451 return;
452 /* we just use em for BE/BK/VI/VO */
453 for (tid = 7; tid >= 0; tid--) {
454 u8 hw_queue = ac_to_hwq[rtl_tid_to_ac(tid)];
455 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[hw_queue];
456
457 while (!mac->act_scanning &&
458 rtlpriv->psc.rfpwr_state == ERFON) {
459 struct rtl_tcb_desc tcb_desc;
460
461 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc));
462
463 spin_lock(&rtlpriv->locks.waitq_lock);
464 if (!skb_queue_empty(&mac->skb_waitq[tid]) &&
465 (ring->entries - skb_queue_len(&ring->queue) >
466 rtlhal->max_earlymode_num)) {
467 skb = skb_dequeue(&mac->skb_waitq[tid]);
468 } else {
469 spin_unlock(&rtlpriv->locks.waitq_lock);
470 break;
471 }
472 spin_unlock(&rtlpriv->locks.waitq_lock);
473
474 /* Some macaddr can't do early mode. like
475 * multicast/broadcast/no_qos data
476 */
477 info = IEEE80211_SKB_CB(skb);
478 if (info->flags & IEEE80211_TX_CTL_AMPDU)
479 _rtl_update_earlymode_info(hw, skb,
480 &tcb_desc, tid);
481
482 rtlpriv->intf_ops->adapter_tx(hw, NULL, skb, &tcb_desc);
483 }
484 }
485 }
486
_rtl_pci_tx_isr(struct ieee80211_hw * hw,int prio)487 static void _rtl_pci_tx_isr(struct ieee80211_hw *hw, int prio)
488 {
489 struct rtl_priv *rtlpriv = rtl_priv(hw);
490 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
491
492 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
493
494 while (skb_queue_len(&ring->queue)) {
495 struct sk_buff *skb;
496 struct ieee80211_tx_info *info;
497 __le16 fc;
498 u8 tid;
499 u8 *entry;
500
501 if (rtlpriv->use_new_trx_flow)
502 entry = (u8 *)(&ring->buffer_desc[ring->idx]);
503 else
504 entry = (u8 *)(&ring->desc[ring->idx]);
505
506 if (!rtlpriv->cfg->ops->is_tx_desc_closed(hw, prio, ring->idx))
507 return;
508 ring->idx = (ring->idx + 1) % ring->entries;
509
510 skb = __skb_dequeue(&ring->queue);
511 dma_unmap_single(&rtlpci->pdev->dev,
512 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry,
513 true, HW_DESC_TXBUFF_ADDR),
514 skb->len, DMA_TO_DEVICE);
515
516 /* remove early mode header */
517 if (rtlpriv->rtlhal.earlymode_enable)
518 skb_pull(skb, EM_HDR_LEN);
519
520 rtl_dbg(rtlpriv, (COMP_INTR | COMP_SEND), DBG_TRACE,
521 "new ring->idx:%d, free: skb_queue_len:%d, free: seq:%x\n",
522 ring->idx,
523 skb_queue_len(&ring->queue),
524 *(u16 *)(skb->data + 22));
525
526 if (prio == TXCMD_QUEUE) {
527 dev_kfree_skb(skb);
528 goto tx_status_ok;
529 }
530
531 /* for sw LPS, just after NULL skb send out, we can
532 * sure AP knows we are sleeping, we should not let
533 * rf sleep
534 */
535 fc = rtl_get_fc(skb);
536 if (ieee80211_is_nullfunc(fc)) {
537 if (ieee80211_has_pm(fc)) {
538 rtlpriv->mac80211.offchan_delay = true;
539 rtlpriv->psc.state_inap = true;
540 } else {
541 rtlpriv->psc.state_inap = false;
542 }
543 }
544 if (ieee80211_is_action(fc)) {
545 struct ieee80211_mgmt *action_frame =
546 (struct ieee80211_mgmt *)skb->data;
547 if (action_frame->u.action.u.ht_smps.action ==
548 WLAN_HT_ACTION_SMPS) {
549 dev_kfree_skb(skb);
550 goto tx_status_ok;
551 }
552 }
553
554 /* update tid tx pkt num */
555 tid = rtl_get_tid(skb);
556 if (tid <= 7)
557 rtlpriv->link_info.tidtx_inperiod[tid]++;
558
559 info = IEEE80211_SKB_CB(skb);
560
561 if (likely(!ieee80211_is_nullfunc(fc))) {
562 ieee80211_tx_info_clear_status(info);
563 info->flags |= IEEE80211_TX_STAT_ACK;
564 /*info->status.rates[0].count = 1; */
565 ieee80211_tx_status_irqsafe(hw, skb);
566 } else {
567 rtl_tx_ackqueue(hw, skb);
568 }
569
570 if ((ring->entries - skb_queue_len(&ring->queue)) <= 4) {
571 rtl_dbg(rtlpriv, COMP_ERR, DBG_DMESG,
572 "more desc left, wake skb_queue@%d, ring->idx = %d, skb_queue_len = 0x%x\n",
573 prio, ring->idx,
574 skb_queue_len(&ring->queue));
575
576 ieee80211_wake_queue(hw, skb_get_queue_mapping(skb));
577 }
578 tx_status_ok:
579 skb = NULL;
580 }
581
582 if (((rtlpriv->link_info.num_rx_inperiod +
583 rtlpriv->link_info.num_tx_inperiod) > 8) ||
584 rtlpriv->link_info.num_rx_inperiod > 2)
585 rtl_lps_leave(hw, false);
586 }
587
_rtl_pci_init_one_rxdesc(struct ieee80211_hw * hw,struct sk_buff * new_skb,u8 * entry,int rxring_idx,int desc_idx)588 static int _rtl_pci_init_one_rxdesc(struct ieee80211_hw *hw,
589 struct sk_buff *new_skb, u8 *entry,
590 int rxring_idx, int desc_idx)
591 {
592 struct rtl_priv *rtlpriv = rtl_priv(hw);
593 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
594 u32 bufferaddress;
595 u8 tmp_one = 1;
596 struct sk_buff *skb;
597
598 if (likely(new_skb)) {
599 skb = new_skb;
600 goto remap;
601 }
602 skb = dev_alloc_skb(rtlpci->rxbuffersize);
603 if (!skb)
604 return 0;
605
606 remap:
607 /* just set skb->cb to mapping addr for pci_unmap_single use */
608 *((dma_addr_t *)skb->cb) =
609 dma_map_single(&rtlpci->pdev->dev, skb_tail_pointer(skb),
610 rtlpci->rxbuffersize, DMA_FROM_DEVICE);
611 bufferaddress = *((dma_addr_t *)skb->cb);
612 if (dma_mapping_error(&rtlpci->pdev->dev, bufferaddress))
613 return 0;
614 rtlpci->rx_ring[rxring_idx].rx_buf[desc_idx] = skb;
615 if (rtlpriv->use_new_trx_flow) {
616 /* skb->cb may be 64 bit address */
617 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
618 HW_DESC_RX_PREPARE,
619 (u8 *)(dma_addr_t *)skb->cb);
620 } else {
621 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
622 HW_DESC_RXBUFF_ADDR,
623 (u8 *)&bufferaddress);
624 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
625 HW_DESC_RXPKT_LEN,
626 (u8 *)&rtlpci->rxbuffersize);
627 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
628 HW_DESC_RXOWN,
629 (u8 *)&tmp_one);
630 }
631 return 1;
632 }
633
634 /* inorder to receive 8K AMSDU we have set skb to
635 * 9100bytes in init rx ring, but if this packet is
636 * not a AMSDU, this large packet will be sent to
637 * TCP/IP directly, this cause big packet ping fail
638 * like: "ping -s 65507", so here we will realloc skb
639 * based on the true size of packet, Mac80211
640 * Probably will do it better, but does not yet.
641 *
642 * Some platform will fail when alloc skb sometimes.
643 * in this condition, we will send the old skb to
644 * mac80211 directly, this will not cause any other
645 * issues, but only this packet will be lost by TCP/IP
646 */
_rtl_pci_rx_to_mac80211(struct ieee80211_hw * hw,struct sk_buff * skb,struct ieee80211_rx_status rx_status)647 static void _rtl_pci_rx_to_mac80211(struct ieee80211_hw *hw,
648 struct sk_buff *skb,
649 struct ieee80211_rx_status rx_status)
650 {
651 if (unlikely(!rtl_action_proc(hw, skb, false))) {
652 dev_kfree_skb_any(skb);
653 } else {
654 struct sk_buff *uskb = NULL;
655
656 uskb = dev_alloc_skb(skb->len + 128);
657 if (likely(uskb)) {
658 memcpy(IEEE80211_SKB_RXCB(uskb), &rx_status,
659 sizeof(rx_status));
660 skb_put_data(uskb, skb->data, skb->len);
661 dev_kfree_skb_any(skb);
662 ieee80211_rx_irqsafe(hw, uskb);
663 } else {
664 ieee80211_rx_irqsafe(hw, skb);
665 }
666 }
667 }
668
669 /*hsisr interrupt handler*/
_rtl_pci_hs_interrupt(struct ieee80211_hw * hw)670 static void _rtl_pci_hs_interrupt(struct ieee80211_hw *hw)
671 {
672 struct rtl_priv *rtlpriv = rtl_priv(hw);
673 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
674
675 rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[MAC_HSISR],
676 rtl_read_byte(rtlpriv, rtlpriv->cfg->maps[MAC_HSISR]) |
677 rtlpci->sys_irq_mask);
678 }
679
_rtl_pci_rx_interrupt(struct ieee80211_hw * hw)680 static void _rtl_pci_rx_interrupt(struct ieee80211_hw *hw)
681 {
682 struct rtl_priv *rtlpriv = rtl_priv(hw);
683 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
684 int rxring_idx = RTL_PCI_RX_MPDU_QUEUE;
685 struct ieee80211_rx_status rx_status = { 0 };
686 unsigned int count = rtlpci->rxringcount;
687 u8 own;
688 u8 tmp_one;
689 bool unicast = false;
690 u8 hw_queue = 0;
691 unsigned int rx_remained_cnt = 0;
692 struct rtl_stats stats = {
693 .signal = 0,
694 .rate = 0,
695 };
696
697 /*RX NORMAL PKT */
698 while (count--) {
699 struct ieee80211_hdr *hdr;
700 __le16 fc;
701 u16 len;
702 /*rx buffer descriptor */
703 struct rtl_rx_buffer_desc *buffer_desc = NULL;
704 /*if use new trx flow, it means wifi info */
705 struct rtl_rx_desc *pdesc = NULL;
706 /*rx pkt */
707 struct sk_buff *skb = rtlpci->rx_ring[rxring_idx].rx_buf[
708 rtlpci->rx_ring[rxring_idx].idx];
709 struct sk_buff *new_skb;
710
711 if (rtlpriv->use_new_trx_flow) {
712 if (rx_remained_cnt == 0)
713 rx_remained_cnt =
714 rtlpriv->cfg->ops->rx_desc_buff_remained_cnt(hw,
715 hw_queue);
716 if (rx_remained_cnt == 0)
717 return;
718 buffer_desc = &rtlpci->rx_ring[rxring_idx].buffer_desc[
719 rtlpci->rx_ring[rxring_idx].idx];
720 pdesc = (struct rtl_rx_desc *)skb->data;
721 } else { /* rx descriptor */
722 pdesc = &rtlpci->rx_ring[rxring_idx].desc[
723 rtlpci->rx_ring[rxring_idx].idx];
724
725 own = (u8)rtlpriv->cfg->ops->get_desc(hw, (u8 *)pdesc,
726 false,
727 HW_DESC_OWN);
728 if (own) /* wait data to be filled by hardware */
729 return;
730 }
731
732 /* Reaching this point means: data is filled already
733 * AAAAAAttention !!!
734 * We can NOT access 'skb' before 'pci_unmap_single'
735 */
736 dma_unmap_single(&rtlpci->pdev->dev, *((dma_addr_t *)skb->cb),
737 rtlpci->rxbuffersize, DMA_FROM_DEVICE);
738
739 /* get a new skb - if fail, old one will be reused */
740 new_skb = dev_alloc_skb(rtlpci->rxbuffersize);
741 if (unlikely(!new_skb))
742 goto no_new;
743 memset(&rx_status, 0, sizeof(rx_status));
744 rtlpriv->cfg->ops->query_rx_desc(hw, &stats,
745 &rx_status, (u8 *)pdesc, skb);
746
747 if (rtlpriv->use_new_trx_flow)
748 rtlpriv->cfg->ops->rx_check_dma_ok(hw,
749 (u8 *)buffer_desc,
750 hw_queue);
751
752 len = rtlpriv->cfg->ops->get_desc(hw, (u8 *)pdesc, false,
753 HW_DESC_RXPKT_LEN);
754
755 if (skb->end - skb->tail > len) {
756 skb_put(skb, len);
757 if (rtlpriv->use_new_trx_flow)
758 skb_reserve(skb, stats.rx_drvinfo_size +
759 stats.rx_bufshift + 24);
760 else
761 skb_reserve(skb, stats.rx_drvinfo_size +
762 stats.rx_bufshift);
763 } else {
764 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
765 "skb->end - skb->tail = %d, len is %d\n",
766 skb->end - skb->tail, len);
767 dev_kfree_skb_any(skb);
768 goto new_trx_end;
769 }
770 /* handle command packet here */
771 if (stats.packet_report_type == C2H_PACKET) {
772 rtl_c2hcmd_enqueue(hw, skb);
773 goto new_trx_end;
774 }
775
776 /* NOTICE This can not be use for mac80211,
777 * this is done in mac80211 code,
778 * if done here sec DHCP will fail
779 * skb_trim(skb, skb->len - 4);
780 */
781
782 hdr = rtl_get_hdr(skb);
783 fc = rtl_get_fc(skb);
784
785 if (!stats.crc && !stats.hwerror && (skb->len > FCS_LEN)) {
786 memcpy(IEEE80211_SKB_RXCB(skb), &rx_status,
787 sizeof(rx_status));
788
789 if (is_broadcast_ether_addr(hdr->addr1)) {
790 ;/*TODO*/
791 } else if (is_multicast_ether_addr(hdr->addr1)) {
792 ;/*TODO*/
793 } else {
794 unicast = true;
795 rtlpriv->stats.rxbytesunicast += skb->len;
796 }
797 rtl_is_special_data(hw, skb, false, true);
798
799 if (ieee80211_is_data(fc)) {
800 rtlpriv->cfg->ops->led_control(hw, LED_CTL_RX);
801 if (unicast)
802 rtlpriv->link_info.num_rx_inperiod++;
803 }
804
805 rtl_collect_scan_list(hw, skb);
806
807 /* static bcn for roaming */
808 rtl_beacon_statistic(hw, skb);
809 rtl_p2p_info(hw, (void *)skb->data, skb->len);
810 /* for sw lps */
811 rtl_swlps_beacon(hw, (void *)skb->data, skb->len);
812 rtl_recognize_peer(hw, (void *)skb->data, skb->len);
813 if (rtlpriv->mac80211.opmode == NL80211_IFTYPE_AP &&
814 rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G &&
815 (ieee80211_is_beacon(fc) ||
816 ieee80211_is_probe_resp(fc))) {
817 dev_kfree_skb_any(skb);
818 } else {
819 _rtl_pci_rx_to_mac80211(hw, skb, rx_status);
820 }
821 } else {
822 /* drop packets with errors or those too short */
823 dev_kfree_skb_any(skb);
824 }
825 new_trx_end:
826 if (rtlpriv->use_new_trx_flow) {
827 rtlpci->rx_ring[hw_queue].next_rx_rp += 1;
828 rtlpci->rx_ring[hw_queue].next_rx_rp %=
829 RTL_PCI_MAX_RX_COUNT;
830
831 rx_remained_cnt--;
832 rtl_write_word(rtlpriv, 0x3B4,
833 rtlpci->rx_ring[hw_queue].next_rx_rp);
834 }
835 if (((rtlpriv->link_info.num_rx_inperiod +
836 rtlpriv->link_info.num_tx_inperiod) > 8) ||
837 rtlpriv->link_info.num_rx_inperiod > 2)
838 rtl_lps_leave(hw, false);
839 skb = new_skb;
840 no_new:
841 if (rtlpriv->use_new_trx_flow) {
842 _rtl_pci_init_one_rxdesc(hw, skb, (u8 *)buffer_desc,
843 rxring_idx,
844 rtlpci->rx_ring[rxring_idx].idx);
845 } else {
846 _rtl_pci_init_one_rxdesc(hw, skb, (u8 *)pdesc,
847 rxring_idx,
848 rtlpci->rx_ring[rxring_idx].idx);
849 if (rtlpci->rx_ring[rxring_idx].idx ==
850 rtlpci->rxringcount - 1)
851 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc,
852 false,
853 HW_DESC_RXERO,
854 (u8 *)&tmp_one);
855 }
856 rtlpci->rx_ring[rxring_idx].idx =
857 (rtlpci->rx_ring[rxring_idx].idx + 1) %
858 rtlpci->rxringcount;
859 }
860 }
861
_rtl_pci_interrupt(int irq,void * dev_id)862 static irqreturn_t _rtl_pci_interrupt(int irq, void *dev_id)
863 {
864 struct ieee80211_hw *hw = dev_id;
865 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
866 struct rtl_priv *rtlpriv = rtl_priv(hw);
867 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
868 unsigned long flags;
869 struct rtl_int intvec = {0};
870
871 irqreturn_t ret = IRQ_HANDLED;
872
873 if (rtlpci->irq_enabled == 0)
874 return ret;
875
876 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
877 rtlpriv->cfg->ops->disable_interrupt(hw);
878
879 /*read ISR: 4/8bytes */
880 rtlpriv->cfg->ops->interrupt_recognized(hw, &intvec);
881
882 /*Shared IRQ or HW disappeared */
883 if (!intvec.inta || intvec.inta == 0xffff)
884 goto done;
885
886 /*<1> beacon related */
887 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_TBDOK])
888 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
889 "beacon ok interrupt!\n");
890
891 if (unlikely(intvec.inta & rtlpriv->cfg->maps[RTL_IMR_TBDER]))
892 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
893 "beacon err interrupt!\n");
894
895 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_BDOK])
896 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, "beacon interrupt!\n");
897
898 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_BCNINT]) {
899 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
900 "prepare beacon for interrupt!\n");
901 tasklet_schedule(&rtlpriv->works.irq_prepare_bcn_tasklet);
902 }
903
904 /*<2> Tx related */
905 if (unlikely(intvec.intb & rtlpriv->cfg->maps[RTL_IMR_TXFOVW]))
906 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, "IMR_TXFOVW!\n");
907
908 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_MGNTDOK]) {
909 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
910 "Manage ok interrupt!\n");
911 _rtl_pci_tx_isr(hw, MGNT_QUEUE);
912 }
913
914 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_HIGHDOK]) {
915 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
916 "HIGH_QUEUE ok interrupt!\n");
917 _rtl_pci_tx_isr(hw, HIGH_QUEUE);
918 }
919
920 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_BKDOK]) {
921 rtlpriv->link_info.num_tx_inperiod++;
922
923 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
924 "BK Tx OK interrupt!\n");
925 _rtl_pci_tx_isr(hw, BK_QUEUE);
926 }
927
928 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_BEDOK]) {
929 rtlpriv->link_info.num_tx_inperiod++;
930
931 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
932 "BE TX OK interrupt!\n");
933 _rtl_pci_tx_isr(hw, BE_QUEUE);
934 }
935
936 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_VIDOK]) {
937 rtlpriv->link_info.num_tx_inperiod++;
938
939 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
940 "VI TX OK interrupt!\n");
941 _rtl_pci_tx_isr(hw, VI_QUEUE);
942 }
943
944 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_VODOK]) {
945 rtlpriv->link_info.num_tx_inperiod++;
946
947 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
948 "Vo TX OK interrupt!\n");
949 _rtl_pci_tx_isr(hw, VO_QUEUE);
950 }
951
952 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8822BE) {
953 if (intvec.intd & rtlpriv->cfg->maps[RTL_IMR_H2CDOK]) {
954 rtlpriv->link_info.num_tx_inperiod++;
955
956 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
957 "H2C TX OK interrupt!\n");
958 _rtl_pci_tx_isr(hw, H2C_QUEUE);
959 }
960 }
961
962 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) {
963 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_COMDOK]) {
964 rtlpriv->link_info.num_tx_inperiod++;
965
966 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
967 "CMD TX OK interrupt!\n");
968 _rtl_pci_tx_isr(hw, TXCMD_QUEUE);
969 }
970 }
971
972 /*<3> Rx related */
973 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_ROK]) {
974 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, "Rx ok interrupt!\n");
975 _rtl_pci_rx_interrupt(hw);
976 }
977
978 if (unlikely(intvec.inta & rtlpriv->cfg->maps[RTL_IMR_RDU])) {
979 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
980 "rx descriptor unavailable!\n");
981 _rtl_pci_rx_interrupt(hw);
982 }
983
984 if (unlikely(intvec.intb & rtlpriv->cfg->maps[RTL_IMR_RXFOVW])) {
985 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, "rx overflow !\n");
986 _rtl_pci_rx_interrupt(hw);
987 }
988
989 /*<4> fw related*/
990 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8723AE) {
991 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_C2HCMD]) {
992 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
993 "firmware interrupt!\n");
994 queue_delayed_work(rtlpriv->works.rtl_wq,
995 &rtlpriv->works.fwevt_wq, 0);
996 }
997 }
998
999 /*<5> hsisr related*/
1000 /* Only 8188EE & 8723BE Supported.
1001 * If Other ICs Come in, System will corrupt,
1002 * because maps[RTL_IMR_HSISR_IND] & maps[MAC_HSISR]
1003 * are not initialized
1004 */
1005 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8188EE ||
1006 rtlhal->hw_type == HARDWARE_TYPE_RTL8723BE) {
1007 if (unlikely(intvec.inta &
1008 rtlpriv->cfg->maps[RTL_IMR_HSISR_IND])) {
1009 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
1010 "hsisr interrupt!\n");
1011 _rtl_pci_hs_interrupt(hw);
1012 }
1013 }
1014
1015 if (rtlpriv->rtlhal.earlymode_enable)
1016 tasklet_schedule(&rtlpriv->works.irq_tasklet);
1017
1018 done:
1019 rtlpriv->cfg->ops->enable_interrupt(hw);
1020 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1021 return ret;
1022 }
1023
_rtl_pci_irq_tasklet(struct tasklet_struct * t)1024 static void _rtl_pci_irq_tasklet(struct tasklet_struct *t)
1025 {
1026 struct rtl_priv *rtlpriv = from_tasklet(rtlpriv, t, works.irq_tasklet);
1027 struct ieee80211_hw *hw = rtlpriv->hw;
1028 _rtl_pci_tx_chk_waitq(hw);
1029 }
1030
_rtl_pci_prepare_bcn_tasklet(struct tasklet_struct * t)1031 static void _rtl_pci_prepare_bcn_tasklet(struct tasklet_struct *t)
1032 {
1033 struct rtl_priv *rtlpriv = from_tasklet(rtlpriv, t,
1034 works.irq_prepare_bcn_tasklet);
1035 struct ieee80211_hw *hw = rtlpriv->hw;
1036 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1037 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1038 struct rtl8192_tx_ring *ring = NULL;
1039 struct ieee80211_hdr *hdr = NULL;
1040 struct ieee80211_tx_info *info = NULL;
1041 struct sk_buff *pskb = NULL;
1042 struct rtl_tx_desc *pdesc = NULL;
1043 struct rtl_tcb_desc tcb_desc;
1044 /*This is for new trx flow*/
1045 struct rtl_tx_buffer_desc *pbuffer_desc = NULL;
1046 u8 temp_one = 1;
1047 u8 *entry;
1048
1049 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc));
1050 ring = &rtlpci->tx_ring[BEACON_QUEUE];
1051 pskb = __skb_dequeue(&ring->queue);
1052 if (rtlpriv->use_new_trx_flow)
1053 entry = (u8 *)(&ring->buffer_desc[ring->idx]);
1054 else
1055 entry = (u8 *)(&ring->desc[ring->idx]);
1056 if (pskb) {
1057 dma_unmap_single(&rtlpci->pdev->dev,
1058 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry,
1059 true, HW_DESC_TXBUFF_ADDR),
1060 pskb->len, DMA_TO_DEVICE);
1061 kfree_skb(pskb);
1062 }
1063
1064 /*NB: the beacon data buffer must be 32-bit aligned. */
1065 pskb = ieee80211_beacon_get(hw, mac->vif);
1066 if (!pskb)
1067 return;
1068 hdr = rtl_get_hdr(pskb);
1069 info = IEEE80211_SKB_CB(pskb);
1070 pdesc = &ring->desc[0];
1071 if (rtlpriv->use_new_trx_flow)
1072 pbuffer_desc = &ring->buffer_desc[0];
1073
1074 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *)pdesc,
1075 (u8 *)pbuffer_desc, info, NULL, pskb,
1076 BEACON_QUEUE, &tcb_desc);
1077
1078 __skb_queue_tail(&ring->queue, pskb);
1079
1080 if (rtlpriv->use_new_trx_flow) {
1081 temp_one = 4;
1082 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pbuffer_desc, true,
1083 HW_DESC_OWN, (u8 *)&temp_one);
1084 } else {
1085 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true, HW_DESC_OWN,
1086 &temp_one);
1087 }
1088 }
1089
_rtl_pci_init_trx_var(struct ieee80211_hw * hw)1090 static void _rtl_pci_init_trx_var(struct ieee80211_hw *hw)
1091 {
1092 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1093 struct rtl_priv *rtlpriv = rtl_priv(hw);
1094 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1095 u8 i;
1096 u16 desc_num;
1097
1098 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192EE)
1099 desc_num = TX_DESC_NUM_92E;
1100 else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8822BE)
1101 desc_num = TX_DESC_NUM_8822B;
1102 else
1103 desc_num = RT_TXDESC_NUM;
1104
1105 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1106 rtlpci->txringcount[i] = desc_num;
1107
1108 /*we just alloc 2 desc for beacon queue,
1109 *because we just need first desc in hw beacon.
1110 */
1111 rtlpci->txringcount[BEACON_QUEUE] = 2;
1112
1113 /*BE queue need more descriptor for performance
1114 *consideration or, No more tx desc will happen,
1115 *and may cause mac80211 mem leakage.
1116 */
1117 if (!rtl_priv(hw)->use_new_trx_flow)
1118 rtlpci->txringcount[BE_QUEUE] = RT_TXDESC_NUM_BE_QUEUE;
1119
1120 rtlpci->rxbuffersize = 9100; /*2048/1024; */
1121 rtlpci->rxringcount = RTL_PCI_MAX_RX_COUNT; /*64; */
1122 }
1123
_rtl_pci_init_struct(struct ieee80211_hw * hw,struct pci_dev * pdev)1124 static void _rtl_pci_init_struct(struct ieee80211_hw *hw,
1125 struct pci_dev *pdev)
1126 {
1127 struct rtl_priv *rtlpriv = rtl_priv(hw);
1128 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1129 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1130 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1131
1132 rtlpci->up_first_time = true;
1133 rtlpci->being_init_adapter = false;
1134
1135 rtlhal->hw = hw;
1136 rtlpci->pdev = pdev;
1137
1138 /*Tx/Rx related var */
1139 _rtl_pci_init_trx_var(hw);
1140
1141 /*IBSS*/
1142 mac->beacon_interval = 100;
1143
1144 /*AMPDU*/
1145 mac->min_space_cfg = 0;
1146 mac->max_mss_density = 0;
1147 /*set sane AMPDU defaults */
1148 mac->current_ampdu_density = 7;
1149 mac->current_ampdu_factor = 3;
1150
1151 /*Retry Limit*/
1152 mac->retry_short = 7;
1153 mac->retry_long = 7;
1154
1155 /*QOS*/
1156 rtlpci->acm_method = EACMWAY2_SW;
1157
1158 /*task */
1159 tasklet_setup(&rtlpriv->works.irq_tasklet, _rtl_pci_irq_tasklet);
1160 tasklet_setup(&rtlpriv->works.irq_prepare_bcn_tasklet,
1161 _rtl_pci_prepare_bcn_tasklet);
1162 INIT_WORK(&rtlpriv->works.lps_change_work,
1163 rtl_lps_change_work_callback);
1164 }
1165
_rtl_pci_init_tx_ring(struct ieee80211_hw * hw,unsigned int prio,unsigned int entries)1166 static int _rtl_pci_init_tx_ring(struct ieee80211_hw *hw,
1167 unsigned int prio, unsigned int entries)
1168 {
1169 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1170 struct rtl_priv *rtlpriv = rtl_priv(hw);
1171 struct rtl_tx_buffer_desc *buffer_desc;
1172 struct rtl_tx_desc *desc;
1173 dma_addr_t buffer_desc_dma, desc_dma;
1174 u32 nextdescaddress;
1175 int i;
1176
1177 /* alloc tx buffer desc for new trx flow*/
1178 if (rtlpriv->use_new_trx_flow) {
1179 buffer_desc =
1180 dma_alloc_coherent(&rtlpci->pdev->dev,
1181 sizeof(*buffer_desc) * entries,
1182 &buffer_desc_dma, GFP_KERNEL);
1183
1184 if (!buffer_desc || (unsigned long)buffer_desc & 0xFF) {
1185 pr_err("Cannot allocate TX ring (prio = %d)\n",
1186 prio);
1187 return -ENOMEM;
1188 }
1189
1190 rtlpci->tx_ring[prio].buffer_desc = buffer_desc;
1191 rtlpci->tx_ring[prio].buffer_desc_dma = buffer_desc_dma;
1192
1193 rtlpci->tx_ring[prio].cur_tx_rp = 0;
1194 rtlpci->tx_ring[prio].cur_tx_wp = 0;
1195 }
1196
1197 /* alloc dma for this ring */
1198 desc = dma_alloc_coherent(&rtlpci->pdev->dev, sizeof(*desc) * entries,
1199 &desc_dma, GFP_KERNEL);
1200
1201 if (!desc || (unsigned long)desc & 0xFF) {
1202 pr_err("Cannot allocate TX ring (prio = %d)\n", prio);
1203 return -ENOMEM;
1204 }
1205
1206 rtlpci->tx_ring[prio].desc = desc;
1207 rtlpci->tx_ring[prio].dma = desc_dma;
1208
1209 rtlpci->tx_ring[prio].idx = 0;
1210 rtlpci->tx_ring[prio].entries = entries;
1211 skb_queue_head_init(&rtlpci->tx_ring[prio].queue);
1212
1213 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "queue:%d, ring_addr:%p\n",
1214 prio, desc);
1215
1216 /* init every desc in this ring */
1217 if (!rtlpriv->use_new_trx_flow) {
1218 for (i = 0; i < entries; i++) {
1219 nextdescaddress = (u32)desc_dma +
1220 ((i + 1) % entries) *
1221 sizeof(*desc);
1222
1223 rtlpriv->cfg->ops->set_desc(hw, (u8 *)&desc[i],
1224 true,
1225 HW_DESC_TX_NEXTDESC_ADDR,
1226 (u8 *)&nextdescaddress);
1227 }
1228 }
1229 return 0;
1230 }
1231
_rtl_pci_init_rx_ring(struct ieee80211_hw * hw,int rxring_idx)1232 static int _rtl_pci_init_rx_ring(struct ieee80211_hw *hw, int rxring_idx)
1233 {
1234 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1235 struct rtl_priv *rtlpriv = rtl_priv(hw);
1236 int i;
1237
1238 if (rtlpriv->use_new_trx_flow) {
1239 struct rtl_rx_buffer_desc *entry = NULL;
1240 /* alloc dma for this ring */
1241 rtlpci->rx_ring[rxring_idx].buffer_desc =
1242 dma_alloc_coherent(&rtlpci->pdev->dev,
1243 sizeof(*rtlpci->rx_ring[rxring_idx].buffer_desc) *
1244 rtlpci->rxringcount,
1245 &rtlpci->rx_ring[rxring_idx].dma, GFP_KERNEL);
1246 if (!rtlpci->rx_ring[rxring_idx].buffer_desc ||
1247 (ulong)rtlpci->rx_ring[rxring_idx].buffer_desc & 0xFF) {
1248 pr_err("Cannot allocate RX ring\n");
1249 return -ENOMEM;
1250 }
1251
1252 /* init every desc in this ring */
1253 rtlpci->rx_ring[rxring_idx].idx = 0;
1254 for (i = 0; i < rtlpci->rxringcount; i++) {
1255 entry = &rtlpci->rx_ring[rxring_idx].buffer_desc[i];
1256 if (!_rtl_pci_init_one_rxdesc(hw, NULL, (u8 *)entry,
1257 rxring_idx, i))
1258 return -ENOMEM;
1259 }
1260 } else {
1261 struct rtl_rx_desc *entry = NULL;
1262 u8 tmp_one = 1;
1263 /* alloc dma for this ring */
1264 rtlpci->rx_ring[rxring_idx].desc =
1265 dma_alloc_coherent(&rtlpci->pdev->dev,
1266 sizeof(*rtlpci->rx_ring[rxring_idx].desc) *
1267 rtlpci->rxringcount,
1268 &rtlpci->rx_ring[rxring_idx].dma, GFP_KERNEL);
1269 if (!rtlpci->rx_ring[rxring_idx].desc ||
1270 (unsigned long)rtlpci->rx_ring[rxring_idx].desc & 0xFF) {
1271 pr_err("Cannot allocate RX ring\n");
1272 return -ENOMEM;
1273 }
1274
1275 /* init every desc in this ring */
1276 rtlpci->rx_ring[rxring_idx].idx = 0;
1277
1278 for (i = 0; i < rtlpci->rxringcount; i++) {
1279 entry = &rtlpci->rx_ring[rxring_idx].desc[i];
1280 if (!_rtl_pci_init_one_rxdesc(hw, NULL, (u8 *)entry,
1281 rxring_idx, i))
1282 return -ENOMEM;
1283 }
1284
1285 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
1286 HW_DESC_RXERO, &tmp_one);
1287 }
1288 return 0;
1289 }
1290
_rtl_pci_free_tx_ring(struct ieee80211_hw * hw,unsigned int prio)1291 static void _rtl_pci_free_tx_ring(struct ieee80211_hw *hw,
1292 unsigned int prio)
1293 {
1294 struct rtl_priv *rtlpriv = rtl_priv(hw);
1295 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1296 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
1297
1298 /* free every desc in this ring */
1299 while (skb_queue_len(&ring->queue)) {
1300 u8 *entry;
1301 struct sk_buff *skb = __skb_dequeue(&ring->queue);
1302
1303 if (rtlpriv->use_new_trx_flow)
1304 entry = (u8 *)(&ring->buffer_desc[ring->idx]);
1305 else
1306 entry = (u8 *)(&ring->desc[ring->idx]);
1307
1308 dma_unmap_single(&rtlpci->pdev->dev,
1309 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry,
1310 true, HW_DESC_TXBUFF_ADDR),
1311 skb->len, DMA_TO_DEVICE);
1312 kfree_skb(skb);
1313 ring->idx = (ring->idx + 1) % ring->entries;
1314 }
1315
1316 /* free dma of this ring */
1317 dma_free_coherent(&rtlpci->pdev->dev,
1318 sizeof(*ring->desc) * ring->entries, ring->desc,
1319 ring->dma);
1320 ring->desc = NULL;
1321 if (rtlpriv->use_new_trx_flow) {
1322 dma_free_coherent(&rtlpci->pdev->dev,
1323 sizeof(*ring->buffer_desc) * ring->entries,
1324 ring->buffer_desc, ring->buffer_desc_dma);
1325 ring->buffer_desc = NULL;
1326 }
1327 }
1328
_rtl_pci_free_rx_ring(struct ieee80211_hw * hw,int rxring_idx)1329 static void _rtl_pci_free_rx_ring(struct ieee80211_hw *hw, int rxring_idx)
1330 {
1331 struct rtl_priv *rtlpriv = rtl_priv(hw);
1332 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1333 int i;
1334
1335 /* free every desc in this ring */
1336 for (i = 0; i < rtlpci->rxringcount; i++) {
1337 struct sk_buff *skb = rtlpci->rx_ring[rxring_idx].rx_buf[i];
1338
1339 if (!skb)
1340 continue;
1341 dma_unmap_single(&rtlpci->pdev->dev, *((dma_addr_t *)skb->cb),
1342 rtlpci->rxbuffersize, DMA_FROM_DEVICE);
1343 kfree_skb(skb);
1344 }
1345
1346 /* free dma of this ring */
1347 if (rtlpriv->use_new_trx_flow) {
1348 dma_free_coherent(&rtlpci->pdev->dev,
1349 sizeof(*rtlpci->rx_ring[rxring_idx].buffer_desc) *
1350 rtlpci->rxringcount,
1351 rtlpci->rx_ring[rxring_idx].buffer_desc,
1352 rtlpci->rx_ring[rxring_idx].dma);
1353 rtlpci->rx_ring[rxring_idx].buffer_desc = NULL;
1354 } else {
1355 dma_free_coherent(&rtlpci->pdev->dev,
1356 sizeof(*rtlpci->rx_ring[rxring_idx].desc) *
1357 rtlpci->rxringcount,
1358 rtlpci->rx_ring[rxring_idx].desc,
1359 rtlpci->rx_ring[rxring_idx].dma);
1360 rtlpci->rx_ring[rxring_idx].desc = NULL;
1361 }
1362 }
1363
_rtl_pci_init_trx_ring(struct ieee80211_hw * hw)1364 static int _rtl_pci_init_trx_ring(struct ieee80211_hw *hw)
1365 {
1366 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1367 int ret;
1368 int i, rxring_idx;
1369
1370 /* rxring_idx 0:RX_MPDU_QUEUE
1371 * rxring_idx 1:RX_CMD_QUEUE
1372 */
1373 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) {
1374 ret = _rtl_pci_init_rx_ring(hw, rxring_idx);
1375 if (ret)
1376 return ret;
1377 }
1378
1379 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
1380 ret = _rtl_pci_init_tx_ring(hw, i, rtlpci->txringcount[i]);
1381 if (ret)
1382 goto err_free_rings;
1383 }
1384
1385 return 0;
1386
1387 err_free_rings:
1388 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++)
1389 _rtl_pci_free_rx_ring(hw, rxring_idx);
1390
1391 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1392 if (rtlpci->tx_ring[i].desc ||
1393 rtlpci->tx_ring[i].buffer_desc)
1394 _rtl_pci_free_tx_ring(hw, i);
1395
1396 return 1;
1397 }
1398
_rtl_pci_deinit_trx_ring(struct ieee80211_hw * hw)1399 static int _rtl_pci_deinit_trx_ring(struct ieee80211_hw *hw)
1400 {
1401 u32 i, rxring_idx;
1402
1403 /*free rx rings */
1404 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++)
1405 _rtl_pci_free_rx_ring(hw, rxring_idx);
1406
1407 /*free tx rings */
1408 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1409 _rtl_pci_free_tx_ring(hw, i);
1410
1411 return 0;
1412 }
1413
rtl_pci_reset_trx_ring(struct ieee80211_hw * hw)1414 int rtl_pci_reset_trx_ring(struct ieee80211_hw *hw)
1415 {
1416 struct rtl_priv *rtlpriv = rtl_priv(hw);
1417 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1418 int i, rxring_idx;
1419 unsigned long flags;
1420 u8 tmp_one = 1;
1421 u32 bufferaddress;
1422 /* rxring_idx 0:RX_MPDU_QUEUE */
1423 /* rxring_idx 1:RX_CMD_QUEUE */
1424 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) {
1425 /* force the rx_ring[RX_MPDU_QUEUE/
1426 * RX_CMD_QUEUE].idx to the first one
1427 *new trx flow, do nothing
1428 */
1429 if (!rtlpriv->use_new_trx_flow &&
1430 rtlpci->rx_ring[rxring_idx].desc) {
1431 struct rtl_rx_desc *entry = NULL;
1432
1433 rtlpci->rx_ring[rxring_idx].idx = 0;
1434 for (i = 0; i < rtlpci->rxringcount; i++) {
1435 entry = &rtlpci->rx_ring[rxring_idx].desc[i];
1436 bufferaddress =
1437 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry,
1438 false, HW_DESC_RXBUFF_ADDR);
1439 memset((u8 *)entry, 0,
1440 sizeof(*rtlpci->rx_ring
1441 [rxring_idx].desc));/*clear one entry*/
1442 if (rtlpriv->use_new_trx_flow) {
1443 rtlpriv->cfg->ops->set_desc(hw,
1444 (u8 *)entry, false,
1445 HW_DESC_RX_PREPARE,
1446 (u8 *)&bufferaddress);
1447 } else {
1448 rtlpriv->cfg->ops->set_desc(hw,
1449 (u8 *)entry, false,
1450 HW_DESC_RXBUFF_ADDR,
1451 (u8 *)&bufferaddress);
1452 rtlpriv->cfg->ops->set_desc(hw,
1453 (u8 *)entry, false,
1454 HW_DESC_RXPKT_LEN,
1455 (u8 *)&rtlpci->rxbuffersize);
1456 rtlpriv->cfg->ops->set_desc(hw,
1457 (u8 *)entry, false,
1458 HW_DESC_RXOWN,
1459 (u8 *)&tmp_one);
1460 }
1461 }
1462 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
1463 HW_DESC_RXERO, (u8 *)&tmp_one);
1464 }
1465 rtlpci->rx_ring[rxring_idx].idx = 0;
1466 }
1467
1468 /*after reset, release previous pending packet,
1469 *and force the tx idx to the first one
1470 */
1471 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
1472 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
1473 if (rtlpci->tx_ring[i].desc ||
1474 rtlpci->tx_ring[i].buffer_desc) {
1475 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[i];
1476
1477 while (skb_queue_len(&ring->queue)) {
1478 u8 *entry;
1479 struct sk_buff *skb =
1480 __skb_dequeue(&ring->queue);
1481 if (rtlpriv->use_new_trx_flow)
1482 entry = (u8 *)(&ring->buffer_desc
1483 [ring->idx]);
1484 else
1485 entry = (u8 *)(&ring->desc[ring->idx]);
1486
1487 dma_unmap_single(&rtlpci->pdev->dev,
1488 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry,
1489 true, HW_DESC_TXBUFF_ADDR),
1490 skb->len, DMA_TO_DEVICE);
1491 dev_kfree_skb_irq(skb);
1492 ring->idx = (ring->idx + 1) % ring->entries;
1493 }
1494
1495 if (rtlpriv->use_new_trx_flow) {
1496 rtlpci->tx_ring[i].cur_tx_rp = 0;
1497 rtlpci->tx_ring[i].cur_tx_wp = 0;
1498 }
1499
1500 ring->idx = 0;
1501 ring->entries = rtlpci->txringcount[i];
1502 }
1503 }
1504 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1505
1506 return 0;
1507 }
1508
rtl_pci_tx_chk_waitq_insert(struct ieee80211_hw * hw,struct ieee80211_sta * sta,struct sk_buff * skb)1509 static bool rtl_pci_tx_chk_waitq_insert(struct ieee80211_hw *hw,
1510 struct ieee80211_sta *sta,
1511 struct sk_buff *skb)
1512 {
1513 struct rtl_priv *rtlpriv = rtl_priv(hw);
1514 struct rtl_sta_info *sta_entry = NULL;
1515 u8 tid = rtl_get_tid(skb);
1516 __le16 fc = rtl_get_fc(skb);
1517
1518 if (!sta)
1519 return false;
1520 sta_entry = (struct rtl_sta_info *)sta->drv_priv;
1521
1522 if (!rtlpriv->rtlhal.earlymode_enable)
1523 return false;
1524 if (ieee80211_is_nullfunc(fc))
1525 return false;
1526 if (ieee80211_is_qos_nullfunc(fc))
1527 return false;
1528 if (ieee80211_is_pspoll(fc))
1529 return false;
1530 if (sta_entry->tids[tid].agg.agg_state != RTL_AGG_OPERATIONAL)
1531 return false;
1532 if (_rtl_mac_to_hwqueue(hw, skb) > VO_QUEUE)
1533 return false;
1534 if (tid > 7)
1535 return false;
1536
1537 /* maybe every tid should be checked */
1538 if (!rtlpriv->link_info.higher_busytxtraffic[tid])
1539 return false;
1540
1541 spin_lock_bh(&rtlpriv->locks.waitq_lock);
1542 skb_queue_tail(&rtlpriv->mac80211.skb_waitq[tid], skb);
1543 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
1544
1545 return true;
1546 }
1547
rtl_pci_tx(struct ieee80211_hw * hw,struct ieee80211_sta * sta,struct sk_buff * skb,struct rtl_tcb_desc * ptcb_desc)1548 static int rtl_pci_tx(struct ieee80211_hw *hw,
1549 struct ieee80211_sta *sta,
1550 struct sk_buff *skb,
1551 struct rtl_tcb_desc *ptcb_desc)
1552 {
1553 struct rtl_priv *rtlpriv = rtl_priv(hw);
1554 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1555 struct rtl8192_tx_ring *ring;
1556 struct rtl_tx_desc *pdesc;
1557 struct rtl_tx_buffer_desc *ptx_bd_desc = NULL;
1558 u16 idx;
1559 u8 hw_queue = _rtl_mac_to_hwqueue(hw, skb);
1560 unsigned long flags;
1561 struct ieee80211_hdr *hdr = rtl_get_hdr(skb);
1562 __le16 fc = rtl_get_fc(skb);
1563 u8 *pda_addr = hdr->addr1;
1564 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1565 u8 own;
1566 u8 temp_one = 1;
1567
1568 if (ieee80211_is_mgmt(fc))
1569 rtl_tx_mgmt_proc(hw, skb);
1570
1571 if (rtlpriv->psc.sw_ps_enabled) {
1572 if (ieee80211_is_data(fc) && !ieee80211_is_nullfunc(fc) &&
1573 !ieee80211_has_pm(fc))
1574 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
1575 }
1576
1577 rtl_action_proc(hw, skb, true);
1578
1579 if (is_multicast_ether_addr(pda_addr))
1580 rtlpriv->stats.txbytesmulticast += skb->len;
1581 else if (is_broadcast_ether_addr(pda_addr))
1582 rtlpriv->stats.txbytesbroadcast += skb->len;
1583 else
1584 rtlpriv->stats.txbytesunicast += skb->len;
1585
1586 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
1587 ring = &rtlpci->tx_ring[hw_queue];
1588 if (hw_queue != BEACON_QUEUE) {
1589 if (rtlpriv->use_new_trx_flow)
1590 idx = ring->cur_tx_wp;
1591 else
1592 idx = (ring->idx + skb_queue_len(&ring->queue)) %
1593 ring->entries;
1594 } else {
1595 idx = 0;
1596 }
1597
1598 pdesc = &ring->desc[idx];
1599 if (rtlpriv->use_new_trx_flow) {
1600 ptx_bd_desc = &ring->buffer_desc[idx];
1601 } else {
1602 own = (u8)rtlpriv->cfg->ops->get_desc(hw, (u8 *)pdesc,
1603 true, HW_DESC_OWN);
1604
1605 if (own == 1 && hw_queue != BEACON_QUEUE) {
1606 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
1607 "No more TX desc@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%x\n",
1608 hw_queue, ring->idx, idx,
1609 skb_queue_len(&ring->queue));
1610
1611 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock,
1612 flags);
1613 return skb->len;
1614 }
1615 }
1616
1617 if (rtlpriv->cfg->ops->get_available_desc &&
1618 rtlpriv->cfg->ops->get_available_desc(hw, hw_queue) == 0) {
1619 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
1620 "get_available_desc fail\n");
1621 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1622 return skb->len;
1623 }
1624
1625 if (ieee80211_is_data(fc))
1626 rtlpriv->cfg->ops->led_control(hw, LED_CTL_TX);
1627
1628 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *)pdesc,
1629 (u8 *)ptx_bd_desc, info, sta, skb, hw_queue, ptcb_desc);
1630
1631 __skb_queue_tail(&ring->queue, skb);
1632
1633 if (rtlpriv->use_new_trx_flow) {
1634 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true,
1635 HW_DESC_OWN, &hw_queue);
1636 } else {
1637 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true,
1638 HW_DESC_OWN, &temp_one);
1639 }
1640
1641 if ((ring->entries - skb_queue_len(&ring->queue)) < 2 &&
1642 hw_queue != BEACON_QUEUE) {
1643 rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD,
1644 "less desc left, stop skb_queue@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%x\n",
1645 hw_queue, ring->idx, idx,
1646 skb_queue_len(&ring->queue));
1647
1648 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
1649 }
1650
1651 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1652
1653 rtlpriv->cfg->ops->tx_polling(hw, hw_queue);
1654
1655 return 0;
1656 }
1657
rtl_pci_flush(struct ieee80211_hw * hw,u32 queues,bool drop)1658 static void rtl_pci_flush(struct ieee80211_hw *hw, u32 queues, bool drop)
1659 {
1660 struct rtl_priv *rtlpriv = rtl_priv(hw);
1661 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1662 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1663 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1664 u16 i = 0;
1665 int queue_id;
1666 struct rtl8192_tx_ring *ring;
1667
1668 if (mac->skip_scan)
1669 return;
1670
1671 for (queue_id = RTL_PCI_MAX_TX_QUEUE_COUNT - 1; queue_id >= 0;) {
1672 u32 queue_len;
1673
1674 if (((queues >> queue_id) & 0x1) == 0) {
1675 queue_id--;
1676 continue;
1677 }
1678 ring = &pcipriv->dev.tx_ring[queue_id];
1679 queue_len = skb_queue_len(&ring->queue);
1680 if (queue_len == 0 || queue_id == BEACON_QUEUE ||
1681 queue_id == TXCMD_QUEUE) {
1682 queue_id--;
1683 continue;
1684 } else {
1685 msleep(20);
1686 i++;
1687 }
1688
1689 /* we just wait 1s for all queues */
1690 if (rtlpriv->psc.rfpwr_state == ERFOFF ||
1691 is_hal_stop(rtlhal) || i >= 200)
1692 return;
1693 }
1694 }
1695
rtl_pci_deinit(struct ieee80211_hw * hw)1696 static void rtl_pci_deinit(struct ieee80211_hw *hw)
1697 {
1698 struct rtl_priv *rtlpriv = rtl_priv(hw);
1699 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1700
1701 _rtl_pci_deinit_trx_ring(hw);
1702
1703 synchronize_irq(rtlpci->pdev->irq);
1704 tasklet_kill(&rtlpriv->works.irq_tasklet);
1705 cancel_work_sync(&rtlpriv->works.lps_change_work);
1706
1707 flush_workqueue(rtlpriv->works.rtl_wq);
1708 destroy_workqueue(rtlpriv->works.rtl_wq);
1709 }
1710
rtl_pci_init(struct ieee80211_hw * hw,struct pci_dev * pdev)1711 static int rtl_pci_init(struct ieee80211_hw *hw, struct pci_dev *pdev)
1712 {
1713 int err;
1714
1715 _rtl_pci_init_struct(hw, pdev);
1716
1717 err = _rtl_pci_init_trx_ring(hw);
1718 if (err) {
1719 pr_err("tx ring initialization failed\n");
1720 return err;
1721 }
1722
1723 return 0;
1724 }
1725
rtl_pci_start(struct ieee80211_hw * hw)1726 static int rtl_pci_start(struct ieee80211_hw *hw)
1727 {
1728 struct rtl_priv *rtlpriv = rtl_priv(hw);
1729 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1730 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1731 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1732 struct rtl_mac *rtlmac = rtl_mac(rtl_priv(hw));
1733 struct rtl_btc_ops *btc_ops = rtlpriv->btcoexist.btc_ops;
1734
1735 int err;
1736
1737 rtl_pci_reset_trx_ring(hw);
1738
1739 rtlpci->driver_is_goingto_unload = false;
1740 if (rtlpriv->cfg->ops->get_btc_status &&
1741 rtlpriv->cfg->ops->get_btc_status()) {
1742 rtlpriv->btcoexist.btc_info.ap_num = 36;
1743 btc_ops->btc_init_variables(rtlpriv);
1744 btc_ops->btc_init_hal_vars(rtlpriv);
1745 } else if (btc_ops) {
1746 btc_ops->btc_init_variables_wifi_only(rtlpriv);
1747 }
1748
1749 err = rtlpriv->cfg->ops->hw_init(hw);
1750 if (err) {
1751 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
1752 "Failed to config hardware!\n");
1753 kfree(rtlpriv->btcoexist.btc_context);
1754 kfree(rtlpriv->btcoexist.wifi_only_context);
1755 return err;
1756 }
1757 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RETRY_LIMIT,
1758 &rtlmac->retry_long);
1759
1760 rtlpriv->cfg->ops->enable_interrupt(hw);
1761 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "enable_interrupt OK\n");
1762
1763 rtl_init_rx_config(hw);
1764
1765 /*should be after adapter start and interrupt enable. */
1766 set_hal_start(rtlhal);
1767
1768 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1769
1770 rtlpci->up_first_time = false;
1771
1772 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "%s OK\n", __func__);
1773 return 0;
1774 }
1775
rtl_pci_stop(struct ieee80211_hw * hw)1776 static void rtl_pci_stop(struct ieee80211_hw *hw)
1777 {
1778 struct rtl_priv *rtlpriv = rtl_priv(hw);
1779 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1780 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1781 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1782 unsigned long flags;
1783 u8 rf_timeout = 0;
1784
1785 if (rtlpriv->cfg->ops->get_btc_status())
1786 rtlpriv->btcoexist.btc_ops->btc_halt_notify(rtlpriv);
1787
1788 if (rtlpriv->btcoexist.btc_ops)
1789 rtlpriv->btcoexist.btc_ops->btc_deinit_variables(rtlpriv);
1790
1791 /*should be before disable interrupt&adapter
1792 *and will do it immediately.
1793 */
1794 set_hal_stop(rtlhal);
1795
1796 rtlpci->driver_is_goingto_unload = true;
1797 rtlpriv->cfg->ops->disable_interrupt(hw);
1798 cancel_work_sync(&rtlpriv->works.lps_change_work);
1799
1800 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1801 while (ppsc->rfchange_inprogress) {
1802 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1803 if (rf_timeout > 100) {
1804 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1805 break;
1806 }
1807 mdelay(1);
1808 rf_timeout++;
1809 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1810 }
1811 ppsc->rfchange_inprogress = true;
1812 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1813
1814 rtlpriv->cfg->ops->hw_disable(hw);
1815 /* some things are not needed if firmware not available */
1816 if (!rtlpriv->max_fw_size)
1817 return;
1818 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1819
1820 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1821 ppsc->rfchange_inprogress = false;
1822 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1823
1824 rtl_pci_enable_aspm(hw);
1825 }
1826
_rtl_pci_find_adapter(struct pci_dev * pdev,struct ieee80211_hw * hw)1827 static bool _rtl_pci_find_adapter(struct pci_dev *pdev,
1828 struct ieee80211_hw *hw)
1829 {
1830 struct rtl_priv *rtlpriv = rtl_priv(hw);
1831 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1832 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1833 struct pci_dev *bridge_pdev = pdev->bus->self;
1834 u16 venderid;
1835 u16 deviceid;
1836 u8 revisionid;
1837 u16 irqline;
1838 u8 tmp;
1839
1840 pcipriv->ndis_adapter.pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN;
1841 venderid = pdev->vendor;
1842 deviceid = pdev->device;
1843 pci_read_config_byte(pdev, 0x8, &revisionid);
1844 pci_read_config_word(pdev, 0x3C, &irqline);
1845
1846 /* PCI ID 0x10ec:0x8192 occurs for both RTL8192E, which uses
1847 * r8192e_pci, and RTL8192SE, which uses this driver. If the
1848 * revision ID is RTL_PCI_REVISION_ID_8192PCIE (0x01), then
1849 * the correct driver is r8192e_pci, thus this routine should
1850 * return false.
1851 */
1852 if (deviceid == RTL_PCI_8192SE_DID &&
1853 revisionid == RTL_PCI_REVISION_ID_8192PCIE)
1854 return false;
1855
1856 if (deviceid == RTL_PCI_8192_DID ||
1857 deviceid == RTL_PCI_0044_DID ||
1858 deviceid == RTL_PCI_0047_DID ||
1859 deviceid == RTL_PCI_8192SE_DID ||
1860 deviceid == RTL_PCI_8174_DID ||
1861 deviceid == RTL_PCI_8173_DID ||
1862 deviceid == RTL_PCI_8172_DID ||
1863 deviceid == RTL_PCI_8171_DID) {
1864 switch (revisionid) {
1865 case RTL_PCI_REVISION_ID_8192PCIE:
1866 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
1867 "8192 PCI-E is found - vid/did=%x/%x\n",
1868 venderid, deviceid);
1869 rtlhal->hw_type = HARDWARE_TYPE_RTL8192E;
1870 return false;
1871 case RTL_PCI_REVISION_ID_8192SE:
1872 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
1873 "8192SE is found - vid/did=%x/%x\n",
1874 venderid, deviceid);
1875 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
1876 break;
1877 default:
1878 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
1879 "Err: Unknown device - vid/did=%x/%x\n",
1880 venderid, deviceid);
1881 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
1882 break;
1883 }
1884 } else if (deviceid == RTL_PCI_8723AE_DID) {
1885 rtlhal->hw_type = HARDWARE_TYPE_RTL8723AE;
1886 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
1887 "8723AE PCI-E is found - vid/did=%x/%x\n",
1888 venderid, deviceid);
1889 } else if (deviceid == RTL_PCI_8192CET_DID ||
1890 deviceid == RTL_PCI_8192CE_DID ||
1891 deviceid == RTL_PCI_8191CE_DID ||
1892 deviceid == RTL_PCI_8188CE_DID) {
1893 rtlhal->hw_type = HARDWARE_TYPE_RTL8192CE;
1894 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
1895 "8192C PCI-E is found - vid/did=%x/%x\n",
1896 venderid, deviceid);
1897 } else if (deviceid == RTL_PCI_8192DE_DID ||
1898 deviceid == RTL_PCI_8192DE_DID2) {
1899 rtlhal->hw_type = HARDWARE_TYPE_RTL8192DE;
1900 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
1901 "8192D PCI-E is found - vid/did=%x/%x\n",
1902 venderid, deviceid);
1903 } else if (deviceid == RTL_PCI_8188EE_DID) {
1904 rtlhal->hw_type = HARDWARE_TYPE_RTL8188EE;
1905 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1906 "Find adapter, Hardware type is 8188EE\n");
1907 } else if (deviceid == RTL_PCI_8723BE_DID) {
1908 rtlhal->hw_type = HARDWARE_TYPE_RTL8723BE;
1909 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1910 "Find adapter, Hardware type is 8723BE\n");
1911 } else if (deviceid == RTL_PCI_8192EE_DID) {
1912 rtlhal->hw_type = HARDWARE_TYPE_RTL8192EE;
1913 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1914 "Find adapter, Hardware type is 8192EE\n");
1915 } else if (deviceid == RTL_PCI_8821AE_DID) {
1916 rtlhal->hw_type = HARDWARE_TYPE_RTL8821AE;
1917 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1918 "Find adapter, Hardware type is 8821AE\n");
1919 } else if (deviceid == RTL_PCI_8812AE_DID) {
1920 rtlhal->hw_type = HARDWARE_TYPE_RTL8812AE;
1921 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1922 "Find adapter, Hardware type is 8812AE\n");
1923 } else if (deviceid == RTL_PCI_8822BE_DID) {
1924 rtlhal->hw_type = HARDWARE_TYPE_RTL8822BE;
1925 rtlhal->bandset = BAND_ON_BOTH;
1926 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1927 "Find adapter, Hardware type is 8822BE\n");
1928 } else {
1929 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
1930 "Err: Unknown device - vid/did=%x/%x\n",
1931 venderid, deviceid);
1932
1933 rtlhal->hw_type = RTL_DEFAULT_HARDWARE_TYPE;
1934 }
1935
1936 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE) {
1937 if (revisionid == 0 || revisionid == 1) {
1938 if (revisionid == 0) {
1939 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1940 "Find 92DE MAC0\n");
1941 rtlhal->interfaceindex = 0;
1942 } else if (revisionid == 1) {
1943 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1944 "Find 92DE MAC1\n");
1945 rtlhal->interfaceindex = 1;
1946 }
1947 } else {
1948 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1949 "Unknown device - VendorID/DeviceID=%x/%x, Revision=%x\n",
1950 venderid, deviceid, revisionid);
1951 rtlhal->interfaceindex = 0;
1952 }
1953 }
1954
1955 switch (rtlhal->hw_type) {
1956 case HARDWARE_TYPE_RTL8192EE:
1957 case HARDWARE_TYPE_RTL8822BE:
1958 /* use new trx flow */
1959 rtlpriv->use_new_trx_flow = true;
1960 break;
1961
1962 default:
1963 rtlpriv->use_new_trx_flow = false;
1964 break;
1965 }
1966
1967 /*find bus info */
1968 pcipriv->ndis_adapter.busnumber = pdev->bus->number;
1969 pcipriv->ndis_adapter.devnumber = PCI_SLOT(pdev->devfn);
1970 pcipriv->ndis_adapter.funcnumber = PCI_FUNC(pdev->devfn);
1971
1972 /*find bridge info */
1973 pcipriv->ndis_adapter.pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN;
1974 /* some ARM have no bridge_pdev and will crash here
1975 * so we should check if bridge_pdev is NULL
1976 */
1977 if (bridge_pdev) {
1978 /*find bridge info if available */
1979 pcipriv->ndis_adapter.pcibridge_vendorid = bridge_pdev->vendor;
1980 for (tmp = 0; tmp < PCI_BRIDGE_VENDOR_MAX; tmp++) {
1981 if (bridge_pdev->vendor == pcibridge_vendors[tmp]) {
1982 pcipriv->ndis_adapter.pcibridge_vendor = tmp;
1983 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
1984 "Pci Bridge Vendor is found index: %d\n",
1985 tmp);
1986 break;
1987 }
1988 }
1989 }
1990
1991 if (pcipriv->ndis_adapter.pcibridge_vendor !=
1992 PCI_BRIDGE_VENDOR_UNKNOWN) {
1993 pcipriv->ndis_adapter.pcibridge_busnum =
1994 bridge_pdev->bus->number;
1995 pcipriv->ndis_adapter.pcibridge_devnum =
1996 PCI_SLOT(bridge_pdev->devfn);
1997 pcipriv->ndis_adapter.pcibridge_funcnum =
1998 PCI_FUNC(bridge_pdev->devfn);
1999
2000 if (pcipriv->ndis_adapter.pcibridge_vendor ==
2001 PCI_BRIDGE_VENDOR_AMD) {
2002 pcipriv->ndis_adapter.amd_l1_patch =
2003 rtl_pci_get_amd_l1_patch(hw);
2004 }
2005 }
2006
2007 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
2008 "pcidev busnumber:devnumber:funcnumber:vendor:link_ctl %d:%d:%d:%x:%x\n",
2009 pcipriv->ndis_adapter.busnumber,
2010 pcipriv->ndis_adapter.devnumber,
2011 pcipriv->ndis_adapter.funcnumber,
2012 pdev->vendor, pcipriv->ndis_adapter.linkctrl_reg);
2013
2014 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
2015 "pci_bridge busnumber:devnumber:funcnumber:vendor:amd %d:%d:%d:%x:%x\n",
2016 pcipriv->ndis_adapter.pcibridge_busnum,
2017 pcipriv->ndis_adapter.pcibridge_devnum,
2018 pcipriv->ndis_adapter.pcibridge_funcnum,
2019 pcibridge_vendors[pcipriv->ndis_adapter.pcibridge_vendor],
2020 pcipriv->ndis_adapter.amd_l1_patch);
2021
2022 rtl_pci_parse_configuration(pdev, hw);
2023 list_add_tail(&rtlpriv->list, &rtlpriv->glb_var->glb_priv_list);
2024
2025 return true;
2026 }
2027
rtl_pci_intr_mode_msi(struct ieee80211_hw * hw)2028 static int rtl_pci_intr_mode_msi(struct ieee80211_hw *hw)
2029 {
2030 struct rtl_priv *rtlpriv = rtl_priv(hw);
2031 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2032 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
2033 int ret;
2034
2035 ret = pci_enable_msi(rtlpci->pdev);
2036 if (ret < 0)
2037 return ret;
2038
2039 ret = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt,
2040 IRQF_SHARED, KBUILD_MODNAME, hw);
2041 if (ret < 0) {
2042 pci_disable_msi(rtlpci->pdev);
2043 return ret;
2044 }
2045
2046 rtlpci->using_msi = true;
2047
2048 rtl_dbg(rtlpriv, COMP_INIT | COMP_INTR, DBG_DMESG,
2049 "MSI Interrupt Mode!\n");
2050 return 0;
2051 }
2052
rtl_pci_intr_mode_legacy(struct ieee80211_hw * hw)2053 static int rtl_pci_intr_mode_legacy(struct ieee80211_hw *hw)
2054 {
2055 struct rtl_priv *rtlpriv = rtl_priv(hw);
2056 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2057 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
2058 int ret;
2059
2060 ret = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt,
2061 IRQF_SHARED, KBUILD_MODNAME, hw);
2062 if (ret < 0)
2063 return ret;
2064
2065 rtlpci->using_msi = false;
2066 rtl_dbg(rtlpriv, COMP_INIT | COMP_INTR, DBG_DMESG,
2067 "Pin-based Interrupt Mode!\n");
2068 return 0;
2069 }
2070
rtl_pci_intr_mode_decide(struct ieee80211_hw * hw)2071 static int rtl_pci_intr_mode_decide(struct ieee80211_hw *hw)
2072 {
2073 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2074 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
2075 int ret;
2076
2077 if (rtlpci->msi_support) {
2078 ret = rtl_pci_intr_mode_msi(hw);
2079 if (ret < 0)
2080 ret = rtl_pci_intr_mode_legacy(hw);
2081 } else {
2082 ret = rtl_pci_intr_mode_legacy(hw);
2083 }
2084 return ret;
2085 }
2086
platform_enable_dma64(struct pci_dev * pdev,bool dma64)2087 static void platform_enable_dma64(struct pci_dev *pdev, bool dma64)
2088 {
2089 u8 value;
2090
2091 pci_read_config_byte(pdev, 0x719, &value);
2092
2093 /* 0x719 Bit5 is DMA64 bit fetch. */
2094 if (dma64)
2095 value |= BIT(5);
2096 else
2097 value &= ~BIT(5);
2098
2099 pci_write_config_byte(pdev, 0x719, value);
2100 }
2101
rtl_pci_probe(struct pci_dev * pdev,const struct pci_device_id * id)2102 int rtl_pci_probe(struct pci_dev *pdev,
2103 const struct pci_device_id *id)
2104 {
2105 struct ieee80211_hw *hw = NULL;
2106
2107 struct rtl_priv *rtlpriv = NULL;
2108 struct rtl_pci_priv *pcipriv = NULL;
2109 struct rtl_pci *rtlpci;
2110 unsigned long pmem_start, pmem_len, pmem_flags;
2111 int err;
2112
2113 err = pci_enable_device(pdev);
2114 if (err) {
2115 WARN_ONCE(true, "%s : Cannot enable new PCI device\n",
2116 pci_name(pdev));
2117 return err;
2118 }
2119
2120 if (((struct rtl_hal_cfg *)id->driver_data)->mod_params->dma64 &&
2121 !dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) {
2122 if (dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
2123 WARN_ONCE(true,
2124 "Unable to obtain 64bit DMA for consistent allocations\n");
2125 err = -ENOMEM;
2126 goto fail1;
2127 }
2128
2129 platform_enable_dma64(pdev, true);
2130 } else if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(32))) {
2131 if (dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32))) {
2132 WARN_ONCE(true,
2133 "rtlwifi: Unable to obtain 32bit DMA for consistent allocations\n");
2134 err = -ENOMEM;
2135 goto fail1;
2136 }
2137
2138 platform_enable_dma64(pdev, false);
2139 }
2140
2141 pci_set_master(pdev);
2142
2143 hw = ieee80211_alloc_hw(sizeof(struct rtl_pci_priv) +
2144 sizeof(struct rtl_priv), &rtl_ops);
2145 if (!hw) {
2146 WARN_ONCE(true,
2147 "%s : ieee80211 alloc failed\n", pci_name(pdev));
2148 err = -ENOMEM;
2149 goto fail1;
2150 }
2151
2152 SET_IEEE80211_DEV(hw, &pdev->dev);
2153 pci_set_drvdata(pdev, hw);
2154
2155 rtlpriv = hw->priv;
2156 rtlpriv->hw = hw;
2157 pcipriv = (void *)rtlpriv->priv;
2158 pcipriv->dev.pdev = pdev;
2159 init_completion(&rtlpriv->firmware_loading_complete);
2160 /*proximity init here*/
2161 rtlpriv->proximity.proxim_on = false;
2162
2163 pcipriv = (void *)rtlpriv->priv;
2164 pcipriv->dev.pdev = pdev;
2165
2166 /* init cfg & intf_ops */
2167 rtlpriv->rtlhal.interface = INTF_PCI;
2168 rtlpriv->cfg = (struct rtl_hal_cfg *)(id->driver_data);
2169 rtlpriv->intf_ops = &rtl_pci_ops;
2170 rtlpriv->glb_var = &rtl_global_var;
2171 rtl_efuse_ops_init(hw);
2172
2173 /* MEM map */
2174 err = pci_request_regions(pdev, KBUILD_MODNAME);
2175 if (err) {
2176 WARN_ONCE(true, "rtlwifi: Can't obtain PCI resources\n");
2177 goto fail1;
2178 }
2179
2180 pmem_start = pci_resource_start(pdev, rtlpriv->cfg->bar_id);
2181 pmem_len = pci_resource_len(pdev, rtlpriv->cfg->bar_id);
2182 pmem_flags = pci_resource_flags(pdev, rtlpriv->cfg->bar_id);
2183
2184 /*shared mem start */
2185 rtlpriv->io.pci_mem_start =
2186 (unsigned long)pci_iomap(pdev,
2187 rtlpriv->cfg->bar_id, pmem_len);
2188 if (rtlpriv->io.pci_mem_start == 0) {
2189 WARN_ONCE(true, "rtlwifi: Can't map PCI mem\n");
2190 err = -ENOMEM;
2191 goto fail2;
2192 }
2193
2194 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
2195 "mem mapped space: start: 0x%08lx len:%08lx flags:%08lx, after map:0x%08lx\n",
2196 pmem_start, pmem_len, pmem_flags,
2197 rtlpriv->io.pci_mem_start);
2198
2199 /* Disable Clk Request */
2200 pci_write_config_byte(pdev, 0x81, 0);
2201 /* leave D3 mode */
2202 pci_write_config_byte(pdev, 0x44, 0);
2203 pci_write_config_byte(pdev, 0x04, 0x06);
2204 pci_write_config_byte(pdev, 0x04, 0x07);
2205
2206 /* find adapter */
2207 if (!_rtl_pci_find_adapter(pdev, hw)) {
2208 err = -ENODEV;
2209 goto fail2;
2210 }
2211
2212 /* Init IO handler */
2213 _rtl_pci_io_handler_init(&pdev->dev, hw);
2214
2215 /*like read eeprom and so on */
2216 rtlpriv->cfg->ops->read_eeprom_info(hw);
2217
2218 if (rtlpriv->cfg->ops->init_sw_vars(hw)) {
2219 pr_err("Can't init_sw_vars\n");
2220 err = -ENODEV;
2221 goto fail3;
2222 }
2223 rtlpriv->cfg->ops->init_sw_leds(hw);
2224
2225 /*aspm */
2226 rtl_pci_init_aspm(hw);
2227
2228 /* Init mac80211 sw */
2229 err = rtl_init_core(hw);
2230 if (err) {
2231 pr_err("Can't allocate sw for mac80211\n");
2232 goto fail3;
2233 }
2234
2235 /* Init PCI sw */
2236 err = rtl_pci_init(hw, pdev);
2237 if (err) {
2238 pr_err("Failed to init PCI\n");
2239 goto fail3;
2240 }
2241
2242 err = ieee80211_register_hw(hw);
2243 if (err) {
2244 pr_err("Can't register mac80211 hw.\n");
2245 err = -ENODEV;
2246 goto fail3;
2247 }
2248 rtlpriv->mac80211.mac80211_registered = 1;
2249
2250 /* add for debug */
2251 rtl_debug_add_one(hw);
2252
2253 /*init rfkill */
2254 rtl_init_rfkill(hw); /* Init PCI sw */
2255
2256 rtlpci = rtl_pcidev(pcipriv);
2257 err = rtl_pci_intr_mode_decide(hw);
2258 if (err) {
2259 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
2260 "%s: failed to register IRQ handler\n",
2261 wiphy_name(hw->wiphy));
2262 goto fail3;
2263 }
2264 rtlpci->irq_alloc = 1;
2265
2266 set_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status);
2267 return 0;
2268
2269 fail3:
2270 pci_set_drvdata(pdev, NULL);
2271 rtl_deinit_core(hw);
2272
2273 fail2:
2274 if (rtlpriv->io.pci_mem_start != 0)
2275 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start);
2276
2277 pci_release_regions(pdev);
2278 complete(&rtlpriv->firmware_loading_complete);
2279
2280 fail1:
2281 if (hw)
2282 ieee80211_free_hw(hw);
2283 pci_disable_device(pdev);
2284
2285 return err;
2286 }
2287 EXPORT_SYMBOL(rtl_pci_probe);
2288
rtl_pci_disconnect(struct pci_dev * pdev)2289 void rtl_pci_disconnect(struct pci_dev *pdev)
2290 {
2291 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2292 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2293 struct rtl_priv *rtlpriv = rtl_priv(hw);
2294 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
2295 struct rtl_mac *rtlmac = rtl_mac(rtlpriv);
2296
2297 /* just in case driver is removed before firmware callback */
2298 wait_for_completion(&rtlpriv->firmware_loading_complete);
2299 clear_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status);
2300
2301 /* remove form debug */
2302 rtl_debug_remove_one(hw);
2303
2304 /*ieee80211_unregister_hw will call ops_stop */
2305 if (rtlmac->mac80211_registered == 1) {
2306 ieee80211_unregister_hw(hw);
2307 rtlmac->mac80211_registered = 0;
2308 } else {
2309 rtl_deinit_deferred_work(hw, false);
2310 rtlpriv->intf_ops->adapter_stop(hw);
2311 }
2312 rtlpriv->cfg->ops->disable_interrupt(hw);
2313
2314 /*deinit rfkill */
2315 rtl_deinit_rfkill(hw);
2316
2317 rtl_pci_deinit(hw);
2318 rtl_deinit_core(hw);
2319 rtlpriv->cfg->ops->deinit_sw_vars(hw);
2320
2321 if (rtlpci->irq_alloc) {
2322 free_irq(rtlpci->pdev->irq, hw);
2323 rtlpci->irq_alloc = 0;
2324 }
2325
2326 if (rtlpci->using_msi)
2327 pci_disable_msi(rtlpci->pdev);
2328
2329 list_del(&rtlpriv->list);
2330 if (rtlpriv->io.pci_mem_start != 0) {
2331 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start);
2332 pci_release_regions(pdev);
2333 }
2334
2335 pci_disable_device(pdev);
2336
2337 rtl_pci_disable_aspm(hw);
2338
2339 pci_set_drvdata(pdev, NULL);
2340
2341 ieee80211_free_hw(hw);
2342 }
2343 EXPORT_SYMBOL(rtl_pci_disconnect);
2344
2345 #ifdef CONFIG_PM_SLEEP
2346 /***************************************
2347 * kernel pci power state define:
2348 * PCI_D0 ((pci_power_t __force) 0)
2349 * PCI_D1 ((pci_power_t __force) 1)
2350 * PCI_D2 ((pci_power_t __force) 2)
2351 * PCI_D3hot ((pci_power_t __force) 3)
2352 * PCI_D3cold ((pci_power_t __force) 4)
2353 * PCI_UNKNOWN ((pci_power_t __force) 5)
2354
2355 * This function is called when system
2356 * goes into suspend state mac80211 will
2357 * call rtl_mac_stop() from the mac80211
2358 * suspend function first, So there is
2359 * no need to call hw_disable here.
2360 ****************************************/
rtl_pci_suspend(struct device * dev)2361 int rtl_pci_suspend(struct device *dev)
2362 {
2363 struct ieee80211_hw *hw = dev_get_drvdata(dev);
2364 struct rtl_priv *rtlpriv = rtl_priv(hw);
2365
2366 rtlpriv->cfg->ops->hw_suspend(hw);
2367 rtl_deinit_rfkill(hw);
2368
2369 return 0;
2370 }
2371 EXPORT_SYMBOL(rtl_pci_suspend);
2372
rtl_pci_resume(struct device * dev)2373 int rtl_pci_resume(struct device *dev)
2374 {
2375 struct ieee80211_hw *hw = dev_get_drvdata(dev);
2376 struct rtl_priv *rtlpriv = rtl_priv(hw);
2377
2378 rtlpriv->cfg->ops->hw_resume(hw);
2379 rtl_init_rfkill(hw);
2380 return 0;
2381 }
2382 EXPORT_SYMBOL(rtl_pci_resume);
2383 #endif /* CONFIG_PM_SLEEP */
2384
2385 const struct rtl_intf_ops rtl_pci_ops = {
2386 .read_efuse_byte = read_efuse_byte,
2387 .adapter_start = rtl_pci_start,
2388 .adapter_stop = rtl_pci_stop,
2389 .check_buddy_priv = rtl_pci_check_buddy_priv,
2390 .adapter_tx = rtl_pci_tx,
2391 .flush = rtl_pci_flush,
2392 .reset_trx_ring = rtl_pci_reset_trx_ring,
2393 .waitq_insert = rtl_pci_tx_chk_waitq_insert,
2394
2395 .disable_aspm = rtl_pci_disable_aspm,
2396 .enable_aspm = rtl_pci_enable_aspm,
2397 };
2398