1 // SPDX-License-Identifier: GPL-2.0
2 /* Marvell OcteonTx2 RVU Admin Function driver
3 *
4 * Copyright (C) 2018 Marvell International Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11 #include <linux/bitfield.h>
12 #include <linux/module.h>
13 #include <linux/pci.h>
14
15 #include "rvu_struct.h"
16 #include "rvu_reg.h"
17 #include "rvu.h"
18 #include "npc.h"
19 #include "cgx.h"
20 #include "npc_profile.h"
21
22 #define RSVD_MCAM_ENTRIES_PER_PF 2 /* Bcast & Promisc */
23 #define RSVD_MCAM_ENTRIES_PER_NIXLF 1 /* Ucast for LFs */
24
25 #define NIXLF_UCAST_ENTRY 0
26 #define NIXLF_BCAST_ENTRY 1
27 #define NIXLF_PROMISC_ENTRY 2
28
29 #define NPC_PARSE_RESULT_DMAC_OFFSET 8
30 #define NPC_HW_TSTAMP_OFFSET 8ULL
31
32 static const char def_pfl_name[] = "default";
33
34 static void npc_mcam_free_all_entries(struct rvu *rvu, struct npc_mcam *mcam,
35 int blkaddr, u16 pcifunc);
36 static void npc_mcam_free_all_counters(struct rvu *rvu, struct npc_mcam *mcam,
37 u16 pcifunc);
38
rvu_npc_set_pkind(struct rvu * rvu,int pkind,struct rvu_pfvf * pfvf)39 void rvu_npc_set_pkind(struct rvu *rvu, int pkind, struct rvu_pfvf *pfvf)
40 {
41 int blkaddr;
42 u64 val = 0;
43
44 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
45 if (blkaddr < 0)
46 return;
47
48 /* Config CPI base for the PKIND */
49 val = pkind | 1ULL << 62;
50 rvu_write64(rvu, blkaddr, NPC_AF_PKINDX_CPI_DEFX(pkind, 0), val);
51 }
52
rvu_npc_get_pkind(struct rvu * rvu,u16 pf)53 int rvu_npc_get_pkind(struct rvu *rvu, u16 pf)
54 {
55 struct npc_pkind *pkind = &rvu->hw->pkind;
56 u32 map;
57 int i;
58
59 for (i = 0; i < pkind->rsrc.max; i++) {
60 map = pkind->pfchan_map[i];
61 if (((map >> 16) & 0x3F) == pf)
62 return i;
63 }
64 return -1;
65 }
66
67 #define NPC_AF_ACTION0_PTR_ADVANCE GENMASK_ULL(27, 20)
68
npc_config_ts_kpuaction(struct rvu * rvu,int pf,u16 pcifunc,bool enable)69 int npc_config_ts_kpuaction(struct rvu *rvu, int pf, u16 pcifunc, bool enable)
70 {
71 int pkind, blkaddr;
72 u64 val;
73
74 pkind = rvu_npc_get_pkind(rvu, pf);
75 if (pkind < 0) {
76 dev_err(rvu->dev, "%s: pkind not mapped\n", __func__);
77 return -EINVAL;
78 }
79
80 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, pcifunc);
81 if (blkaddr < 0) {
82 dev_err(rvu->dev, "%s: NPC block not implemented\n", __func__);
83 return -EINVAL;
84 }
85
86 val = rvu_read64(rvu, blkaddr, NPC_AF_PKINDX_ACTION0(pkind));
87 val &= ~NPC_AF_ACTION0_PTR_ADVANCE;
88 /* If timestamp is enabled then configure NPC to shift 8 bytes */
89 if (enable)
90 val |= FIELD_PREP(NPC_AF_ACTION0_PTR_ADVANCE,
91 NPC_HW_TSTAMP_OFFSET);
92 rvu_write64(rvu, blkaddr, NPC_AF_PKINDX_ACTION0(pkind), val);
93
94 return 0;
95 }
96
npc_get_nixlf_mcam_index(struct npc_mcam * mcam,u16 pcifunc,int nixlf,int type)97 static int npc_get_nixlf_mcam_index(struct npc_mcam *mcam,
98 u16 pcifunc, int nixlf, int type)
99 {
100 int pf = rvu_get_pf(pcifunc);
101 int index;
102
103 /* Check if this is for a PF */
104 if (pf && !(pcifunc & RVU_PFVF_FUNC_MASK)) {
105 /* Reserved entries exclude PF0 */
106 pf--;
107 index = mcam->pf_offset + (pf * RSVD_MCAM_ENTRIES_PER_PF);
108 /* Broadcast address matching entry should be first so
109 * that the packet can be replicated to all VFs.
110 */
111 if (type == NIXLF_BCAST_ENTRY)
112 return index;
113 else if (type == NIXLF_PROMISC_ENTRY)
114 return index + 1;
115 }
116
117 return (mcam->nixlf_offset + (nixlf * RSVD_MCAM_ENTRIES_PER_NIXLF));
118 }
119
npc_get_bank(struct npc_mcam * mcam,int index)120 static int npc_get_bank(struct npc_mcam *mcam, int index)
121 {
122 int bank = index / mcam->banksize;
123
124 /* 0,1 & 2,3 banks are combined for this keysize */
125 if (mcam->keysize == NPC_MCAM_KEY_X2)
126 return bank ? 2 : 0;
127
128 return bank;
129 }
130
is_mcam_entry_enabled(struct rvu * rvu,struct npc_mcam * mcam,int blkaddr,int index)131 static bool is_mcam_entry_enabled(struct rvu *rvu, struct npc_mcam *mcam,
132 int blkaddr, int index)
133 {
134 int bank = npc_get_bank(mcam, index);
135 u64 cfg;
136
137 index &= (mcam->banksize - 1);
138 cfg = rvu_read64(rvu, blkaddr, NPC_AF_MCAMEX_BANKX_CFG(index, bank));
139 return (cfg & 1);
140 }
141
npc_enable_mcam_entry(struct rvu * rvu,struct npc_mcam * mcam,int blkaddr,int index,bool enable)142 static void npc_enable_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam,
143 int blkaddr, int index, bool enable)
144 {
145 int bank = npc_get_bank(mcam, index);
146 int actbank = bank;
147
148 index &= (mcam->banksize - 1);
149 for (; bank < (actbank + mcam->banks_per_entry); bank++) {
150 rvu_write64(rvu, blkaddr,
151 NPC_AF_MCAMEX_BANKX_CFG(index, bank),
152 enable ? 1 : 0);
153 }
154 }
155
npc_clear_mcam_entry(struct rvu * rvu,struct npc_mcam * mcam,int blkaddr,int index)156 static void npc_clear_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam,
157 int blkaddr, int index)
158 {
159 int bank = npc_get_bank(mcam, index);
160 int actbank = bank;
161
162 index &= (mcam->banksize - 1);
163 for (; bank < (actbank + mcam->banks_per_entry); bank++) {
164 rvu_write64(rvu, blkaddr,
165 NPC_AF_MCAMEX_BANKX_CAMX_INTF(index, bank, 1), 0);
166 rvu_write64(rvu, blkaddr,
167 NPC_AF_MCAMEX_BANKX_CAMX_INTF(index, bank, 0), 0);
168
169 rvu_write64(rvu, blkaddr,
170 NPC_AF_MCAMEX_BANKX_CAMX_W0(index, bank, 1), 0);
171 rvu_write64(rvu, blkaddr,
172 NPC_AF_MCAMEX_BANKX_CAMX_W0(index, bank, 0), 0);
173
174 rvu_write64(rvu, blkaddr,
175 NPC_AF_MCAMEX_BANKX_CAMX_W1(index, bank, 1), 0);
176 rvu_write64(rvu, blkaddr,
177 NPC_AF_MCAMEX_BANKX_CAMX_W1(index, bank, 0), 0);
178 }
179 }
180
npc_get_keyword(struct mcam_entry * entry,int idx,u64 * cam0,u64 * cam1)181 static void npc_get_keyword(struct mcam_entry *entry, int idx,
182 u64 *cam0, u64 *cam1)
183 {
184 u64 kw_mask = 0x00;
185
186 #define CAM_MASK(n) (BIT_ULL(n) - 1)
187
188 /* 0, 2, 4, 6 indices refer to BANKX_CAMX_W0 and
189 * 1, 3, 5, 7 indices refer to BANKX_CAMX_W1.
190 *
191 * Also, only 48 bits of BANKX_CAMX_W1 are valid.
192 */
193 switch (idx) {
194 case 0:
195 /* BANK(X)_CAM_W0<63:0> = MCAM_KEY[KW0]<63:0> */
196 *cam1 = entry->kw[0];
197 kw_mask = entry->kw_mask[0];
198 break;
199 case 1:
200 /* BANK(X)_CAM_W1<47:0> = MCAM_KEY[KW1]<47:0> */
201 *cam1 = entry->kw[1] & CAM_MASK(48);
202 kw_mask = entry->kw_mask[1] & CAM_MASK(48);
203 break;
204 case 2:
205 /* BANK(X + 1)_CAM_W0<15:0> = MCAM_KEY[KW1]<63:48>
206 * BANK(X + 1)_CAM_W0<63:16> = MCAM_KEY[KW2]<47:0>
207 */
208 *cam1 = (entry->kw[1] >> 48) & CAM_MASK(16);
209 *cam1 |= ((entry->kw[2] & CAM_MASK(48)) << 16);
210 kw_mask = (entry->kw_mask[1] >> 48) & CAM_MASK(16);
211 kw_mask |= ((entry->kw_mask[2] & CAM_MASK(48)) << 16);
212 break;
213 case 3:
214 /* BANK(X + 1)_CAM_W1<15:0> = MCAM_KEY[KW2]<63:48>
215 * BANK(X + 1)_CAM_W1<47:16> = MCAM_KEY[KW3]<31:0>
216 */
217 *cam1 = (entry->kw[2] >> 48) & CAM_MASK(16);
218 *cam1 |= ((entry->kw[3] & CAM_MASK(32)) << 16);
219 kw_mask = (entry->kw_mask[2] >> 48) & CAM_MASK(16);
220 kw_mask |= ((entry->kw_mask[3] & CAM_MASK(32)) << 16);
221 break;
222 case 4:
223 /* BANK(X + 2)_CAM_W0<31:0> = MCAM_KEY[KW3]<63:32>
224 * BANK(X + 2)_CAM_W0<63:32> = MCAM_KEY[KW4]<31:0>
225 */
226 *cam1 = (entry->kw[3] >> 32) & CAM_MASK(32);
227 *cam1 |= ((entry->kw[4] & CAM_MASK(32)) << 32);
228 kw_mask = (entry->kw_mask[3] >> 32) & CAM_MASK(32);
229 kw_mask |= ((entry->kw_mask[4] & CAM_MASK(32)) << 32);
230 break;
231 case 5:
232 /* BANK(X + 2)_CAM_W1<31:0> = MCAM_KEY[KW4]<63:32>
233 * BANK(X + 2)_CAM_W1<47:32> = MCAM_KEY[KW5]<15:0>
234 */
235 *cam1 = (entry->kw[4] >> 32) & CAM_MASK(32);
236 *cam1 |= ((entry->kw[5] & CAM_MASK(16)) << 32);
237 kw_mask = (entry->kw_mask[4] >> 32) & CAM_MASK(32);
238 kw_mask |= ((entry->kw_mask[5] & CAM_MASK(16)) << 32);
239 break;
240 case 6:
241 /* BANK(X + 3)_CAM_W0<47:0> = MCAM_KEY[KW5]<63:16>
242 * BANK(X + 3)_CAM_W0<63:48> = MCAM_KEY[KW6]<15:0>
243 */
244 *cam1 = (entry->kw[5] >> 16) & CAM_MASK(48);
245 *cam1 |= ((entry->kw[6] & CAM_MASK(16)) << 48);
246 kw_mask = (entry->kw_mask[5] >> 16) & CAM_MASK(48);
247 kw_mask |= ((entry->kw_mask[6] & CAM_MASK(16)) << 48);
248 break;
249 case 7:
250 /* BANK(X + 3)_CAM_W1<47:0> = MCAM_KEY[KW6]<63:16> */
251 *cam1 = (entry->kw[6] >> 16) & CAM_MASK(48);
252 kw_mask = (entry->kw_mask[6] >> 16) & CAM_MASK(48);
253 break;
254 }
255
256 *cam1 &= kw_mask;
257 *cam0 = ~*cam1 & kw_mask;
258 }
259
npc_config_mcam_entry(struct rvu * rvu,struct npc_mcam * mcam,int blkaddr,int index,u8 intf,struct mcam_entry * entry,bool enable)260 static void npc_config_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam,
261 int blkaddr, int index, u8 intf,
262 struct mcam_entry *entry, bool enable)
263 {
264 int bank = npc_get_bank(mcam, index);
265 int kw = 0, actbank, actindex;
266 u64 cam0, cam1;
267
268 actbank = bank; /* Save bank id, to set action later on */
269 actindex = index;
270 index &= (mcam->banksize - 1);
271
272 /* Disable before mcam entry update */
273 npc_enable_mcam_entry(rvu, mcam, blkaddr, actindex, false);
274
275 /* Clear mcam entry to avoid writes being suppressed by NPC */
276 npc_clear_mcam_entry(rvu, mcam, blkaddr, actindex);
277
278 /* CAM1 takes the comparison value and
279 * CAM0 specifies match for a bit in key being '0' or '1' or 'dontcare'.
280 * CAM1<n> = 0 & CAM0<n> = 1 => match if key<n> = 0
281 * CAM1<n> = 1 & CAM0<n> = 0 => match if key<n> = 1
282 * CAM1<n> = 0 & CAM0<n> = 0 => always match i.e dontcare.
283 */
284 for (; bank < (actbank + mcam->banks_per_entry); bank++, kw = kw + 2) {
285 /* Interface should be set in all banks */
286 rvu_write64(rvu, blkaddr,
287 NPC_AF_MCAMEX_BANKX_CAMX_INTF(index, bank, 1),
288 intf);
289 rvu_write64(rvu, blkaddr,
290 NPC_AF_MCAMEX_BANKX_CAMX_INTF(index, bank, 0),
291 ~intf & 0x3);
292
293 /* Set the match key */
294 npc_get_keyword(entry, kw, &cam0, &cam1);
295 rvu_write64(rvu, blkaddr,
296 NPC_AF_MCAMEX_BANKX_CAMX_W0(index, bank, 1), cam1);
297 rvu_write64(rvu, blkaddr,
298 NPC_AF_MCAMEX_BANKX_CAMX_W0(index, bank, 0), cam0);
299
300 npc_get_keyword(entry, kw + 1, &cam0, &cam1);
301 rvu_write64(rvu, blkaddr,
302 NPC_AF_MCAMEX_BANKX_CAMX_W1(index, bank, 1), cam1);
303 rvu_write64(rvu, blkaddr,
304 NPC_AF_MCAMEX_BANKX_CAMX_W1(index, bank, 0), cam0);
305 }
306
307 /* Set 'action' */
308 rvu_write64(rvu, blkaddr,
309 NPC_AF_MCAMEX_BANKX_ACTION(index, actbank), entry->action);
310
311 /* Set TAG 'action' */
312 rvu_write64(rvu, blkaddr, NPC_AF_MCAMEX_BANKX_TAG_ACT(index, actbank),
313 entry->vtag_action);
314
315 /* Enable the entry */
316 if (enable)
317 npc_enable_mcam_entry(rvu, mcam, blkaddr, actindex, true);
318 }
319
npc_copy_mcam_entry(struct rvu * rvu,struct npc_mcam * mcam,int blkaddr,u16 src,u16 dest)320 static void npc_copy_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam,
321 int blkaddr, u16 src, u16 dest)
322 {
323 int dbank = npc_get_bank(mcam, dest);
324 int sbank = npc_get_bank(mcam, src);
325 u64 cfg, sreg, dreg;
326 int bank, i;
327
328 src &= (mcam->banksize - 1);
329 dest &= (mcam->banksize - 1);
330
331 /* Copy INTF's, W0's, W1's CAM0 and CAM1 configuration */
332 for (bank = 0; bank < mcam->banks_per_entry; bank++) {
333 sreg = NPC_AF_MCAMEX_BANKX_CAMX_INTF(src, sbank + bank, 0);
334 dreg = NPC_AF_MCAMEX_BANKX_CAMX_INTF(dest, dbank + bank, 0);
335 for (i = 0; i < 6; i++) {
336 cfg = rvu_read64(rvu, blkaddr, sreg + (i * 8));
337 rvu_write64(rvu, blkaddr, dreg + (i * 8), cfg);
338 }
339 }
340
341 /* Copy action */
342 cfg = rvu_read64(rvu, blkaddr,
343 NPC_AF_MCAMEX_BANKX_ACTION(src, sbank));
344 rvu_write64(rvu, blkaddr,
345 NPC_AF_MCAMEX_BANKX_ACTION(dest, dbank), cfg);
346
347 /* Copy TAG action */
348 cfg = rvu_read64(rvu, blkaddr,
349 NPC_AF_MCAMEX_BANKX_TAG_ACT(src, sbank));
350 rvu_write64(rvu, blkaddr,
351 NPC_AF_MCAMEX_BANKX_TAG_ACT(dest, dbank), cfg);
352
353 /* Enable or disable */
354 cfg = rvu_read64(rvu, blkaddr,
355 NPC_AF_MCAMEX_BANKX_CFG(src, sbank));
356 rvu_write64(rvu, blkaddr,
357 NPC_AF_MCAMEX_BANKX_CFG(dest, dbank), cfg);
358 }
359
npc_get_mcam_action(struct rvu * rvu,struct npc_mcam * mcam,int blkaddr,int index)360 static u64 npc_get_mcam_action(struct rvu *rvu, struct npc_mcam *mcam,
361 int blkaddr, int index)
362 {
363 int bank = npc_get_bank(mcam, index);
364
365 index &= (mcam->banksize - 1);
366 return rvu_read64(rvu, blkaddr,
367 NPC_AF_MCAMEX_BANKX_ACTION(index, bank));
368 }
369
rvu_npc_install_ucast_entry(struct rvu * rvu,u16 pcifunc,int nixlf,u64 chan,u8 * mac_addr)370 void rvu_npc_install_ucast_entry(struct rvu *rvu, u16 pcifunc,
371 int nixlf, u64 chan, u8 *mac_addr)
372 {
373 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc);
374 struct npc_mcam *mcam = &rvu->hw->mcam;
375 struct mcam_entry entry = { {0} };
376 struct nix_rx_action action;
377 int blkaddr, index, kwi;
378 u64 mac = 0;
379
380 /* AF's VFs work in promiscuous mode */
381 if (is_afvf(pcifunc))
382 return;
383
384 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
385 if (blkaddr < 0)
386 return;
387
388 for (index = ETH_ALEN - 1; index >= 0; index--)
389 mac |= ((u64)*mac_addr++) << (8 * index);
390
391 index = npc_get_nixlf_mcam_index(mcam, pcifunc,
392 nixlf, NIXLF_UCAST_ENTRY);
393
394 /* Match ingress channel and DMAC */
395 entry.kw[0] = chan;
396 entry.kw_mask[0] = 0xFFFULL;
397
398 kwi = NPC_PARSE_RESULT_DMAC_OFFSET / sizeof(u64);
399 entry.kw[kwi] = mac;
400 entry.kw_mask[kwi] = BIT_ULL(48) - 1;
401
402 /* Don't change the action if entry is already enabled
403 * Otherwise RSS action may get overwritten.
404 */
405 if (is_mcam_entry_enabled(rvu, mcam, blkaddr, index)) {
406 *(u64 *)&action = npc_get_mcam_action(rvu, mcam,
407 blkaddr, index);
408 } else {
409 *(u64 *)&action = 0x00;
410 action.op = NIX_RX_ACTIONOP_UCAST;
411 action.pf_func = pcifunc;
412 }
413
414 entry.action = *(u64 *)&action;
415 npc_config_mcam_entry(rvu, mcam, blkaddr, index,
416 NIX_INTF_RX, &entry, true);
417
418 /* add VLAN matching, setup action and save entry back for later */
419 entry.kw[0] |= (NPC_LT_LB_STAG_QINQ | NPC_LT_LB_CTAG) << 20;
420 entry.kw_mask[0] |= (NPC_LT_LB_STAG_QINQ & NPC_LT_LB_CTAG) << 20;
421
422 entry.vtag_action = VTAG0_VALID_BIT |
423 FIELD_PREP(VTAG0_TYPE_MASK, 0) |
424 FIELD_PREP(VTAG0_LID_MASK, NPC_LID_LA) |
425 FIELD_PREP(VTAG0_RELPTR_MASK, 12);
426
427 memcpy(&pfvf->entry, &entry, sizeof(entry));
428 }
429
rvu_npc_install_promisc_entry(struct rvu * rvu,u16 pcifunc,int nixlf,u64 chan,bool allmulti)430 void rvu_npc_install_promisc_entry(struct rvu *rvu, u16 pcifunc,
431 int nixlf, u64 chan, bool allmulti)
432 {
433 struct npc_mcam *mcam = &rvu->hw->mcam;
434 int blkaddr, ucast_idx, index, kwi;
435 struct mcam_entry entry = { {0} };
436 struct nix_rx_action action = { };
437
438 /* Only PF or AF VF can add a promiscuous entry */
439 if ((pcifunc & RVU_PFVF_FUNC_MASK) && !is_afvf(pcifunc))
440 return;
441
442 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
443 if (blkaddr < 0)
444 return;
445
446 index = npc_get_nixlf_mcam_index(mcam, pcifunc,
447 nixlf, NIXLF_PROMISC_ENTRY);
448
449 entry.kw[0] = chan;
450 entry.kw_mask[0] = 0xFFFULL;
451
452 if (allmulti) {
453 kwi = NPC_KEXOF_DMAC / sizeof(u64);
454 entry.kw[kwi] = BIT_ULL(40); /* LSB bit of 1st byte in DMAC */
455 entry.kw_mask[kwi] = BIT_ULL(40);
456 }
457
458 ucast_idx = npc_get_nixlf_mcam_index(mcam, pcifunc,
459 nixlf, NIXLF_UCAST_ENTRY);
460
461 /* If the corresponding PF's ucast action is RSS,
462 * use the same action for promisc also
463 */
464 if (is_mcam_entry_enabled(rvu, mcam, blkaddr, ucast_idx))
465 *(u64 *)&action = npc_get_mcam_action(rvu, mcam,
466 blkaddr, ucast_idx);
467
468 if (action.op != NIX_RX_ACTIONOP_RSS) {
469 *(u64 *)&action = 0x00;
470 action.op = NIX_RX_ACTIONOP_UCAST;
471 action.pf_func = pcifunc;
472 }
473
474 entry.action = *(u64 *)&action;
475 npc_config_mcam_entry(rvu, mcam, blkaddr, index,
476 NIX_INTF_RX, &entry, true);
477 }
478
npc_enadis_promisc_entry(struct rvu * rvu,u16 pcifunc,int nixlf,bool enable)479 static void npc_enadis_promisc_entry(struct rvu *rvu, u16 pcifunc,
480 int nixlf, bool enable)
481 {
482 struct npc_mcam *mcam = &rvu->hw->mcam;
483 int blkaddr, index;
484
485 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
486 if (blkaddr < 0)
487 return;
488
489 /* Only PF's have a promiscuous entry */
490 if (pcifunc & RVU_PFVF_FUNC_MASK)
491 return;
492
493 index = npc_get_nixlf_mcam_index(mcam, pcifunc,
494 nixlf, NIXLF_PROMISC_ENTRY);
495 npc_enable_mcam_entry(rvu, mcam, blkaddr, index, enable);
496 }
497
rvu_npc_disable_promisc_entry(struct rvu * rvu,u16 pcifunc,int nixlf)498 void rvu_npc_disable_promisc_entry(struct rvu *rvu, u16 pcifunc, int nixlf)
499 {
500 npc_enadis_promisc_entry(rvu, pcifunc, nixlf, false);
501 }
502
rvu_npc_enable_promisc_entry(struct rvu * rvu,u16 pcifunc,int nixlf)503 void rvu_npc_enable_promisc_entry(struct rvu *rvu, u16 pcifunc, int nixlf)
504 {
505 npc_enadis_promisc_entry(rvu, pcifunc, nixlf, true);
506 }
507
rvu_npc_install_bcast_match_entry(struct rvu * rvu,u16 pcifunc,int nixlf,u64 chan)508 void rvu_npc_install_bcast_match_entry(struct rvu *rvu, u16 pcifunc,
509 int nixlf, u64 chan)
510 {
511 struct npc_mcam *mcam = &rvu->hw->mcam;
512 struct mcam_entry entry = { {0} };
513 struct rvu_hwinfo *hw = rvu->hw;
514 struct nix_rx_action action;
515 struct rvu_pfvf *pfvf;
516 int blkaddr, index;
517
518 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
519 if (blkaddr < 0)
520 return;
521
522 /* Skip LBK VFs */
523 if (is_afvf(pcifunc))
524 return;
525
526 /* If pkt replication is not supported,
527 * then only PF is allowed to add a bcast match entry.
528 */
529 if (!hw->cap.nix_rx_multicast && pcifunc & RVU_PFVF_FUNC_MASK)
530 return;
531
532 /* Get 'pcifunc' of PF device */
533 pcifunc = pcifunc & ~RVU_PFVF_FUNC_MASK;
534 index = npc_get_nixlf_mcam_index(mcam, pcifunc,
535 nixlf, NIXLF_BCAST_ENTRY);
536
537 /* Match ingress channel */
538 entry.kw[0] = chan;
539 entry.kw_mask[0] = 0xfffull;
540
541 /* Match broadcast MAC address.
542 * DMAC is extracted at 0th bit of PARSE_KEX::KW1
543 */
544 entry.kw[1] = 0xffffffffffffull;
545 entry.kw_mask[1] = 0xffffffffffffull;
546
547 *(u64 *)&action = 0x00;
548 if (!hw->cap.nix_rx_multicast) {
549 /* Early silicon doesn't support pkt replication,
550 * so install entry with UCAST action, so that PF
551 * receives all broadcast packets.
552 */
553 action.op = NIX_RX_ACTIONOP_UCAST;
554 action.pf_func = pcifunc;
555 } else {
556 pfvf = rvu_get_pfvf(rvu, pcifunc);
557 action.index = pfvf->bcast_mce_idx;
558 action.op = NIX_RX_ACTIONOP_MCAST;
559 }
560
561 entry.action = *(u64 *)&action;
562 npc_config_mcam_entry(rvu, mcam, blkaddr, index,
563 NIX_INTF_RX, &entry, true);
564 }
565
rvu_npc_enable_bcast_entry(struct rvu * rvu,u16 pcifunc,bool enable)566 void rvu_npc_enable_bcast_entry(struct rvu *rvu, u16 pcifunc, bool enable)
567 {
568 struct npc_mcam *mcam = &rvu->hw->mcam;
569 int blkaddr, index;
570
571 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
572 if (blkaddr < 0)
573 return;
574
575 /* Get 'pcifunc' of PF device */
576 pcifunc = pcifunc & ~RVU_PFVF_FUNC_MASK;
577
578 index = npc_get_nixlf_mcam_index(mcam, pcifunc, 0, NIXLF_BCAST_ENTRY);
579 npc_enable_mcam_entry(rvu, mcam, blkaddr, index, enable);
580 }
581
rvu_npc_update_flowkey_alg_idx(struct rvu * rvu,u16 pcifunc,int nixlf,int group,int alg_idx,int mcam_index)582 void rvu_npc_update_flowkey_alg_idx(struct rvu *rvu, u16 pcifunc, int nixlf,
583 int group, int alg_idx, int mcam_index)
584 {
585 struct npc_mcam *mcam = &rvu->hw->mcam;
586 struct nix_rx_action action;
587 int blkaddr, index, bank;
588
589 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
590 if (blkaddr < 0)
591 return;
592
593 /* Check if this is for reserved default entry */
594 if (mcam_index < 0) {
595 if (group != DEFAULT_RSS_CONTEXT_GROUP)
596 return;
597 index = npc_get_nixlf_mcam_index(mcam, pcifunc,
598 nixlf, NIXLF_UCAST_ENTRY);
599 } else {
600 /* TODO: validate this mcam index */
601 index = mcam_index;
602 }
603
604 if (index >= mcam->total_entries)
605 return;
606
607 bank = npc_get_bank(mcam, index);
608 index &= (mcam->banksize - 1);
609
610 *(u64 *)&action = rvu_read64(rvu, blkaddr,
611 NPC_AF_MCAMEX_BANKX_ACTION(index, bank));
612 /* Ignore if no action was set earlier */
613 if (!*(u64 *)&action)
614 return;
615
616 action.op = NIX_RX_ACTIONOP_RSS;
617 action.pf_func = pcifunc;
618 action.index = group;
619 action.flow_key_alg = alg_idx;
620
621 rvu_write64(rvu, blkaddr,
622 NPC_AF_MCAMEX_BANKX_ACTION(index, bank), *(u64 *)&action);
623
624 index = npc_get_nixlf_mcam_index(mcam, pcifunc,
625 nixlf, NIXLF_PROMISC_ENTRY);
626
627 /* If PF's promiscuous entry is enabled,
628 * Set RSS action for that entry as well
629 */
630 if (is_mcam_entry_enabled(rvu, mcam, blkaddr, index)) {
631 bank = npc_get_bank(mcam, index);
632 index &= (mcam->banksize - 1);
633
634 rvu_write64(rvu, blkaddr,
635 NPC_AF_MCAMEX_BANKX_ACTION(index, bank),
636 *(u64 *)&action);
637 }
638
639 rvu_npc_update_rxvlan(rvu, pcifunc, nixlf);
640 }
641
npc_enadis_default_entries(struct rvu * rvu,u16 pcifunc,int nixlf,bool enable)642 static void npc_enadis_default_entries(struct rvu *rvu, u16 pcifunc,
643 int nixlf, bool enable)
644 {
645 struct npc_mcam *mcam = &rvu->hw->mcam;
646 struct nix_rx_action action;
647 int index, bank, blkaddr;
648
649 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
650 if (blkaddr < 0)
651 return;
652
653 /* Ucast MCAM match entry of this PF/VF */
654 index = npc_get_nixlf_mcam_index(mcam, pcifunc,
655 nixlf, NIXLF_UCAST_ENTRY);
656 npc_enable_mcam_entry(rvu, mcam, blkaddr, index, enable);
657
658 /* For PF, ena/dis promisc and bcast MCAM match entries.
659 * For VFs add/delete from bcast list when RX multicast
660 * feature is present.
661 */
662 if (pcifunc & RVU_PFVF_FUNC_MASK && !rvu->hw->cap.nix_rx_multicast)
663 return;
664
665 /* For bcast, enable/disable only if it's action is not
666 * packet replication, incase if action is replication
667 * then this PF/VF's nixlf is removed from bcast replication
668 * list.
669 */
670 index = npc_get_nixlf_mcam_index(mcam, pcifunc & ~RVU_PFVF_FUNC_MASK,
671 nixlf, NIXLF_BCAST_ENTRY);
672 bank = npc_get_bank(mcam, index);
673 *(u64 *)&action = rvu_read64(rvu, blkaddr,
674 NPC_AF_MCAMEX_BANKX_ACTION(index & (mcam->banksize - 1), bank));
675
676 /* VFs will not have BCAST entry */
677 if (action.op != NIX_RX_ACTIONOP_MCAST &&
678 !(pcifunc & RVU_PFVF_FUNC_MASK)) {
679 npc_enable_mcam_entry(rvu, mcam,
680 blkaddr, index, enable);
681 } else {
682 nix_update_bcast_mce_list(rvu, pcifunc, enable);
683 /* Enable PF's BCAST entry for packet replication */
684 rvu_npc_enable_bcast_entry(rvu, pcifunc, enable);
685 }
686
687 if (enable)
688 rvu_npc_enable_promisc_entry(rvu, pcifunc, nixlf);
689 else
690 rvu_npc_disable_promisc_entry(rvu, pcifunc, nixlf);
691
692 rvu_npc_update_rxvlan(rvu, pcifunc, nixlf);
693 }
694
rvu_npc_disable_default_entries(struct rvu * rvu,u16 pcifunc,int nixlf)695 void rvu_npc_disable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf)
696 {
697 npc_enadis_default_entries(rvu, pcifunc, nixlf, false);
698 }
699
rvu_npc_enable_default_entries(struct rvu * rvu,u16 pcifunc,int nixlf)700 void rvu_npc_enable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf)
701 {
702 npc_enadis_default_entries(rvu, pcifunc, nixlf, true);
703 }
704
rvu_npc_disable_mcam_entries(struct rvu * rvu,u16 pcifunc,int nixlf)705 void rvu_npc_disable_mcam_entries(struct rvu *rvu, u16 pcifunc, int nixlf)
706 {
707 struct npc_mcam *mcam = &rvu->hw->mcam;
708 int blkaddr;
709
710 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
711 if (blkaddr < 0)
712 return;
713
714 mutex_lock(&mcam->lock);
715
716 /* Disable and free all MCAM entries mapped to this 'pcifunc' */
717 npc_mcam_free_all_entries(rvu, mcam, blkaddr, pcifunc);
718
719 /* Free all MCAM counters mapped to this 'pcifunc' */
720 npc_mcam_free_all_counters(rvu, mcam, pcifunc);
721
722 mutex_unlock(&mcam->lock);
723
724 rvu_npc_disable_default_entries(rvu, pcifunc, nixlf);
725 }
726
727 #define SET_KEX_LD(intf, lid, ltype, ld, cfg) \
728 rvu_write64(rvu, blkaddr, \
729 NPC_AF_INTFX_LIDX_LTX_LDX_CFG(intf, lid, ltype, ld), cfg)
730
731 #define SET_KEX_LDFLAGS(intf, ld, flags, cfg) \
732 rvu_write64(rvu, blkaddr, \
733 NPC_AF_INTFX_LDATAX_FLAGSX_CFG(intf, ld, flags), cfg)
734
npc_program_mkex_profile(struct rvu * rvu,int blkaddr,const struct npc_mcam_kex * mkex)735 static void npc_program_mkex_profile(struct rvu *rvu, int blkaddr,
736 const struct npc_mcam_kex *mkex)
737 {
738 int lid, lt, ld, fl;
739
740 rvu_write64(rvu, blkaddr, NPC_AF_INTFX_KEX_CFG(NIX_INTF_RX),
741 mkex->keyx_cfg[NIX_INTF_RX]);
742 rvu_write64(rvu, blkaddr, NPC_AF_INTFX_KEX_CFG(NIX_INTF_TX),
743 mkex->keyx_cfg[NIX_INTF_TX]);
744
745 for (ld = 0; ld < NPC_MAX_LD; ld++)
746 rvu_write64(rvu, blkaddr, NPC_AF_KEX_LDATAX_FLAGS_CFG(ld),
747 mkex->kex_ld_flags[ld]);
748
749 for (lid = 0; lid < NPC_MAX_LID; lid++) {
750 for (lt = 0; lt < NPC_MAX_LT; lt++) {
751 for (ld = 0; ld < NPC_MAX_LD; ld++) {
752 SET_KEX_LD(NIX_INTF_RX, lid, lt, ld,
753 mkex->intf_lid_lt_ld[NIX_INTF_RX]
754 [lid][lt][ld]);
755
756 SET_KEX_LD(NIX_INTF_TX, lid, lt, ld,
757 mkex->intf_lid_lt_ld[NIX_INTF_TX]
758 [lid][lt][ld]);
759 }
760 }
761 }
762
763 for (ld = 0; ld < NPC_MAX_LD; ld++) {
764 for (fl = 0; fl < NPC_MAX_LFL; fl++) {
765 SET_KEX_LDFLAGS(NIX_INTF_RX, ld, fl,
766 mkex->intf_ld_flags[NIX_INTF_RX]
767 [ld][fl]);
768
769 SET_KEX_LDFLAGS(NIX_INTF_TX, ld, fl,
770 mkex->intf_ld_flags[NIX_INTF_TX]
771 [ld][fl]);
772 }
773 }
774 }
775
776 #define MKEX_END_SIGN 0xdeadbeef
777
npc_load_mkex_profile(struct rvu * rvu,int blkaddr,const char * mkex_profile)778 static void npc_load_mkex_profile(struct rvu *rvu, int blkaddr,
779 const char *mkex_profile)
780 {
781 struct device *dev = &rvu->pdev->dev;
782 struct npc_mcam_kex *mcam_kex;
783 void *mkex_prfl_addr = NULL;
784 u64 prfl_addr, prfl_sz;
785
786 /* If user not selected mkex profile */
787 if (!strncmp(mkex_profile, def_pfl_name, MKEX_NAME_LEN))
788 goto program_mkex;
789
790 if (!rvu->fwdata)
791 goto program_mkex;
792 prfl_addr = rvu->fwdata->mcam_addr;
793 prfl_sz = rvu->fwdata->mcam_sz;
794
795 if (!prfl_addr || !prfl_sz)
796 goto program_mkex;
797
798 mkex_prfl_addr = memremap(prfl_addr, prfl_sz, MEMREMAP_WC);
799 if (!mkex_prfl_addr)
800 goto program_mkex;
801
802 mcam_kex = (struct npc_mcam_kex *)mkex_prfl_addr;
803
804 while (((s64)prfl_sz > 0) && (mcam_kex->mkex_sign != MKEX_END_SIGN)) {
805 /* Compare with mkex mod_param name string */
806 if (mcam_kex->mkex_sign == MKEX_SIGN &&
807 !strncmp(mcam_kex->name, mkex_profile, MKEX_NAME_LEN)) {
808 /* Due to an errata (35786) in A0/B0 pass silicon,
809 * parse nibble enable configuration has to be
810 * identical for both Rx and Tx interfaces.
811 */
812 if (!is_rvu_96xx_B0(rvu) ||
813 mcam_kex->keyx_cfg[NIX_INTF_RX] == mcam_kex->keyx_cfg[NIX_INTF_TX])
814 rvu->kpu.mkex = mcam_kex;
815 goto program_mkex;
816 }
817
818 mcam_kex++;
819 prfl_sz -= sizeof(struct npc_mcam_kex);
820 }
821 dev_warn(dev, "Failed to load requested profile: %s\n", mkex_profile);
822
823 program_mkex:
824 dev_info(rvu->dev, "Using %s mkex profile\n", rvu->kpu.mkex->name);
825 /* Program selected mkex profile */
826 npc_program_mkex_profile(rvu, blkaddr, rvu->kpu.mkex);
827 if (mkex_prfl_addr)
828 memunmap(mkex_prfl_addr);
829 }
830
npc_config_kpuaction(struct rvu * rvu,int blkaddr,const struct npc_kpu_profile_action * kpuaction,int kpu,int entry,bool pkind)831 static void npc_config_kpuaction(struct rvu *rvu, int blkaddr,
832 const struct npc_kpu_profile_action *kpuaction,
833 int kpu, int entry, bool pkind)
834 {
835 struct npc_kpu_action0 action0 = {0};
836 struct npc_kpu_action1 action1 = {0};
837 u64 reg;
838
839 action1.errlev = kpuaction->errlev;
840 action1.errcode = kpuaction->errcode;
841 action1.dp0_offset = kpuaction->dp0_offset;
842 action1.dp1_offset = kpuaction->dp1_offset;
843 action1.dp2_offset = kpuaction->dp2_offset;
844
845 if (pkind)
846 reg = NPC_AF_PKINDX_ACTION1(entry);
847 else
848 reg = NPC_AF_KPUX_ENTRYX_ACTION1(kpu, entry);
849
850 rvu_write64(rvu, blkaddr, reg, *(u64 *)&action1);
851
852 action0.byp_count = kpuaction->bypass_count;
853 action0.capture_ena = kpuaction->cap_ena;
854 action0.parse_done = kpuaction->parse_done;
855 action0.next_state = kpuaction->next_state;
856 action0.capture_lid = kpuaction->lid;
857 action0.capture_ltype = kpuaction->ltype;
858 action0.capture_flags = kpuaction->flags;
859 action0.ptr_advance = kpuaction->ptr_advance;
860 action0.var_len_offset = kpuaction->offset;
861 action0.var_len_mask = kpuaction->mask;
862 action0.var_len_right = kpuaction->right;
863 action0.var_len_shift = kpuaction->shift;
864
865 if (pkind)
866 reg = NPC_AF_PKINDX_ACTION0(entry);
867 else
868 reg = NPC_AF_KPUX_ENTRYX_ACTION0(kpu, entry);
869
870 rvu_write64(rvu, blkaddr, reg, *(u64 *)&action0);
871 }
872
npc_config_kpucam(struct rvu * rvu,int blkaddr,const struct npc_kpu_profile_cam * kpucam,int kpu,int entry)873 static void npc_config_kpucam(struct rvu *rvu, int blkaddr,
874 const struct npc_kpu_profile_cam *kpucam,
875 int kpu, int entry)
876 {
877 struct npc_kpu_cam cam0 = {0};
878 struct npc_kpu_cam cam1 = {0};
879
880 cam1.state = kpucam->state & kpucam->state_mask;
881 cam1.dp0_data = kpucam->dp0 & kpucam->dp0_mask;
882 cam1.dp1_data = kpucam->dp1 & kpucam->dp1_mask;
883 cam1.dp2_data = kpucam->dp2 & kpucam->dp2_mask;
884
885 cam0.state = ~kpucam->state & kpucam->state_mask;
886 cam0.dp0_data = ~kpucam->dp0 & kpucam->dp0_mask;
887 cam0.dp1_data = ~kpucam->dp1 & kpucam->dp1_mask;
888 cam0.dp2_data = ~kpucam->dp2 & kpucam->dp2_mask;
889
890 rvu_write64(rvu, blkaddr,
891 NPC_AF_KPUX_ENTRYX_CAMX(kpu, entry, 0), *(u64 *)&cam0);
892 rvu_write64(rvu, blkaddr,
893 NPC_AF_KPUX_ENTRYX_CAMX(kpu, entry, 1), *(u64 *)&cam1);
894 }
895
enable_mask(int count)896 static inline u64 enable_mask(int count)
897 {
898 return (((count) < 64) ? ~(BIT_ULL(count) - 1) : (0x00ULL));
899 }
900
npc_program_kpu_profile(struct rvu * rvu,int blkaddr,int kpu,const struct npc_kpu_profile * profile)901 static void npc_program_kpu_profile(struct rvu *rvu, int blkaddr, int kpu,
902 const struct npc_kpu_profile *profile)
903 {
904 int entry, num_entries, max_entries;
905
906 if (profile->cam_entries != profile->action_entries) {
907 dev_err(rvu->dev,
908 "KPU%d: CAM and action entries [%d != %d] not equal\n",
909 kpu, profile->cam_entries, profile->action_entries);
910 }
911
912 max_entries = rvu_read64(rvu, blkaddr, NPC_AF_CONST1) & 0xFFF;
913
914 /* Program CAM match entries for previous KPU extracted data */
915 num_entries = min_t(int, profile->cam_entries, max_entries);
916 for (entry = 0; entry < num_entries; entry++)
917 npc_config_kpucam(rvu, blkaddr,
918 &profile->cam[entry], kpu, entry);
919
920 /* Program this KPU's actions */
921 num_entries = min_t(int, profile->action_entries, max_entries);
922 for (entry = 0; entry < num_entries; entry++)
923 npc_config_kpuaction(rvu, blkaddr, &profile->action[entry],
924 kpu, entry, false);
925
926 /* Enable all programmed entries */
927 num_entries = min_t(int, profile->action_entries, profile->cam_entries);
928 rvu_write64(rvu, blkaddr,
929 NPC_AF_KPUX_ENTRY_DISX(kpu, 0), enable_mask(num_entries));
930 if (num_entries > 64) {
931 rvu_write64(rvu, blkaddr,
932 NPC_AF_KPUX_ENTRY_DISX(kpu, 1),
933 enable_mask(num_entries - 64));
934 }
935
936 /* Enable this KPU */
937 rvu_write64(rvu, blkaddr, NPC_AF_KPUX_CFG(kpu), 0x01);
938 }
939
npc_prepare_default_kpu(struct npc_kpu_profile_adapter * profile)940 static int npc_prepare_default_kpu(struct npc_kpu_profile_adapter *profile)
941 {
942 profile->name = def_pfl_name;
943 profile->version = NPC_KPU_PROFILE_VER;
944 profile->ikpu = ikpu_action_entries;
945 profile->pkinds = ARRAY_SIZE(ikpu_action_entries);
946 profile->kpu = npc_kpu_profiles;
947 profile->kpus = ARRAY_SIZE(npc_kpu_profiles);
948 profile->lt_def = &npc_lt_defaults;
949 profile->mkex = &npc_mkex_default;
950
951 return 0;
952 }
953
npc_load_kpu_profile(struct rvu * rvu)954 static void npc_load_kpu_profile(struct rvu *rvu)
955 {
956 struct npc_kpu_profile_adapter *profile = &rvu->kpu;
957
958 npc_prepare_default_kpu(profile);
959 }
960
npc_parser_profile_init(struct rvu * rvu,int blkaddr)961 static void npc_parser_profile_init(struct rvu *rvu, int blkaddr)
962 {
963 struct rvu_hwinfo *hw = rvu->hw;
964 int num_pkinds, num_kpus, idx;
965 struct npc_pkind *pkind;
966
967 /* Get HW limits */
968 hw->npc_kpus = (rvu_read64(rvu, blkaddr, NPC_AF_CONST) >> 8) & 0x1F;
969
970 /* Disable all KPUs and their entries */
971 for (idx = 0; idx < hw->npc_kpus; idx++) {
972 rvu_write64(rvu, blkaddr,
973 NPC_AF_KPUX_ENTRY_DISX(idx, 0), ~0ULL);
974 rvu_write64(rvu, blkaddr,
975 NPC_AF_KPUX_ENTRY_DISX(idx, 1), ~0ULL);
976 rvu_write64(rvu, blkaddr, NPC_AF_KPUX_CFG(idx), 0x00);
977 }
978
979 /* Load and customize KPU profile. */
980 npc_load_kpu_profile(rvu);
981
982 /* First program IKPU profile i.e PKIND configs.
983 * Check HW max count to avoid configuring junk or
984 * writing to unsupported CSR addresses.
985 */
986 pkind = &hw->pkind;
987 num_pkinds = rvu->kpu.pkinds;
988 num_pkinds = min_t(int, pkind->rsrc.max, num_pkinds);
989
990 for (idx = 0; idx < num_pkinds; idx++)
991 npc_config_kpuaction(rvu, blkaddr, &rvu->kpu.ikpu[idx], 0, idx, true);
992
993 /* Program KPU CAM and Action profiles */
994 num_kpus = rvu->kpu.kpus;
995 num_kpus = min_t(int, hw->npc_kpus, num_kpus);
996
997 for (idx = 0; idx < num_kpus; idx++)
998 npc_program_kpu_profile(rvu, blkaddr, idx, &rvu->kpu.kpu[idx]);
999 }
1000
npc_mcam_rsrcs_init(struct rvu * rvu,int blkaddr)1001 static int npc_mcam_rsrcs_init(struct rvu *rvu, int blkaddr)
1002 {
1003 int nixlf_count = rvu_get_nixlf_count(rvu);
1004 struct npc_mcam *mcam = &rvu->hw->mcam;
1005 int rsvd, err;
1006 u64 cfg;
1007
1008 /* Get HW limits */
1009 cfg = rvu_read64(rvu, blkaddr, NPC_AF_CONST);
1010 mcam->banks = (cfg >> 44) & 0xF;
1011 mcam->banksize = (cfg >> 28) & 0xFFFF;
1012 mcam->counters.max = (cfg >> 48) & 0xFFFF;
1013
1014 /* Actual number of MCAM entries vary by entry size */
1015 cfg = (rvu_read64(rvu, blkaddr,
1016 NPC_AF_INTFX_KEX_CFG(0)) >> 32) & 0x07;
1017 mcam->total_entries = (mcam->banks / BIT_ULL(cfg)) * mcam->banksize;
1018 mcam->keysize = cfg;
1019
1020 /* Number of banks combined per MCAM entry */
1021 if (cfg == NPC_MCAM_KEY_X4)
1022 mcam->banks_per_entry = 4;
1023 else if (cfg == NPC_MCAM_KEY_X2)
1024 mcam->banks_per_entry = 2;
1025 else
1026 mcam->banks_per_entry = 1;
1027
1028 /* Reserve one MCAM entry for each of the NIX LF to
1029 * guarantee space to install default matching DMAC rule.
1030 * Also reserve 2 MCAM entries for each PF for default
1031 * channel based matching or 'bcast & promisc' matching to
1032 * support BCAST and PROMISC modes of operation for PFs.
1033 * PF0 is excluded.
1034 */
1035 rsvd = (nixlf_count * RSVD_MCAM_ENTRIES_PER_NIXLF) +
1036 ((rvu->hw->total_pfs - 1) * RSVD_MCAM_ENTRIES_PER_PF);
1037 if (mcam->total_entries <= rsvd) {
1038 dev_warn(rvu->dev,
1039 "Insufficient NPC MCAM size %d for pkt I/O, exiting\n",
1040 mcam->total_entries);
1041 return -ENOMEM;
1042 }
1043
1044 mcam->bmap_entries = mcam->total_entries - rsvd;
1045 mcam->nixlf_offset = mcam->bmap_entries;
1046 mcam->pf_offset = mcam->nixlf_offset + nixlf_count;
1047
1048 /* Allocate bitmaps for managing MCAM entries */
1049 mcam->bmap = devm_kcalloc(rvu->dev, BITS_TO_LONGS(mcam->bmap_entries),
1050 sizeof(long), GFP_KERNEL);
1051 if (!mcam->bmap)
1052 return -ENOMEM;
1053
1054 mcam->bmap_reverse = devm_kcalloc(rvu->dev,
1055 BITS_TO_LONGS(mcam->bmap_entries),
1056 sizeof(long), GFP_KERNEL);
1057 if (!mcam->bmap_reverse)
1058 return -ENOMEM;
1059
1060 mcam->bmap_fcnt = mcam->bmap_entries;
1061
1062 /* Alloc memory for saving entry to RVU PFFUNC allocation mapping */
1063 mcam->entry2pfvf_map = devm_kcalloc(rvu->dev, mcam->bmap_entries,
1064 sizeof(u16), GFP_KERNEL);
1065 if (!mcam->entry2pfvf_map)
1066 return -ENOMEM;
1067
1068 /* Reserve 1/8th of MCAM entries at the bottom for low priority
1069 * allocations and another 1/8th at the top for high priority
1070 * allocations.
1071 */
1072 mcam->lprio_count = mcam->bmap_entries / 8;
1073 if (mcam->lprio_count > BITS_PER_LONG)
1074 mcam->lprio_count = round_down(mcam->lprio_count,
1075 BITS_PER_LONG);
1076 mcam->lprio_start = mcam->bmap_entries - mcam->lprio_count;
1077 mcam->hprio_count = mcam->lprio_count;
1078 mcam->hprio_end = mcam->hprio_count;
1079
1080 /* Reserve last counter for MCAM RX miss action which is set to
1081 * drop pkt. This way we will know how many pkts didn't match
1082 * any MCAM entry.
1083 */
1084 mcam->counters.max--;
1085 mcam->rx_miss_act_cntr = mcam->counters.max;
1086
1087 /* Allocate bitmap for managing MCAM counters and memory
1088 * for saving counter to RVU PFFUNC allocation mapping.
1089 */
1090 err = rvu_alloc_bitmap(&mcam->counters);
1091 if (err)
1092 return err;
1093
1094 mcam->cntr2pfvf_map = devm_kcalloc(rvu->dev, mcam->counters.max,
1095 sizeof(u16), GFP_KERNEL);
1096 if (!mcam->cntr2pfvf_map)
1097 goto free_mem;
1098
1099 /* Alloc memory for MCAM entry to counter mapping and for tracking
1100 * counter's reference count.
1101 */
1102 mcam->entry2cntr_map = devm_kcalloc(rvu->dev, mcam->bmap_entries,
1103 sizeof(u16), GFP_KERNEL);
1104 if (!mcam->entry2cntr_map)
1105 goto free_mem;
1106
1107 mcam->cntr_refcnt = devm_kcalloc(rvu->dev, mcam->counters.max,
1108 sizeof(u16), GFP_KERNEL);
1109 if (!mcam->cntr_refcnt)
1110 goto free_mem;
1111
1112 mutex_init(&mcam->lock);
1113
1114 return 0;
1115
1116 free_mem:
1117 kfree(mcam->counters.bmap);
1118 return -ENOMEM;
1119 }
1120
rvu_npc_init(struct rvu * rvu)1121 int rvu_npc_init(struct rvu *rvu)
1122 {
1123 struct npc_kpu_profile_adapter *kpu = &rvu->kpu;
1124 struct npc_pkind *pkind = &rvu->hw->pkind;
1125 struct npc_mcam *mcam = &rvu->hw->mcam;
1126 u64 cfg, nibble_ena, rx_kex, tx_kex;
1127 int blkaddr, entry, bank, err;
1128
1129 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
1130 if (blkaddr < 0) {
1131 dev_err(rvu->dev, "%s: NPC block not implemented\n", __func__);
1132 return -ENODEV;
1133 }
1134
1135 /* First disable all MCAM entries, to stop traffic towards NIXLFs */
1136 cfg = rvu_read64(rvu, blkaddr, NPC_AF_CONST);
1137 for (bank = 0; bank < ((cfg >> 44) & 0xF); bank++) {
1138 for (entry = 0; entry < ((cfg >> 28) & 0xFFFF); entry++)
1139 rvu_write64(rvu, blkaddr,
1140 NPC_AF_MCAMEX_BANKX_CFG(entry, bank), 0);
1141 }
1142
1143 /* Allocate resource bimap for pkind*/
1144 pkind->rsrc.max = (rvu_read64(rvu, blkaddr,
1145 NPC_AF_CONST1) >> 12) & 0xFF;
1146 err = rvu_alloc_bitmap(&pkind->rsrc);
1147 if (err)
1148 return err;
1149
1150 /* Allocate mem for pkind to PF and channel mapping info */
1151 pkind->pfchan_map = devm_kcalloc(rvu->dev, pkind->rsrc.max,
1152 sizeof(u32), GFP_KERNEL);
1153 if (!pkind->pfchan_map)
1154 return -ENOMEM;
1155
1156 /* Configure KPU profile */
1157 npc_parser_profile_init(rvu, blkaddr);
1158
1159 /* Config Outer L2, IPv4's NPC layer info */
1160 rvu_write64(rvu, blkaddr, NPC_AF_PCK_DEF_OL2,
1161 (kpu->lt_def->pck_ol2.lid << 8) | (kpu->lt_def->pck_ol2.ltype_match << 4) |
1162 kpu->lt_def->pck_ol2.ltype_mask);
1163 rvu_write64(rvu, blkaddr, NPC_AF_PCK_DEF_OIP4,
1164 (kpu->lt_def->pck_oip4.lid << 8) | (kpu->lt_def->pck_oip4.ltype_match << 4) |
1165 kpu->lt_def->pck_oip4.ltype_mask);
1166
1167 /* Config Inner IPV4 NPC layer info */
1168 rvu_write64(rvu, blkaddr, NPC_AF_PCK_DEF_IIP4,
1169 (kpu->lt_def->pck_iip4.lid << 8) | (kpu->lt_def->pck_iip4.ltype_match << 4) |
1170 kpu->lt_def->pck_iip4.ltype_mask);
1171
1172 /* Enable below for Rx pkts.
1173 * - Outer IPv4 header checksum validation.
1174 * - Detect outer L2 broadcast address and set NPC_RESULT_S[L2B].
1175 * - Detect outer L2 multicast address and set NPC_RESULT_S[L2M].
1176 * - Inner IPv4 header checksum validation.
1177 * - Set non zero checksum error code value
1178 */
1179 rvu_write64(rvu, blkaddr, NPC_AF_PCK_CFG,
1180 rvu_read64(rvu, blkaddr, NPC_AF_PCK_CFG) |
1181 ((u64)NPC_EC_OIP4_CSUM << 32) | (NPC_EC_IIP4_CSUM << 24) |
1182 BIT_ULL(7) | BIT_ULL(6) | BIT_ULL(2) | BIT_ULL(1));
1183
1184 /* Set RX and TX side MCAM search key size.
1185 * LA..LD (ltype only) + Channel
1186 */
1187 rx_kex = npc_mkex_default.keyx_cfg[NIX_INTF_RX];
1188 tx_kex = npc_mkex_default.keyx_cfg[NIX_INTF_TX];
1189 nibble_ena = FIELD_GET(NPC_PARSE_NIBBLE, rx_kex);
1190 rvu_write64(rvu, blkaddr, NPC_AF_INTFX_KEX_CFG(NIX_INTF_RX), rx_kex);
1191 /* Due to an errata (35786) in A0 pass silicon, parse nibble enable
1192 * configuration has to be identical for both Rx and Tx interfaces.
1193 */
1194 if (is_rvu_96xx_B0(rvu)) {
1195 tx_kex &= ~NPC_PARSE_NIBBLE;
1196 tx_kex |= FIELD_PREP(NPC_PARSE_NIBBLE, nibble_ena);
1197 }
1198 rvu_write64(rvu, blkaddr, NPC_AF_INTFX_KEX_CFG(NIX_INTF_TX), tx_kex);
1199
1200 err = npc_mcam_rsrcs_init(rvu, blkaddr);
1201 if (err)
1202 return err;
1203
1204 /* Configure MKEX profile */
1205 npc_load_mkex_profile(rvu, blkaddr, rvu->mkex_pfl_name);
1206
1207 /* Set TX miss action to UCAST_DEFAULT i.e
1208 * transmit the packet on NIX LF SQ's default channel.
1209 */
1210 rvu_write64(rvu, blkaddr, NPC_AF_INTFX_MISS_ACT(NIX_INTF_TX),
1211 NIX_TX_ACTIONOP_UCAST_DEFAULT);
1212
1213 /* If MCAM lookup doesn't result in a match, drop the received packet.
1214 * And map this action to a counter to count dropped pkts.
1215 */
1216 rvu_write64(rvu, blkaddr, NPC_AF_INTFX_MISS_ACT(NIX_INTF_RX),
1217 NIX_RX_ACTIONOP_DROP);
1218 rvu_write64(rvu, blkaddr, NPC_AF_INTFX_MISS_STAT_ACT(NIX_INTF_RX),
1219 BIT_ULL(9) | mcam->rx_miss_act_cntr);
1220
1221 return 0;
1222 }
1223
rvu_npc_freemem(struct rvu * rvu)1224 void rvu_npc_freemem(struct rvu *rvu)
1225 {
1226 struct npc_pkind *pkind = &rvu->hw->pkind;
1227 struct npc_mcam *mcam = &rvu->hw->mcam;
1228
1229 kfree(pkind->rsrc.bmap);
1230 kfree(mcam->counters.bmap);
1231 mutex_destroy(&mcam->lock);
1232 }
1233
rvu_npc_get_mcam_entry_alloc_info(struct rvu * rvu,u16 pcifunc,int blkaddr,int * alloc_cnt,int * enable_cnt)1234 void rvu_npc_get_mcam_entry_alloc_info(struct rvu *rvu, u16 pcifunc,
1235 int blkaddr, int *alloc_cnt,
1236 int *enable_cnt)
1237 {
1238 struct npc_mcam *mcam = &rvu->hw->mcam;
1239 int entry;
1240
1241 *alloc_cnt = 0;
1242 *enable_cnt = 0;
1243
1244 for (entry = 0; entry < mcam->bmap_entries; entry++) {
1245 if (mcam->entry2pfvf_map[entry] == pcifunc) {
1246 (*alloc_cnt)++;
1247 if (is_mcam_entry_enabled(rvu, mcam, blkaddr, entry))
1248 (*enable_cnt)++;
1249 }
1250 }
1251 }
1252
rvu_npc_get_mcam_counter_alloc_info(struct rvu * rvu,u16 pcifunc,int blkaddr,int * alloc_cnt,int * enable_cnt)1253 void rvu_npc_get_mcam_counter_alloc_info(struct rvu *rvu, u16 pcifunc,
1254 int blkaddr, int *alloc_cnt,
1255 int *enable_cnt)
1256 {
1257 struct npc_mcam *mcam = &rvu->hw->mcam;
1258 int cntr;
1259
1260 *alloc_cnt = 0;
1261 *enable_cnt = 0;
1262
1263 for (cntr = 0; cntr < mcam->counters.max; cntr++) {
1264 if (mcam->cntr2pfvf_map[cntr] == pcifunc) {
1265 (*alloc_cnt)++;
1266 if (mcam->cntr_refcnt[cntr])
1267 (*enable_cnt)++;
1268 }
1269 }
1270 }
1271
npc_mcam_verify_entry(struct npc_mcam * mcam,u16 pcifunc,int entry)1272 static int npc_mcam_verify_entry(struct npc_mcam *mcam,
1273 u16 pcifunc, int entry)
1274 {
1275 /* Verify if entry is valid and if it is indeed
1276 * allocated to the requesting PFFUNC.
1277 */
1278 if (entry >= mcam->bmap_entries)
1279 return NPC_MCAM_INVALID_REQ;
1280
1281 if (pcifunc != mcam->entry2pfvf_map[entry])
1282 return NPC_MCAM_PERM_DENIED;
1283
1284 return 0;
1285 }
1286
npc_mcam_verify_counter(struct npc_mcam * mcam,u16 pcifunc,int cntr)1287 static int npc_mcam_verify_counter(struct npc_mcam *mcam,
1288 u16 pcifunc, int cntr)
1289 {
1290 /* Verify if counter is valid and if it is indeed
1291 * allocated to the requesting PFFUNC.
1292 */
1293 if (cntr >= mcam->counters.max)
1294 return NPC_MCAM_INVALID_REQ;
1295
1296 if (pcifunc != mcam->cntr2pfvf_map[cntr])
1297 return NPC_MCAM_PERM_DENIED;
1298
1299 return 0;
1300 }
1301
npc_map_mcam_entry_and_cntr(struct rvu * rvu,struct npc_mcam * mcam,int blkaddr,u16 entry,u16 cntr)1302 static void npc_map_mcam_entry_and_cntr(struct rvu *rvu, struct npc_mcam *mcam,
1303 int blkaddr, u16 entry, u16 cntr)
1304 {
1305 u16 index = entry & (mcam->banksize - 1);
1306 u16 bank = npc_get_bank(mcam, entry);
1307
1308 /* Set mapping and increment counter's refcnt */
1309 mcam->entry2cntr_map[entry] = cntr;
1310 mcam->cntr_refcnt[cntr]++;
1311 /* Enable stats */
1312 rvu_write64(rvu, blkaddr,
1313 NPC_AF_MCAMEX_BANKX_STAT_ACT(index, bank),
1314 BIT_ULL(9) | cntr);
1315 }
1316
npc_unmap_mcam_entry_and_cntr(struct rvu * rvu,struct npc_mcam * mcam,int blkaddr,u16 entry,u16 cntr)1317 static void npc_unmap_mcam_entry_and_cntr(struct rvu *rvu,
1318 struct npc_mcam *mcam,
1319 int blkaddr, u16 entry, u16 cntr)
1320 {
1321 u16 index = entry & (mcam->banksize - 1);
1322 u32 bank = npc_get_bank(mcam, entry);
1323
1324 /* Remove mapping and reduce counter's refcnt */
1325 mcam->entry2cntr_map[entry] = NPC_MCAM_INVALID_MAP;
1326 mcam->cntr_refcnt[cntr]--;
1327 /* Disable stats */
1328 rvu_write64(rvu, blkaddr,
1329 NPC_AF_MCAMEX_BANKX_STAT_ACT(index, bank), 0x00);
1330 }
1331
1332 /* Sets MCAM entry in bitmap as used. Update
1333 * reverse bitmap too. Should be called with
1334 * 'mcam->lock' held.
1335 */
npc_mcam_set_bit(struct npc_mcam * mcam,u16 index)1336 static void npc_mcam_set_bit(struct npc_mcam *mcam, u16 index)
1337 {
1338 u16 entry, rentry;
1339
1340 entry = index;
1341 rentry = mcam->bmap_entries - index - 1;
1342
1343 __set_bit(entry, mcam->bmap);
1344 __set_bit(rentry, mcam->bmap_reverse);
1345 mcam->bmap_fcnt--;
1346 }
1347
1348 /* Sets MCAM entry in bitmap as free. Update
1349 * reverse bitmap too. Should be called with
1350 * 'mcam->lock' held.
1351 */
npc_mcam_clear_bit(struct npc_mcam * mcam,u16 index)1352 static void npc_mcam_clear_bit(struct npc_mcam *mcam, u16 index)
1353 {
1354 u16 entry, rentry;
1355
1356 entry = index;
1357 rentry = mcam->bmap_entries - index - 1;
1358
1359 __clear_bit(entry, mcam->bmap);
1360 __clear_bit(rentry, mcam->bmap_reverse);
1361 mcam->bmap_fcnt++;
1362 }
1363
npc_mcam_free_all_entries(struct rvu * rvu,struct npc_mcam * mcam,int blkaddr,u16 pcifunc)1364 static void npc_mcam_free_all_entries(struct rvu *rvu, struct npc_mcam *mcam,
1365 int blkaddr, u16 pcifunc)
1366 {
1367 u16 index, cntr;
1368
1369 /* Scan all MCAM entries and free the ones mapped to 'pcifunc' */
1370 for (index = 0; index < mcam->bmap_entries; index++) {
1371 if (mcam->entry2pfvf_map[index] == pcifunc) {
1372 mcam->entry2pfvf_map[index] = NPC_MCAM_INVALID_MAP;
1373 /* Free the entry in bitmap */
1374 npc_mcam_clear_bit(mcam, index);
1375 /* Disable the entry */
1376 npc_enable_mcam_entry(rvu, mcam, blkaddr, index, false);
1377
1378 /* Update entry2counter mapping */
1379 cntr = mcam->entry2cntr_map[index];
1380 if (cntr != NPC_MCAM_INVALID_MAP)
1381 npc_unmap_mcam_entry_and_cntr(rvu, mcam,
1382 blkaddr, index,
1383 cntr);
1384 }
1385 }
1386 }
1387
npc_mcam_free_all_counters(struct rvu * rvu,struct npc_mcam * mcam,u16 pcifunc)1388 static void npc_mcam_free_all_counters(struct rvu *rvu, struct npc_mcam *mcam,
1389 u16 pcifunc)
1390 {
1391 u16 cntr;
1392
1393 /* Scan all MCAM counters and free the ones mapped to 'pcifunc' */
1394 for (cntr = 0; cntr < mcam->counters.max; cntr++) {
1395 if (mcam->cntr2pfvf_map[cntr] == pcifunc) {
1396 mcam->cntr2pfvf_map[cntr] = NPC_MCAM_INVALID_MAP;
1397 mcam->cntr_refcnt[cntr] = 0;
1398 rvu_free_rsrc(&mcam->counters, cntr);
1399 /* This API is expected to be called after freeing
1400 * MCAM entries, which inturn will remove
1401 * 'entry to counter' mapping.
1402 * No need to do it again.
1403 */
1404 }
1405 }
1406 }
1407
1408 /* Find area of contiguous free entries of size 'nr'.
1409 * If not found return max contiguous free entries available.
1410 */
npc_mcam_find_zero_area(unsigned long * map,u16 size,u16 start,u16 nr,u16 * max_area)1411 static u16 npc_mcam_find_zero_area(unsigned long *map, u16 size, u16 start,
1412 u16 nr, u16 *max_area)
1413 {
1414 u16 max_area_start = 0;
1415 u16 index, next, end;
1416
1417 *max_area = 0;
1418
1419 again:
1420 index = find_next_zero_bit(map, size, start);
1421 if (index >= size)
1422 return max_area_start;
1423
1424 end = ((index + nr) >= size) ? size : index + nr;
1425 next = find_next_bit(map, end, index);
1426 if (*max_area < (next - index)) {
1427 *max_area = next - index;
1428 max_area_start = index;
1429 }
1430
1431 if (next < end) {
1432 start = next + 1;
1433 goto again;
1434 }
1435
1436 return max_area_start;
1437 }
1438
1439 /* Find number of free MCAM entries available
1440 * within range i.e in between 'start' and 'end'.
1441 */
npc_mcam_get_free_count(unsigned long * map,u16 start,u16 end)1442 static u16 npc_mcam_get_free_count(unsigned long *map, u16 start, u16 end)
1443 {
1444 u16 index, next;
1445 u16 fcnt = 0;
1446
1447 again:
1448 if (start >= end)
1449 return fcnt;
1450
1451 index = find_next_zero_bit(map, end, start);
1452 if (index >= end)
1453 return fcnt;
1454
1455 next = find_next_bit(map, end, index);
1456 if (next <= end) {
1457 fcnt += next - index;
1458 start = next + 1;
1459 goto again;
1460 }
1461
1462 fcnt += end - index;
1463 return fcnt;
1464 }
1465
1466 static void
npc_get_mcam_search_range_priority(struct npc_mcam * mcam,struct npc_mcam_alloc_entry_req * req,u16 * start,u16 * end,bool * reverse)1467 npc_get_mcam_search_range_priority(struct npc_mcam *mcam,
1468 struct npc_mcam_alloc_entry_req *req,
1469 u16 *start, u16 *end, bool *reverse)
1470 {
1471 u16 fcnt;
1472
1473 if (req->priority == NPC_MCAM_HIGHER_PRIO)
1474 goto hprio;
1475
1476 /* For a low priority entry allocation
1477 * - If reference entry is not in hprio zone then
1478 * search range: ref_entry to end.
1479 * - If reference entry is in hprio zone and if
1480 * request can be accomodated in non-hprio zone then
1481 * search range: 'start of middle zone' to 'end'
1482 * - else search in reverse, so that less number of hprio
1483 * zone entries are allocated.
1484 */
1485
1486 *reverse = false;
1487 *start = req->ref_entry + 1;
1488 *end = mcam->bmap_entries;
1489
1490 if (req->ref_entry >= mcam->hprio_end)
1491 return;
1492
1493 fcnt = npc_mcam_get_free_count(mcam->bmap,
1494 mcam->hprio_end, mcam->bmap_entries);
1495 if (fcnt > req->count)
1496 *start = mcam->hprio_end;
1497 else
1498 *reverse = true;
1499 return;
1500
1501 hprio:
1502 /* For a high priority entry allocation, search is always
1503 * in reverse to preserve hprio zone entries.
1504 * - If reference entry is not in lprio zone then
1505 * search range: 0 to ref_entry.
1506 * - If reference entry is in lprio zone and if
1507 * request can be accomodated in middle zone then
1508 * search range: 'hprio_end' to 'lprio_start'
1509 */
1510
1511 *reverse = true;
1512 *start = 0;
1513 *end = req->ref_entry;
1514
1515 if (req->ref_entry <= mcam->lprio_start)
1516 return;
1517
1518 fcnt = npc_mcam_get_free_count(mcam->bmap,
1519 mcam->hprio_end, mcam->lprio_start);
1520 if (fcnt < req->count)
1521 return;
1522 *start = mcam->hprio_end;
1523 *end = mcam->lprio_start;
1524 }
1525
npc_mcam_alloc_entries(struct npc_mcam * mcam,u16 pcifunc,struct npc_mcam_alloc_entry_req * req,struct npc_mcam_alloc_entry_rsp * rsp)1526 static int npc_mcam_alloc_entries(struct npc_mcam *mcam, u16 pcifunc,
1527 struct npc_mcam_alloc_entry_req *req,
1528 struct npc_mcam_alloc_entry_rsp *rsp)
1529 {
1530 u16 entry_list[NPC_MAX_NONCONTIG_ENTRIES];
1531 u16 fcnt, hp_fcnt, lp_fcnt;
1532 u16 start, end, index;
1533 int entry, next_start;
1534 bool reverse = false;
1535 unsigned long *bmap;
1536 u16 max_contig;
1537
1538 mutex_lock(&mcam->lock);
1539
1540 /* Check if there are any free entries */
1541 if (!mcam->bmap_fcnt) {
1542 mutex_unlock(&mcam->lock);
1543 return NPC_MCAM_ALLOC_FAILED;
1544 }
1545
1546 /* MCAM entries are divided into high priority, middle and
1547 * low priority zones. Idea is to not allocate top and lower
1548 * most entries as much as possible, this is to increase
1549 * probability of honouring priority allocation requests.
1550 *
1551 * Two bitmaps are used for mcam entry management,
1552 * mcam->bmap for forward search i.e '0 to mcam->bmap_entries'.
1553 * mcam->bmap_reverse for reverse search i.e 'mcam->bmap_entries to 0'.
1554 *
1555 * Reverse bitmap is used to allocate entries
1556 * - when a higher priority entry is requested
1557 * - when available free entries are less.
1558 * Lower priority ones out of avaialble free entries are always
1559 * chosen when 'high vs low' question arises.
1560 */
1561
1562 /* Get the search range for priority allocation request */
1563 if (req->priority) {
1564 npc_get_mcam_search_range_priority(mcam, req,
1565 &start, &end, &reverse);
1566 goto alloc;
1567 }
1568
1569 /* Find out the search range for non-priority allocation request
1570 *
1571 * Get MCAM free entry count in middle zone.
1572 */
1573 lp_fcnt = npc_mcam_get_free_count(mcam->bmap,
1574 mcam->lprio_start,
1575 mcam->bmap_entries);
1576 hp_fcnt = npc_mcam_get_free_count(mcam->bmap, 0, mcam->hprio_end);
1577 fcnt = mcam->bmap_fcnt - lp_fcnt - hp_fcnt;
1578
1579 /* Check if request can be accomodated in the middle zone */
1580 if (fcnt > req->count) {
1581 start = mcam->hprio_end;
1582 end = mcam->lprio_start;
1583 } else if ((fcnt + (hp_fcnt / 2) + (lp_fcnt / 2)) > req->count) {
1584 /* Expand search zone from half of hprio zone to
1585 * half of lprio zone.
1586 */
1587 start = mcam->hprio_end / 2;
1588 end = mcam->bmap_entries - (mcam->lprio_count / 2);
1589 reverse = true;
1590 } else {
1591 /* Not enough free entries, search all entries in reverse,
1592 * so that low priority ones will get used up.
1593 */
1594 reverse = true;
1595 start = 0;
1596 end = mcam->bmap_entries;
1597 }
1598
1599 alloc:
1600 if (reverse) {
1601 bmap = mcam->bmap_reverse;
1602 start = mcam->bmap_entries - start;
1603 end = mcam->bmap_entries - end;
1604 index = start;
1605 start = end;
1606 end = index;
1607 } else {
1608 bmap = mcam->bmap;
1609 }
1610
1611 if (req->contig) {
1612 /* Allocate requested number of contiguous entries, if
1613 * unsuccessful find max contiguous entries available.
1614 */
1615 index = npc_mcam_find_zero_area(bmap, end, start,
1616 req->count, &max_contig);
1617 rsp->count = max_contig;
1618 if (reverse)
1619 rsp->entry = mcam->bmap_entries - index - max_contig;
1620 else
1621 rsp->entry = index;
1622 } else {
1623 /* Allocate requested number of non-contiguous entries,
1624 * if unsuccessful allocate as many as possible.
1625 */
1626 rsp->count = 0;
1627 next_start = start;
1628 for (entry = 0; entry < req->count; entry++) {
1629 index = find_next_zero_bit(bmap, end, next_start);
1630 if (index >= end)
1631 break;
1632
1633 next_start = start + (index - start) + 1;
1634
1635 /* Save the entry's index */
1636 if (reverse)
1637 index = mcam->bmap_entries - index - 1;
1638 entry_list[entry] = index;
1639 rsp->count++;
1640 }
1641 }
1642
1643 /* If allocating requested no of entries is unsucessful,
1644 * expand the search range to full bitmap length and retry.
1645 */
1646 if (!req->priority && (rsp->count < req->count) &&
1647 ((end - start) != mcam->bmap_entries)) {
1648 reverse = true;
1649 start = 0;
1650 end = mcam->bmap_entries;
1651 goto alloc;
1652 }
1653
1654 /* For priority entry allocation requests, if allocation is
1655 * failed then expand search to max possible range and retry.
1656 */
1657 if (req->priority && rsp->count < req->count) {
1658 if (req->priority == NPC_MCAM_LOWER_PRIO &&
1659 (start != (req->ref_entry + 1))) {
1660 start = req->ref_entry + 1;
1661 end = mcam->bmap_entries;
1662 reverse = false;
1663 goto alloc;
1664 } else if ((req->priority == NPC_MCAM_HIGHER_PRIO) &&
1665 ((end - start) != req->ref_entry)) {
1666 start = 0;
1667 end = req->ref_entry;
1668 reverse = true;
1669 goto alloc;
1670 }
1671 }
1672
1673 /* Copy MCAM entry indices into mbox response entry_list.
1674 * Requester always expects indices in ascending order, so
1675 * so reverse the list if reverse bitmap is used for allocation.
1676 */
1677 if (!req->contig && rsp->count) {
1678 index = 0;
1679 for (entry = rsp->count - 1; entry >= 0; entry--) {
1680 if (reverse)
1681 rsp->entry_list[index++] = entry_list[entry];
1682 else
1683 rsp->entry_list[entry] = entry_list[entry];
1684 }
1685 }
1686
1687 /* Mark the allocated entries as used and set nixlf mapping */
1688 for (entry = 0; entry < rsp->count; entry++) {
1689 index = req->contig ?
1690 (rsp->entry + entry) : rsp->entry_list[entry];
1691 npc_mcam_set_bit(mcam, index);
1692 mcam->entry2pfvf_map[index] = pcifunc;
1693 mcam->entry2cntr_map[index] = NPC_MCAM_INVALID_MAP;
1694 }
1695
1696 /* Update available free count in mbox response */
1697 rsp->free_count = mcam->bmap_fcnt;
1698
1699 mutex_unlock(&mcam->lock);
1700 return 0;
1701 }
1702
rvu_mbox_handler_npc_mcam_alloc_entry(struct rvu * rvu,struct npc_mcam_alloc_entry_req * req,struct npc_mcam_alloc_entry_rsp * rsp)1703 int rvu_mbox_handler_npc_mcam_alloc_entry(struct rvu *rvu,
1704 struct npc_mcam_alloc_entry_req *req,
1705 struct npc_mcam_alloc_entry_rsp *rsp)
1706 {
1707 struct npc_mcam *mcam = &rvu->hw->mcam;
1708 u16 pcifunc = req->hdr.pcifunc;
1709 int blkaddr;
1710
1711 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
1712 if (blkaddr < 0)
1713 return NPC_MCAM_INVALID_REQ;
1714
1715 rsp->entry = NPC_MCAM_ENTRY_INVALID;
1716 rsp->free_count = 0;
1717
1718 /* Check if ref_entry is within range */
1719 if (req->priority && req->ref_entry >= mcam->bmap_entries)
1720 return NPC_MCAM_INVALID_REQ;
1721
1722 /* ref_entry can't be '0' if requested priority is high.
1723 * Can't be last entry if requested priority is low.
1724 */
1725 if ((!req->ref_entry && req->priority == NPC_MCAM_HIGHER_PRIO) ||
1726 ((req->ref_entry == (mcam->bmap_entries - 1)) &&
1727 req->priority == NPC_MCAM_LOWER_PRIO))
1728 return NPC_MCAM_INVALID_REQ;
1729
1730 /* Since list of allocated indices needs to be sent to requester,
1731 * max number of non-contiguous entries per mbox msg is limited.
1732 */
1733 if (!req->contig && req->count > NPC_MAX_NONCONTIG_ENTRIES)
1734 return NPC_MCAM_INVALID_REQ;
1735
1736 /* Alloc request from PFFUNC with no NIXLF attached should be denied */
1737 if (!is_nixlf_attached(rvu, pcifunc))
1738 return NPC_MCAM_ALLOC_DENIED;
1739
1740 return npc_mcam_alloc_entries(mcam, pcifunc, req, rsp);
1741 }
1742
rvu_mbox_handler_npc_mcam_free_entry(struct rvu * rvu,struct npc_mcam_free_entry_req * req,struct msg_rsp * rsp)1743 int rvu_mbox_handler_npc_mcam_free_entry(struct rvu *rvu,
1744 struct npc_mcam_free_entry_req *req,
1745 struct msg_rsp *rsp)
1746 {
1747 struct npc_mcam *mcam = &rvu->hw->mcam;
1748 u16 pcifunc = req->hdr.pcifunc;
1749 int blkaddr, rc = 0;
1750 u16 cntr;
1751
1752 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
1753 if (blkaddr < 0)
1754 return NPC_MCAM_INVALID_REQ;
1755
1756 /* Free request from PFFUNC with no NIXLF attached, ignore */
1757 if (!is_nixlf_attached(rvu, pcifunc))
1758 return NPC_MCAM_INVALID_REQ;
1759
1760 mutex_lock(&mcam->lock);
1761
1762 if (req->all)
1763 goto free_all;
1764
1765 rc = npc_mcam_verify_entry(mcam, pcifunc, req->entry);
1766 if (rc)
1767 goto exit;
1768
1769 mcam->entry2pfvf_map[req->entry] = 0;
1770 npc_mcam_clear_bit(mcam, req->entry);
1771 npc_enable_mcam_entry(rvu, mcam, blkaddr, req->entry, false);
1772
1773 /* Update entry2counter mapping */
1774 cntr = mcam->entry2cntr_map[req->entry];
1775 if (cntr != NPC_MCAM_INVALID_MAP)
1776 npc_unmap_mcam_entry_and_cntr(rvu, mcam, blkaddr,
1777 req->entry, cntr);
1778
1779 goto exit;
1780
1781 free_all:
1782 /* Free up all entries allocated to requesting PFFUNC */
1783 npc_mcam_free_all_entries(rvu, mcam, blkaddr, pcifunc);
1784 exit:
1785 mutex_unlock(&mcam->lock);
1786 return rc;
1787 }
1788
rvu_mbox_handler_npc_mcam_write_entry(struct rvu * rvu,struct npc_mcam_write_entry_req * req,struct msg_rsp * rsp)1789 int rvu_mbox_handler_npc_mcam_write_entry(struct rvu *rvu,
1790 struct npc_mcam_write_entry_req *req,
1791 struct msg_rsp *rsp)
1792 {
1793 struct npc_mcam *mcam = &rvu->hw->mcam;
1794 u16 pcifunc = req->hdr.pcifunc;
1795 int blkaddr, rc;
1796
1797 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
1798 if (blkaddr < 0)
1799 return NPC_MCAM_INVALID_REQ;
1800
1801 mutex_lock(&mcam->lock);
1802 rc = npc_mcam_verify_entry(mcam, pcifunc, req->entry);
1803 if (rc)
1804 goto exit;
1805
1806 if (req->set_cntr &&
1807 npc_mcam_verify_counter(mcam, pcifunc, req->cntr)) {
1808 rc = NPC_MCAM_INVALID_REQ;
1809 goto exit;
1810 }
1811
1812 if (req->intf != NIX_INTF_RX && req->intf != NIX_INTF_TX) {
1813 rc = NPC_MCAM_INVALID_REQ;
1814 goto exit;
1815 }
1816
1817 npc_config_mcam_entry(rvu, mcam, blkaddr, req->entry, req->intf,
1818 &req->entry_data, req->enable_entry);
1819
1820 if (req->set_cntr)
1821 npc_map_mcam_entry_and_cntr(rvu, mcam, blkaddr,
1822 req->entry, req->cntr);
1823
1824 rc = 0;
1825 exit:
1826 mutex_unlock(&mcam->lock);
1827 return rc;
1828 }
1829
rvu_mbox_handler_npc_mcam_ena_entry(struct rvu * rvu,struct npc_mcam_ena_dis_entry_req * req,struct msg_rsp * rsp)1830 int rvu_mbox_handler_npc_mcam_ena_entry(struct rvu *rvu,
1831 struct npc_mcam_ena_dis_entry_req *req,
1832 struct msg_rsp *rsp)
1833 {
1834 struct npc_mcam *mcam = &rvu->hw->mcam;
1835 u16 pcifunc = req->hdr.pcifunc;
1836 int blkaddr, rc;
1837
1838 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
1839 if (blkaddr < 0)
1840 return NPC_MCAM_INVALID_REQ;
1841
1842 mutex_lock(&mcam->lock);
1843 rc = npc_mcam_verify_entry(mcam, pcifunc, req->entry);
1844 mutex_unlock(&mcam->lock);
1845 if (rc)
1846 return rc;
1847
1848 npc_enable_mcam_entry(rvu, mcam, blkaddr, req->entry, true);
1849
1850 return 0;
1851 }
1852
rvu_mbox_handler_npc_mcam_dis_entry(struct rvu * rvu,struct npc_mcam_ena_dis_entry_req * req,struct msg_rsp * rsp)1853 int rvu_mbox_handler_npc_mcam_dis_entry(struct rvu *rvu,
1854 struct npc_mcam_ena_dis_entry_req *req,
1855 struct msg_rsp *rsp)
1856 {
1857 struct npc_mcam *mcam = &rvu->hw->mcam;
1858 u16 pcifunc = req->hdr.pcifunc;
1859 int blkaddr, rc;
1860
1861 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
1862 if (blkaddr < 0)
1863 return NPC_MCAM_INVALID_REQ;
1864
1865 mutex_lock(&mcam->lock);
1866 rc = npc_mcam_verify_entry(mcam, pcifunc, req->entry);
1867 mutex_unlock(&mcam->lock);
1868 if (rc)
1869 return rc;
1870
1871 npc_enable_mcam_entry(rvu, mcam, blkaddr, req->entry, false);
1872
1873 return 0;
1874 }
1875
rvu_mbox_handler_npc_mcam_shift_entry(struct rvu * rvu,struct npc_mcam_shift_entry_req * req,struct npc_mcam_shift_entry_rsp * rsp)1876 int rvu_mbox_handler_npc_mcam_shift_entry(struct rvu *rvu,
1877 struct npc_mcam_shift_entry_req *req,
1878 struct npc_mcam_shift_entry_rsp *rsp)
1879 {
1880 struct npc_mcam *mcam = &rvu->hw->mcam;
1881 u16 pcifunc = req->hdr.pcifunc;
1882 u16 old_entry, new_entry;
1883 int blkaddr, rc = 0;
1884 u16 index, cntr;
1885
1886 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
1887 if (blkaddr < 0)
1888 return NPC_MCAM_INVALID_REQ;
1889
1890 if (req->shift_count > NPC_MCAM_MAX_SHIFTS)
1891 return NPC_MCAM_INVALID_REQ;
1892
1893 mutex_lock(&mcam->lock);
1894 for (index = 0; index < req->shift_count; index++) {
1895 old_entry = req->curr_entry[index];
1896 new_entry = req->new_entry[index];
1897
1898 /* Check if both old and new entries are valid and
1899 * does belong to this PFFUNC or not.
1900 */
1901 rc = npc_mcam_verify_entry(mcam, pcifunc, old_entry);
1902 if (rc)
1903 break;
1904
1905 rc = npc_mcam_verify_entry(mcam, pcifunc, new_entry);
1906 if (rc)
1907 break;
1908
1909 /* new_entry should not have a counter mapped */
1910 if (mcam->entry2cntr_map[new_entry] != NPC_MCAM_INVALID_MAP) {
1911 rc = NPC_MCAM_PERM_DENIED;
1912 break;
1913 }
1914
1915 /* Disable the new_entry */
1916 npc_enable_mcam_entry(rvu, mcam, blkaddr, new_entry, false);
1917
1918 /* Copy rule from old entry to new entry */
1919 npc_copy_mcam_entry(rvu, mcam, blkaddr, old_entry, new_entry);
1920
1921 /* Copy counter mapping, if any */
1922 cntr = mcam->entry2cntr_map[old_entry];
1923 if (cntr != NPC_MCAM_INVALID_MAP) {
1924 npc_unmap_mcam_entry_and_cntr(rvu, mcam, blkaddr,
1925 old_entry, cntr);
1926 npc_map_mcam_entry_and_cntr(rvu, mcam, blkaddr,
1927 new_entry, cntr);
1928 }
1929
1930 /* Enable new_entry and disable old_entry */
1931 npc_enable_mcam_entry(rvu, mcam, blkaddr, new_entry, true);
1932 npc_enable_mcam_entry(rvu, mcam, blkaddr, old_entry, false);
1933 }
1934
1935 /* If shift has failed then report the failed index */
1936 if (index != req->shift_count) {
1937 rc = NPC_MCAM_PERM_DENIED;
1938 rsp->failed_entry_idx = index;
1939 }
1940
1941 mutex_unlock(&mcam->lock);
1942 return rc;
1943 }
1944
rvu_mbox_handler_npc_mcam_alloc_counter(struct rvu * rvu,struct npc_mcam_alloc_counter_req * req,struct npc_mcam_alloc_counter_rsp * rsp)1945 int rvu_mbox_handler_npc_mcam_alloc_counter(struct rvu *rvu,
1946 struct npc_mcam_alloc_counter_req *req,
1947 struct npc_mcam_alloc_counter_rsp *rsp)
1948 {
1949 struct npc_mcam *mcam = &rvu->hw->mcam;
1950 u16 pcifunc = req->hdr.pcifunc;
1951 u16 max_contig, cntr;
1952 int blkaddr, index;
1953
1954 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
1955 if (blkaddr < 0)
1956 return NPC_MCAM_INVALID_REQ;
1957
1958 /* If the request is from a PFFUNC with no NIXLF attached, ignore */
1959 if (!is_nixlf_attached(rvu, pcifunc))
1960 return NPC_MCAM_INVALID_REQ;
1961
1962 /* Since list of allocated counter IDs needs to be sent to requester,
1963 * max number of non-contiguous counters per mbox msg is limited.
1964 */
1965 if (!req->contig && req->count > NPC_MAX_NONCONTIG_COUNTERS)
1966 return NPC_MCAM_INVALID_REQ;
1967
1968 mutex_lock(&mcam->lock);
1969
1970 /* Check if unused counters are available or not */
1971 if (!rvu_rsrc_free_count(&mcam->counters)) {
1972 mutex_unlock(&mcam->lock);
1973 return NPC_MCAM_ALLOC_FAILED;
1974 }
1975
1976 rsp->count = 0;
1977
1978 if (req->contig) {
1979 /* Allocate requested number of contiguous counters, if
1980 * unsuccessful find max contiguous entries available.
1981 */
1982 index = npc_mcam_find_zero_area(mcam->counters.bmap,
1983 mcam->counters.max, 0,
1984 req->count, &max_contig);
1985 rsp->count = max_contig;
1986 rsp->cntr = index;
1987 for (cntr = index; cntr < (index + max_contig); cntr++) {
1988 __set_bit(cntr, mcam->counters.bmap);
1989 mcam->cntr2pfvf_map[cntr] = pcifunc;
1990 }
1991 } else {
1992 /* Allocate requested number of non-contiguous counters,
1993 * if unsuccessful allocate as many as possible.
1994 */
1995 for (cntr = 0; cntr < req->count; cntr++) {
1996 index = rvu_alloc_rsrc(&mcam->counters);
1997 if (index < 0)
1998 break;
1999 rsp->cntr_list[cntr] = index;
2000 rsp->count++;
2001 mcam->cntr2pfvf_map[index] = pcifunc;
2002 }
2003 }
2004
2005 mutex_unlock(&mcam->lock);
2006 return 0;
2007 }
2008
rvu_mbox_handler_npc_mcam_free_counter(struct rvu * rvu,struct npc_mcam_oper_counter_req * req,struct msg_rsp * rsp)2009 int rvu_mbox_handler_npc_mcam_free_counter(struct rvu *rvu,
2010 struct npc_mcam_oper_counter_req *req, struct msg_rsp *rsp)
2011 {
2012 struct npc_mcam *mcam = &rvu->hw->mcam;
2013 u16 index, entry = 0;
2014 int blkaddr, err;
2015
2016 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
2017 if (blkaddr < 0)
2018 return NPC_MCAM_INVALID_REQ;
2019
2020 mutex_lock(&mcam->lock);
2021 err = npc_mcam_verify_counter(mcam, req->hdr.pcifunc, req->cntr);
2022 if (err) {
2023 mutex_unlock(&mcam->lock);
2024 return err;
2025 }
2026
2027 /* Mark counter as free/unused */
2028 mcam->cntr2pfvf_map[req->cntr] = NPC_MCAM_INVALID_MAP;
2029 rvu_free_rsrc(&mcam->counters, req->cntr);
2030
2031 /* Disable all MCAM entry's stats which are using this counter */
2032 while (entry < mcam->bmap_entries) {
2033 if (!mcam->cntr_refcnt[req->cntr])
2034 break;
2035
2036 index = find_next_bit(mcam->bmap, mcam->bmap_entries, entry);
2037 if (index >= mcam->bmap_entries)
2038 break;
2039 entry = index + 1;
2040 if (mcam->entry2cntr_map[index] != req->cntr)
2041 continue;
2042
2043 npc_unmap_mcam_entry_and_cntr(rvu, mcam, blkaddr,
2044 index, req->cntr);
2045 }
2046
2047 mutex_unlock(&mcam->lock);
2048 return 0;
2049 }
2050
rvu_mbox_handler_npc_mcam_unmap_counter(struct rvu * rvu,struct npc_mcam_unmap_counter_req * req,struct msg_rsp * rsp)2051 int rvu_mbox_handler_npc_mcam_unmap_counter(struct rvu *rvu,
2052 struct npc_mcam_unmap_counter_req *req, struct msg_rsp *rsp)
2053 {
2054 struct npc_mcam *mcam = &rvu->hw->mcam;
2055 u16 index, entry = 0;
2056 int blkaddr, rc;
2057
2058 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
2059 if (blkaddr < 0)
2060 return NPC_MCAM_INVALID_REQ;
2061
2062 mutex_lock(&mcam->lock);
2063 rc = npc_mcam_verify_counter(mcam, req->hdr.pcifunc, req->cntr);
2064 if (rc)
2065 goto exit;
2066
2067 /* Unmap the MCAM entry and counter */
2068 if (!req->all) {
2069 rc = npc_mcam_verify_entry(mcam, req->hdr.pcifunc, req->entry);
2070 if (rc)
2071 goto exit;
2072 npc_unmap_mcam_entry_and_cntr(rvu, mcam, blkaddr,
2073 req->entry, req->cntr);
2074 goto exit;
2075 }
2076
2077 /* Disable all MCAM entry's stats which are using this counter */
2078 while (entry < mcam->bmap_entries) {
2079 if (!mcam->cntr_refcnt[req->cntr])
2080 break;
2081
2082 index = find_next_bit(mcam->bmap, mcam->bmap_entries, entry);
2083 if (index >= mcam->bmap_entries)
2084 break;
2085 entry = index + 1;
2086
2087 if (mcam->entry2cntr_map[index] != req->cntr)
2088 continue;
2089
2090 npc_unmap_mcam_entry_and_cntr(rvu, mcam, blkaddr,
2091 index, req->cntr);
2092 }
2093 exit:
2094 mutex_unlock(&mcam->lock);
2095 return rc;
2096 }
2097
rvu_mbox_handler_npc_mcam_clear_counter(struct rvu * rvu,struct npc_mcam_oper_counter_req * req,struct msg_rsp * rsp)2098 int rvu_mbox_handler_npc_mcam_clear_counter(struct rvu *rvu,
2099 struct npc_mcam_oper_counter_req *req, struct msg_rsp *rsp)
2100 {
2101 struct npc_mcam *mcam = &rvu->hw->mcam;
2102 int blkaddr, err;
2103
2104 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
2105 if (blkaddr < 0)
2106 return NPC_MCAM_INVALID_REQ;
2107
2108 mutex_lock(&mcam->lock);
2109 err = npc_mcam_verify_counter(mcam, req->hdr.pcifunc, req->cntr);
2110 mutex_unlock(&mcam->lock);
2111 if (err)
2112 return err;
2113
2114 rvu_write64(rvu, blkaddr, NPC_AF_MATCH_STATX(req->cntr), 0x00);
2115
2116 return 0;
2117 }
2118
rvu_mbox_handler_npc_mcam_counter_stats(struct rvu * rvu,struct npc_mcam_oper_counter_req * req,struct npc_mcam_oper_counter_rsp * rsp)2119 int rvu_mbox_handler_npc_mcam_counter_stats(struct rvu *rvu,
2120 struct npc_mcam_oper_counter_req *req,
2121 struct npc_mcam_oper_counter_rsp *rsp)
2122 {
2123 struct npc_mcam *mcam = &rvu->hw->mcam;
2124 int blkaddr, err;
2125
2126 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
2127 if (blkaddr < 0)
2128 return NPC_MCAM_INVALID_REQ;
2129
2130 mutex_lock(&mcam->lock);
2131 err = npc_mcam_verify_counter(mcam, req->hdr.pcifunc, req->cntr);
2132 mutex_unlock(&mcam->lock);
2133 if (err)
2134 return err;
2135
2136 rsp->stat = rvu_read64(rvu, blkaddr, NPC_AF_MATCH_STATX(req->cntr));
2137 rsp->stat &= BIT_ULL(48) - 1;
2138
2139 return 0;
2140 }
2141
rvu_mbox_handler_npc_mcam_alloc_and_write_entry(struct rvu * rvu,struct npc_mcam_alloc_and_write_entry_req * req,struct npc_mcam_alloc_and_write_entry_rsp * rsp)2142 int rvu_mbox_handler_npc_mcam_alloc_and_write_entry(struct rvu *rvu,
2143 struct npc_mcam_alloc_and_write_entry_req *req,
2144 struct npc_mcam_alloc_and_write_entry_rsp *rsp)
2145 {
2146 struct npc_mcam_alloc_counter_req cntr_req;
2147 struct npc_mcam_alloc_counter_rsp cntr_rsp;
2148 struct npc_mcam_alloc_entry_req entry_req;
2149 struct npc_mcam_alloc_entry_rsp entry_rsp;
2150 struct npc_mcam *mcam = &rvu->hw->mcam;
2151 u16 entry = NPC_MCAM_ENTRY_INVALID;
2152 u16 cntr = NPC_MCAM_ENTRY_INVALID;
2153 int blkaddr, rc;
2154
2155 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
2156 if (blkaddr < 0)
2157 return NPC_MCAM_INVALID_REQ;
2158
2159 if (req->intf != NIX_INTF_RX && req->intf != NIX_INTF_TX)
2160 return NPC_MCAM_INVALID_REQ;
2161
2162 /* Try to allocate a MCAM entry */
2163 entry_req.hdr.pcifunc = req->hdr.pcifunc;
2164 entry_req.contig = true;
2165 entry_req.priority = req->priority;
2166 entry_req.ref_entry = req->ref_entry;
2167 entry_req.count = 1;
2168
2169 rc = rvu_mbox_handler_npc_mcam_alloc_entry(rvu,
2170 &entry_req, &entry_rsp);
2171 if (rc)
2172 return rc;
2173
2174 if (!entry_rsp.count)
2175 return NPC_MCAM_ALLOC_FAILED;
2176
2177 entry = entry_rsp.entry;
2178
2179 if (!req->alloc_cntr)
2180 goto write_entry;
2181
2182 /* Now allocate counter */
2183 cntr_req.hdr.pcifunc = req->hdr.pcifunc;
2184 cntr_req.contig = true;
2185 cntr_req.count = 1;
2186
2187 rc = rvu_mbox_handler_npc_mcam_alloc_counter(rvu, &cntr_req, &cntr_rsp);
2188 if (rc) {
2189 /* Free allocated MCAM entry */
2190 mutex_lock(&mcam->lock);
2191 mcam->entry2pfvf_map[entry] = 0;
2192 npc_mcam_clear_bit(mcam, entry);
2193 mutex_unlock(&mcam->lock);
2194 return rc;
2195 }
2196
2197 cntr = cntr_rsp.cntr;
2198
2199 write_entry:
2200 mutex_lock(&mcam->lock);
2201 npc_config_mcam_entry(rvu, mcam, blkaddr, entry, req->intf,
2202 &req->entry_data, req->enable_entry);
2203
2204 if (req->alloc_cntr)
2205 npc_map_mcam_entry_and_cntr(rvu, mcam, blkaddr, entry, cntr);
2206 mutex_unlock(&mcam->lock);
2207
2208 rsp->entry = entry;
2209 rsp->cntr = cntr;
2210
2211 return 0;
2212 }
2213
2214 #define GET_KEX_CFG(intf) \
2215 rvu_read64(rvu, BLKADDR_NPC, NPC_AF_INTFX_KEX_CFG(intf))
2216
2217 #define GET_KEX_FLAGS(ld) \
2218 rvu_read64(rvu, BLKADDR_NPC, NPC_AF_KEX_LDATAX_FLAGS_CFG(ld))
2219
2220 #define GET_KEX_LD(intf, lid, lt, ld) \
2221 rvu_read64(rvu, BLKADDR_NPC, \
2222 NPC_AF_INTFX_LIDX_LTX_LDX_CFG(intf, lid, lt, ld))
2223
2224 #define GET_KEX_LDFLAGS(intf, ld, fl) \
2225 rvu_read64(rvu, BLKADDR_NPC, \
2226 NPC_AF_INTFX_LDATAX_FLAGSX_CFG(intf, ld, fl))
2227
rvu_mbox_handler_npc_get_kex_cfg(struct rvu * rvu,struct msg_req * req,struct npc_get_kex_cfg_rsp * rsp)2228 int rvu_mbox_handler_npc_get_kex_cfg(struct rvu *rvu, struct msg_req *req,
2229 struct npc_get_kex_cfg_rsp *rsp)
2230 {
2231 int lid, lt, ld, fl;
2232
2233 rsp->rx_keyx_cfg = GET_KEX_CFG(NIX_INTF_RX);
2234 rsp->tx_keyx_cfg = GET_KEX_CFG(NIX_INTF_TX);
2235 for (lid = 0; lid < NPC_MAX_LID; lid++) {
2236 for (lt = 0; lt < NPC_MAX_LT; lt++) {
2237 for (ld = 0; ld < NPC_MAX_LD; ld++) {
2238 rsp->intf_lid_lt_ld[NIX_INTF_RX][lid][lt][ld] =
2239 GET_KEX_LD(NIX_INTF_RX, lid, lt, ld);
2240 rsp->intf_lid_lt_ld[NIX_INTF_TX][lid][lt][ld] =
2241 GET_KEX_LD(NIX_INTF_TX, lid, lt, ld);
2242 }
2243 }
2244 }
2245 for (ld = 0; ld < NPC_MAX_LD; ld++)
2246 rsp->kex_ld_flags[ld] = GET_KEX_FLAGS(ld);
2247
2248 for (ld = 0; ld < NPC_MAX_LD; ld++) {
2249 for (fl = 0; fl < NPC_MAX_LFL; fl++) {
2250 rsp->intf_ld_flags[NIX_INTF_RX][ld][fl] =
2251 GET_KEX_LDFLAGS(NIX_INTF_RX, ld, fl);
2252 rsp->intf_ld_flags[NIX_INTF_TX][ld][fl] =
2253 GET_KEX_LDFLAGS(NIX_INTF_TX, ld, fl);
2254 }
2255 }
2256 memcpy(rsp->mkex_pfl_name, rvu->mkex_pfl_name, MKEX_NAME_LEN);
2257 return 0;
2258 }
2259
rvu_npc_update_rxvlan(struct rvu * rvu,u16 pcifunc,int nixlf)2260 int rvu_npc_update_rxvlan(struct rvu *rvu, u16 pcifunc, int nixlf)
2261 {
2262 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc);
2263 struct npc_mcam *mcam = &rvu->hw->mcam;
2264 int blkaddr, index;
2265 bool enable;
2266
2267 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
2268 if (blkaddr < 0)
2269 return NIX_AF_ERR_AF_LF_INVALID;
2270
2271 if (!pfvf->rxvlan)
2272 return 0;
2273
2274 index = npc_get_nixlf_mcam_index(mcam, pcifunc, nixlf,
2275 NIXLF_UCAST_ENTRY);
2276 pfvf->entry.action = npc_get_mcam_action(rvu, mcam, blkaddr, index);
2277 enable = is_mcam_entry_enabled(rvu, mcam, blkaddr, index);
2278 npc_config_mcam_entry(rvu, mcam, blkaddr, pfvf->rxvlan_index,
2279 NIX_INTF_RX, &pfvf->entry, enable);
2280
2281 return 0;
2282 }
2283