1 /* Broadcom NetXtreme-C/E network driver.
2 *
3 * Copyright (c) 2014-2016 Broadcom Corporation
4 * Copyright (c) 2016-2017 Broadcom Limited
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation.
9 */
10
11 #include <linux/ctype.h>
12 #include <linux/stringify.h>
13 #include <linux/ethtool.h>
14 #include <linux/linkmode.h>
15 #include <linux/interrupt.h>
16 #include <linux/pci.h>
17 #include <linux/etherdevice.h>
18 #include <linux/crc32.h>
19 #include <linux/firmware.h>
20 #include <linux/utsname.h>
21 #include <linux/time.h>
22 #include "bnxt_hsi.h"
23 #include "bnxt.h"
24 #include "bnxt_xdp.h"
25 #include "bnxt_ethtool.h"
26 #include "bnxt_nvm_defs.h" /* NVRAM content constant and structure defs */
27 #include "bnxt_fw_hdr.h" /* Firmware hdr constant and structure defs */
28 #include "bnxt_coredump.h"
29 #define FLASH_NVRAM_TIMEOUT ((HWRM_CMD_TIMEOUT) * 100)
30 #define FLASH_PACKAGE_TIMEOUT ((HWRM_CMD_TIMEOUT) * 200)
31 #define INSTALL_PACKAGE_TIMEOUT ((HWRM_CMD_TIMEOUT) * 200)
32
bnxt_get_msglevel(struct net_device * dev)33 static u32 bnxt_get_msglevel(struct net_device *dev)
34 {
35 struct bnxt *bp = netdev_priv(dev);
36
37 return bp->msg_enable;
38 }
39
bnxt_set_msglevel(struct net_device * dev,u32 value)40 static void bnxt_set_msglevel(struct net_device *dev, u32 value)
41 {
42 struct bnxt *bp = netdev_priv(dev);
43
44 bp->msg_enable = value;
45 }
46
bnxt_get_coalesce(struct net_device * dev,struct ethtool_coalesce * coal)47 static int bnxt_get_coalesce(struct net_device *dev,
48 struct ethtool_coalesce *coal)
49 {
50 struct bnxt *bp = netdev_priv(dev);
51 struct bnxt_coal *hw_coal;
52 u16 mult;
53
54 memset(coal, 0, sizeof(*coal));
55
56 coal->use_adaptive_rx_coalesce = bp->flags & BNXT_FLAG_DIM;
57
58 hw_coal = &bp->rx_coal;
59 mult = hw_coal->bufs_per_record;
60 coal->rx_coalesce_usecs = hw_coal->coal_ticks;
61 coal->rx_max_coalesced_frames = hw_coal->coal_bufs / mult;
62 coal->rx_coalesce_usecs_irq = hw_coal->coal_ticks_irq;
63 coal->rx_max_coalesced_frames_irq = hw_coal->coal_bufs_irq / mult;
64
65 hw_coal = &bp->tx_coal;
66 mult = hw_coal->bufs_per_record;
67 coal->tx_coalesce_usecs = hw_coal->coal_ticks;
68 coal->tx_max_coalesced_frames = hw_coal->coal_bufs / mult;
69 coal->tx_coalesce_usecs_irq = hw_coal->coal_ticks_irq;
70 coal->tx_max_coalesced_frames_irq = hw_coal->coal_bufs_irq / mult;
71
72 coal->stats_block_coalesce_usecs = bp->stats_coal_ticks;
73
74 return 0;
75 }
76
bnxt_set_coalesce(struct net_device * dev,struct ethtool_coalesce * coal)77 static int bnxt_set_coalesce(struct net_device *dev,
78 struct ethtool_coalesce *coal)
79 {
80 struct bnxt *bp = netdev_priv(dev);
81 bool update_stats = false;
82 struct bnxt_coal *hw_coal;
83 int rc = 0;
84 u16 mult;
85
86 if (coal->use_adaptive_rx_coalesce) {
87 bp->flags |= BNXT_FLAG_DIM;
88 } else {
89 if (bp->flags & BNXT_FLAG_DIM) {
90 bp->flags &= ~(BNXT_FLAG_DIM);
91 goto reset_coalesce;
92 }
93 }
94
95 hw_coal = &bp->rx_coal;
96 mult = hw_coal->bufs_per_record;
97 hw_coal->coal_ticks = coal->rx_coalesce_usecs;
98 hw_coal->coal_bufs = coal->rx_max_coalesced_frames * mult;
99 hw_coal->coal_ticks_irq = coal->rx_coalesce_usecs_irq;
100 hw_coal->coal_bufs_irq = coal->rx_max_coalesced_frames_irq * mult;
101
102 hw_coal = &bp->tx_coal;
103 mult = hw_coal->bufs_per_record;
104 hw_coal->coal_ticks = coal->tx_coalesce_usecs;
105 hw_coal->coal_bufs = coal->tx_max_coalesced_frames * mult;
106 hw_coal->coal_ticks_irq = coal->tx_coalesce_usecs_irq;
107 hw_coal->coal_bufs_irq = coal->tx_max_coalesced_frames_irq * mult;
108
109 if (bp->stats_coal_ticks != coal->stats_block_coalesce_usecs) {
110 u32 stats_ticks = coal->stats_block_coalesce_usecs;
111
112 /* Allow 0, which means disable. */
113 if (stats_ticks)
114 stats_ticks = clamp_t(u32, stats_ticks,
115 BNXT_MIN_STATS_COAL_TICKS,
116 BNXT_MAX_STATS_COAL_TICKS);
117 stats_ticks = rounddown(stats_ticks, BNXT_MIN_STATS_COAL_TICKS);
118 bp->stats_coal_ticks = stats_ticks;
119 if (bp->stats_coal_ticks)
120 bp->current_interval =
121 bp->stats_coal_ticks * HZ / 1000000;
122 else
123 bp->current_interval = BNXT_TIMER_INTERVAL;
124 update_stats = true;
125 }
126
127 reset_coalesce:
128 if (test_bit(BNXT_STATE_OPEN, &bp->state)) {
129 if (update_stats) {
130 rc = bnxt_close_nic(bp, true, false);
131 if (!rc)
132 rc = bnxt_open_nic(bp, true, false);
133 } else {
134 rc = bnxt_hwrm_set_coal(bp);
135 }
136 }
137
138 return rc;
139 }
140
141 static const char * const bnxt_ring_rx_stats_str[] = {
142 "rx_ucast_packets",
143 "rx_mcast_packets",
144 "rx_bcast_packets",
145 "rx_discards",
146 "rx_errors",
147 "rx_ucast_bytes",
148 "rx_mcast_bytes",
149 "rx_bcast_bytes",
150 };
151
152 static const char * const bnxt_ring_tx_stats_str[] = {
153 "tx_ucast_packets",
154 "tx_mcast_packets",
155 "tx_bcast_packets",
156 "tx_errors",
157 "tx_discards",
158 "tx_ucast_bytes",
159 "tx_mcast_bytes",
160 "tx_bcast_bytes",
161 };
162
163 static const char * const bnxt_ring_tpa_stats_str[] = {
164 "tpa_packets",
165 "tpa_bytes",
166 "tpa_events",
167 "tpa_aborts",
168 };
169
170 static const char * const bnxt_ring_tpa2_stats_str[] = {
171 "rx_tpa_eligible_pkt",
172 "rx_tpa_eligible_bytes",
173 "rx_tpa_pkt",
174 "rx_tpa_bytes",
175 "rx_tpa_errors",
176 "rx_tpa_events",
177 };
178
179 static const char * const bnxt_rx_sw_stats_str[] = {
180 "rx_l4_csum_errors",
181 "rx_resets",
182 "rx_buf_errors",
183 };
184
185 static const char * const bnxt_cmn_sw_stats_str[] = {
186 "missed_irqs",
187 };
188
189 #define BNXT_RX_STATS_ENTRY(counter) \
190 { BNXT_RX_STATS_OFFSET(counter), __stringify(counter) }
191
192 #define BNXT_TX_STATS_ENTRY(counter) \
193 { BNXT_TX_STATS_OFFSET(counter), __stringify(counter) }
194
195 #define BNXT_RX_STATS_EXT_ENTRY(counter) \
196 { BNXT_RX_STATS_EXT_OFFSET(counter), __stringify(counter) }
197
198 #define BNXT_TX_STATS_EXT_ENTRY(counter) \
199 { BNXT_TX_STATS_EXT_OFFSET(counter), __stringify(counter) }
200
201 #define BNXT_RX_STATS_EXT_PFC_ENTRY(n) \
202 BNXT_RX_STATS_EXT_ENTRY(pfc_pri##n##_rx_duration_us), \
203 BNXT_RX_STATS_EXT_ENTRY(pfc_pri##n##_rx_transitions)
204
205 #define BNXT_TX_STATS_EXT_PFC_ENTRY(n) \
206 BNXT_TX_STATS_EXT_ENTRY(pfc_pri##n##_tx_duration_us), \
207 BNXT_TX_STATS_EXT_ENTRY(pfc_pri##n##_tx_transitions)
208
209 #define BNXT_RX_STATS_EXT_PFC_ENTRIES \
210 BNXT_RX_STATS_EXT_PFC_ENTRY(0), \
211 BNXT_RX_STATS_EXT_PFC_ENTRY(1), \
212 BNXT_RX_STATS_EXT_PFC_ENTRY(2), \
213 BNXT_RX_STATS_EXT_PFC_ENTRY(3), \
214 BNXT_RX_STATS_EXT_PFC_ENTRY(4), \
215 BNXT_RX_STATS_EXT_PFC_ENTRY(5), \
216 BNXT_RX_STATS_EXT_PFC_ENTRY(6), \
217 BNXT_RX_STATS_EXT_PFC_ENTRY(7)
218
219 #define BNXT_TX_STATS_EXT_PFC_ENTRIES \
220 BNXT_TX_STATS_EXT_PFC_ENTRY(0), \
221 BNXT_TX_STATS_EXT_PFC_ENTRY(1), \
222 BNXT_TX_STATS_EXT_PFC_ENTRY(2), \
223 BNXT_TX_STATS_EXT_PFC_ENTRY(3), \
224 BNXT_TX_STATS_EXT_PFC_ENTRY(4), \
225 BNXT_TX_STATS_EXT_PFC_ENTRY(5), \
226 BNXT_TX_STATS_EXT_PFC_ENTRY(6), \
227 BNXT_TX_STATS_EXT_PFC_ENTRY(7)
228
229 #define BNXT_RX_STATS_EXT_COS_ENTRY(n) \
230 BNXT_RX_STATS_EXT_ENTRY(rx_bytes_cos##n), \
231 BNXT_RX_STATS_EXT_ENTRY(rx_packets_cos##n)
232
233 #define BNXT_TX_STATS_EXT_COS_ENTRY(n) \
234 BNXT_TX_STATS_EXT_ENTRY(tx_bytes_cos##n), \
235 BNXT_TX_STATS_EXT_ENTRY(tx_packets_cos##n)
236
237 #define BNXT_RX_STATS_EXT_COS_ENTRIES \
238 BNXT_RX_STATS_EXT_COS_ENTRY(0), \
239 BNXT_RX_STATS_EXT_COS_ENTRY(1), \
240 BNXT_RX_STATS_EXT_COS_ENTRY(2), \
241 BNXT_RX_STATS_EXT_COS_ENTRY(3), \
242 BNXT_RX_STATS_EXT_COS_ENTRY(4), \
243 BNXT_RX_STATS_EXT_COS_ENTRY(5), \
244 BNXT_RX_STATS_EXT_COS_ENTRY(6), \
245 BNXT_RX_STATS_EXT_COS_ENTRY(7) \
246
247 #define BNXT_TX_STATS_EXT_COS_ENTRIES \
248 BNXT_TX_STATS_EXT_COS_ENTRY(0), \
249 BNXT_TX_STATS_EXT_COS_ENTRY(1), \
250 BNXT_TX_STATS_EXT_COS_ENTRY(2), \
251 BNXT_TX_STATS_EXT_COS_ENTRY(3), \
252 BNXT_TX_STATS_EXT_COS_ENTRY(4), \
253 BNXT_TX_STATS_EXT_COS_ENTRY(5), \
254 BNXT_TX_STATS_EXT_COS_ENTRY(6), \
255 BNXT_TX_STATS_EXT_COS_ENTRY(7) \
256
257 #define BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(n) \
258 BNXT_RX_STATS_EXT_ENTRY(rx_discard_bytes_cos##n), \
259 BNXT_RX_STATS_EXT_ENTRY(rx_discard_packets_cos##n)
260
261 #define BNXT_RX_STATS_EXT_DISCARD_COS_ENTRIES \
262 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(0), \
263 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(1), \
264 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(2), \
265 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(3), \
266 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(4), \
267 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(5), \
268 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(6), \
269 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(7)
270
271 #define BNXT_RX_STATS_PRI_ENTRY(counter, n) \
272 { BNXT_RX_STATS_EXT_OFFSET(counter##_cos0), \
273 __stringify(counter##_pri##n) }
274
275 #define BNXT_TX_STATS_PRI_ENTRY(counter, n) \
276 { BNXT_TX_STATS_EXT_OFFSET(counter##_cos0), \
277 __stringify(counter##_pri##n) }
278
279 #define BNXT_RX_STATS_PRI_ENTRIES(counter) \
280 BNXT_RX_STATS_PRI_ENTRY(counter, 0), \
281 BNXT_RX_STATS_PRI_ENTRY(counter, 1), \
282 BNXT_RX_STATS_PRI_ENTRY(counter, 2), \
283 BNXT_RX_STATS_PRI_ENTRY(counter, 3), \
284 BNXT_RX_STATS_PRI_ENTRY(counter, 4), \
285 BNXT_RX_STATS_PRI_ENTRY(counter, 5), \
286 BNXT_RX_STATS_PRI_ENTRY(counter, 6), \
287 BNXT_RX_STATS_PRI_ENTRY(counter, 7)
288
289 #define BNXT_TX_STATS_PRI_ENTRIES(counter) \
290 BNXT_TX_STATS_PRI_ENTRY(counter, 0), \
291 BNXT_TX_STATS_PRI_ENTRY(counter, 1), \
292 BNXT_TX_STATS_PRI_ENTRY(counter, 2), \
293 BNXT_TX_STATS_PRI_ENTRY(counter, 3), \
294 BNXT_TX_STATS_PRI_ENTRY(counter, 4), \
295 BNXT_TX_STATS_PRI_ENTRY(counter, 5), \
296 BNXT_TX_STATS_PRI_ENTRY(counter, 6), \
297 BNXT_TX_STATS_PRI_ENTRY(counter, 7)
298
299 enum {
300 RX_TOTAL_DISCARDS,
301 TX_TOTAL_DISCARDS,
302 };
303
304 static struct {
305 u64 counter;
306 char string[ETH_GSTRING_LEN];
307 } bnxt_sw_func_stats[] = {
308 {0, "rx_total_discard_pkts"},
309 {0, "tx_total_discard_pkts"},
310 };
311
312 #define NUM_RING_RX_SW_STATS ARRAY_SIZE(bnxt_rx_sw_stats_str)
313 #define NUM_RING_CMN_SW_STATS ARRAY_SIZE(bnxt_cmn_sw_stats_str)
314 #define NUM_RING_RX_HW_STATS ARRAY_SIZE(bnxt_ring_rx_stats_str)
315 #define NUM_RING_TX_HW_STATS ARRAY_SIZE(bnxt_ring_tx_stats_str)
316
317 static const struct {
318 long offset;
319 char string[ETH_GSTRING_LEN];
320 } bnxt_port_stats_arr[] = {
321 BNXT_RX_STATS_ENTRY(rx_64b_frames),
322 BNXT_RX_STATS_ENTRY(rx_65b_127b_frames),
323 BNXT_RX_STATS_ENTRY(rx_128b_255b_frames),
324 BNXT_RX_STATS_ENTRY(rx_256b_511b_frames),
325 BNXT_RX_STATS_ENTRY(rx_512b_1023b_frames),
326 BNXT_RX_STATS_ENTRY(rx_1024b_1518b_frames),
327 BNXT_RX_STATS_ENTRY(rx_good_vlan_frames),
328 BNXT_RX_STATS_ENTRY(rx_1519b_2047b_frames),
329 BNXT_RX_STATS_ENTRY(rx_2048b_4095b_frames),
330 BNXT_RX_STATS_ENTRY(rx_4096b_9216b_frames),
331 BNXT_RX_STATS_ENTRY(rx_9217b_16383b_frames),
332 BNXT_RX_STATS_ENTRY(rx_total_frames),
333 BNXT_RX_STATS_ENTRY(rx_ucast_frames),
334 BNXT_RX_STATS_ENTRY(rx_mcast_frames),
335 BNXT_RX_STATS_ENTRY(rx_bcast_frames),
336 BNXT_RX_STATS_ENTRY(rx_fcs_err_frames),
337 BNXT_RX_STATS_ENTRY(rx_ctrl_frames),
338 BNXT_RX_STATS_ENTRY(rx_pause_frames),
339 BNXT_RX_STATS_ENTRY(rx_pfc_frames),
340 BNXT_RX_STATS_ENTRY(rx_align_err_frames),
341 BNXT_RX_STATS_ENTRY(rx_ovrsz_frames),
342 BNXT_RX_STATS_ENTRY(rx_jbr_frames),
343 BNXT_RX_STATS_ENTRY(rx_mtu_err_frames),
344 BNXT_RX_STATS_ENTRY(rx_tagged_frames),
345 BNXT_RX_STATS_ENTRY(rx_double_tagged_frames),
346 BNXT_RX_STATS_ENTRY(rx_good_frames),
347 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri0),
348 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri1),
349 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri2),
350 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri3),
351 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri4),
352 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri5),
353 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri6),
354 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri7),
355 BNXT_RX_STATS_ENTRY(rx_undrsz_frames),
356 BNXT_RX_STATS_ENTRY(rx_eee_lpi_events),
357 BNXT_RX_STATS_ENTRY(rx_eee_lpi_duration),
358 BNXT_RX_STATS_ENTRY(rx_bytes),
359 BNXT_RX_STATS_ENTRY(rx_runt_bytes),
360 BNXT_RX_STATS_ENTRY(rx_runt_frames),
361 BNXT_RX_STATS_ENTRY(rx_stat_discard),
362 BNXT_RX_STATS_ENTRY(rx_stat_err),
363
364 BNXT_TX_STATS_ENTRY(tx_64b_frames),
365 BNXT_TX_STATS_ENTRY(tx_65b_127b_frames),
366 BNXT_TX_STATS_ENTRY(tx_128b_255b_frames),
367 BNXT_TX_STATS_ENTRY(tx_256b_511b_frames),
368 BNXT_TX_STATS_ENTRY(tx_512b_1023b_frames),
369 BNXT_TX_STATS_ENTRY(tx_1024b_1518b_frames),
370 BNXT_TX_STATS_ENTRY(tx_good_vlan_frames),
371 BNXT_TX_STATS_ENTRY(tx_1519b_2047b_frames),
372 BNXT_TX_STATS_ENTRY(tx_2048b_4095b_frames),
373 BNXT_TX_STATS_ENTRY(tx_4096b_9216b_frames),
374 BNXT_TX_STATS_ENTRY(tx_9217b_16383b_frames),
375 BNXT_TX_STATS_ENTRY(tx_good_frames),
376 BNXT_TX_STATS_ENTRY(tx_total_frames),
377 BNXT_TX_STATS_ENTRY(tx_ucast_frames),
378 BNXT_TX_STATS_ENTRY(tx_mcast_frames),
379 BNXT_TX_STATS_ENTRY(tx_bcast_frames),
380 BNXT_TX_STATS_ENTRY(tx_pause_frames),
381 BNXT_TX_STATS_ENTRY(tx_pfc_frames),
382 BNXT_TX_STATS_ENTRY(tx_jabber_frames),
383 BNXT_TX_STATS_ENTRY(tx_fcs_err_frames),
384 BNXT_TX_STATS_ENTRY(tx_err),
385 BNXT_TX_STATS_ENTRY(tx_fifo_underruns),
386 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri0),
387 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri1),
388 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri2),
389 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri3),
390 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri4),
391 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri5),
392 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri6),
393 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri7),
394 BNXT_TX_STATS_ENTRY(tx_eee_lpi_events),
395 BNXT_TX_STATS_ENTRY(tx_eee_lpi_duration),
396 BNXT_TX_STATS_ENTRY(tx_total_collisions),
397 BNXT_TX_STATS_ENTRY(tx_bytes),
398 BNXT_TX_STATS_ENTRY(tx_xthol_frames),
399 BNXT_TX_STATS_ENTRY(tx_stat_discard),
400 BNXT_TX_STATS_ENTRY(tx_stat_error),
401 };
402
403 static const struct {
404 long offset;
405 char string[ETH_GSTRING_LEN];
406 } bnxt_port_stats_ext_arr[] = {
407 BNXT_RX_STATS_EXT_ENTRY(link_down_events),
408 BNXT_RX_STATS_EXT_ENTRY(continuous_pause_events),
409 BNXT_RX_STATS_EXT_ENTRY(resume_pause_events),
410 BNXT_RX_STATS_EXT_ENTRY(continuous_roce_pause_events),
411 BNXT_RX_STATS_EXT_ENTRY(resume_roce_pause_events),
412 BNXT_RX_STATS_EXT_COS_ENTRIES,
413 BNXT_RX_STATS_EXT_PFC_ENTRIES,
414 BNXT_RX_STATS_EXT_ENTRY(rx_bits),
415 BNXT_RX_STATS_EXT_ENTRY(rx_buffer_passed_threshold),
416 BNXT_RX_STATS_EXT_ENTRY(rx_pcs_symbol_err),
417 BNXT_RX_STATS_EXT_ENTRY(rx_corrected_bits),
418 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRIES,
419 };
420
421 static const struct {
422 long offset;
423 char string[ETH_GSTRING_LEN];
424 } bnxt_tx_port_stats_ext_arr[] = {
425 BNXT_TX_STATS_EXT_COS_ENTRIES,
426 BNXT_TX_STATS_EXT_PFC_ENTRIES,
427 };
428
429 static const struct {
430 long base_off;
431 char string[ETH_GSTRING_LEN];
432 } bnxt_rx_bytes_pri_arr[] = {
433 BNXT_RX_STATS_PRI_ENTRIES(rx_bytes),
434 };
435
436 static const struct {
437 long base_off;
438 char string[ETH_GSTRING_LEN];
439 } bnxt_rx_pkts_pri_arr[] = {
440 BNXT_RX_STATS_PRI_ENTRIES(rx_packets),
441 };
442
443 static const struct {
444 long base_off;
445 char string[ETH_GSTRING_LEN];
446 } bnxt_tx_bytes_pri_arr[] = {
447 BNXT_TX_STATS_PRI_ENTRIES(tx_bytes),
448 };
449
450 static const struct {
451 long base_off;
452 char string[ETH_GSTRING_LEN];
453 } bnxt_tx_pkts_pri_arr[] = {
454 BNXT_TX_STATS_PRI_ENTRIES(tx_packets),
455 };
456
457 #define BNXT_NUM_SW_FUNC_STATS ARRAY_SIZE(bnxt_sw_func_stats)
458 #define BNXT_NUM_PORT_STATS ARRAY_SIZE(bnxt_port_stats_arr)
459 #define BNXT_NUM_STATS_PRI \
460 (ARRAY_SIZE(bnxt_rx_bytes_pri_arr) + \
461 ARRAY_SIZE(bnxt_rx_pkts_pri_arr) + \
462 ARRAY_SIZE(bnxt_tx_bytes_pri_arr) + \
463 ARRAY_SIZE(bnxt_tx_pkts_pri_arr))
464
bnxt_get_num_tpa_ring_stats(struct bnxt * bp)465 static int bnxt_get_num_tpa_ring_stats(struct bnxt *bp)
466 {
467 if (BNXT_SUPPORTS_TPA(bp)) {
468 if (bp->max_tpa_v2) {
469 if (BNXT_CHIP_P5_THOR(bp))
470 return BNXT_NUM_TPA_RING_STATS_P5;
471 return BNXT_NUM_TPA_RING_STATS_P5_SR2;
472 }
473 return BNXT_NUM_TPA_RING_STATS;
474 }
475 return 0;
476 }
477
bnxt_get_num_ring_stats(struct bnxt * bp)478 static int bnxt_get_num_ring_stats(struct bnxt *bp)
479 {
480 int rx, tx, cmn;
481
482 rx = NUM_RING_RX_HW_STATS + NUM_RING_RX_SW_STATS +
483 bnxt_get_num_tpa_ring_stats(bp);
484 tx = NUM_RING_TX_HW_STATS;
485 cmn = NUM_RING_CMN_SW_STATS;
486 return rx * bp->rx_nr_rings + tx * bp->tx_nr_rings +
487 cmn * bp->cp_nr_rings;
488 }
489
bnxt_get_num_stats(struct bnxt * bp)490 static int bnxt_get_num_stats(struct bnxt *bp)
491 {
492 int num_stats = bnxt_get_num_ring_stats(bp);
493
494 num_stats += BNXT_NUM_SW_FUNC_STATS;
495
496 if (bp->flags & BNXT_FLAG_PORT_STATS)
497 num_stats += BNXT_NUM_PORT_STATS;
498
499 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) {
500 num_stats += bp->fw_rx_stats_ext_size +
501 bp->fw_tx_stats_ext_size;
502 if (bp->pri2cos_valid)
503 num_stats += BNXT_NUM_STATS_PRI;
504 }
505
506 return num_stats;
507 }
508
bnxt_get_sset_count(struct net_device * dev,int sset)509 static int bnxt_get_sset_count(struct net_device *dev, int sset)
510 {
511 struct bnxt *bp = netdev_priv(dev);
512
513 switch (sset) {
514 case ETH_SS_STATS:
515 return bnxt_get_num_stats(bp);
516 case ETH_SS_TEST:
517 if (!bp->num_tests)
518 return -EOPNOTSUPP;
519 return bp->num_tests;
520 default:
521 return -EOPNOTSUPP;
522 }
523 }
524
is_rx_ring(struct bnxt * bp,int ring_num)525 static bool is_rx_ring(struct bnxt *bp, int ring_num)
526 {
527 return ring_num < bp->rx_nr_rings;
528 }
529
is_tx_ring(struct bnxt * bp,int ring_num)530 static bool is_tx_ring(struct bnxt *bp, int ring_num)
531 {
532 int tx_base = 0;
533
534 if (!(bp->flags & BNXT_FLAG_SHARED_RINGS))
535 tx_base = bp->rx_nr_rings;
536
537 if (ring_num >= tx_base && ring_num < (tx_base + bp->tx_nr_rings))
538 return true;
539 return false;
540 }
541
bnxt_get_ethtool_stats(struct net_device * dev,struct ethtool_stats * stats,u64 * buf)542 static void bnxt_get_ethtool_stats(struct net_device *dev,
543 struct ethtool_stats *stats, u64 *buf)
544 {
545 u32 i, j = 0;
546 struct bnxt *bp = netdev_priv(dev);
547 u32 tpa_stats;
548
549 if (!bp->bnapi) {
550 j += bnxt_get_num_ring_stats(bp) + BNXT_NUM_SW_FUNC_STATS;
551 goto skip_ring_stats;
552 }
553
554 for (i = 0; i < BNXT_NUM_SW_FUNC_STATS; i++)
555 bnxt_sw_func_stats[i].counter = 0;
556
557 tpa_stats = bnxt_get_num_tpa_ring_stats(bp);
558 for (i = 0; i < bp->cp_nr_rings; i++) {
559 struct bnxt_napi *bnapi = bp->bnapi[i];
560 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
561 u64 *sw_stats = cpr->stats.sw_stats;
562 u64 *sw;
563 int k;
564
565 if (is_rx_ring(bp, i)) {
566 for (k = 0; k < NUM_RING_RX_HW_STATS; j++, k++)
567 buf[j] = sw_stats[k];
568 }
569 if (is_tx_ring(bp, i)) {
570 k = NUM_RING_RX_HW_STATS;
571 for (; k < NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS;
572 j++, k++)
573 buf[j] = sw_stats[k];
574 }
575 if (!tpa_stats || !is_rx_ring(bp, i))
576 goto skip_tpa_ring_stats;
577
578 k = NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS;
579 for (; k < NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS +
580 tpa_stats; j++, k++)
581 buf[j] = sw_stats[k];
582
583 skip_tpa_ring_stats:
584 sw = (u64 *)&cpr->sw_stats.rx;
585 if (is_rx_ring(bp, i)) {
586 for (k = 0; k < NUM_RING_RX_SW_STATS; j++, k++)
587 buf[j] = sw[k];
588 }
589
590 sw = (u64 *)&cpr->sw_stats.cmn;
591 for (k = 0; k < NUM_RING_CMN_SW_STATS; j++, k++)
592 buf[j] = sw[k];
593
594 bnxt_sw_func_stats[RX_TOTAL_DISCARDS].counter +=
595 BNXT_GET_RING_STATS64(sw_stats, rx_discard_pkts);
596 bnxt_sw_func_stats[TX_TOTAL_DISCARDS].counter +=
597 BNXT_GET_RING_STATS64(sw_stats, tx_discard_pkts);
598 }
599
600 for (i = 0; i < BNXT_NUM_SW_FUNC_STATS; i++, j++)
601 buf[j] = bnxt_sw_func_stats[i].counter;
602
603 skip_ring_stats:
604 if (bp->flags & BNXT_FLAG_PORT_STATS) {
605 u64 *port_stats = bp->port_stats.sw_stats;
606
607 for (i = 0; i < BNXT_NUM_PORT_STATS; i++, j++)
608 buf[j] = *(port_stats + bnxt_port_stats_arr[i].offset);
609 }
610 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) {
611 u64 *rx_port_stats_ext = bp->rx_port_stats_ext.sw_stats;
612 u64 *tx_port_stats_ext = bp->tx_port_stats_ext.sw_stats;
613
614 for (i = 0; i < bp->fw_rx_stats_ext_size; i++, j++) {
615 buf[j] = *(rx_port_stats_ext +
616 bnxt_port_stats_ext_arr[i].offset);
617 }
618 for (i = 0; i < bp->fw_tx_stats_ext_size; i++, j++) {
619 buf[j] = *(tx_port_stats_ext +
620 bnxt_tx_port_stats_ext_arr[i].offset);
621 }
622 if (bp->pri2cos_valid) {
623 for (i = 0; i < 8; i++, j++) {
624 long n = bnxt_rx_bytes_pri_arr[i].base_off +
625 bp->pri2cos_idx[i];
626
627 buf[j] = *(rx_port_stats_ext + n);
628 }
629 for (i = 0; i < 8; i++, j++) {
630 long n = bnxt_rx_pkts_pri_arr[i].base_off +
631 bp->pri2cos_idx[i];
632
633 buf[j] = *(rx_port_stats_ext + n);
634 }
635 for (i = 0; i < 8; i++, j++) {
636 long n = bnxt_tx_bytes_pri_arr[i].base_off +
637 bp->pri2cos_idx[i];
638
639 buf[j] = *(tx_port_stats_ext + n);
640 }
641 for (i = 0; i < 8; i++, j++) {
642 long n = bnxt_tx_pkts_pri_arr[i].base_off +
643 bp->pri2cos_idx[i];
644
645 buf[j] = *(tx_port_stats_ext + n);
646 }
647 }
648 }
649 }
650
bnxt_get_strings(struct net_device * dev,u32 stringset,u8 * buf)651 static void bnxt_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
652 {
653 struct bnxt *bp = netdev_priv(dev);
654 static const char * const *str;
655 u32 i, j, num_str;
656
657 switch (stringset) {
658 case ETH_SS_STATS:
659 for (i = 0; i < bp->cp_nr_rings; i++) {
660 if (is_rx_ring(bp, i)) {
661 num_str = NUM_RING_RX_HW_STATS;
662 for (j = 0; j < num_str; j++) {
663 sprintf(buf, "[%d]: %s", i,
664 bnxt_ring_rx_stats_str[j]);
665 buf += ETH_GSTRING_LEN;
666 }
667 }
668 if (is_tx_ring(bp, i)) {
669 num_str = NUM_RING_TX_HW_STATS;
670 for (j = 0; j < num_str; j++) {
671 sprintf(buf, "[%d]: %s", i,
672 bnxt_ring_tx_stats_str[j]);
673 buf += ETH_GSTRING_LEN;
674 }
675 }
676 num_str = bnxt_get_num_tpa_ring_stats(bp);
677 if (!num_str || !is_rx_ring(bp, i))
678 goto skip_tpa_stats;
679
680 if (bp->max_tpa_v2)
681 str = bnxt_ring_tpa2_stats_str;
682 else
683 str = bnxt_ring_tpa_stats_str;
684
685 for (j = 0; j < num_str; j++) {
686 sprintf(buf, "[%d]: %s", i, str[j]);
687 buf += ETH_GSTRING_LEN;
688 }
689 skip_tpa_stats:
690 if (is_rx_ring(bp, i)) {
691 num_str = NUM_RING_RX_SW_STATS;
692 for (j = 0; j < num_str; j++) {
693 sprintf(buf, "[%d]: %s", i,
694 bnxt_rx_sw_stats_str[j]);
695 buf += ETH_GSTRING_LEN;
696 }
697 }
698 num_str = NUM_RING_CMN_SW_STATS;
699 for (j = 0; j < num_str; j++) {
700 sprintf(buf, "[%d]: %s", i,
701 bnxt_cmn_sw_stats_str[j]);
702 buf += ETH_GSTRING_LEN;
703 }
704 }
705 for (i = 0; i < BNXT_NUM_SW_FUNC_STATS; i++) {
706 strcpy(buf, bnxt_sw_func_stats[i].string);
707 buf += ETH_GSTRING_LEN;
708 }
709
710 if (bp->flags & BNXT_FLAG_PORT_STATS) {
711 for (i = 0; i < BNXT_NUM_PORT_STATS; i++) {
712 strcpy(buf, bnxt_port_stats_arr[i].string);
713 buf += ETH_GSTRING_LEN;
714 }
715 }
716 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) {
717 for (i = 0; i < bp->fw_rx_stats_ext_size; i++) {
718 strcpy(buf, bnxt_port_stats_ext_arr[i].string);
719 buf += ETH_GSTRING_LEN;
720 }
721 for (i = 0; i < bp->fw_tx_stats_ext_size; i++) {
722 strcpy(buf,
723 bnxt_tx_port_stats_ext_arr[i].string);
724 buf += ETH_GSTRING_LEN;
725 }
726 if (bp->pri2cos_valid) {
727 for (i = 0; i < 8; i++) {
728 strcpy(buf,
729 bnxt_rx_bytes_pri_arr[i].string);
730 buf += ETH_GSTRING_LEN;
731 }
732 for (i = 0; i < 8; i++) {
733 strcpy(buf,
734 bnxt_rx_pkts_pri_arr[i].string);
735 buf += ETH_GSTRING_LEN;
736 }
737 for (i = 0; i < 8; i++) {
738 strcpy(buf,
739 bnxt_tx_bytes_pri_arr[i].string);
740 buf += ETH_GSTRING_LEN;
741 }
742 for (i = 0; i < 8; i++) {
743 strcpy(buf,
744 bnxt_tx_pkts_pri_arr[i].string);
745 buf += ETH_GSTRING_LEN;
746 }
747 }
748 }
749 break;
750 case ETH_SS_TEST:
751 if (bp->num_tests)
752 memcpy(buf, bp->test_info->string,
753 bp->num_tests * ETH_GSTRING_LEN);
754 break;
755 default:
756 netdev_err(bp->dev, "bnxt_get_strings invalid request %x\n",
757 stringset);
758 break;
759 }
760 }
761
bnxt_get_ringparam(struct net_device * dev,struct ethtool_ringparam * ering)762 static void bnxt_get_ringparam(struct net_device *dev,
763 struct ethtool_ringparam *ering)
764 {
765 struct bnxt *bp = netdev_priv(dev);
766
767 ering->rx_max_pending = BNXT_MAX_RX_DESC_CNT;
768 ering->rx_jumbo_max_pending = BNXT_MAX_RX_JUM_DESC_CNT;
769 ering->tx_max_pending = BNXT_MAX_TX_DESC_CNT;
770
771 ering->rx_pending = bp->rx_ring_size;
772 ering->rx_jumbo_pending = bp->rx_agg_ring_size;
773 ering->tx_pending = bp->tx_ring_size;
774 }
775
bnxt_set_ringparam(struct net_device * dev,struct ethtool_ringparam * ering)776 static int bnxt_set_ringparam(struct net_device *dev,
777 struct ethtool_ringparam *ering)
778 {
779 struct bnxt *bp = netdev_priv(dev);
780
781 if ((ering->rx_pending > BNXT_MAX_RX_DESC_CNT) ||
782 (ering->tx_pending > BNXT_MAX_TX_DESC_CNT) ||
783 (ering->tx_pending < BNXT_MIN_TX_DESC_CNT))
784 return -EINVAL;
785
786 if (netif_running(dev))
787 bnxt_close_nic(bp, false, false);
788
789 bp->rx_ring_size = ering->rx_pending;
790 bp->tx_ring_size = ering->tx_pending;
791 bnxt_set_ring_params(bp);
792
793 if (netif_running(dev))
794 return bnxt_open_nic(bp, false, false);
795
796 return 0;
797 }
798
bnxt_get_channels(struct net_device * dev,struct ethtool_channels * channel)799 static void bnxt_get_channels(struct net_device *dev,
800 struct ethtool_channels *channel)
801 {
802 struct bnxt *bp = netdev_priv(dev);
803 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
804 int max_rx_rings, max_tx_rings, tcs;
805 int max_tx_sch_inputs, tx_grps;
806
807 /* Get the most up-to-date max_tx_sch_inputs. */
808 if (netif_running(dev) && BNXT_NEW_RM(bp))
809 bnxt_hwrm_func_resc_qcaps(bp, false);
810 max_tx_sch_inputs = hw_resc->max_tx_sch_inputs;
811
812 bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, true);
813 if (max_tx_sch_inputs)
814 max_tx_rings = min_t(int, max_tx_rings, max_tx_sch_inputs);
815
816 tcs = netdev_get_num_tc(dev);
817 tx_grps = max(tcs, 1);
818 if (bp->tx_nr_rings_xdp)
819 tx_grps++;
820 max_tx_rings /= tx_grps;
821 channel->max_combined = min_t(int, max_rx_rings, max_tx_rings);
822
823 if (bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, false)) {
824 max_rx_rings = 0;
825 max_tx_rings = 0;
826 }
827 if (max_tx_sch_inputs)
828 max_tx_rings = min_t(int, max_tx_rings, max_tx_sch_inputs);
829
830 if (tcs > 1)
831 max_tx_rings /= tcs;
832
833 channel->max_rx = max_rx_rings;
834 channel->max_tx = max_tx_rings;
835 channel->max_other = 0;
836 if (bp->flags & BNXT_FLAG_SHARED_RINGS) {
837 channel->combined_count = bp->rx_nr_rings;
838 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
839 channel->combined_count--;
840 } else {
841 if (!BNXT_CHIP_TYPE_NITRO_A0(bp)) {
842 channel->rx_count = bp->rx_nr_rings;
843 channel->tx_count = bp->tx_nr_rings_per_tc;
844 }
845 }
846 }
847
bnxt_set_channels(struct net_device * dev,struct ethtool_channels * channel)848 static int bnxt_set_channels(struct net_device *dev,
849 struct ethtool_channels *channel)
850 {
851 struct bnxt *bp = netdev_priv(dev);
852 int req_tx_rings, req_rx_rings, tcs;
853 bool sh = false;
854 int tx_xdp = 0;
855 int rc = 0;
856
857 if (channel->other_count)
858 return -EINVAL;
859
860 if (!channel->combined_count &&
861 (!channel->rx_count || !channel->tx_count))
862 return -EINVAL;
863
864 if (channel->combined_count &&
865 (channel->rx_count || channel->tx_count))
866 return -EINVAL;
867
868 if (BNXT_CHIP_TYPE_NITRO_A0(bp) && (channel->rx_count ||
869 channel->tx_count))
870 return -EINVAL;
871
872 if (channel->combined_count)
873 sh = true;
874
875 tcs = netdev_get_num_tc(dev);
876
877 req_tx_rings = sh ? channel->combined_count : channel->tx_count;
878 req_rx_rings = sh ? channel->combined_count : channel->rx_count;
879 if (bp->tx_nr_rings_xdp) {
880 if (!sh) {
881 netdev_err(dev, "Only combined mode supported when XDP is enabled.\n");
882 return -EINVAL;
883 }
884 tx_xdp = req_rx_rings;
885 }
886 rc = bnxt_check_rings(bp, req_tx_rings, req_rx_rings, sh, tcs, tx_xdp);
887 if (rc) {
888 netdev_warn(dev, "Unable to allocate the requested rings\n");
889 return rc;
890 }
891
892 if (bnxt_get_nr_rss_ctxs(bp, req_rx_rings) !=
893 bnxt_get_nr_rss_ctxs(bp, bp->rx_nr_rings) &&
894 (dev->priv_flags & IFF_RXFH_CONFIGURED)) {
895 netdev_warn(dev, "RSS table size change required, RSS table entries must be default to proceed\n");
896 return -EINVAL;
897 }
898
899 if (netif_running(dev)) {
900 if (BNXT_PF(bp)) {
901 /* TODO CHIMP_FW: Send message to all VF's
902 * before PF unload
903 */
904 }
905 rc = bnxt_close_nic(bp, true, false);
906 if (rc) {
907 netdev_err(bp->dev, "Set channel failure rc :%x\n",
908 rc);
909 return rc;
910 }
911 }
912
913 if (sh) {
914 bp->flags |= BNXT_FLAG_SHARED_RINGS;
915 bp->rx_nr_rings = channel->combined_count;
916 bp->tx_nr_rings_per_tc = channel->combined_count;
917 } else {
918 bp->flags &= ~BNXT_FLAG_SHARED_RINGS;
919 bp->rx_nr_rings = channel->rx_count;
920 bp->tx_nr_rings_per_tc = channel->tx_count;
921 }
922 bp->tx_nr_rings_xdp = tx_xdp;
923 bp->tx_nr_rings = bp->tx_nr_rings_per_tc + tx_xdp;
924 if (tcs > 1)
925 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tcs + tx_xdp;
926
927 bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
928 bp->tx_nr_rings + bp->rx_nr_rings;
929
930 /* After changing number of rx channels, update NTUPLE feature. */
931 netdev_update_features(dev);
932 if (netif_running(dev)) {
933 rc = bnxt_open_nic(bp, true, false);
934 if ((!rc) && BNXT_PF(bp)) {
935 /* TODO CHIMP_FW: Send message to all VF's
936 * to renable
937 */
938 }
939 } else {
940 rc = bnxt_reserve_rings(bp, true);
941 }
942
943 return rc;
944 }
945
946 #ifdef CONFIG_RFS_ACCEL
bnxt_grxclsrlall(struct bnxt * bp,struct ethtool_rxnfc * cmd,u32 * rule_locs)947 static int bnxt_grxclsrlall(struct bnxt *bp, struct ethtool_rxnfc *cmd,
948 u32 *rule_locs)
949 {
950 int i, j = 0;
951
952 cmd->data = bp->ntp_fltr_count;
953 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
954 struct hlist_head *head;
955 struct bnxt_ntuple_filter *fltr;
956
957 head = &bp->ntp_fltr_hash_tbl[i];
958 rcu_read_lock();
959 hlist_for_each_entry_rcu(fltr, head, hash) {
960 if (j == cmd->rule_cnt)
961 break;
962 rule_locs[j++] = fltr->sw_id;
963 }
964 rcu_read_unlock();
965 if (j == cmd->rule_cnt)
966 break;
967 }
968 cmd->rule_cnt = j;
969 return 0;
970 }
971
bnxt_grxclsrule(struct bnxt * bp,struct ethtool_rxnfc * cmd)972 static int bnxt_grxclsrule(struct bnxt *bp, struct ethtool_rxnfc *cmd)
973 {
974 struct ethtool_rx_flow_spec *fs =
975 (struct ethtool_rx_flow_spec *)&cmd->fs;
976 struct bnxt_ntuple_filter *fltr;
977 struct flow_keys *fkeys;
978 int i, rc = -EINVAL;
979
980 if (fs->location >= BNXT_NTP_FLTR_MAX_FLTR)
981 return rc;
982
983 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
984 struct hlist_head *head;
985
986 head = &bp->ntp_fltr_hash_tbl[i];
987 rcu_read_lock();
988 hlist_for_each_entry_rcu(fltr, head, hash) {
989 if (fltr->sw_id == fs->location)
990 goto fltr_found;
991 }
992 rcu_read_unlock();
993 }
994 return rc;
995
996 fltr_found:
997 fkeys = &fltr->fkeys;
998 if (fkeys->basic.n_proto == htons(ETH_P_IP)) {
999 if (fkeys->basic.ip_proto == IPPROTO_TCP)
1000 fs->flow_type = TCP_V4_FLOW;
1001 else if (fkeys->basic.ip_proto == IPPROTO_UDP)
1002 fs->flow_type = UDP_V4_FLOW;
1003 else
1004 goto fltr_err;
1005
1006 fs->h_u.tcp_ip4_spec.ip4src = fkeys->addrs.v4addrs.src;
1007 fs->m_u.tcp_ip4_spec.ip4src = cpu_to_be32(~0);
1008
1009 fs->h_u.tcp_ip4_spec.ip4dst = fkeys->addrs.v4addrs.dst;
1010 fs->m_u.tcp_ip4_spec.ip4dst = cpu_to_be32(~0);
1011
1012 fs->h_u.tcp_ip4_spec.psrc = fkeys->ports.src;
1013 fs->m_u.tcp_ip4_spec.psrc = cpu_to_be16(~0);
1014
1015 fs->h_u.tcp_ip4_spec.pdst = fkeys->ports.dst;
1016 fs->m_u.tcp_ip4_spec.pdst = cpu_to_be16(~0);
1017 } else {
1018 int i;
1019
1020 if (fkeys->basic.ip_proto == IPPROTO_TCP)
1021 fs->flow_type = TCP_V6_FLOW;
1022 else if (fkeys->basic.ip_proto == IPPROTO_UDP)
1023 fs->flow_type = UDP_V6_FLOW;
1024 else
1025 goto fltr_err;
1026
1027 *(struct in6_addr *)&fs->h_u.tcp_ip6_spec.ip6src[0] =
1028 fkeys->addrs.v6addrs.src;
1029 *(struct in6_addr *)&fs->h_u.tcp_ip6_spec.ip6dst[0] =
1030 fkeys->addrs.v6addrs.dst;
1031 for (i = 0; i < 4; i++) {
1032 fs->m_u.tcp_ip6_spec.ip6src[i] = cpu_to_be32(~0);
1033 fs->m_u.tcp_ip6_spec.ip6dst[i] = cpu_to_be32(~0);
1034 }
1035 fs->h_u.tcp_ip6_spec.psrc = fkeys->ports.src;
1036 fs->m_u.tcp_ip6_spec.psrc = cpu_to_be16(~0);
1037
1038 fs->h_u.tcp_ip6_spec.pdst = fkeys->ports.dst;
1039 fs->m_u.tcp_ip6_spec.pdst = cpu_to_be16(~0);
1040 }
1041
1042 fs->ring_cookie = fltr->rxq;
1043 rc = 0;
1044
1045 fltr_err:
1046 rcu_read_unlock();
1047
1048 return rc;
1049 }
1050 #endif
1051
get_ethtool_ipv4_rss(struct bnxt * bp)1052 static u64 get_ethtool_ipv4_rss(struct bnxt *bp)
1053 {
1054 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4)
1055 return RXH_IP_SRC | RXH_IP_DST;
1056 return 0;
1057 }
1058
get_ethtool_ipv6_rss(struct bnxt * bp)1059 static u64 get_ethtool_ipv6_rss(struct bnxt *bp)
1060 {
1061 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6)
1062 return RXH_IP_SRC | RXH_IP_DST;
1063 return 0;
1064 }
1065
bnxt_grxfh(struct bnxt * bp,struct ethtool_rxnfc * cmd)1066 static int bnxt_grxfh(struct bnxt *bp, struct ethtool_rxnfc *cmd)
1067 {
1068 cmd->data = 0;
1069 switch (cmd->flow_type) {
1070 case TCP_V4_FLOW:
1071 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4)
1072 cmd->data |= RXH_IP_SRC | RXH_IP_DST |
1073 RXH_L4_B_0_1 | RXH_L4_B_2_3;
1074 cmd->data |= get_ethtool_ipv4_rss(bp);
1075 break;
1076 case UDP_V4_FLOW:
1077 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4)
1078 cmd->data |= RXH_IP_SRC | RXH_IP_DST |
1079 RXH_L4_B_0_1 | RXH_L4_B_2_3;
1080 fallthrough;
1081 case SCTP_V4_FLOW:
1082 case AH_ESP_V4_FLOW:
1083 case AH_V4_FLOW:
1084 case ESP_V4_FLOW:
1085 case IPV4_FLOW:
1086 cmd->data |= get_ethtool_ipv4_rss(bp);
1087 break;
1088
1089 case TCP_V6_FLOW:
1090 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6)
1091 cmd->data |= RXH_IP_SRC | RXH_IP_DST |
1092 RXH_L4_B_0_1 | RXH_L4_B_2_3;
1093 cmd->data |= get_ethtool_ipv6_rss(bp);
1094 break;
1095 case UDP_V6_FLOW:
1096 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6)
1097 cmd->data |= RXH_IP_SRC | RXH_IP_DST |
1098 RXH_L4_B_0_1 | RXH_L4_B_2_3;
1099 fallthrough;
1100 case SCTP_V6_FLOW:
1101 case AH_ESP_V6_FLOW:
1102 case AH_V6_FLOW:
1103 case ESP_V6_FLOW:
1104 case IPV6_FLOW:
1105 cmd->data |= get_ethtool_ipv6_rss(bp);
1106 break;
1107 }
1108 return 0;
1109 }
1110
1111 #define RXH_4TUPLE (RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 | RXH_L4_B_2_3)
1112 #define RXH_2TUPLE (RXH_IP_SRC | RXH_IP_DST)
1113
bnxt_srxfh(struct bnxt * bp,struct ethtool_rxnfc * cmd)1114 static int bnxt_srxfh(struct bnxt *bp, struct ethtool_rxnfc *cmd)
1115 {
1116 u32 rss_hash_cfg = bp->rss_hash_cfg;
1117 int tuple, rc = 0;
1118
1119 if (cmd->data == RXH_4TUPLE)
1120 tuple = 4;
1121 else if (cmd->data == RXH_2TUPLE)
1122 tuple = 2;
1123 else if (!cmd->data)
1124 tuple = 0;
1125 else
1126 return -EINVAL;
1127
1128 if (cmd->flow_type == TCP_V4_FLOW) {
1129 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4;
1130 if (tuple == 4)
1131 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4;
1132 } else if (cmd->flow_type == UDP_V4_FLOW) {
1133 if (tuple == 4 && !(bp->flags & BNXT_FLAG_UDP_RSS_CAP))
1134 return -EINVAL;
1135 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4;
1136 if (tuple == 4)
1137 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4;
1138 } else if (cmd->flow_type == TCP_V6_FLOW) {
1139 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6;
1140 if (tuple == 4)
1141 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6;
1142 } else if (cmd->flow_type == UDP_V6_FLOW) {
1143 if (tuple == 4 && !(bp->flags & BNXT_FLAG_UDP_RSS_CAP))
1144 return -EINVAL;
1145 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6;
1146 if (tuple == 4)
1147 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6;
1148 } else if (tuple == 4) {
1149 return -EINVAL;
1150 }
1151
1152 switch (cmd->flow_type) {
1153 case TCP_V4_FLOW:
1154 case UDP_V4_FLOW:
1155 case SCTP_V4_FLOW:
1156 case AH_ESP_V4_FLOW:
1157 case AH_V4_FLOW:
1158 case ESP_V4_FLOW:
1159 case IPV4_FLOW:
1160 if (tuple == 2)
1161 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4;
1162 else if (!tuple)
1163 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4;
1164 break;
1165
1166 case TCP_V6_FLOW:
1167 case UDP_V6_FLOW:
1168 case SCTP_V6_FLOW:
1169 case AH_ESP_V6_FLOW:
1170 case AH_V6_FLOW:
1171 case ESP_V6_FLOW:
1172 case IPV6_FLOW:
1173 if (tuple == 2)
1174 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6;
1175 else if (!tuple)
1176 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6;
1177 break;
1178 }
1179
1180 if (bp->rss_hash_cfg == rss_hash_cfg)
1181 return 0;
1182
1183 bp->rss_hash_cfg = rss_hash_cfg;
1184 if (netif_running(bp->dev)) {
1185 bnxt_close_nic(bp, false, false);
1186 rc = bnxt_open_nic(bp, false, false);
1187 }
1188 return rc;
1189 }
1190
bnxt_get_rxnfc(struct net_device * dev,struct ethtool_rxnfc * cmd,u32 * rule_locs)1191 static int bnxt_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
1192 u32 *rule_locs)
1193 {
1194 struct bnxt *bp = netdev_priv(dev);
1195 int rc = 0;
1196
1197 switch (cmd->cmd) {
1198 #ifdef CONFIG_RFS_ACCEL
1199 case ETHTOOL_GRXRINGS:
1200 cmd->data = bp->rx_nr_rings;
1201 break;
1202
1203 case ETHTOOL_GRXCLSRLCNT:
1204 cmd->rule_cnt = bp->ntp_fltr_count;
1205 cmd->data = BNXT_NTP_FLTR_MAX_FLTR;
1206 break;
1207
1208 case ETHTOOL_GRXCLSRLALL:
1209 rc = bnxt_grxclsrlall(bp, cmd, (u32 *)rule_locs);
1210 break;
1211
1212 case ETHTOOL_GRXCLSRULE:
1213 rc = bnxt_grxclsrule(bp, cmd);
1214 break;
1215 #endif
1216
1217 case ETHTOOL_GRXFH:
1218 rc = bnxt_grxfh(bp, cmd);
1219 break;
1220
1221 default:
1222 rc = -EOPNOTSUPP;
1223 break;
1224 }
1225
1226 return rc;
1227 }
1228
bnxt_set_rxnfc(struct net_device * dev,struct ethtool_rxnfc * cmd)1229 static int bnxt_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
1230 {
1231 struct bnxt *bp = netdev_priv(dev);
1232 int rc;
1233
1234 switch (cmd->cmd) {
1235 case ETHTOOL_SRXFH:
1236 rc = bnxt_srxfh(bp, cmd);
1237 break;
1238
1239 default:
1240 rc = -EOPNOTSUPP;
1241 break;
1242 }
1243 return rc;
1244 }
1245
bnxt_get_rxfh_indir_size(struct net_device * dev)1246 u32 bnxt_get_rxfh_indir_size(struct net_device *dev)
1247 {
1248 struct bnxt *bp = netdev_priv(dev);
1249
1250 if (bp->flags & BNXT_FLAG_CHIP_P5)
1251 return ALIGN(bp->rx_nr_rings, BNXT_RSS_TABLE_ENTRIES_P5);
1252 return HW_HASH_INDEX_SIZE;
1253 }
1254
bnxt_get_rxfh_key_size(struct net_device * dev)1255 static u32 bnxt_get_rxfh_key_size(struct net_device *dev)
1256 {
1257 return HW_HASH_KEY_SIZE;
1258 }
1259
bnxt_get_rxfh(struct net_device * dev,u32 * indir,u8 * key,u8 * hfunc)1260 static int bnxt_get_rxfh(struct net_device *dev, u32 *indir, u8 *key,
1261 u8 *hfunc)
1262 {
1263 struct bnxt *bp = netdev_priv(dev);
1264 struct bnxt_vnic_info *vnic;
1265 u32 i, tbl_size;
1266
1267 if (hfunc)
1268 *hfunc = ETH_RSS_HASH_TOP;
1269
1270 if (!bp->vnic_info)
1271 return 0;
1272
1273 vnic = &bp->vnic_info[0];
1274 if (indir && bp->rss_indir_tbl) {
1275 tbl_size = bnxt_get_rxfh_indir_size(dev);
1276 for (i = 0; i < tbl_size; i++)
1277 indir[i] = bp->rss_indir_tbl[i];
1278 }
1279
1280 if (key && vnic->rss_hash_key)
1281 memcpy(key, vnic->rss_hash_key, HW_HASH_KEY_SIZE);
1282
1283 return 0;
1284 }
1285
bnxt_set_rxfh(struct net_device * dev,const u32 * indir,const u8 * key,const u8 hfunc)1286 static int bnxt_set_rxfh(struct net_device *dev, const u32 *indir,
1287 const u8 *key, const u8 hfunc)
1288 {
1289 struct bnxt *bp = netdev_priv(dev);
1290 int rc = 0;
1291
1292 if (hfunc && hfunc != ETH_RSS_HASH_TOP)
1293 return -EOPNOTSUPP;
1294
1295 if (key)
1296 return -EOPNOTSUPP;
1297
1298 if (indir) {
1299 u32 i, pad, tbl_size = bnxt_get_rxfh_indir_size(dev);
1300
1301 for (i = 0; i < tbl_size; i++)
1302 bp->rss_indir_tbl[i] = indir[i];
1303 pad = bp->rss_indir_tbl_entries - tbl_size;
1304 if (pad)
1305 memset(&bp->rss_indir_tbl[i], 0, pad * sizeof(u16));
1306 }
1307
1308 if (netif_running(bp->dev)) {
1309 bnxt_close_nic(bp, false, false);
1310 rc = bnxt_open_nic(bp, false, false);
1311 }
1312 return rc;
1313 }
1314
bnxt_get_drvinfo(struct net_device * dev,struct ethtool_drvinfo * info)1315 static void bnxt_get_drvinfo(struct net_device *dev,
1316 struct ethtool_drvinfo *info)
1317 {
1318 struct bnxt *bp = netdev_priv(dev);
1319
1320 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
1321 strlcpy(info->fw_version, bp->fw_ver_str, sizeof(info->fw_version));
1322 strlcpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info));
1323 info->n_stats = bnxt_get_num_stats(bp);
1324 info->testinfo_len = bp->num_tests;
1325 /* TODO CHIMP_FW: eeprom dump details */
1326 info->eedump_len = 0;
1327 /* TODO CHIMP FW: reg dump details */
1328 info->regdump_len = 0;
1329 }
1330
bnxt_get_regs_len(struct net_device * dev)1331 static int bnxt_get_regs_len(struct net_device *dev)
1332 {
1333 struct bnxt *bp = netdev_priv(dev);
1334 int reg_len;
1335
1336 if (!BNXT_PF(bp))
1337 return -EOPNOTSUPP;
1338
1339 reg_len = BNXT_PXP_REG_LEN;
1340
1341 if (bp->fw_cap & BNXT_FW_CAP_PCIE_STATS_SUPPORTED)
1342 reg_len += sizeof(struct pcie_ctx_hw_stats);
1343
1344 return reg_len;
1345 }
1346
bnxt_get_regs(struct net_device * dev,struct ethtool_regs * regs,void * _p)1347 static void bnxt_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1348 void *_p)
1349 {
1350 struct pcie_ctx_hw_stats *hw_pcie_stats;
1351 struct hwrm_pcie_qstats_input req = {0};
1352 struct bnxt *bp = netdev_priv(dev);
1353 dma_addr_t hw_pcie_stats_addr;
1354 int rc;
1355
1356 regs->version = 0;
1357 bnxt_dbg_hwrm_rd_reg(bp, 0, BNXT_PXP_REG_LEN / 4, _p);
1358
1359 if (!(bp->fw_cap & BNXT_FW_CAP_PCIE_STATS_SUPPORTED))
1360 return;
1361
1362 hw_pcie_stats = dma_alloc_coherent(&bp->pdev->dev,
1363 sizeof(*hw_pcie_stats),
1364 &hw_pcie_stats_addr, GFP_KERNEL);
1365 if (!hw_pcie_stats)
1366 return;
1367
1368 regs->version = 1;
1369 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PCIE_QSTATS, -1, -1);
1370 req.pcie_stat_size = cpu_to_le16(sizeof(*hw_pcie_stats));
1371 req.pcie_stat_host_addr = cpu_to_le64(hw_pcie_stats_addr);
1372 mutex_lock(&bp->hwrm_cmd_lock);
1373 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
1374 if (!rc) {
1375 __le64 *src = (__le64 *)hw_pcie_stats;
1376 u64 *dst = (u64 *)(_p + BNXT_PXP_REG_LEN);
1377 int i;
1378
1379 for (i = 0; i < sizeof(*hw_pcie_stats) / sizeof(__le64); i++)
1380 dst[i] = le64_to_cpu(src[i]);
1381 }
1382 mutex_unlock(&bp->hwrm_cmd_lock);
1383 dma_free_coherent(&bp->pdev->dev, sizeof(*hw_pcie_stats), hw_pcie_stats,
1384 hw_pcie_stats_addr);
1385 }
1386
bnxt_get_wol(struct net_device * dev,struct ethtool_wolinfo * wol)1387 static void bnxt_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1388 {
1389 struct bnxt *bp = netdev_priv(dev);
1390
1391 wol->supported = 0;
1392 wol->wolopts = 0;
1393 memset(&wol->sopass, 0, sizeof(wol->sopass));
1394 if (bp->flags & BNXT_FLAG_WOL_CAP) {
1395 wol->supported = WAKE_MAGIC;
1396 if (bp->wol)
1397 wol->wolopts = WAKE_MAGIC;
1398 }
1399 }
1400
bnxt_set_wol(struct net_device * dev,struct ethtool_wolinfo * wol)1401 static int bnxt_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1402 {
1403 struct bnxt *bp = netdev_priv(dev);
1404
1405 if (wol->wolopts & ~WAKE_MAGIC)
1406 return -EINVAL;
1407
1408 if (wol->wolopts & WAKE_MAGIC) {
1409 if (!(bp->flags & BNXT_FLAG_WOL_CAP))
1410 return -EINVAL;
1411 if (!bp->wol) {
1412 if (bnxt_hwrm_alloc_wol_fltr(bp))
1413 return -EBUSY;
1414 bp->wol = 1;
1415 }
1416 } else {
1417 if (bp->wol) {
1418 if (bnxt_hwrm_free_wol_fltr(bp))
1419 return -EBUSY;
1420 bp->wol = 0;
1421 }
1422 }
1423 return 0;
1424 }
1425
_bnxt_fw_to_ethtool_adv_spds(u16 fw_speeds,u8 fw_pause)1426 u32 _bnxt_fw_to_ethtool_adv_spds(u16 fw_speeds, u8 fw_pause)
1427 {
1428 u32 speed_mask = 0;
1429
1430 /* TODO: support 25GB, 40GB, 50GB with different cable type */
1431 /* set the advertised speeds */
1432 if (fw_speeds & BNXT_LINK_SPEED_MSK_100MB)
1433 speed_mask |= ADVERTISED_100baseT_Full;
1434 if (fw_speeds & BNXT_LINK_SPEED_MSK_1GB)
1435 speed_mask |= ADVERTISED_1000baseT_Full;
1436 if (fw_speeds & BNXT_LINK_SPEED_MSK_2_5GB)
1437 speed_mask |= ADVERTISED_2500baseX_Full;
1438 if (fw_speeds & BNXT_LINK_SPEED_MSK_10GB)
1439 speed_mask |= ADVERTISED_10000baseT_Full;
1440 if (fw_speeds & BNXT_LINK_SPEED_MSK_40GB)
1441 speed_mask |= ADVERTISED_40000baseCR4_Full;
1442
1443 if ((fw_pause & BNXT_LINK_PAUSE_BOTH) == BNXT_LINK_PAUSE_BOTH)
1444 speed_mask |= ADVERTISED_Pause;
1445 else if (fw_pause & BNXT_LINK_PAUSE_TX)
1446 speed_mask |= ADVERTISED_Asym_Pause;
1447 else if (fw_pause & BNXT_LINK_PAUSE_RX)
1448 speed_mask |= ADVERTISED_Pause | ADVERTISED_Asym_Pause;
1449
1450 return speed_mask;
1451 }
1452
1453 #define BNXT_FW_TO_ETHTOOL_SPDS(fw_speeds, fw_pause, lk_ksettings, name)\
1454 { \
1455 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_100MB) \
1456 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\
1457 100baseT_Full); \
1458 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_1GB) \
1459 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\
1460 1000baseT_Full); \
1461 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_10GB) \
1462 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\
1463 10000baseT_Full); \
1464 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_25GB) \
1465 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\
1466 25000baseCR_Full); \
1467 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_40GB) \
1468 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\
1469 40000baseCR4_Full);\
1470 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_50GB) \
1471 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\
1472 50000baseCR2_Full);\
1473 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_100GB) \
1474 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\
1475 100000baseCR4_Full);\
1476 if ((fw_pause) & BNXT_LINK_PAUSE_RX) { \
1477 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\
1478 Pause); \
1479 if (!((fw_pause) & BNXT_LINK_PAUSE_TX)) \
1480 ethtool_link_ksettings_add_link_mode( \
1481 lk_ksettings, name, Asym_Pause);\
1482 } else if ((fw_pause) & BNXT_LINK_PAUSE_TX) { \
1483 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\
1484 Asym_Pause); \
1485 } \
1486 }
1487
1488 #define BNXT_ETHTOOL_TO_FW_SPDS(fw_speeds, lk_ksettings, name) \
1489 { \
1490 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \
1491 100baseT_Full) || \
1492 ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \
1493 100baseT_Half)) \
1494 (fw_speeds) |= BNXT_LINK_SPEED_MSK_100MB; \
1495 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \
1496 1000baseT_Full) || \
1497 ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \
1498 1000baseT_Half)) \
1499 (fw_speeds) |= BNXT_LINK_SPEED_MSK_1GB; \
1500 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \
1501 10000baseT_Full)) \
1502 (fw_speeds) |= BNXT_LINK_SPEED_MSK_10GB; \
1503 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \
1504 25000baseCR_Full)) \
1505 (fw_speeds) |= BNXT_LINK_SPEED_MSK_25GB; \
1506 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \
1507 40000baseCR4_Full)) \
1508 (fw_speeds) |= BNXT_LINK_SPEED_MSK_40GB; \
1509 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \
1510 50000baseCR2_Full)) \
1511 (fw_speeds) |= BNXT_LINK_SPEED_MSK_50GB; \
1512 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \
1513 100000baseCR4_Full)) \
1514 (fw_speeds) |= BNXT_LINK_SPEED_MSK_100GB; \
1515 }
1516
1517 #define BNXT_FW_TO_ETHTOOL_PAM4_SPDS(fw_speeds, lk_ksettings, name) \
1518 { \
1519 if ((fw_speeds) & BNXT_LINK_PAM4_SPEED_MSK_50GB) \
1520 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\
1521 50000baseCR_Full); \
1522 if ((fw_speeds) & BNXT_LINK_PAM4_SPEED_MSK_100GB) \
1523 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\
1524 100000baseCR2_Full);\
1525 if ((fw_speeds) & BNXT_LINK_PAM4_SPEED_MSK_200GB) \
1526 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\
1527 200000baseCR4_Full);\
1528 }
1529
1530 #define BNXT_ETHTOOL_TO_FW_PAM4_SPDS(fw_speeds, lk_ksettings, name) \
1531 { \
1532 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \
1533 50000baseCR_Full)) \
1534 (fw_speeds) |= BNXT_LINK_PAM4_SPEED_MSK_50GB; \
1535 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \
1536 100000baseCR2_Full)) \
1537 (fw_speeds) |= BNXT_LINK_PAM4_SPEED_MSK_100GB; \
1538 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \
1539 200000baseCR4_Full)) \
1540 (fw_speeds) |= BNXT_LINK_PAM4_SPEED_MSK_200GB; \
1541 }
1542
bnxt_fw_to_ethtool_advertised_fec(struct bnxt_link_info * link_info,struct ethtool_link_ksettings * lk_ksettings)1543 static void bnxt_fw_to_ethtool_advertised_fec(struct bnxt_link_info *link_info,
1544 struct ethtool_link_ksettings *lk_ksettings)
1545 {
1546 u16 fec_cfg = link_info->fec_cfg;
1547
1548 if ((fec_cfg & BNXT_FEC_NONE) || !(fec_cfg & BNXT_FEC_AUTONEG)) {
1549 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT,
1550 lk_ksettings->link_modes.advertising);
1551 return;
1552 }
1553 if (fec_cfg & BNXT_FEC_ENC_BASE_R)
1554 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT,
1555 lk_ksettings->link_modes.advertising);
1556 if (fec_cfg & BNXT_FEC_ENC_RS)
1557 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT,
1558 lk_ksettings->link_modes.advertising);
1559 if (fec_cfg & BNXT_FEC_ENC_LLRS)
1560 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT,
1561 lk_ksettings->link_modes.advertising);
1562 }
1563
bnxt_fw_to_ethtool_advertised_spds(struct bnxt_link_info * link_info,struct ethtool_link_ksettings * lk_ksettings)1564 static void bnxt_fw_to_ethtool_advertised_spds(struct bnxt_link_info *link_info,
1565 struct ethtool_link_ksettings *lk_ksettings)
1566 {
1567 u16 fw_speeds = link_info->advertising;
1568 u8 fw_pause = 0;
1569
1570 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL)
1571 fw_pause = link_info->auto_pause_setting;
1572
1573 BNXT_FW_TO_ETHTOOL_SPDS(fw_speeds, fw_pause, lk_ksettings, advertising);
1574 fw_speeds = link_info->advertising_pam4;
1575 BNXT_FW_TO_ETHTOOL_PAM4_SPDS(fw_speeds, lk_ksettings, advertising);
1576 bnxt_fw_to_ethtool_advertised_fec(link_info, lk_ksettings);
1577 }
1578
bnxt_fw_to_ethtool_lp_adv(struct bnxt_link_info * link_info,struct ethtool_link_ksettings * lk_ksettings)1579 static void bnxt_fw_to_ethtool_lp_adv(struct bnxt_link_info *link_info,
1580 struct ethtool_link_ksettings *lk_ksettings)
1581 {
1582 u16 fw_speeds = link_info->lp_auto_link_speeds;
1583 u8 fw_pause = 0;
1584
1585 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL)
1586 fw_pause = link_info->lp_pause;
1587
1588 BNXT_FW_TO_ETHTOOL_SPDS(fw_speeds, fw_pause, lk_ksettings,
1589 lp_advertising);
1590 fw_speeds = link_info->lp_auto_pam4_link_speeds;
1591 BNXT_FW_TO_ETHTOOL_PAM4_SPDS(fw_speeds, lk_ksettings, lp_advertising);
1592 }
1593
bnxt_fw_to_ethtool_support_fec(struct bnxt_link_info * link_info,struct ethtool_link_ksettings * lk_ksettings)1594 static void bnxt_fw_to_ethtool_support_fec(struct bnxt_link_info *link_info,
1595 struct ethtool_link_ksettings *lk_ksettings)
1596 {
1597 u16 fec_cfg = link_info->fec_cfg;
1598
1599 if (fec_cfg & BNXT_FEC_NONE) {
1600 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT,
1601 lk_ksettings->link_modes.supported);
1602 return;
1603 }
1604 if (fec_cfg & BNXT_FEC_ENC_BASE_R_CAP)
1605 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT,
1606 lk_ksettings->link_modes.supported);
1607 if (fec_cfg & BNXT_FEC_ENC_RS_CAP)
1608 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT,
1609 lk_ksettings->link_modes.supported);
1610 if (fec_cfg & BNXT_FEC_ENC_LLRS_CAP)
1611 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT,
1612 lk_ksettings->link_modes.supported);
1613 }
1614
bnxt_fw_to_ethtool_support_spds(struct bnxt_link_info * link_info,struct ethtool_link_ksettings * lk_ksettings)1615 static void bnxt_fw_to_ethtool_support_spds(struct bnxt_link_info *link_info,
1616 struct ethtool_link_ksettings *lk_ksettings)
1617 {
1618 u16 fw_speeds = link_info->support_speeds;
1619
1620 BNXT_FW_TO_ETHTOOL_SPDS(fw_speeds, 0, lk_ksettings, supported);
1621 fw_speeds = link_info->support_pam4_speeds;
1622 BNXT_FW_TO_ETHTOOL_PAM4_SPDS(fw_speeds, lk_ksettings, supported);
1623
1624 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported, Pause);
1625 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported,
1626 Asym_Pause);
1627
1628 if (link_info->support_auto_speeds ||
1629 link_info->support_pam4_auto_speeds)
1630 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported,
1631 Autoneg);
1632 bnxt_fw_to_ethtool_support_fec(link_info, lk_ksettings);
1633 }
1634
bnxt_fw_to_ethtool_speed(u16 fw_link_speed)1635 u32 bnxt_fw_to_ethtool_speed(u16 fw_link_speed)
1636 {
1637 switch (fw_link_speed) {
1638 case BNXT_LINK_SPEED_100MB:
1639 return SPEED_100;
1640 case BNXT_LINK_SPEED_1GB:
1641 return SPEED_1000;
1642 case BNXT_LINK_SPEED_2_5GB:
1643 return SPEED_2500;
1644 case BNXT_LINK_SPEED_10GB:
1645 return SPEED_10000;
1646 case BNXT_LINK_SPEED_20GB:
1647 return SPEED_20000;
1648 case BNXT_LINK_SPEED_25GB:
1649 return SPEED_25000;
1650 case BNXT_LINK_SPEED_40GB:
1651 return SPEED_40000;
1652 case BNXT_LINK_SPEED_50GB:
1653 return SPEED_50000;
1654 case BNXT_LINK_SPEED_100GB:
1655 return SPEED_100000;
1656 case BNXT_LINK_SPEED_200GB:
1657 return SPEED_200000;
1658 default:
1659 return SPEED_UNKNOWN;
1660 }
1661 }
1662
bnxt_get_link_ksettings(struct net_device * dev,struct ethtool_link_ksettings * lk_ksettings)1663 static int bnxt_get_link_ksettings(struct net_device *dev,
1664 struct ethtool_link_ksettings *lk_ksettings)
1665 {
1666 struct bnxt *bp = netdev_priv(dev);
1667 struct bnxt_link_info *link_info = &bp->link_info;
1668 struct ethtool_link_settings *base = &lk_ksettings->base;
1669 u32 ethtool_speed;
1670
1671 ethtool_link_ksettings_zero_link_mode(lk_ksettings, supported);
1672 mutex_lock(&bp->link_lock);
1673 bnxt_fw_to_ethtool_support_spds(link_info, lk_ksettings);
1674
1675 ethtool_link_ksettings_zero_link_mode(lk_ksettings, advertising);
1676 if (link_info->autoneg) {
1677 bnxt_fw_to_ethtool_advertised_spds(link_info, lk_ksettings);
1678 ethtool_link_ksettings_add_link_mode(lk_ksettings,
1679 advertising, Autoneg);
1680 base->autoneg = AUTONEG_ENABLE;
1681 base->duplex = DUPLEX_UNKNOWN;
1682 if (link_info->phy_link_status == BNXT_LINK_LINK) {
1683 bnxt_fw_to_ethtool_lp_adv(link_info, lk_ksettings);
1684 if (link_info->duplex & BNXT_LINK_DUPLEX_FULL)
1685 base->duplex = DUPLEX_FULL;
1686 else
1687 base->duplex = DUPLEX_HALF;
1688 }
1689 ethtool_speed = bnxt_fw_to_ethtool_speed(link_info->link_speed);
1690 } else {
1691 base->autoneg = AUTONEG_DISABLE;
1692 ethtool_speed =
1693 bnxt_fw_to_ethtool_speed(link_info->req_link_speed);
1694 base->duplex = DUPLEX_HALF;
1695 if (link_info->req_duplex == BNXT_LINK_DUPLEX_FULL)
1696 base->duplex = DUPLEX_FULL;
1697 }
1698 base->speed = ethtool_speed;
1699
1700 base->port = PORT_NONE;
1701 if (link_info->media_type == PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP) {
1702 base->port = PORT_TP;
1703 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported,
1704 TP);
1705 ethtool_link_ksettings_add_link_mode(lk_ksettings, advertising,
1706 TP);
1707 } else {
1708 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported,
1709 FIBRE);
1710 ethtool_link_ksettings_add_link_mode(lk_ksettings, advertising,
1711 FIBRE);
1712
1713 if (link_info->media_type == PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC)
1714 base->port = PORT_DA;
1715 else if (link_info->media_type ==
1716 PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE)
1717 base->port = PORT_FIBRE;
1718 }
1719 base->phy_address = link_info->phy_addr;
1720 mutex_unlock(&bp->link_lock);
1721
1722 return 0;
1723 }
1724
bnxt_force_link_speed(struct net_device * dev,u32 ethtool_speed)1725 static int bnxt_force_link_speed(struct net_device *dev, u32 ethtool_speed)
1726 {
1727 struct bnxt *bp = netdev_priv(dev);
1728 struct bnxt_link_info *link_info = &bp->link_info;
1729 u16 support_pam4_spds = link_info->support_pam4_speeds;
1730 u16 support_spds = link_info->support_speeds;
1731 u8 sig_mode = BNXT_SIG_MODE_NRZ;
1732 u16 fw_speed = 0;
1733
1734 switch (ethtool_speed) {
1735 case SPEED_100:
1736 if (support_spds & BNXT_LINK_SPEED_MSK_100MB)
1737 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100MB;
1738 break;
1739 case SPEED_1000:
1740 if (support_spds & BNXT_LINK_SPEED_MSK_1GB)
1741 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB;
1742 break;
1743 case SPEED_2500:
1744 if (support_spds & BNXT_LINK_SPEED_MSK_2_5GB)
1745 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2_5GB;
1746 break;
1747 case SPEED_10000:
1748 if (support_spds & BNXT_LINK_SPEED_MSK_10GB)
1749 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB;
1750 break;
1751 case SPEED_20000:
1752 if (support_spds & BNXT_LINK_SPEED_MSK_20GB)
1753 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_20GB;
1754 break;
1755 case SPEED_25000:
1756 if (support_spds & BNXT_LINK_SPEED_MSK_25GB)
1757 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB;
1758 break;
1759 case SPEED_40000:
1760 if (support_spds & BNXT_LINK_SPEED_MSK_40GB)
1761 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB;
1762 break;
1763 case SPEED_50000:
1764 if (support_spds & BNXT_LINK_SPEED_MSK_50GB) {
1765 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB;
1766 } else if (support_pam4_spds & BNXT_LINK_PAM4_SPEED_MSK_50GB) {
1767 fw_speed = PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_50GB;
1768 sig_mode = BNXT_SIG_MODE_PAM4;
1769 }
1770 break;
1771 case SPEED_100000:
1772 if (support_spds & BNXT_LINK_SPEED_MSK_100GB) {
1773 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB;
1774 } else if (support_pam4_spds & BNXT_LINK_PAM4_SPEED_MSK_100GB) {
1775 fw_speed = PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_100GB;
1776 sig_mode = BNXT_SIG_MODE_PAM4;
1777 }
1778 break;
1779 case SPEED_200000:
1780 if (support_pam4_spds & BNXT_LINK_PAM4_SPEED_MSK_200GB) {
1781 fw_speed = PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_200GB;
1782 sig_mode = BNXT_SIG_MODE_PAM4;
1783 }
1784 break;
1785 }
1786
1787 if (!fw_speed) {
1788 netdev_err(dev, "unsupported speed!\n");
1789 return -EINVAL;
1790 }
1791
1792 if (link_info->req_link_speed == fw_speed &&
1793 link_info->req_signal_mode == sig_mode &&
1794 link_info->autoneg == 0)
1795 return -EALREADY;
1796
1797 link_info->req_link_speed = fw_speed;
1798 link_info->req_signal_mode = sig_mode;
1799 link_info->req_duplex = BNXT_LINK_DUPLEX_FULL;
1800 link_info->autoneg = 0;
1801 link_info->advertising = 0;
1802 link_info->advertising_pam4 = 0;
1803
1804 return 0;
1805 }
1806
bnxt_get_fw_auto_link_speeds(u32 advertising)1807 u16 bnxt_get_fw_auto_link_speeds(u32 advertising)
1808 {
1809 u16 fw_speed_mask = 0;
1810
1811 /* only support autoneg at speed 100, 1000, and 10000 */
1812 if (advertising & (ADVERTISED_100baseT_Full |
1813 ADVERTISED_100baseT_Half)) {
1814 fw_speed_mask |= BNXT_LINK_SPEED_MSK_100MB;
1815 }
1816 if (advertising & (ADVERTISED_1000baseT_Full |
1817 ADVERTISED_1000baseT_Half)) {
1818 fw_speed_mask |= BNXT_LINK_SPEED_MSK_1GB;
1819 }
1820 if (advertising & ADVERTISED_10000baseT_Full)
1821 fw_speed_mask |= BNXT_LINK_SPEED_MSK_10GB;
1822
1823 if (advertising & ADVERTISED_40000baseCR4_Full)
1824 fw_speed_mask |= BNXT_LINK_SPEED_MSK_40GB;
1825
1826 return fw_speed_mask;
1827 }
1828
bnxt_set_link_ksettings(struct net_device * dev,const struct ethtool_link_ksettings * lk_ksettings)1829 static int bnxt_set_link_ksettings(struct net_device *dev,
1830 const struct ethtool_link_ksettings *lk_ksettings)
1831 {
1832 struct bnxt *bp = netdev_priv(dev);
1833 struct bnxt_link_info *link_info = &bp->link_info;
1834 const struct ethtool_link_settings *base = &lk_ksettings->base;
1835 bool set_pause = false;
1836 u32 speed;
1837 int rc = 0;
1838
1839 if (!BNXT_PHY_CFG_ABLE(bp))
1840 return -EOPNOTSUPP;
1841
1842 mutex_lock(&bp->link_lock);
1843 if (base->autoneg == AUTONEG_ENABLE) {
1844 link_info->advertising = 0;
1845 link_info->advertising_pam4 = 0;
1846 BNXT_ETHTOOL_TO_FW_SPDS(link_info->advertising, lk_ksettings,
1847 advertising);
1848 BNXT_ETHTOOL_TO_FW_PAM4_SPDS(link_info->advertising_pam4,
1849 lk_ksettings, advertising);
1850 link_info->autoneg |= BNXT_AUTONEG_SPEED;
1851 if (!link_info->advertising && !link_info->advertising_pam4) {
1852 link_info->advertising = link_info->support_auto_speeds;
1853 link_info->advertising_pam4 =
1854 link_info->support_pam4_auto_speeds;
1855 }
1856 /* any change to autoneg will cause link change, therefore the
1857 * driver should put back the original pause setting in autoneg
1858 */
1859 set_pause = true;
1860 } else {
1861 u8 phy_type = link_info->phy_type;
1862
1863 if (phy_type == PORT_PHY_QCFG_RESP_PHY_TYPE_BASET ||
1864 phy_type == PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE ||
1865 link_info->media_type == PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP) {
1866 netdev_err(dev, "10GBase-T devices must autoneg\n");
1867 rc = -EINVAL;
1868 goto set_setting_exit;
1869 }
1870 if (base->duplex == DUPLEX_HALF) {
1871 netdev_err(dev, "HALF DUPLEX is not supported!\n");
1872 rc = -EINVAL;
1873 goto set_setting_exit;
1874 }
1875 speed = base->speed;
1876 rc = bnxt_force_link_speed(dev, speed);
1877 if (rc) {
1878 if (rc == -EALREADY)
1879 rc = 0;
1880 goto set_setting_exit;
1881 }
1882 }
1883
1884 if (netif_running(dev))
1885 rc = bnxt_hwrm_set_link_setting(bp, set_pause, false);
1886
1887 set_setting_exit:
1888 mutex_unlock(&bp->link_lock);
1889 return rc;
1890 }
1891
bnxt_get_fecparam(struct net_device * dev,struct ethtool_fecparam * fec)1892 static int bnxt_get_fecparam(struct net_device *dev,
1893 struct ethtool_fecparam *fec)
1894 {
1895 struct bnxt *bp = netdev_priv(dev);
1896 struct bnxt_link_info *link_info;
1897 u8 active_fec;
1898 u16 fec_cfg;
1899
1900 link_info = &bp->link_info;
1901 fec_cfg = link_info->fec_cfg;
1902 active_fec = link_info->active_fec_sig_mode &
1903 PORT_PHY_QCFG_RESP_ACTIVE_FEC_MASK;
1904 if (fec_cfg & BNXT_FEC_NONE) {
1905 fec->fec = ETHTOOL_FEC_NONE;
1906 fec->active_fec = ETHTOOL_FEC_NONE;
1907 return 0;
1908 }
1909 if (fec_cfg & BNXT_FEC_AUTONEG)
1910 fec->fec |= ETHTOOL_FEC_AUTO;
1911 if (fec_cfg & BNXT_FEC_ENC_BASE_R)
1912 fec->fec |= ETHTOOL_FEC_BASER;
1913 if (fec_cfg & BNXT_FEC_ENC_RS)
1914 fec->fec |= ETHTOOL_FEC_RS;
1915 if (fec_cfg & BNXT_FEC_ENC_LLRS)
1916 fec->fec |= ETHTOOL_FEC_LLRS;
1917
1918 switch (active_fec) {
1919 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE74_ACTIVE:
1920 fec->active_fec |= ETHTOOL_FEC_BASER;
1921 break;
1922 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE91_ACTIVE:
1923 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_1XN_ACTIVE:
1924 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_IEEE_ACTIVE:
1925 fec->active_fec |= ETHTOOL_FEC_RS;
1926 break;
1927 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_1XN_ACTIVE:
1928 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE:
1929 fec->active_fec |= ETHTOOL_FEC_LLRS;
1930 break;
1931 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_NONE_ACTIVE:
1932 fec->active_fec |= ETHTOOL_FEC_OFF;
1933 break;
1934 }
1935 return 0;
1936 }
1937
bnxt_ethtool_forced_fec_to_fw(struct bnxt_link_info * link_info,u32 fec)1938 static u32 bnxt_ethtool_forced_fec_to_fw(struct bnxt_link_info *link_info,
1939 u32 fec)
1940 {
1941 u32 fw_fec = PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE;
1942
1943 if (fec & ETHTOOL_FEC_BASER)
1944 fw_fec |= BNXT_FEC_BASE_R_ON(link_info);
1945 else if (fec & ETHTOOL_FEC_RS)
1946 fw_fec |= BNXT_FEC_RS_ON(link_info);
1947 else if (fec & ETHTOOL_FEC_LLRS)
1948 fw_fec |= BNXT_FEC_LLRS_ON;
1949 return fw_fec;
1950 }
1951
bnxt_set_fecparam(struct net_device * dev,struct ethtool_fecparam * fecparam)1952 static int bnxt_set_fecparam(struct net_device *dev,
1953 struct ethtool_fecparam *fecparam)
1954 {
1955 struct hwrm_port_phy_cfg_input req = {0};
1956 struct bnxt *bp = netdev_priv(dev);
1957 struct bnxt_link_info *link_info;
1958 u32 new_cfg, fec = fecparam->fec;
1959 u16 fec_cfg;
1960 int rc;
1961
1962 link_info = &bp->link_info;
1963 fec_cfg = link_info->fec_cfg;
1964 if (fec_cfg & BNXT_FEC_NONE)
1965 return -EOPNOTSUPP;
1966
1967 if (fec & ETHTOOL_FEC_OFF) {
1968 new_cfg = PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE |
1969 BNXT_FEC_ALL_OFF(link_info);
1970 goto apply_fec;
1971 }
1972 if (((fec & ETHTOOL_FEC_AUTO) && !(fec_cfg & BNXT_FEC_AUTONEG_CAP)) ||
1973 ((fec & ETHTOOL_FEC_RS) && !(fec_cfg & BNXT_FEC_ENC_RS_CAP)) ||
1974 ((fec & ETHTOOL_FEC_LLRS) && !(fec_cfg & BNXT_FEC_ENC_LLRS_CAP)) ||
1975 ((fec & ETHTOOL_FEC_BASER) && !(fec_cfg & BNXT_FEC_ENC_BASE_R_CAP)))
1976 return -EINVAL;
1977
1978 if (fec & ETHTOOL_FEC_AUTO) {
1979 if (!link_info->autoneg)
1980 return -EINVAL;
1981 new_cfg = PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_ENABLE;
1982 } else {
1983 new_cfg = bnxt_ethtool_forced_fec_to_fw(link_info, fec);
1984 }
1985
1986 apply_fec:
1987 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
1988 req.flags = cpu_to_le32(new_cfg | PORT_PHY_CFG_REQ_FLAGS_RESET_PHY);
1989 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
1990 /* update current settings */
1991 if (!rc) {
1992 mutex_lock(&bp->link_lock);
1993 bnxt_update_link(bp, false);
1994 mutex_unlock(&bp->link_lock);
1995 }
1996 return rc;
1997 }
1998
bnxt_get_pauseparam(struct net_device * dev,struct ethtool_pauseparam * epause)1999 static void bnxt_get_pauseparam(struct net_device *dev,
2000 struct ethtool_pauseparam *epause)
2001 {
2002 struct bnxt *bp = netdev_priv(dev);
2003 struct bnxt_link_info *link_info = &bp->link_info;
2004
2005 if (BNXT_VF(bp))
2006 return;
2007 epause->autoneg = !!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL);
2008 epause->rx_pause = !!(link_info->req_flow_ctrl & BNXT_LINK_PAUSE_RX);
2009 epause->tx_pause = !!(link_info->req_flow_ctrl & BNXT_LINK_PAUSE_TX);
2010 }
2011
bnxt_get_pause_stats(struct net_device * dev,struct ethtool_pause_stats * epstat)2012 static void bnxt_get_pause_stats(struct net_device *dev,
2013 struct ethtool_pause_stats *epstat)
2014 {
2015 struct bnxt *bp = netdev_priv(dev);
2016 u64 *rx, *tx;
2017
2018 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS))
2019 return;
2020
2021 rx = bp->port_stats.sw_stats;
2022 tx = bp->port_stats.sw_stats + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8;
2023
2024 epstat->rx_pause_frames = BNXT_GET_RX_PORT_STATS64(rx, rx_pause_frames);
2025 epstat->tx_pause_frames = BNXT_GET_TX_PORT_STATS64(tx, tx_pause_frames);
2026 }
2027
bnxt_set_pauseparam(struct net_device * dev,struct ethtool_pauseparam * epause)2028 static int bnxt_set_pauseparam(struct net_device *dev,
2029 struct ethtool_pauseparam *epause)
2030 {
2031 int rc = 0;
2032 struct bnxt *bp = netdev_priv(dev);
2033 struct bnxt_link_info *link_info = &bp->link_info;
2034
2035 if (!BNXT_PHY_CFG_ABLE(bp))
2036 return -EOPNOTSUPP;
2037
2038 mutex_lock(&bp->link_lock);
2039 if (epause->autoneg) {
2040 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
2041 rc = -EINVAL;
2042 goto pause_exit;
2043 }
2044
2045 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
2046 link_info->req_flow_ctrl = 0;
2047 } else {
2048 /* when transition from auto pause to force pause,
2049 * force a link change
2050 */
2051 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL)
2052 link_info->force_link_chng = true;
2053 link_info->autoneg &= ~BNXT_AUTONEG_FLOW_CTRL;
2054 link_info->req_flow_ctrl = 0;
2055 }
2056 if (epause->rx_pause)
2057 link_info->req_flow_ctrl |= BNXT_LINK_PAUSE_RX;
2058
2059 if (epause->tx_pause)
2060 link_info->req_flow_ctrl |= BNXT_LINK_PAUSE_TX;
2061
2062 if (netif_running(dev))
2063 rc = bnxt_hwrm_set_pause(bp);
2064
2065 pause_exit:
2066 mutex_unlock(&bp->link_lock);
2067 return rc;
2068 }
2069
bnxt_get_link(struct net_device * dev)2070 static u32 bnxt_get_link(struct net_device *dev)
2071 {
2072 struct bnxt *bp = netdev_priv(dev);
2073
2074 /* TODO: handle MF, VF, driver close case */
2075 return bp->link_info.link_up;
2076 }
2077
bnxt_hwrm_nvm_get_dev_info(struct bnxt * bp,struct hwrm_nvm_get_dev_info_output * nvm_dev_info)2078 int bnxt_hwrm_nvm_get_dev_info(struct bnxt *bp,
2079 struct hwrm_nvm_get_dev_info_output *nvm_dev_info)
2080 {
2081 struct hwrm_nvm_get_dev_info_output *resp = bp->hwrm_cmd_resp_addr;
2082 struct hwrm_nvm_get_dev_info_input req = {0};
2083 int rc;
2084
2085 if (BNXT_VF(bp))
2086 return -EOPNOTSUPP;
2087
2088 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_NVM_GET_DEV_INFO, -1, -1);
2089 mutex_lock(&bp->hwrm_cmd_lock);
2090 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2091 if (!rc)
2092 memcpy(nvm_dev_info, resp, sizeof(*resp));
2093 mutex_unlock(&bp->hwrm_cmd_lock);
2094 return rc;
2095 }
2096
bnxt_print_admin_err(struct bnxt * bp)2097 static void bnxt_print_admin_err(struct bnxt *bp)
2098 {
2099 netdev_info(bp->dev, "PF does not have admin privileges to flash or reset the device\n");
2100 }
2101
2102 static int bnxt_find_nvram_item(struct net_device *dev, u16 type, u16 ordinal,
2103 u16 ext, u16 *index, u32 *item_length,
2104 u32 *data_length);
2105
bnxt_flash_nvram(struct net_device * dev,u16 dir_type,u16 dir_ordinal,u16 dir_ext,u16 dir_attr,const u8 * data,size_t data_len)2106 static int bnxt_flash_nvram(struct net_device *dev,
2107 u16 dir_type,
2108 u16 dir_ordinal,
2109 u16 dir_ext,
2110 u16 dir_attr,
2111 const u8 *data,
2112 size_t data_len)
2113 {
2114 struct bnxt *bp = netdev_priv(dev);
2115 int rc;
2116 struct hwrm_nvm_write_input req = {0};
2117 dma_addr_t dma_handle;
2118 u8 *kmem;
2119
2120 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_NVM_WRITE, -1, -1);
2121
2122 req.dir_type = cpu_to_le16(dir_type);
2123 req.dir_ordinal = cpu_to_le16(dir_ordinal);
2124 req.dir_ext = cpu_to_le16(dir_ext);
2125 req.dir_attr = cpu_to_le16(dir_attr);
2126 req.dir_data_length = cpu_to_le32(data_len);
2127
2128 kmem = dma_alloc_coherent(&bp->pdev->dev, data_len, &dma_handle,
2129 GFP_KERNEL);
2130 if (!kmem) {
2131 netdev_err(dev, "dma_alloc_coherent failure, length = %u\n",
2132 (unsigned)data_len);
2133 return -ENOMEM;
2134 }
2135 memcpy(kmem, data, data_len);
2136 req.host_src_addr = cpu_to_le64(dma_handle);
2137
2138 rc = hwrm_send_message(bp, &req, sizeof(req), FLASH_NVRAM_TIMEOUT);
2139 dma_free_coherent(&bp->pdev->dev, data_len, kmem, dma_handle);
2140
2141 if (rc == -EACCES)
2142 bnxt_print_admin_err(bp);
2143 return rc;
2144 }
2145
bnxt_hwrm_firmware_reset(struct net_device * dev,u8 proc_type,u8 self_reset,u8 flags)2146 static int bnxt_hwrm_firmware_reset(struct net_device *dev, u8 proc_type,
2147 u8 self_reset, u8 flags)
2148 {
2149 struct hwrm_fw_reset_input req = {0};
2150 struct bnxt *bp = netdev_priv(dev);
2151 int rc;
2152
2153 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FW_RESET, -1, -1);
2154
2155 req.embedded_proc_type = proc_type;
2156 req.selfrst_status = self_reset;
2157 req.flags = flags;
2158
2159 if (proc_type == FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP) {
2160 rc = hwrm_send_message_silent(bp, &req, sizeof(req),
2161 HWRM_CMD_TIMEOUT);
2162 } else {
2163 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2164 if (rc == -EACCES)
2165 bnxt_print_admin_err(bp);
2166 }
2167 return rc;
2168 }
2169
bnxt_firmware_reset(struct net_device * dev,enum bnxt_nvm_directory_type dir_type)2170 static int bnxt_firmware_reset(struct net_device *dev,
2171 enum bnxt_nvm_directory_type dir_type)
2172 {
2173 u8 self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE;
2174 u8 proc_type, flags = 0;
2175
2176 /* TODO: Address self-reset of APE/KONG/BONO/TANG or ungraceful reset */
2177 /* (e.g. when firmware isn't already running) */
2178 switch (dir_type) {
2179 case BNX_DIR_TYPE_CHIMP_PATCH:
2180 case BNX_DIR_TYPE_BOOTCODE:
2181 case BNX_DIR_TYPE_BOOTCODE_2:
2182 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT;
2183 /* Self-reset ChiMP upon next PCIe reset: */
2184 self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST;
2185 break;
2186 case BNX_DIR_TYPE_APE_FW:
2187 case BNX_DIR_TYPE_APE_PATCH:
2188 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT;
2189 /* Self-reset APE upon next PCIe reset: */
2190 self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST;
2191 break;
2192 case BNX_DIR_TYPE_KONG_FW:
2193 case BNX_DIR_TYPE_KONG_PATCH:
2194 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL;
2195 break;
2196 case BNX_DIR_TYPE_BONO_FW:
2197 case BNX_DIR_TYPE_BONO_PATCH:
2198 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE;
2199 break;
2200 default:
2201 return -EINVAL;
2202 }
2203
2204 return bnxt_hwrm_firmware_reset(dev, proc_type, self_reset, flags);
2205 }
2206
bnxt_firmware_reset_chip(struct net_device * dev)2207 static int bnxt_firmware_reset_chip(struct net_device *dev)
2208 {
2209 struct bnxt *bp = netdev_priv(dev);
2210 u8 flags = 0;
2211
2212 if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET)
2213 flags = FW_RESET_REQ_FLAGS_RESET_GRACEFUL;
2214
2215 return bnxt_hwrm_firmware_reset(dev,
2216 FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP,
2217 FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP,
2218 flags);
2219 }
2220
bnxt_firmware_reset_ap(struct net_device * dev)2221 static int bnxt_firmware_reset_ap(struct net_device *dev)
2222 {
2223 return bnxt_hwrm_firmware_reset(dev, FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP,
2224 FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE,
2225 0);
2226 }
2227
bnxt_flash_firmware(struct net_device * dev,u16 dir_type,const u8 * fw_data,size_t fw_size)2228 static int bnxt_flash_firmware(struct net_device *dev,
2229 u16 dir_type,
2230 const u8 *fw_data,
2231 size_t fw_size)
2232 {
2233 int rc = 0;
2234 u16 code_type;
2235 u32 stored_crc;
2236 u32 calculated_crc;
2237 struct bnxt_fw_header *header = (struct bnxt_fw_header *)fw_data;
2238
2239 switch (dir_type) {
2240 case BNX_DIR_TYPE_BOOTCODE:
2241 case BNX_DIR_TYPE_BOOTCODE_2:
2242 code_type = CODE_BOOT;
2243 break;
2244 case BNX_DIR_TYPE_CHIMP_PATCH:
2245 code_type = CODE_CHIMP_PATCH;
2246 break;
2247 case BNX_DIR_TYPE_APE_FW:
2248 code_type = CODE_MCTP_PASSTHRU;
2249 break;
2250 case BNX_DIR_TYPE_APE_PATCH:
2251 code_type = CODE_APE_PATCH;
2252 break;
2253 case BNX_DIR_TYPE_KONG_FW:
2254 code_type = CODE_KONG_FW;
2255 break;
2256 case BNX_DIR_TYPE_KONG_PATCH:
2257 code_type = CODE_KONG_PATCH;
2258 break;
2259 case BNX_DIR_TYPE_BONO_FW:
2260 code_type = CODE_BONO_FW;
2261 break;
2262 case BNX_DIR_TYPE_BONO_PATCH:
2263 code_type = CODE_BONO_PATCH;
2264 break;
2265 default:
2266 netdev_err(dev, "Unsupported directory entry type: %u\n",
2267 dir_type);
2268 return -EINVAL;
2269 }
2270 if (fw_size < sizeof(struct bnxt_fw_header)) {
2271 netdev_err(dev, "Invalid firmware file size: %u\n",
2272 (unsigned int)fw_size);
2273 return -EINVAL;
2274 }
2275 if (header->signature != cpu_to_le32(BNXT_FIRMWARE_BIN_SIGNATURE)) {
2276 netdev_err(dev, "Invalid firmware signature: %08X\n",
2277 le32_to_cpu(header->signature));
2278 return -EINVAL;
2279 }
2280 if (header->code_type != code_type) {
2281 netdev_err(dev, "Expected firmware type: %d, read: %d\n",
2282 code_type, header->code_type);
2283 return -EINVAL;
2284 }
2285 if (header->device != DEVICE_CUMULUS_FAMILY) {
2286 netdev_err(dev, "Expected firmware device family %d, read: %d\n",
2287 DEVICE_CUMULUS_FAMILY, header->device);
2288 return -EINVAL;
2289 }
2290 /* Confirm the CRC32 checksum of the file: */
2291 stored_crc = le32_to_cpu(*(__le32 *)(fw_data + fw_size -
2292 sizeof(stored_crc)));
2293 calculated_crc = ~crc32(~0, fw_data, fw_size - sizeof(stored_crc));
2294 if (calculated_crc != stored_crc) {
2295 netdev_err(dev, "Firmware file CRC32 checksum (%08lX) does not match calculated checksum (%08lX)\n",
2296 (unsigned long)stored_crc,
2297 (unsigned long)calculated_crc);
2298 return -EINVAL;
2299 }
2300 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST,
2301 0, 0, fw_data, fw_size);
2302 if (rc == 0) /* Firmware update successful */
2303 rc = bnxt_firmware_reset(dev, dir_type);
2304
2305 return rc;
2306 }
2307
bnxt_flash_microcode(struct net_device * dev,u16 dir_type,const u8 * fw_data,size_t fw_size)2308 static int bnxt_flash_microcode(struct net_device *dev,
2309 u16 dir_type,
2310 const u8 *fw_data,
2311 size_t fw_size)
2312 {
2313 struct bnxt_ucode_trailer *trailer;
2314 u32 calculated_crc;
2315 u32 stored_crc;
2316 int rc = 0;
2317
2318 if (fw_size < sizeof(struct bnxt_ucode_trailer)) {
2319 netdev_err(dev, "Invalid microcode file size: %u\n",
2320 (unsigned int)fw_size);
2321 return -EINVAL;
2322 }
2323 trailer = (struct bnxt_ucode_trailer *)(fw_data + (fw_size -
2324 sizeof(*trailer)));
2325 if (trailer->sig != cpu_to_le32(BNXT_UCODE_TRAILER_SIGNATURE)) {
2326 netdev_err(dev, "Invalid microcode trailer signature: %08X\n",
2327 le32_to_cpu(trailer->sig));
2328 return -EINVAL;
2329 }
2330 if (le16_to_cpu(trailer->dir_type) != dir_type) {
2331 netdev_err(dev, "Expected microcode type: %d, read: %d\n",
2332 dir_type, le16_to_cpu(trailer->dir_type));
2333 return -EINVAL;
2334 }
2335 if (le16_to_cpu(trailer->trailer_length) <
2336 sizeof(struct bnxt_ucode_trailer)) {
2337 netdev_err(dev, "Invalid microcode trailer length: %d\n",
2338 le16_to_cpu(trailer->trailer_length));
2339 return -EINVAL;
2340 }
2341
2342 /* Confirm the CRC32 checksum of the file: */
2343 stored_crc = le32_to_cpu(*(__le32 *)(fw_data + fw_size -
2344 sizeof(stored_crc)));
2345 calculated_crc = ~crc32(~0, fw_data, fw_size - sizeof(stored_crc));
2346 if (calculated_crc != stored_crc) {
2347 netdev_err(dev,
2348 "CRC32 (%08lX) does not match calculated: %08lX\n",
2349 (unsigned long)stored_crc,
2350 (unsigned long)calculated_crc);
2351 return -EINVAL;
2352 }
2353 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST,
2354 0, 0, fw_data, fw_size);
2355
2356 return rc;
2357 }
2358
bnxt_dir_type_is_ape_bin_format(u16 dir_type)2359 static bool bnxt_dir_type_is_ape_bin_format(u16 dir_type)
2360 {
2361 switch (dir_type) {
2362 case BNX_DIR_TYPE_CHIMP_PATCH:
2363 case BNX_DIR_TYPE_BOOTCODE:
2364 case BNX_DIR_TYPE_BOOTCODE_2:
2365 case BNX_DIR_TYPE_APE_FW:
2366 case BNX_DIR_TYPE_APE_PATCH:
2367 case BNX_DIR_TYPE_KONG_FW:
2368 case BNX_DIR_TYPE_KONG_PATCH:
2369 case BNX_DIR_TYPE_BONO_FW:
2370 case BNX_DIR_TYPE_BONO_PATCH:
2371 return true;
2372 }
2373
2374 return false;
2375 }
2376
bnxt_dir_type_is_other_exec_format(u16 dir_type)2377 static bool bnxt_dir_type_is_other_exec_format(u16 dir_type)
2378 {
2379 switch (dir_type) {
2380 case BNX_DIR_TYPE_AVS:
2381 case BNX_DIR_TYPE_EXP_ROM_MBA:
2382 case BNX_DIR_TYPE_PCIE:
2383 case BNX_DIR_TYPE_TSCF_UCODE:
2384 case BNX_DIR_TYPE_EXT_PHY:
2385 case BNX_DIR_TYPE_CCM:
2386 case BNX_DIR_TYPE_ISCSI_BOOT:
2387 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
2388 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
2389 return true;
2390 }
2391
2392 return false;
2393 }
2394
bnxt_dir_type_is_executable(u16 dir_type)2395 static bool bnxt_dir_type_is_executable(u16 dir_type)
2396 {
2397 return bnxt_dir_type_is_ape_bin_format(dir_type) ||
2398 bnxt_dir_type_is_other_exec_format(dir_type);
2399 }
2400
bnxt_flash_firmware_from_file(struct net_device * dev,u16 dir_type,const char * filename)2401 static int bnxt_flash_firmware_from_file(struct net_device *dev,
2402 u16 dir_type,
2403 const char *filename)
2404 {
2405 const struct firmware *fw;
2406 int rc;
2407
2408 rc = request_firmware(&fw, filename, &dev->dev);
2409 if (rc != 0) {
2410 netdev_err(dev, "Error %d requesting firmware file: %s\n",
2411 rc, filename);
2412 return rc;
2413 }
2414 if (bnxt_dir_type_is_ape_bin_format(dir_type))
2415 rc = bnxt_flash_firmware(dev, dir_type, fw->data, fw->size);
2416 else if (bnxt_dir_type_is_other_exec_format(dir_type))
2417 rc = bnxt_flash_microcode(dev, dir_type, fw->data, fw->size);
2418 else
2419 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST,
2420 0, 0, fw->data, fw->size);
2421 release_firmware(fw);
2422 return rc;
2423 }
2424
bnxt_flash_package_from_file(struct net_device * dev,const char * filename,u32 install_type)2425 int bnxt_flash_package_from_file(struct net_device *dev, const char *filename,
2426 u32 install_type)
2427 {
2428 struct bnxt *bp = netdev_priv(dev);
2429 struct hwrm_nvm_install_update_output *resp = bp->hwrm_cmd_resp_addr;
2430 struct hwrm_nvm_install_update_input install = {0};
2431 const struct firmware *fw;
2432 u32 item_len;
2433 int rc = 0;
2434 u16 index;
2435
2436 bnxt_hwrm_fw_set_time(bp);
2437
2438 rc = bnxt_find_nvram_item(dev, BNX_DIR_TYPE_UPDATE,
2439 BNX_DIR_ORDINAL_FIRST, BNX_DIR_EXT_NONE,
2440 &index, &item_len, NULL);
2441 if (rc) {
2442 netdev_err(dev, "PKG update area not created in nvram\n");
2443 return rc;
2444 }
2445
2446 rc = request_firmware(&fw, filename, &dev->dev);
2447 if (rc != 0) {
2448 netdev_err(dev, "PKG error %d requesting file: %s\n",
2449 rc, filename);
2450 return rc;
2451 }
2452
2453 if (fw->size > item_len) {
2454 netdev_err(dev, "PKG insufficient update area in nvram: %lu\n",
2455 (unsigned long)fw->size);
2456 rc = -EFBIG;
2457 } else {
2458 dma_addr_t dma_handle;
2459 u8 *kmem;
2460 struct hwrm_nvm_modify_input modify = {0};
2461
2462 bnxt_hwrm_cmd_hdr_init(bp, &modify, HWRM_NVM_MODIFY, -1, -1);
2463
2464 modify.dir_idx = cpu_to_le16(index);
2465 modify.len = cpu_to_le32(fw->size);
2466
2467 kmem = dma_alloc_coherent(&bp->pdev->dev, fw->size,
2468 &dma_handle, GFP_KERNEL);
2469 if (!kmem) {
2470 netdev_err(dev,
2471 "dma_alloc_coherent failure, length = %u\n",
2472 (unsigned int)fw->size);
2473 rc = -ENOMEM;
2474 } else {
2475 memcpy(kmem, fw->data, fw->size);
2476 modify.host_src_addr = cpu_to_le64(dma_handle);
2477
2478 rc = hwrm_send_message(bp, &modify, sizeof(modify),
2479 FLASH_PACKAGE_TIMEOUT);
2480 dma_free_coherent(&bp->pdev->dev, fw->size, kmem,
2481 dma_handle);
2482 }
2483 }
2484 release_firmware(fw);
2485 if (rc)
2486 goto err_exit;
2487
2488 if ((install_type & 0xffff) == 0)
2489 install_type >>= 16;
2490 bnxt_hwrm_cmd_hdr_init(bp, &install, HWRM_NVM_INSTALL_UPDATE, -1, -1);
2491 install.install_type = cpu_to_le32(install_type);
2492
2493 mutex_lock(&bp->hwrm_cmd_lock);
2494 rc = _hwrm_send_message(bp, &install, sizeof(install),
2495 INSTALL_PACKAGE_TIMEOUT);
2496 if (rc) {
2497 u8 error_code = ((struct hwrm_err_output *)resp)->cmd_err;
2498
2499 if (resp->error_code && error_code ==
2500 NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR) {
2501 install.flags |= cpu_to_le16(
2502 NVM_INSTALL_UPDATE_REQ_FLAGS_ALLOWED_TO_DEFRAG);
2503 rc = _hwrm_send_message(bp, &install, sizeof(install),
2504 INSTALL_PACKAGE_TIMEOUT);
2505 }
2506 if (rc)
2507 goto flash_pkg_exit;
2508 }
2509
2510 if (resp->result) {
2511 netdev_err(dev, "PKG install error = %d, problem_item = %d\n",
2512 (s8)resp->result, (int)resp->problem_item);
2513 rc = -ENOPKG;
2514 }
2515 flash_pkg_exit:
2516 mutex_unlock(&bp->hwrm_cmd_lock);
2517 err_exit:
2518 if (rc == -EACCES)
2519 bnxt_print_admin_err(bp);
2520 return rc;
2521 }
2522
bnxt_flash_device(struct net_device * dev,struct ethtool_flash * flash)2523 static int bnxt_flash_device(struct net_device *dev,
2524 struct ethtool_flash *flash)
2525 {
2526 if (!BNXT_PF((struct bnxt *)netdev_priv(dev))) {
2527 netdev_err(dev, "flashdev not supported from a virtual function\n");
2528 return -EINVAL;
2529 }
2530
2531 if (flash->region == ETHTOOL_FLASH_ALL_REGIONS ||
2532 flash->region > 0xffff)
2533 return bnxt_flash_package_from_file(dev, flash->data,
2534 flash->region);
2535
2536 return bnxt_flash_firmware_from_file(dev, flash->region, flash->data);
2537 }
2538
nvm_get_dir_info(struct net_device * dev,u32 * entries,u32 * length)2539 static int nvm_get_dir_info(struct net_device *dev, u32 *entries, u32 *length)
2540 {
2541 struct bnxt *bp = netdev_priv(dev);
2542 int rc;
2543 struct hwrm_nvm_get_dir_info_input req = {0};
2544 struct hwrm_nvm_get_dir_info_output *output = bp->hwrm_cmd_resp_addr;
2545
2546 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_NVM_GET_DIR_INFO, -1, -1);
2547
2548 mutex_lock(&bp->hwrm_cmd_lock);
2549 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2550 if (!rc) {
2551 *entries = le32_to_cpu(output->entries);
2552 *length = le32_to_cpu(output->entry_length);
2553 }
2554 mutex_unlock(&bp->hwrm_cmd_lock);
2555 return rc;
2556 }
2557
bnxt_get_eeprom_len(struct net_device * dev)2558 static int bnxt_get_eeprom_len(struct net_device *dev)
2559 {
2560 struct bnxt *bp = netdev_priv(dev);
2561
2562 if (BNXT_VF(bp))
2563 return 0;
2564
2565 /* The -1 return value allows the entire 32-bit range of offsets to be
2566 * passed via the ethtool command-line utility.
2567 */
2568 return -1;
2569 }
2570
bnxt_get_nvram_directory(struct net_device * dev,u32 len,u8 * data)2571 static int bnxt_get_nvram_directory(struct net_device *dev, u32 len, u8 *data)
2572 {
2573 struct bnxt *bp = netdev_priv(dev);
2574 int rc;
2575 u32 dir_entries;
2576 u32 entry_length;
2577 u8 *buf;
2578 size_t buflen;
2579 dma_addr_t dma_handle;
2580 struct hwrm_nvm_get_dir_entries_input req = {0};
2581
2582 rc = nvm_get_dir_info(dev, &dir_entries, &entry_length);
2583 if (rc != 0)
2584 return rc;
2585
2586 if (!dir_entries || !entry_length)
2587 return -EIO;
2588
2589 /* Insert 2 bytes of directory info (count and size of entries) */
2590 if (len < 2)
2591 return -EINVAL;
2592
2593 *data++ = dir_entries;
2594 *data++ = entry_length;
2595 len -= 2;
2596 memset(data, 0xff, len);
2597
2598 buflen = dir_entries * entry_length;
2599 buf = dma_alloc_coherent(&bp->pdev->dev, buflen, &dma_handle,
2600 GFP_KERNEL);
2601 if (!buf) {
2602 netdev_err(dev, "dma_alloc_coherent failure, length = %u\n",
2603 (unsigned)buflen);
2604 return -ENOMEM;
2605 }
2606 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_NVM_GET_DIR_ENTRIES, -1, -1);
2607 req.host_dest_addr = cpu_to_le64(dma_handle);
2608 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2609 if (rc == 0)
2610 memcpy(data, buf, len > buflen ? buflen : len);
2611 dma_free_coherent(&bp->pdev->dev, buflen, buf, dma_handle);
2612 return rc;
2613 }
2614
bnxt_get_nvram_item(struct net_device * dev,u32 index,u32 offset,u32 length,u8 * data)2615 static int bnxt_get_nvram_item(struct net_device *dev, u32 index, u32 offset,
2616 u32 length, u8 *data)
2617 {
2618 struct bnxt *bp = netdev_priv(dev);
2619 int rc;
2620 u8 *buf;
2621 dma_addr_t dma_handle;
2622 struct hwrm_nvm_read_input req = {0};
2623
2624 if (!length)
2625 return -EINVAL;
2626
2627 buf = dma_alloc_coherent(&bp->pdev->dev, length, &dma_handle,
2628 GFP_KERNEL);
2629 if (!buf) {
2630 netdev_err(dev, "dma_alloc_coherent failure, length = %u\n",
2631 (unsigned)length);
2632 return -ENOMEM;
2633 }
2634 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_NVM_READ, -1, -1);
2635 req.host_dest_addr = cpu_to_le64(dma_handle);
2636 req.dir_idx = cpu_to_le16(index);
2637 req.offset = cpu_to_le32(offset);
2638 req.len = cpu_to_le32(length);
2639
2640 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2641 if (rc == 0)
2642 memcpy(data, buf, length);
2643 dma_free_coherent(&bp->pdev->dev, length, buf, dma_handle);
2644 return rc;
2645 }
2646
bnxt_find_nvram_item(struct net_device * dev,u16 type,u16 ordinal,u16 ext,u16 * index,u32 * item_length,u32 * data_length)2647 static int bnxt_find_nvram_item(struct net_device *dev, u16 type, u16 ordinal,
2648 u16 ext, u16 *index, u32 *item_length,
2649 u32 *data_length)
2650 {
2651 struct bnxt *bp = netdev_priv(dev);
2652 int rc;
2653 struct hwrm_nvm_find_dir_entry_input req = {0};
2654 struct hwrm_nvm_find_dir_entry_output *output = bp->hwrm_cmd_resp_addr;
2655
2656 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_NVM_FIND_DIR_ENTRY, -1, -1);
2657 req.enables = 0;
2658 req.dir_idx = 0;
2659 req.dir_type = cpu_to_le16(type);
2660 req.dir_ordinal = cpu_to_le16(ordinal);
2661 req.dir_ext = cpu_to_le16(ext);
2662 req.opt_ordinal = NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_EQ;
2663 mutex_lock(&bp->hwrm_cmd_lock);
2664 rc = _hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2665 if (rc == 0) {
2666 if (index)
2667 *index = le16_to_cpu(output->dir_idx);
2668 if (item_length)
2669 *item_length = le32_to_cpu(output->dir_item_length);
2670 if (data_length)
2671 *data_length = le32_to_cpu(output->dir_data_length);
2672 }
2673 mutex_unlock(&bp->hwrm_cmd_lock);
2674 return rc;
2675 }
2676
bnxt_parse_pkglog(int desired_field,u8 * data,size_t datalen)2677 static char *bnxt_parse_pkglog(int desired_field, u8 *data, size_t datalen)
2678 {
2679 char *retval = NULL;
2680 char *p;
2681 char *value;
2682 int field = 0;
2683
2684 if (datalen < 1)
2685 return NULL;
2686 /* null-terminate the log data (removing last '\n'): */
2687 data[datalen - 1] = 0;
2688 for (p = data; *p != 0; p++) {
2689 field = 0;
2690 retval = NULL;
2691 while (*p != 0 && *p != '\n') {
2692 value = p;
2693 while (*p != 0 && *p != '\t' && *p != '\n')
2694 p++;
2695 if (field == desired_field)
2696 retval = value;
2697 if (*p != '\t')
2698 break;
2699 *p = 0;
2700 field++;
2701 p++;
2702 }
2703 if (*p == 0)
2704 break;
2705 *p = 0;
2706 }
2707 return retval;
2708 }
2709
bnxt_get_pkgver(struct net_device * dev)2710 static void bnxt_get_pkgver(struct net_device *dev)
2711 {
2712 struct bnxt *bp = netdev_priv(dev);
2713 u16 index = 0;
2714 char *pkgver;
2715 u32 pkglen;
2716 u8 *pkgbuf;
2717 int len;
2718
2719 if (bnxt_find_nvram_item(dev, BNX_DIR_TYPE_PKG_LOG,
2720 BNX_DIR_ORDINAL_FIRST, BNX_DIR_EXT_NONE,
2721 &index, NULL, &pkglen) != 0)
2722 return;
2723
2724 pkgbuf = kzalloc(pkglen, GFP_KERNEL);
2725 if (!pkgbuf) {
2726 dev_err(&bp->pdev->dev, "Unable to allocate memory for pkg version, length = %u\n",
2727 pkglen);
2728 return;
2729 }
2730
2731 if (bnxt_get_nvram_item(dev, index, 0, pkglen, pkgbuf))
2732 goto err;
2733
2734 pkgver = bnxt_parse_pkglog(BNX_PKG_LOG_FIELD_IDX_PKG_VERSION, pkgbuf,
2735 pkglen);
2736 if (pkgver && *pkgver != 0 && isdigit(*pkgver)) {
2737 len = strlen(bp->fw_ver_str);
2738 snprintf(bp->fw_ver_str + len, FW_VER_STR_LEN - len - 1,
2739 "/pkg %s", pkgver);
2740 }
2741 err:
2742 kfree(pkgbuf);
2743 }
2744
bnxt_get_eeprom(struct net_device * dev,struct ethtool_eeprom * eeprom,u8 * data)2745 static int bnxt_get_eeprom(struct net_device *dev,
2746 struct ethtool_eeprom *eeprom,
2747 u8 *data)
2748 {
2749 u32 index;
2750 u32 offset;
2751
2752 if (eeprom->offset == 0) /* special offset value to get directory */
2753 return bnxt_get_nvram_directory(dev, eeprom->len, data);
2754
2755 index = eeprom->offset >> 24;
2756 offset = eeprom->offset & 0xffffff;
2757
2758 if (index == 0) {
2759 netdev_err(dev, "unsupported index value: %d\n", index);
2760 return -EINVAL;
2761 }
2762
2763 return bnxt_get_nvram_item(dev, index - 1, offset, eeprom->len, data);
2764 }
2765
bnxt_erase_nvram_directory(struct net_device * dev,u8 index)2766 static int bnxt_erase_nvram_directory(struct net_device *dev, u8 index)
2767 {
2768 struct bnxt *bp = netdev_priv(dev);
2769 struct hwrm_nvm_erase_dir_entry_input req = {0};
2770
2771 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_NVM_ERASE_DIR_ENTRY, -1, -1);
2772 req.dir_idx = cpu_to_le16(index);
2773 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2774 }
2775
bnxt_set_eeprom(struct net_device * dev,struct ethtool_eeprom * eeprom,u8 * data)2776 static int bnxt_set_eeprom(struct net_device *dev,
2777 struct ethtool_eeprom *eeprom,
2778 u8 *data)
2779 {
2780 struct bnxt *bp = netdev_priv(dev);
2781 u8 index, dir_op;
2782 u16 type, ext, ordinal, attr;
2783
2784 if (!BNXT_PF(bp)) {
2785 netdev_err(dev, "NVM write not supported from a virtual function\n");
2786 return -EINVAL;
2787 }
2788
2789 type = eeprom->magic >> 16;
2790
2791 if (type == 0xffff) { /* special value for directory operations */
2792 index = eeprom->magic & 0xff;
2793 dir_op = eeprom->magic >> 8;
2794 if (index == 0)
2795 return -EINVAL;
2796 switch (dir_op) {
2797 case 0x0e: /* erase */
2798 if (eeprom->offset != ~eeprom->magic)
2799 return -EINVAL;
2800 return bnxt_erase_nvram_directory(dev, index - 1);
2801 default:
2802 return -EINVAL;
2803 }
2804 }
2805
2806 /* Create or re-write an NVM item: */
2807 if (bnxt_dir_type_is_executable(type))
2808 return -EOPNOTSUPP;
2809 ext = eeprom->magic & 0xffff;
2810 ordinal = eeprom->offset >> 16;
2811 attr = eeprom->offset & 0xffff;
2812
2813 return bnxt_flash_nvram(dev, type, ordinal, ext, attr, data,
2814 eeprom->len);
2815 }
2816
bnxt_set_eee(struct net_device * dev,struct ethtool_eee * edata)2817 static int bnxt_set_eee(struct net_device *dev, struct ethtool_eee *edata)
2818 {
2819 struct bnxt *bp = netdev_priv(dev);
2820 struct ethtool_eee *eee = &bp->eee;
2821 struct bnxt_link_info *link_info = &bp->link_info;
2822 u32 advertising;
2823 int rc = 0;
2824
2825 if (!BNXT_PHY_CFG_ABLE(bp))
2826 return -EOPNOTSUPP;
2827
2828 if (!(bp->flags & BNXT_FLAG_EEE_CAP))
2829 return -EOPNOTSUPP;
2830
2831 mutex_lock(&bp->link_lock);
2832 advertising = _bnxt_fw_to_ethtool_adv_spds(link_info->advertising, 0);
2833 if (!edata->eee_enabled)
2834 goto eee_ok;
2835
2836 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
2837 netdev_warn(dev, "EEE requires autoneg\n");
2838 rc = -EINVAL;
2839 goto eee_exit;
2840 }
2841 if (edata->tx_lpi_enabled) {
2842 if (bp->lpi_tmr_hi && (edata->tx_lpi_timer > bp->lpi_tmr_hi ||
2843 edata->tx_lpi_timer < bp->lpi_tmr_lo)) {
2844 netdev_warn(dev, "Valid LPI timer range is %d and %d microsecs\n",
2845 bp->lpi_tmr_lo, bp->lpi_tmr_hi);
2846 rc = -EINVAL;
2847 goto eee_exit;
2848 } else if (!bp->lpi_tmr_hi) {
2849 edata->tx_lpi_timer = eee->tx_lpi_timer;
2850 }
2851 }
2852 if (!edata->advertised) {
2853 edata->advertised = advertising & eee->supported;
2854 } else if (edata->advertised & ~advertising) {
2855 netdev_warn(dev, "EEE advertised %x must be a subset of autoneg advertised speeds %x\n",
2856 edata->advertised, advertising);
2857 rc = -EINVAL;
2858 goto eee_exit;
2859 }
2860
2861 eee->advertised = edata->advertised;
2862 eee->tx_lpi_enabled = edata->tx_lpi_enabled;
2863 eee->tx_lpi_timer = edata->tx_lpi_timer;
2864 eee_ok:
2865 eee->eee_enabled = edata->eee_enabled;
2866
2867 if (netif_running(dev))
2868 rc = bnxt_hwrm_set_link_setting(bp, false, true);
2869
2870 eee_exit:
2871 mutex_unlock(&bp->link_lock);
2872 return rc;
2873 }
2874
bnxt_get_eee(struct net_device * dev,struct ethtool_eee * edata)2875 static int bnxt_get_eee(struct net_device *dev, struct ethtool_eee *edata)
2876 {
2877 struct bnxt *bp = netdev_priv(dev);
2878
2879 if (!(bp->flags & BNXT_FLAG_EEE_CAP))
2880 return -EOPNOTSUPP;
2881
2882 *edata = bp->eee;
2883 if (!bp->eee.eee_enabled) {
2884 /* Preserve tx_lpi_timer so that the last value will be used
2885 * by default when it is re-enabled.
2886 */
2887 edata->advertised = 0;
2888 edata->tx_lpi_enabled = 0;
2889 }
2890
2891 if (!bp->eee.eee_active)
2892 edata->lp_advertised = 0;
2893
2894 return 0;
2895 }
2896
bnxt_read_sfp_module_eeprom_info(struct bnxt * bp,u16 i2c_addr,u16 page_number,u16 start_addr,u16 data_length,u8 * buf)2897 static int bnxt_read_sfp_module_eeprom_info(struct bnxt *bp, u16 i2c_addr,
2898 u16 page_number, u16 start_addr,
2899 u16 data_length, u8 *buf)
2900 {
2901 struct hwrm_port_phy_i2c_read_input req = {0};
2902 struct hwrm_port_phy_i2c_read_output *output = bp->hwrm_cmd_resp_addr;
2903 int rc, byte_offset = 0;
2904
2905 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_I2C_READ, -1, -1);
2906 req.i2c_slave_addr = i2c_addr;
2907 req.page_number = cpu_to_le16(page_number);
2908 req.port_id = cpu_to_le16(bp->pf.port_id);
2909 do {
2910 u16 xfer_size;
2911
2912 xfer_size = min_t(u16, data_length, BNXT_MAX_PHY_I2C_RESP_SIZE);
2913 data_length -= xfer_size;
2914 req.page_offset = cpu_to_le16(start_addr + byte_offset);
2915 req.data_length = xfer_size;
2916 req.enables = cpu_to_le32(start_addr + byte_offset ?
2917 PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET : 0);
2918 mutex_lock(&bp->hwrm_cmd_lock);
2919 rc = _hwrm_send_message(bp, &req, sizeof(req),
2920 HWRM_CMD_TIMEOUT);
2921 if (!rc)
2922 memcpy(buf + byte_offset, output->data, xfer_size);
2923 mutex_unlock(&bp->hwrm_cmd_lock);
2924 byte_offset += xfer_size;
2925 } while (!rc && data_length > 0);
2926
2927 return rc;
2928 }
2929
bnxt_get_module_info(struct net_device * dev,struct ethtool_modinfo * modinfo)2930 static int bnxt_get_module_info(struct net_device *dev,
2931 struct ethtool_modinfo *modinfo)
2932 {
2933 u8 data[SFF_DIAG_SUPPORT_OFFSET + 1];
2934 struct bnxt *bp = netdev_priv(dev);
2935 int rc;
2936
2937 /* No point in going further if phy status indicates
2938 * module is not inserted or if it is powered down or
2939 * if it is of type 10GBase-T
2940 */
2941 if (bp->link_info.module_status >
2942 PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG)
2943 return -EOPNOTSUPP;
2944
2945 /* This feature is not supported in older firmware versions */
2946 if (bp->hwrm_spec_code < 0x10202)
2947 return -EOPNOTSUPP;
2948
2949 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0,
2950 SFF_DIAG_SUPPORT_OFFSET + 1,
2951 data);
2952 if (!rc) {
2953 u8 module_id = data[0];
2954 u8 diag_supported = data[SFF_DIAG_SUPPORT_OFFSET];
2955
2956 switch (module_id) {
2957 case SFF_MODULE_ID_SFP:
2958 modinfo->type = ETH_MODULE_SFF_8472;
2959 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
2960 if (!diag_supported)
2961 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
2962 break;
2963 case SFF_MODULE_ID_QSFP:
2964 case SFF_MODULE_ID_QSFP_PLUS:
2965 modinfo->type = ETH_MODULE_SFF_8436;
2966 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
2967 break;
2968 case SFF_MODULE_ID_QSFP28:
2969 modinfo->type = ETH_MODULE_SFF_8636;
2970 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
2971 break;
2972 default:
2973 rc = -EOPNOTSUPP;
2974 break;
2975 }
2976 }
2977 return rc;
2978 }
2979
bnxt_get_module_eeprom(struct net_device * dev,struct ethtool_eeprom * eeprom,u8 * data)2980 static int bnxt_get_module_eeprom(struct net_device *dev,
2981 struct ethtool_eeprom *eeprom,
2982 u8 *data)
2983 {
2984 struct bnxt *bp = netdev_priv(dev);
2985 u16 start = eeprom->offset, length = eeprom->len;
2986 int rc = 0;
2987
2988 memset(data, 0, eeprom->len);
2989
2990 /* Read A0 portion of the EEPROM */
2991 if (start < ETH_MODULE_SFF_8436_LEN) {
2992 if (start + eeprom->len > ETH_MODULE_SFF_8436_LEN)
2993 length = ETH_MODULE_SFF_8436_LEN - start;
2994 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0,
2995 start, length, data);
2996 if (rc)
2997 return rc;
2998 start += length;
2999 data += length;
3000 length = eeprom->len - length;
3001 }
3002
3003 /* Read A2 portion of the EEPROM */
3004 if (length) {
3005 start -= ETH_MODULE_SFF_8436_LEN;
3006 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A2, 0,
3007 start, length, data);
3008 }
3009 return rc;
3010 }
3011
bnxt_nway_reset(struct net_device * dev)3012 static int bnxt_nway_reset(struct net_device *dev)
3013 {
3014 int rc = 0;
3015
3016 struct bnxt *bp = netdev_priv(dev);
3017 struct bnxt_link_info *link_info = &bp->link_info;
3018
3019 if (!BNXT_PHY_CFG_ABLE(bp))
3020 return -EOPNOTSUPP;
3021
3022 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED))
3023 return -EINVAL;
3024
3025 if (netif_running(dev))
3026 rc = bnxt_hwrm_set_link_setting(bp, true, false);
3027
3028 return rc;
3029 }
3030
bnxt_set_phys_id(struct net_device * dev,enum ethtool_phys_id_state state)3031 static int bnxt_set_phys_id(struct net_device *dev,
3032 enum ethtool_phys_id_state state)
3033 {
3034 struct hwrm_port_led_cfg_input req = {0};
3035 struct bnxt *bp = netdev_priv(dev);
3036 struct bnxt_pf_info *pf = &bp->pf;
3037 struct bnxt_led_cfg *led_cfg;
3038 u8 led_state;
3039 __le16 duration;
3040 int i;
3041
3042 if (!bp->num_leds || BNXT_VF(bp))
3043 return -EOPNOTSUPP;
3044
3045 if (state == ETHTOOL_ID_ACTIVE) {
3046 led_state = PORT_LED_CFG_REQ_LED0_STATE_BLINKALT;
3047 duration = cpu_to_le16(500);
3048 } else if (state == ETHTOOL_ID_INACTIVE) {
3049 led_state = PORT_LED_CFG_REQ_LED1_STATE_DEFAULT;
3050 duration = cpu_to_le16(0);
3051 } else {
3052 return -EINVAL;
3053 }
3054 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_LED_CFG, -1, -1);
3055 req.port_id = cpu_to_le16(pf->port_id);
3056 req.num_leds = bp->num_leds;
3057 led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
3058 for (i = 0; i < bp->num_leds; i++, led_cfg++) {
3059 req.enables |= BNXT_LED_DFLT_ENABLES(i);
3060 led_cfg->led_id = bp->leds[i].led_id;
3061 led_cfg->led_state = led_state;
3062 led_cfg->led_blink_on = duration;
3063 led_cfg->led_blink_off = duration;
3064 led_cfg->led_group_id = bp->leds[i].led_group_id;
3065 }
3066 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3067 }
3068
bnxt_hwrm_selftest_irq(struct bnxt * bp,u16 cmpl_ring)3069 static int bnxt_hwrm_selftest_irq(struct bnxt *bp, u16 cmpl_ring)
3070 {
3071 struct hwrm_selftest_irq_input req = {0};
3072
3073 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_SELFTEST_IRQ, cmpl_ring, -1);
3074 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3075 }
3076
bnxt_test_irq(struct bnxt * bp)3077 static int bnxt_test_irq(struct bnxt *bp)
3078 {
3079 int i;
3080
3081 for (i = 0; i < bp->cp_nr_rings; i++) {
3082 u16 cmpl_ring = bp->grp_info[i].cp_fw_ring_id;
3083 int rc;
3084
3085 rc = bnxt_hwrm_selftest_irq(bp, cmpl_ring);
3086 if (rc)
3087 return rc;
3088 }
3089 return 0;
3090 }
3091
bnxt_hwrm_mac_loopback(struct bnxt * bp,bool enable)3092 static int bnxt_hwrm_mac_loopback(struct bnxt *bp, bool enable)
3093 {
3094 struct hwrm_port_mac_cfg_input req = {0};
3095
3096 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_MAC_CFG, -1, -1);
3097
3098 req.enables = cpu_to_le32(PORT_MAC_CFG_REQ_ENABLES_LPBK);
3099 if (enable)
3100 req.lpbk = PORT_MAC_CFG_REQ_LPBK_LOCAL;
3101 else
3102 req.lpbk = PORT_MAC_CFG_REQ_LPBK_NONE;
3103 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3104 }
3105
bnxt_query_force_speeds(struct bnxt * bp,u16 * force_speeds)3106 static int bnxt_query_force_speeds(struct bnxt *bp, u16 *force_speeds)
3107 {
3108 struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3109 struct hwrm_port_phy_qcaps_input req = {0};
3110 int rc;
3111
3112 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCAPS, -1, -1);
3113 mutex_lock(&bp->hwrm_cmd_lock);
3114 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3115 if (!rc)
3116 *force_speeds = le16_to_cpu(resp->supported_speeds_force_mode);
3117
3118 mutex_unlock(&bp->hwrm_cmd_lock);
3119 return rc;
3120 }
3121
bnxt_disable_an_for_lpbk(struct bnxt * bp,struct hwrm_port_phy_cfg_input * req)3122 static int bnxt_disable_an_for_lpbk(struct bnxt *bp,
3123 struct hwrm_port_phy_cfg_input *req)
3124 {
3125 struct bnxt_link_info *link_info = &bp->link_info;
3126 u16 fw_advertising;
3127 u16 fw_speed;
3128 int rc;
3129
3130 if (!link_info->autoneg ||
3131 (bp->test_info->flags & BNXT_TEST_FL_AN_PHY_LPBK))
3132 return 0;
3133
3134 rc = bnxt_query_force_speeds(bp, &fw_advertising);
3135 if (rc)
3136 return rc;
3137
3138 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB;
3139 if (bp->link_info.link_up)
3140 fw_speed = bp->link_info.link_speed;
3141 else if (fw_advertising & BNXT_LINK_SPEED_MSK_10GB)
3142 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB;
3143 else if (fw_advertising & BNXT_LINK_SPEED_MSK_25GB)
3144 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB;
3145 else if (fw_advertising & BNXT_LINK_SPEED_MSK_40GB)
3146 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB;
3147 else if (fw_advertising & BNXT_LINK_SPEED_MSK_50GB)
3148 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB;
3149
3150 req->force_link_speed = cpu_to_le16(fw_speed);
3151 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE |
3152 PORT_PHY_CFG_REQ_FLAGS_RESET_PHY);
3153 rc = hwrm_send_message(bp, req, sizeof(*req), HWRM_CMD_TIMEOUT);
3154 req->flags = 0;
3155 req->force_link_speed = cpu_to_le16(0);
3156 return rc;
3157 }
3158
bnxt_hwrm_phy_loopback(struct bnxt * bp,bool enable,bool ext)3159 static int bnxt_hwrm_phy_loopback(struct bnxt *bp, bool enable, bool ext)
3160 {
3161 struct hwrm_port_phy_cfg_input req = {0};
3162
3163 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
3164
3165 if (enable) {
3166 bnxt_disable_an_for_lpbk(bp, &req);
3167 if (ext)
3168 req.lpbk = PORT_PHY_CFG_REQ_LPBK_EXTERNAL;
3169 else
3170 req.lpbk = PORT_PHY_CFG_REQ_LPBK_LOCAL;
3171 } else {
3172 req.lpbk = PORT_PHY_CFG_REQ_LPBK_NONE;
3173 }
3174 req.enables = cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_LPBK);
3175 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3176 }
3177
bnxt_rx_loopback(struct bnxt * bp,struct bnxt_cp_ring_info * cpr,u32 raw_cons,int pkt_size)3178 static int bnxt_rx_loopback(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
3179 u32 raw_cons, int pkt_size)
3180 {
3181 struct bnxt_napi *bnapi = cpr->bnapi;
3182 struct bnxt_rx_ring_info *rxr;
3183 struct bnxt_sw_rx_bd *rx_buf;
3184 struct rx_cmp *rxcmp;
3185 u16 cp_cons, cons;
3186 u8 *data;
3187 u32 len;
3188 int i;
3189
3190 rxr = bnapi->rx_ring;
3191 cp_cons = RING_CMP(raw_cons);
3192 rxcmp = (struct rx_cmp *)
3193 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
3194 cons = rxcmp->rx_cmp_opaque;
3195 rx_buf = &rxr->rx_buf_ring[cons];
3196 data = rx_buf->data_ptr;
3197 len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT;
3198 if (len != pkt_size)
3199 return -EIO;
3200 i = ETH_ALEN;
3201 if (!ether_addr_equal(data + i, bnapi->bp->dev->dev_addr))
3202 return -EIO;
3203 i += ETH_ALEN;
3204 for ( ; i < pkt_size; i++) {
3205 if (data[i] != (u8)(i & 0xff))
3206 return -EIO;
3207 }
3208 return 0;
3209 }
3210
bnxt_poll_loopback(struct bnxt * bp,struct bnxt_cp_ring_info * cpr,int pkt_size)3211 static int bnxt_poll_loopback(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
3212 int pkt_size)
3213 {
3214 struct tx_cmp *txcmp;
3215 int rc = -EIO;
3216 u32 raw_cons;
3217 u32 cons;
3218 int i;
3219
3220 raw_cons = cpr->cp_raw_cons;
3221 for (i = 0; i < 200; i++) {
3222 cons = RING_CMP(raw_cons);
3223 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
3224
3225 if (!TX_CMP_VALID(txcmp, raw_cons)) {
3226 udelay(5);
3227 continue;
3228 }
3229
3230 /* The valid test of the entry must be done first before
3231 * reading any further.
3232 */
3233 dma_rmb();
3234 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_RX_L2_CMP) {
3235 rc = bnxt_rx_loopback(bp, cpr, raw_cons, pkt_size);
3236 raw_cons = NEXT_RAW_CMP(raw_cons);
3237 raw_cons = NEXT_RAW_CMP(raw_cons);
3238 break;
3239 }
3240 raw_cons = NEXT_RAW_CMP(raw_cons);
3241 }
3242 cpr->cp_raw_cons = raw_cons;
3243 return rc;
3244 }
3245
bnxt_run_loopback(struct bnxt * bp)3246 static int bnxt_run_loopback(struct bnxt *bp)
3247 {
3248 struct bnxt_tx_ring_info *txr = &bp->tx_ring[0];
3249 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[0];
3250 struct bnxt_cp_ring_info *cpr;
3251 int pkt_size, i = 0;
3252 struct sk_buff *skb;
3253 dma_addr_t map;
3254 u8 *data;
3255 int rc;
3256
3257 cpr = &rxr->bnapi->cp_ring;
3258 if (bp->flags & BNXT_FLAG_CHIP_P5)
3259 cpr = cpr->cp_ring_arr[BNXT_RX_HDL];
3260 pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_copy_thresh);
3261 skb = netdev_alloc_skb(bp->dev, pkt_size);
3262 if (!skb)
3263 return -ENOMEM;
3264 data = skb_put(skb, pkt_size);
3265 eth_broadcast_addr(data);
3266 i += ETH_ALEN;
3267 ether_addr_copy(&data[i], bp->dev->dev_addr);
3268 i += ETH_ALEN;
3269 for ( ; i < pkt_size; i++)
3270 data[i] = (u8)(i & 0xff);
3271
3272 map = dma_map_single(&bp->pdev->dev, skb->data, pkt_size,
3273 PCI_DMA_TODEVICE);
3274 if (dma_mapping_error(&bp->pdev->dev, map)) {
3275 dev_kfree_skb(skb);
3276 return -EIO;
3277 }
3278 bnxt_xmit_bd(bp, txr, map, pkt_size);
3279
3280 /* Sync BD data before updating doorbell */
3281 wmb();
3282
3283 bnxt_db_write(bp, &txr->tx_db, txr->tx_prod);
3284 rc = bnxt_poll_loopback(bp, cpr, pkt_size);
3285
3286 dma_unmap_single(&bp->pdev->dev, map, pkt_size, PCI_DMA_TODEVICE);
3287 dev_kfree_skb(skb);
3288 return rc;
3289 }
3290
bnxt_run_fw_tests(struct bnxt * bp,u8 test_mask,u8 * test_results)3291 static int bnxt_run_fw_tests(struct bnxt *bp, u8 test_mask, u8 *test_results)
3292 {
3293 struct hwrm_selftest_exec_output *resp = bp->hwrm_cmd_resp_addr;
3294 struct hwrm_selftest_exec_input req = {0};
3295 int rc;
3296
3297 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_SELFTEST_EXEC, -1, -1);
3298 mutex_lock(&bp->hwrm_cmd_lock);
3299 resp->test_success = 0;
3300 req.flags = test_mask;
3301 rc = _hwrm_send_message(bp, &req, sizeof(req), bp->test_info->timeout);
3302 *test_results = resp->test_success;
3303 mutex_unlock(&bp->hwrm_cmd_lock);
3304 return rc;
3305 }
3306
3307 #define BNXT_DRV_TESTS 4
3308 #define BNXT_MACLPBK_TEST_IDX (bp->num_tests - BNXT_DRV_TESTS)
3309 #define BNXT_PHYLPBK_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 1)
3310 #define BNXT_EXTLPBK_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 2)
3311 #define BNXT_IRQ_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 3)
3312
bnxt_self_test(struct net_device * dev,struct ethtool_test * etest,u64 * buf)3313 static void bnxt_self_test(struct net_device *dev, struct ethtool_test *etest,
3314 u64 *buf)
3315 {
3316 struct bnxt *bp = netdev_priv(dev);
3317 bool do_ext_lpbk = false;
3318 bool offline = false;
3319 u8 test_results = 0;
3320 u8 test_mask = 0;
3321 int rc = 0, i;
3322
3323 if (!bp->num_tests || !BNXT_PF(bp))
3324 return;
3325 memset(buf, 0, sizeof(u64) * bp->num_tests);
3326 if (!netif_running(dev)) {
3327 etest->flags |= ETH_TEST_FL_FAILED;
3328 return;
3329 }
3330
3331 if ((etest->flags & ETH_TEST_FL_EXTERNAL_LB) &&
3332 (bp->test_info->flags & BNXT_TEST_FL_EXT_LPBK))
3333 do_ext_lpbk = true;
3334
3335 if (etest->flags & ETH_TEST_FL_OFFLINE) {
3336 if (bp->pf.active_vfs || !BNXT_SINGLE_PF(bp)) {
3337 etest->flags |= ETH_TEST_FL_FAILED;
3338 netdev_warn(dev, "Offline tests cannot be run with active VFs or on shared PF\n");
3339 return;
3340 }
3341 offline = true;
3342 }
3343
3344 for (i = 0; i < bp->num_tests - BNXT_DRV_TESTS; i++) {
3345 u8 bit_val = 1 << i;
3346
3347 if (!(bp->test_info->offline_mask & bit_val))
3348 test_mask |= bit_val;
3349 else if (offline)
3350 test_mask |= bit_val;
3351 }
3352 if (!offline) {
3353 bnxt_run_fw_tests(bp, test_mask, &test_results);
3354 } else {
3355 rc = bnxt_close_nic(bp, false, false);
3356 if (rc)
3357 return;
3358 bnxt_run_fw_tests(bp, test_mask, &test_results);
3359
3360 buf[BNXT_MACLPBK_TEST_IDX] = 1;
3361 bnxt_hwrm_mac_loopback(bp, true);
3362 msleep(250);
3363 rc = bnxt_half_open_nic(bp);
3364 if (rc) {
3365 bnxt_hwrm_mac_loopback(bp, false);
3366 etest->flags |= ETH_TEST_FL_FAILED;
3367 return;
3368 }
3369 if (bnxt_run_loopback(bp))
3370 etest->flags |= ETH_TEST_FL_FAILED;
3371 else
3372 buf[BNXT_MACLPBK_TEST_IDX] = 0;
3373
3374 bnxt_hwrm_mac_loopback(bp, false);
3375 bnxt_hwrm_phy_loopback(bp, true, false);
3376 msleep(1000);
3377 if (bnxt_run_loopback(bp)) {
3378 buf[BNXT_PHYLPBK_TEST_IDX] = 1;
3379 etest->flags |= ETH_TEST_FL_FAILED;
3380 }
3381 if (do_ext_lpbk) {
3382 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE;
3383 bnxt_hwrm_phy_loopback(bp, true, true);
3384 msleep(1000);
3385 if (bnxt_run_loopback(bp)) {
3386 buf[BNXT_EXTLPBK_TEST_IDX] = 1;
3387 etest->flags |= ETH_TEST_FL_FAILED;
3388 }
3389 }
3390 bnxt_hwrm_phy_loopback(bp, false, false);
3391 bnxt_half_close_nic(bp);
3392 rc = bnxt_open_nic(bp, false, true);
3393 }
3394 if (rc || bnxt_test_irq(bp)) {
3395 buf[BNXT_IRQ_TEST_IDX] = 1;
3396 etest->flags |= ETH_TEST_FL_FAILED;
3397 }
3398 for (i = 0; i < bp->num_tests - BNXT_DRV_TESTS; i++) {
3399 u8 bit_val = 1 << i;
3400
3401 if ((test_mask & bit_val) && !(test_results & bit_val)) {
3402 buf[i] = 1;
3403 etest->flags |= ETH_TEST_FL_FAILED;
3404 }
3405 }
3406 }
3407
bnxt_reset(struct net_device * dev,u32 * flags)3408 static int bnxt_reset(struct net_device *dev, u32 *flags)
3409 {
3410 struct bnxt *bp = netdev_priv(dev);
3411 bool reload = false;
3412 u32 req = *flags;
3413
3414 if (!req)
3415 return -EINVAL;
3416
3417 if (!BNXT_PF(bp)) {
3418 netdev_err(dev, "Reset is not supported from a VF\n");
3419 return -EOPNOTSUPP;
3420 }
3421
3422 if (pci_vfs_assigned(bp->pdev) &&
3423 !(bp->fw_cap & BNXT_FW_CAP_HOT_RESET)) {
3424 netdev_err(dev,
3425 "Reset not allowed when VFs are assigned to VMs\n");
3426 return -EBUSY;
3427 }
3428
3429 if ((req & BNXT_FW_RESET_CHIP) == BNXT_FW_RESET_CHIP) {
3430 /* This feature is not supported in older firmware versions */
3431 if (bp->hwrm_spec_code >= 0x10803) {
3432 if (!bnxt_firmware_reset_chip(dev)) {
3433 netdev_info(dev, "Firmware reset request successful.\n");
3434 if (!(bp->fw_cap & BNXT_FW_CAP_HOT_RESET))
3435 reload = true;
3436 *flags &= ~BNXT_FW_RESET_CHIP;
3437 }
3438 } else if (req == BNXT_FW_RESET_CHIP) {
3439 return -EOPNOTSUPP; /* only request, fail hard */
3440 }
3441 }
3442
3443 if (!BNXT_CHIP_P4_PLUS(bp) && (req & BNXT_FW_RESET_AP)) {
3444 /* This feature is not supported in older firmware versions */
3445 if (bp->hwrm_spec_code >= 0x10803) {
3446 if (!bnxt_firmware_reset_ap(dev)) {
3447 netdev_info(dev, "Reset application processor successful.\n");
3448 reload = true;
3449 *flags &= ~BNXT_FW_RESET_AP;
3450 }
3451 } else if (req == BNXT_FW_RESET_AP) {
3452 return -EOPNOTSUPP; /* only request, fail hard */
3453 }
3454 }
3455
3456 if (reload)
3457 netdev_info(dev, "Reload driver to complete reset\n");
3458
3459 return 0;
3460 }
3461
bnxt_hwrm_dbg_dma_data(struct bnxt * bp,void * msg,int msg_len,struct bnxt_hwrm_dbg_dma_info * info)3462 static int bnxt_hwrm_dbg_dma_data(struct bnxt *bp, void *msg, int msg_len,
3463 struct bnxt_hwrm_dbg_dma_info *info)
3464 {
3465 struct hwrm_dbg_cmn_output *cmn_resp = bp->hwrm_cmd_resp_addr;
3466 struct hwrm_dbg_cmn_input *cmn_req = msg;
3467 __le16 *seq_ptr = msg + info->seq_off;
3468 u16 seq = 0, len, segs_off;
3469 void *resp = cmn_resp;
3470 dma_addr_t dma_handle;
3471 int rc, off = 0;
3472 void *dma_buf;
3473
3474 dma_buf = dma_alloc_coherent(&bp->pdev->dev, info->dma_len, &dma_handle,
3475 GFP_KERNEL);
3476 if (!dma_buf)
3477 return -ENOMEM;
3478
3479 segs_off = offsetof(struct hwrm_dbg_coredump_list_output,
3480 total_segments);
3481 cmn_req->host_dest_addr = cpu_to_le64(dma_handle);
3482 cmn_req->host_buf_len = cpu_to_le32(info->dma_len);
3483 mutex_lock(&bp->hwrm_cmd_lock);
3484 while (1) {
3485 *seq_ptr = cpu_to_le16(seq);
3486 rc = _hwrm_send_message(bp, msg, msg_len,
3487 HWRM_COREDUMP_TIMEOUT);
3488 if (rc)
3489 break;
3490
3491 len = le16_to_cpu(*((__le16 *)(resp + info->data_len_off)));
3492 if (!seq &&
3493 cmn_req->req_type == cpu_to_le16(HWRM_DBG_COREDUMP_LIST)) {
3494 info->segs = le16_to_cpu(*((__le16 *)(resp +
3495 segs_off)));
3496 if (!info->segs) {
3497 rc = -EIO;
3498 break;
3499 }
3500
3501 info->dest_buf_size = info->segs *
3502 sizeof(struct coredump_segment_record);
3503 info->dest_buf = kmalloc(info->dest_buf_size,
3504 GFP_KERNEL);
3505 if (!info->dest_buf) {
3506 rc = -ENOMEM;
3507 break;
3508 }
3509 }
3510
3511 if (info->dest_buf) {
3512 if ((info->seg_start + off + len) <=
3513 BNXT_COREDUMP_BUF_LEN(info->buf_len)) {
3514 memcpy(info->dest_buf + off, dma_buf, len);
3515 } else {
3516 rc = -ENOBUFS;
3517 break;
3518 }
3519 }
3520
3521 if (cmn_req->req_type ==
3522 cpu_to_le16(HWRM_DBG_COREDUMP_RETRIEVE))
3523 info->dest_buf_size += len;
3524
3525 if (!(cmn_resp->flags & HWRM_DBG_CMN_FLAGS_MORE))
3526 break;
3527
3528 seq++;
3529 off += len;
3530 }
3531 mutex_unlock(&bp->hwrm_cmd_lock);
3532 dma_free_coherent(&bp->pdev->dev, info->dma_len, dma_buf, dma_handle);
3533 return rc;
3534 }
3535
bnxt_hwrm_dbg_coredump_list(struct bnxt * bp,struct bnxt_coredump * coredump)3536 static int bnxt_hwrm_dbg_coredump_list(struct bnxt *bp,
3537 struct bnxt_coredump *coredump)
3538 {
3539 struct hwrm_dbg_coredump_list_input req = {0};
3540 struct bnxt_hwrm_dbg_dma_info info = {NULL};
3541 int rc;
3542
3543 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_DBG_COREDUMP_LIST, -1, -1);
3544
3545 info.dma_len = COREDUMP_LIST_BUF_LEN;
3546 info.seq_off = offsetof(struct hwrm_dbg_coredump_list_input, seq_no);
3547 info.data_len_off = offsetof(struct hwrm_dbg_coredump_list_output,
3548 data_len);
3549
3550 rc = bnxt_hwrm_dbg_dma_data(bp, &req, sizeof(req), &info);
3551 if (!rc) {
3552 coredump->data = info.dest_buf;
3553 coredump->data_size = info.dest_buf_size;
3554 coredump->total_segs = info.segs;
3555 }
3556 return rc;
3557 }
3558
bnxt_hwrm_dbg_coredump_initiate(struct bnxt * bp,u16 component_id,u16 segment_id)3559 static int bnxt_hwrm_dbg_coredump_initiate(struct bnxt *bp, u16 component_id,
3560 u16 segment_id)
3561 {
3562 struct hwrm_dbg_coredump_initiate_input req = {0};
3563
3564 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_DBG_COREDUMP_INITIATE, -1, -1);
3565 req.component_id = cpu_to_le16(component_id);
3566 req.segment_id = cpu_to_le16(segment_id);
3567
3568 return hwrm_send_message(bp, &req, sizeof(req), HWRM_COREDUMP_TIMEOUT);
3569 }
3570
bnxt_hwrm_dbg_coredump_retrieve(struct bnxt * bp,u16 component_id,u16 segment_id,u32 * seg_len,void * buf,u32 buf_len,u32 offset)3571 static int bnxt_hwrm_dbg_coredump_retrieve(struct bnxt *bp, u16 component_id,
3572 u16 segment_id, u32 *seg_len,
3573 void *buf, u32 buf_len, u32 offset)
3574 {
3575 struct hwrm_dbg_coredump_retrieve_input req = {0};
3576 struct bnxt_hwrm_dbg_dma_info info = {NULL};
3577 int rc;
3578
3579 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_DBG_COREDUMP_RETRIEVE, -1, -1);
3580 req.component_id = cpu_to_le16(component_id);
3581 req.segment_id = cpu_to_le16(segment_id);
3582
3583 info.dma_len = COREDUMP_RETRIEVE_BUF_LEN;
3584 info.seq_off = offsetof(struct hwrm_dbg_coredump_retrieve_input,
3585 seq_no);
3586 info.data_len_off = offsetof(struct hwrm_dbg_coredump_retrieve_output,
3587 data_len);
3588 if (buf) {
3589 info.dest_buf = buf + offset;
3590 info.buf_len = buf_len;
3591 info.seg_start = offset;
3592 }
3593
3594 rc = bnxt_hwrm_dbg_dma_data(bp, &req, sizeof(req), &info);
3595 if (!rc)
3596 *seg_len = info.dest_buf_size;
3597
3598 return rc;
3599 }
3600
3601 static void
bnxt_fill_coredump_seg_hdr(struct bnxt * bp,struct bnxt_coredump_segment_hdr * seg_hdr,struct coredump_segment_record * seg_rec,u32 seg_len,int status,u32 duration,u32 instance)3602 bnxt_fill_coredump_seg_hdr(struct bnxt *bp,
3603 struct bnxt_coredump_segment_hdr *seg_hdr,
3604 struct coredump_segment_record *seg_rec, u32 seg_len,
3605 int status, u32 duration, u32 instance)
3606 {
3607 memset(seg_hdr, 0, sizeof(*seg_hdr));
3608 memcpy(seg_hdr->signature, "sEgM", 4);
3609 if (seg_rec) {
3610 seg_hdr->component_id = (__force __le32)seg_rec->component_id;
3611 seg_hdr->segment_id = (__force __le32)seg_rec->segment_id;
3612 seg_hdr->low_version = seg_rec->version_low;
3613 seg_hdr->high_version = seg_rec->version_hi;
3614 } else {
3615 /* For hwrm_ver_get response Component id = 2
3616 * and Segment id = 0
3617 */
3618 seg_hdr->component_id = cpu_to_le32(2);
3619 seg_hdr->segment_id = 0;
3620 }
3621 seg_hdr->function_id = cpu_to_le16(bp->pdev->devfn);
3622 seg_hdr->length = cpu_to_le32(seg_len);
3623 seg_hdr->status = cpu_to_le32(status);
3624 seg_hdr->duration = cpu_to_le32(duration);
3625 seg_hdr->data_offset = cpu_to_le32(sizeof(*seg_hdr));
3626 seg_hdr->instance = cpu_to_le32(instance);
3627 }
3628
3629 static void
bnxt_fill_coredump_record(struct bnxt * bp,struct bnxt_coredump_record * record,time64_t start,s16 start_utc,u16 total_segs,int status)3630 bnxt_fill_coredump_record(struct bnxt *bp, struct bnxt_coredump_record *record,
3631 time64_t start, s16 start_utc, u16 total_segs,
3632 int status)
3633 {
3634 time64_t end = ktime_get_real_seconds();
3635 u32 os_ver_major = 0, os_ver_minor = 0;
3636 struct tm tm;
3637
3638 time64_to_tm(start, 0, &tm);
3639 memset(record, 0, sizeof(*record));
3640 memcpy(record->signature, "cOrE", 4);
3641 record->flags = 0;
3642 record->low_version = 0;
3643 record->high_version = 1;
3644 record->asic_state = 0;
3645 strlcpy(record->system_name, utsname()->nodename,
3646 sizeof(record->system_name));
3647 record->year = cpu_to_le16(tm.tm_year + 1900);
3648 record->month = cpu_to_le16(tm.tm_mon + 1);
3649 record->day = cpu_to_le16(tm.tm_mday);
3650 record->hour = cpu_to_le16(tm.tm_hour);
3651 record->minute = cpu_to_le16(tm.tm_min);
3652 record->second = cpu_to_le16(tm.tm_sec);
3653 record->utc_bias = cpu_to_le16(start_utc);
3654 strcpy(record->commandline, "ethtool -w");
3655 record->total_segments = cpu_to_le32(total_segs);
3656
3657 sscanf(utsname()->release, "%u.%u", &os_ver_major, &os_ver_minor);
3658 record->os_ver_major = cpu_to_le32(os_ver_major);
3659 record->os_ver_minor = cpu_to_le32(os_ver_minor);
3660
3661 strlcpy(record->os_name, utsname()->sysname, 32);
3662 time64_to_tm(end, 0, &tm);
3663 record->end_year = cpu_to_le16(tm.tm_year + 1900);
3664 record->end_month = cpu_to_le16(tm.tm_mon + 1);
3665 record->end_day = cpu_to_le16(tm.tm_mday);
3666 record->end_hour = cpu_to_le16(tm.tm_hour);
3667 record->end_minute = cpu_to_le16(tm.tm_min);
3668 record->end_second = cpu_to_le16(tm.tm_sec);
3669 record->end_utc_bias = cpu_to_le16(sys_tz.tz_minuteswest * 60);
3670 record->asic_id1 = cpu_to_le32(bp->chip_num << 16 |
3671 bp->ver_resp.chip_rev << 8 |
3672 bp->ver_resp.chip_metal);
3673 record->asic_id2 = 0;
3674 record->coredump_status = cpu_to_le32(status);
3675 record->ioctl_low_version = 0;
3676 record->ioctl_high_version = 0;
3677 }
3678
bnxt_get_coredump(struct bnxt * bp,void * buf,u32 * dump_len)3679 static int bnxt_get_coredump(struct bnxt *bp, void *buf, u32 *dump_len)
3680 {
3681 u32 ver_get_resp_len = sizeof(struct hwrm_ver_get_output);
3682 u32 offset = 0, seg_hdr_len, seg_record_len, buf_len = 0;
3683 struct coredump_segment_record *seg_record = NULL;
3684 struct bnxt_coredump_segment_hdr seg_hdr;
3685 struct bnxt_coredump coredump = {NULL};
3686 time64_t start_time;
3687 u16 start_utc;
3688 int rc = 0, i;
3689
3690 if (buf)
3691 buf_len = *dump_len;
3692
3693 start_time = ktime_get_real_seconds();
3694 start_utc = sys_tz.tz_minuteswest * 60;
3695 seg_hdr_len = sizeof(seg_hdr);
3696
3697 /* First segment should be hwrm_ver_get response */
3698 *dump_len = seg_hdr_len + ver_get_resp_len;
3699 if (buf) {
3700 bnxt_fill_coredump_seg_hdr(bp, &seg_hdr, NULL, ver_get_resp_len,
3701 0, 0, 0);
3702 memcpy(buf + offset, &seg_hdr, seg_hdr_len);
3703 offset += seg_hdr_len;
3704 memcpy(buf + offset, &bp->ver_resp, ver_get_resp_len);
3705 offset += ver_get_resp_len;
3706 }
3707
3708 rc = bnxt_hwrm_dbg_coredump_list(bp, &coredump);
3709 if (rc) {
3710 netdev_err(bp->dev, "Failed to get coredump segment list\n");
3711 goto err;
3712 }
3713
3714 *dump_len += seg_hdr_len * coredump.total_segs;
3715
3716 seg_record = (struct coredump_segment_record *)coredump.data;
3717 seg_record_len = sizeof(*seg_record);
3718
3719 for (i = 0; i < coredump.total_segs; i++) {
3720 u16 comp_id = le16_to_cpu(seg_record->component_id);
3721 u16 seg_id = le16_to_cpu(seg_record->segment_id);
3722 u32 duration = 0, seg_len = 0;
3723 unsigned long start, end;
3724
3725 if (buf && ((offset + seg_hdr_len) >
3726 BNXT_COREDUMP_BUF_LEN(buf_len))) {
3727 rc = -ENOBUFS;
3728 goto err;
3729 }
3730
3731 start = jiffies;
3732
3733 rc = bnxt_hwrm_dbg_coredump_initiate(bp, comp_id, seg_id);
3734 if (rc) {
3735 netdev_err(bp->dev,
3736 "Failed to initiate coredump for seg = %d\n",
3737 seg_record->segment_id);
3738 goto next_seg;
3739 }
3740
3741 /* Write segment data into the buffer */
3742 rc = bnxt_hwrm_dbg_coredump_retrieve(bp, comp_id, seg_id,
3743 &seg_len, buf, buf_len,
3744 offset + seg_hdr_len);
3745 if (rc && rc == -ENOBUFS)
3746 goto err;
3747 else if (rc)
3748 netdev_err(bp->dev,
3749 "Failed to retrieve coredump for seg = %d\n",
3750 seg_record->segment_id);
3751
3752 next_seg:
3753 end = jiffies;
3754 duration = jiffies_to_msecs(end - start);
3755 bnxt_fill_coredump_seg_hdr(bp, &seg_hdr, seg_record, seg_len,
3756 rc, duration, 0);
3757
3758 if (buf) {
3759 /* Write segment header into the buffer */
3760 memcpy(buf + offset, &seg_hdr, seg_hdr_len);
3761 offset += seg_hdr_len + seg_len;
3762 }
3763
3764 *dump_len += seg_len;
3765 seg_record =
3766 (struct coredump_segment_record *)((u8 *)seg_record +
3767 seg_record_len);
3768 }
3769
3770 err:
3771 if (buf)
3772 bnxt_fill_coredump_record(bp, buf + offset, start_time,
3773 start_utc, coredump.total_segs + 1,
3774 rc);
3775 kfree(coredump.data);
3776 *dump_len += sizeof(struct bnxt_coredump_record);
3777 if (rc == -ENOBUFS)
3778 netdev_err(bp->dev, "Firmware returned large coredump buffer\n");
3779 return rc;
3780 }
3781
bnxt_set_dump(struct net_device * dev,struct ethtool_dump * dump)3782 static int bnxt_set_dump(struct net_device *dev, struct ethtool_dump *dump)
3783 {
3784 struct bnxt *bp = netdev_priv(dev);
3785
3786 if (dump->flag > BNXT_DUMP_CRASH) {
3787 netdev_info(dev, "Supports only Live(0) and Crash(1) dumps.\n");
3788 return -EINVAL;
3789 }
3790
3791 if (!IS_ENABLED(CONFIG_TEE_BNXT_FW) && dump->flag == BNXT_DUMP_CRASH) {
3792 netdev_info(dev, "Cannot collect crash dump as TEE_BNXT_FW config option is not enabled.\n");
3793 return -EOPNOTSUPP;
3794 }
3795
3796 bp->dump_flag = dump->flag;
3797 return 0;
3798 }
3799
bnxt_get_dump_flag(struct net_device * dev,struct ethtool_dump * dump)3800 static int bnxt_get_dump_flag(struct net_device *dev, struct ethtool_dump *dump)
3801 {
3802 struct bnxt *bp = netdev_priv(dev);
3803
3804 if (bp->hwrm_spec_code < 0x10801)
3805 return -EOPNOTSUPP;
3806
3807 dump->version = bp->ver_resp.hwrm_fw_maj_8b << 24 |
3808 bp->ver_resp.hwrm_fw_min_8b << 16 |
3809 bp->ver_resp.hwrm_fw_bld_8b << 8 |
3810 bp->ver_resp.hwrm_fw_rsvd_8b;
3811
3812 dump->flag = bp->dump_flag;
3813 if (bp->dump_flag == BNXT_DUMP_CRASH)
3814 dump->len = BNXT_CRASH_DUMP_LEN;
3815 else
3816 bnxt_get_coredump(bp, NULL, &dump->len);
3817 return 0;
3818 }
3819
bnxt_get_dump_data(struct net_device * dev,struct ethtool_dump * dump,void * buf)3820 static int bnxt_get_dump_data(struct net_device *dev, struct ethtool_dump *dump,
3821 void *buf)
3822 {
3823 struct bnxt *bp = netdev_priv(dev);
3824
3825 if (bp->hwrm_spec_code < 0x10801)
3826 return -EOPNOTSUPP;
3827
3828 memset(buf, 0, dump->len);
3829
3830 dump->flag = bp->dump_flag;
3831 if (dump->flag == BNXT_DUMP_CRASH) {
3832 #ifdef CONFIG_TEE_BNXT_FW
3833 return tee_bnxt_copy_coredump(buf, 0, dump->len);
3834 #endif
3835 } else {
3836 return bnxt_get_coredump(bp, buf, &dump->len);
3837 }
3838
3839 return 0;
3840 }
3841
bnxt_ethtool_init(struct bnxt * bp)3842 void bnxt_ethtool_init(struct bnxt *bp)
3843 {
3844 struct hwrm_selftest_qlist_output *resp = bp->hwrm_cmd_resp_addr;
3845 struct hwrm_selftest_qlist_input req = {0};
3846 struct bnxt_test_info *test_info;
3847 struct net_device *dev = bp->dev;
3848 int i, rc;
3849
3850 if (!(bp->fw_cap & BNXT_FW_CAP_PKG_VER))
3851 bnxt_get_pkgver(dev);
3852
3853 bp->num_tests = 0;
3854 if (bp->hwrm_spec_code < 0x10704 || !BNXT_PF(bp))
3855 return;
3856
3857 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_SELFTEST_QLIST, -1, -1);
3858 mutex_lock(&bp->hwrm_cmd_lock);
3859 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3860 if (rc)
3861 goto ethtool_init_exit;
3862
3863 test_info = bp->test_info;
3864 if (!test_info)
3865 test_info = kzalloc(sizeof(*bp->test_info), GFP_KERNEL);
3866 if (!test_info)
3867 goto ethtool_init_exit;
3868
3869 bp->test_info = test_info;
3870 bp->num_tests = resp->num_tests + BNXT_DRV_TESTS;
3871 if (bp->num_tests > BNXT_MAX_TEST)
3872 bp->num_tests = BNXT_MAX_TEST;
3873
3874 test_info->offline_mask = resp->offline_tests;
3875 test_info->timeout = le16_to_cpu(resp->test_timeout);
3876 if (!test_info->timeout)
3877 test_info->timeout = HWRM_CMD_TIMEOUT;
3878 for (i = 0; i < bp->num_tests; i++) {
3879 char *str = test_info->string[i];
3880 char *fw_str = resp->test0_name + i * 32;
3881
3882 if (i == BNXT_MACLPBK_TEST_IDX) {
3883 strcpy(str, "Mac loopback test (offline)");
3884 } else if (i == BNXT_PHYLPBK_TEST_IDX) {
3885 strcpy(str, "Phy loopback test (offline)");
3886 } else if (i == BNXT_EXTLPBK_TEST_IDX) {
3887 strcpy(str, "Ext loopback test (offline)");
3888 } else if (i == BNXT_IRQ_TEST_IDX) {
3889 strcpy(str, "Interrupt_test (offline)");
3890 } else {
3891 strlcpy(str, fw_str, ETH_GSTRING_LEN);
3892 strncat(str, " test", ETH_GSTRING_LEN - strlen(str));
3893 if (test_info->offline_mask & (1 << i))
3894 strncat(str, " (offline)",
3895 ETH_GSTRING_LEN - strlen(str));
3896 else
3897 strncat(str, " (online)",
3898 ETH_GSTRING_LEN - strlen(str));
3899 }
3900 }
3901
3902 ethtool_init_exit:
3903 mutex_unlock(&bp->hwrm_cmd_lock);
3904 }
3905
bnxt_ethtool_free(struct bnxt * bp)3906 void bnxt_ethtool_free(struct bnxt *bp)
3907 {
3908 kfree(bp->test_info);
3909 bp->test_info = NULL;
3910 }
3911
3912 const struct ethtool_ops bnxt_ethtool_ops = {
3913 .supported_coalesce_params = ETHTOOL_COALESCE_USECS |
3914 ETHTOOL_COALESCE_MAX_FRAMES |
3915 ETHTOOL_COALESCE_USECS_IRQ |
3916 ETHTOOL_COALESCE_MAX_FRAMES_IRQ |
3917 ETHTOOL_COALESCE_STATS_BLOCK_USECS |
3918 ETHTOOL_COALESCE_USE_ADAPTIVE_RX,
3919 .get_link_ksettings = bnxt_get_link_ksettings,
3920 .set_link_ksettings = bnxt_set_link_ksettings,
3921 .get_fecparam = bnxt_get_fecparam,
3922 .set_fecparam = bnxt_set_fecparam,
3923 .get_pause_stats = bnxt_get_pause_stats,
3924 .get_pauseparam = bnxt_get_pauseparam,
3925 .set_pauseparam = bnxt_set_pauseparam,
3926 .get_drvinfo = bnxt_get_drvinfo,
3927 .get_regs_len = bnxt_get_regs_len,
3928 .get_regs = bnxt_get_regs,
3929 .get_wol = bnxt_get_wol,
3930 .set_wol = bnxt_set_wol,
3931 .get_coalesce = bnxt_get_coalesce,
3932 .set_coalesce = bnxt_set_coalesce,
3933 .get_msglevel = bnxt_get_msglevel,
3934 .set_msglevel = bnxt_set_msglevel,
3935 .get_sset_count = bnxt_get_sset_count,
3936 .get_strings = bnxt_get_strings,
3937 .get_ethtool_stats = bnxt_get_ethtool_stats,
3938 .set_ringparam = bnxt_set_ringparam,
3939 .get_ringparam = bnxt_get_ringparam,
3940 .get_channels = bnxt_get_channels,
3941 .set_channels = bnxt_set_channels,
3942 .get_rxnfc = bnxt_get_rxnfc,
3943 .set_rxnfc = bnxt_set_rxnfc,
3944 .get_rxfh_indir_size = bnxt_get_rxfh_indir_size,
3945 .get_rxfh_key_size = bnxt_get_rxfh_key_size,
3946 .get_rxfh = bnxt_get_rxfh,
3947 .set_rxfh = bnxt_set_rxfh,
3948 .flash_device = bnxt_flash_device,
3949 .get_eeprom_len = bnxt_get_eeprom_len,
3950 .get_eeprom = bnxt_get_eeprom,
3951 .set_eeprom = bnxt_set_eeprom,
3952 .get_link = bnxt_get_link,
3953 .get_eee = bnxt_get_eee,
3954 .set_eee = bnxt_set_eee,
3955 .get_module_info = bnxt_get_module_info,
3956 .get_module_eeprom = bnxt_get_module_eeprom,
3957 .nway_reset = bnxt_nway_reset,
3958 .set_phys_id = bnxt_set_phys_id,
3959 .self_test = bnxt_self_test,
3960 .reset = bnxt_reset,
3961 .set_dump = bnxt_set_dump,
3962 .get_dump_flag = bnxt_get_dump_flag,
3963 .get_dump_data = bnxt_get_dump_data,
3964 };
3965