1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef DW_SPI_HEADER_H
3 #define DW_SPI_HEADER_H
4
5 #include <linux/bits.h>
6 #include <linux/completion.h>
7 #include <linux/debugfs.h>
8 #include <linux/irqreturn.h>
9 #include <linux/io.h>
10 #include <linux/scatterlist.h>
11 #include <linux/spi/spi-mem.h>
12
13 /* Register offsets */
14 #define DW_SPI_CTRLR0 0x00
15 #define DW_SPI_CTRLR1 0x04
16 #define DW_SPI_SSIENR 0x08
17 #define DW_SPI_MWCR 0x0c
18 #define DW_SPI_SER 0x10
19 #define DW_SPI_BAUDR 0x14
20 #define DW_SPI_TXFTLR 0x18
21 #define DW_SPI_RXFTLR 0x1c
22 #define DW_SPI_TXFLR 0x20
23 #define DW_SPI_RXFLR 0x24
24 #define DW_SPI_SR 0x28
25 #define DW_SPI_IMR 0x2c
26 #define DW_SPI_ISR 0x30
27 #define DW_SPI_RISR 0x34
28 #define DW_SPI_TXOICR 0x38
29 #define DW_SPI_RXOICR 0x3c
30 #define DW_SPI_RXUICR 0x40
31 #define DW_SPI_MSTICR 0x44
32 #define DW_SPI_ICR 0x48
33 #define DW_SPI_DMACR 0x4c
34 #define DW_SPI_DMATDLR 0x50
35 #define DW_SPI_DMARDLR 0x54
36 #define DW_SPI_IDR 0x58
37 #define DW_SPI_VERSION 0x5c
38 #define DW_SPI_DR 0x60
39 #define DW_SPI_RX_SAMPLE_DLY 0xf0
40 #define DW_SPI_CS_OVERRIDE 0xf4
41
42 /* Bit fields in CTRLR0 */
43 #define SPI_DFS_OFFSET 0
44
45 #define SPI_FRF_OFFSET 4
46 #define SPI_FRF_SPI 0x0
47 #define SPI_FRF_SSP 0x1
48 #define SPI_FRF_MICROWIRE 0x2
49 #define SPI_FRF_RESV 0x3
50
51 #define SPI_MODE_OFFSET 6
52 #define SPI_SCPH_OFFSET 6
53 #define SPI_SCOL_OFFSET 7
54
55 #define SPI_TMOD_OFFSET 8
56 #define SPI_TMOD_MASK (0x3 << SPI_TMOD_OFFSET)
57 #define SPI_TMOD_TR 0x0 /* xmit & recv */
58 #define SPI_TMOD_TO 0x1 /* xmit only */
59 #define SPI_TMOD_RO 0x2 /* recv only */
60 #define SPI_TMOD_EPROMREAD 0x3 /* eeprom read mode */
61
62 #define SPI_SLVOE_OFFSET 10
63 #define SPI_SRL_OFFSET 11
64 #define SPI_CFS_OFFSET 12
65
66 /* Bit fields in CTRLR0 based on DWC_ssi_databook.pdf v1.01a */
67 #define DWC_SSI_CTRLR0_SRL_OFFSET 13
68 #define DWC_SSI_CTRLR0_TMOD_OFFSET 10
69 #define DWC_SSI_CTRLR0_TMOD_MASK GENMASK(11, 10)
70 #define DWC_SSI_CTRLR0_SCPOL_OFFSET 9
71 #define DWC_SSI_CTRLR0_SCPH_OFFSET 8
72 #define DWC_SSI_CTRLR0_FRF_OFFSET 6
73 #define DWC_SSI_CTRLR0_DFS_OFFSET 0
74
75 /*
76 * For Keem Bay, CTRLR0[31] is used to select controller mode.
77 * 0: SSI is slave
78 * 1: SSI is master
79 */
80 #define DWC_SSI_CTRLR0_KEEMBAY_MST BIT(31)
81
82 /* Bit fields in CTRLR1 */
83 #define SPI_NDF_MASK GENMASK(15, 0)
84
85 /* Bit fields in SR, 7 bits */
86 #define SR_MASK 0x7f /* cover 7 bits */
87 #define SR_BUSY (1 << 0)
88 #define SR_TF_NOT_FULL (1 << 1)
89 #define SR_TF_EMPT (1 << 2)
90 #define SR_RF_NOT_EMPT (1 << 3)
91 #define SR_RF_FULL (1 << 4)
92 #define SR_TX_ERR (1 << 5)
93 #define SR_DCOL (1 << 6)
94
95 /* Bit fields in ISR, IMR, RISR, 7 bits */
96 #define SPI_INT_TXEI (1 << 0)
97 #define SPI_INT_TXOI (1 << 1)
98 #define SPI_INT_RXUI (1 << 2)
99 #define SPI_INT_RXOI (1 << 3)
100 #define SPI_INT_RXFI (1 << 4)
101 #define SPI_INT_MSTI (1 << 5)
102
103 /* Bit fields in DMACR */
104 #define SPI_DMA_RDMAE (1 << 0)
105 #define SPI_DMA_TDMAE (1 << 1)
106
107 #define SPI_WAIT_RETRIES 5
108 #define SPI_BUF_SIZE \
109 (sizeof_field(struct spi_mem_op, cmd.opcode) + \
110 sizeof_field(struct spi_mem_op, addr.val) + 256)
111 #define SPI_GET_BYTE(_val, _idx) \
112 ((_val) >> (BITS_PER_BYTE * (_idx)) & 0xff)
113
114 enum dw_ssi_type {
115 SSI_MOTO_SPI = 0,
116 SSI_TI_SSP,
117 SSI_NS_MICROWIRE,
118 };
119
120 /* DW SPI capabilities */
121 #define DW_SPI_CAP_CS_OVERRIDE BIT(0)
122 #define DW_SPI_CAP_KEEMBAY_MST BIT(1)
123 #define DW_SPI_CAP_DWC_SSI BIT(2)
124
125 /* Slave spi_transfer/spi_mem_op related */
126 struct dw_spi_cfg {
127 u8 tmode;
128 u8 dfs;
129 u32 ndf;
130 u32 freq;
131 };
132
133 struct dw_spi;
134 struct dw_spi_dma_ops {
135 int (*dma_init)(struct device *dev, struct dw_spi *dws);
136 void (*dma_exit)(struct dw_spi *dws);
137 int (*dma_setup)(struct dw_spi *dws, struct spi_transfer *xfer);
138 bool (*can_dma)(struct spi_controller *master, struct spi_device *spi,
139 struct spi_transfer *xfer);
140 int (*dma_transfer)(struct dw_spi *dws, struct spi_transfer *xfer);
141 void (*dma_stop)(struct dw_spi *dws);
142 };
143
144 struct dw_spi {
145 struct spi_controller *master;
146
147 void __iomem *regs;
148 unsigned long paddr;
149 int irq;
150 u32 fifo_len; /* depth of the FIFO buffer */
151 u32 max_mem_freq; /* max mem-ops bus freq */
152 u32 max_freq; /* max bus freq supported */
153
154 u32 caps; /* DW SPI capabilities */
155
156 u32 reg_io_width; /* DR I/O width in bytes */
157 u16 bus_num;
158 u16 num_cs; /* supported slave numbers */
159 void (*set_cs)(struct spi_device *spi, bool enable);
160
161 /* Current message transfer state info */
162 void *tx;
163 unsigned int tx_len;
164 void *rx;
165 unsigned int rx_len;
166 u8 buf[SPI_BUF_SIZE];
167 int dma_mapped;
168 u8 n_bytes; /* current is a 1/2 bytes op */
169 irqreturn_t (*transfer_handler)(struct dw_spi *dws);
170 u32 current_freq; /* frequency in hz */
171 u32 cur_rx_sample_dly;
172 u32 def_rx_sample_dly_ns;
173
174 /* Custom memory operations */
175 struct spi_controller_mem_ops mem_ops;
176
177 /* DMA info */
178 struct dma_chan *txchan;
179 u32 txburst;
180 struct dma_chan *rxchan;
181 u32 rxburst;
182 u32 dma_sg_burst;
183 unsigned long dma_chan_busy;
184 dma_addr_t dma_addr; /* phy address of the Data register */
185 const struct dw_spi_dma_ops *dma_ops;
186 struct completion dma_completion;
187
188 #ifdef CONFIG_DEBUG_FS
189 struct dentry *debugfs;
190 struct debugfs_regset32 regset;
191 #endif
192 };
193
dw_readl(struct dw_spi * dws,u32 offset)194 static inline u32 dw_readl(struct dw_spi *dws, u32 offset)
195 {
196 return __raw_readl(dws->regs + offset);
197 }
198
dw_writel(struct dw_spi * dws,u32 offset,u32 val)199 static inline void dw_writel(struct dw_spi *dws, u32 offset, u32 val)
200 {
201 __raw_writel(val, dws->regs + offset);
202 }
203
dw_read_io_reg(struct dw_spi * dws,u32 offset)204 static inline u32 dw_read_io_reg(struct dw_spi *dws, u32 offset)
205 {
206 switch (dws->reg_io_width) {
207 case 2:
208 return readw_relaxed(dws->regs + offset);
209 case 4:
210 default:
211 return readl_relaxed(dws->regs + offset);
212 }
213 }
214
dw_write_io_reg(struct dw_spi * dws,u32 offset,u32 val)215 static inline void dw_write_io_reg(struct dw_spi *dws, u32 offset, u32 val)
216 {
217 switch (dws->reg_io_width) {
218 case 2:
219 writew_relaxed(val, dws->regs + offset);
220 break;
221 case 4:
222 default:
223 writel_relaxed(val, dws->regs + offset);
224 break;
225 }
226 }
227
spi_enable_chip(struct dw_spi * dws,int enable)228 static inline void spi_enable_chip(struct dw_spi *dws, int enable)
229 {
230 dw_writel(dws, DW_SPI_SSIENR, (enable ? 1 : 0));
231 }
232
spi_set_clk(struct dw_spi * dws,u16 div)233 static inline void spi_set_clk(struct dw_spi *dws, u16 div)
234 {
235 dw_writel(dws, DW_SPI_BAUDR, div);
236 }
237
238 /* Disable IRQ bits */
spi_mask_intr(struct dw_spi * dws,u32 mask)239 static inline void spi_mask_intr(struct dw_spi *dws, u32 mask)
240 {
241 u32 new_mask;
242
243 new_mask = dw_readl(dws, DW_SPI_IMR) & ~mask;
244 dw_writel(dws, DW_SPI_IMR, new_mask);
245 }
246
247 /* Enable IRQ bits */
spi_umask_intr(struct dw_spi * dws,u32 mask)248 static inline void spi_umask_intr(struct dw_spi *dws, u32 mask)
249 {
250 u32 new_mask;
251
252 new_mask = dw_readl(dws, DW_SPI_IMR) | mask;
253 dw_writel(dws, DW_SPI_IMR, new_mask);
254 }
255
256 /*
257 * This disables the SPI controller, interrupts, clears the interrupts status
258 * and CS, then re-enables the controller back. Transmit and receive FIFO
259 * buffers are cleared when the device is disabled.
260 */
spi_reset_chip(struct dw_spi * dws)261 static inline void spi_reset_chip(struct dw_spi *dws)
262 {
263 spi_enable_chip(dws, 0);
264 spi_mask_intr(dws, 0xff);
265 dw_readl(dws, DW_SPI_ICR);
266 dw_writel(dws, DW_SPI_SER, 0);
267 spi_enable_chip(dws, 1);
268 }
269
spi_shutdown_chip(struct dw_spi * dws)270 static inline void spi_shutdown_chip(struct dw_spi *dws)
271 {
272 spi_enable_chip(dws, 0);
273 spi_set_clk(dws, 0);
274 }
275
276 extern void dw_spi_set_cs(struct spi_device *spi, bool enable);
277 extern void dw_spi_update_config(struct dw_spi *dws, struct spi_device *spi,
278 struct dw_spi_cfg *cfg);
279 extern int dw_spi_check_status(struct dw_spi *dws, bool raw);
280 extern int dw_spi_add_host(struct device *dev, struct dw_spi *dws);
281 extern void dw_spi_remove_host(struct dw_spi *dws);
282 extern int dw_spi_suspend_host(struct dw_spi *dws);
283 extern int dw_spi_resume_host(struct dw_spi *dws);
284
285 #ifdef CONFIG_SPI_DW_DMA
286
287 extern void dw_spi_dma_setup_mfld(struct dw_spi *dws);
288 extern void dw_spi_dma_setup_generic(struct dw_spi *dws);
289
290 #else
291
dw_spi_dma_setup_mfld(struct dw_spi * dws)292 static inline void dw_spi_dma_setup_mfld(struct dw_spi *dws) {}
dw_spi_dma_setup_generic(struct dw_spi * dws)293 static inline void dw_spi_dma_setup_generic(struct dw_spi *dws) {}
294
295 #endif /* !CONFIG_SPI_DW_DMA */
296
297 #endif /* DW_SPI_HEADER_H */
298