1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Copyright (C) Freescale Semicondutor, Inc. 2006-2009. All rights reserved. 4 * 5 * Author: Shlomi Gridish <gridish@freescale.com> 6 * 7 * Description: 8 * Internal header file for UCC Gigabit Ethernet unit routines. 9 * 10 * Changelog: 11 * Jun 28, 2006 Li Yang <LeoLi@freescale.com> 12 * - Rearrange code and style fixes 13 */ 14 #ifndef __UCC_GETH_H__ 15 #define __UCC_GETH_H__ 16 17 #include <linux/kernel.h> 18 #include <linux/list.h> 19 #include <linux/if_ether.h> 20 21 #include <soc/fsl/qe/immap_qe.h> 22 #include <soc/fsl/qe/qe.h> 23 24 #include <soc/fsl/qe/ucc.h> 25 #include <soc/fsl/qe/ucc_fast.h> 26 27 #define DRV_DESC "QE UCC Gigabit Ethernet Controller" 28 #define DRV_NAME "ucc_geth" 29 30 #define NUM_TX_QUEUES 8 31 #define NUM_RX_QUEUES 8 32 #define NUM_BDS_IN_PREFETCHED_BDS 4 33 #define TX_IP_OFFSET_ENTRY_MAX 8 34 #define NUM_OF_PADDRS 4 35 #define ENET_INIT_PARAM_MAX_ENTRIES_RX 9 36 #define ENET_INIT_PARAM_MAX_ENTRIES_TX 8 37 38 struct ucc_geth { 39 struct ucc_fast uccf; 40 u8 res0[0x100 - sizeof(struct ucc_fast)]; 41 42 u32 maccfg1; /* mac configuration reg. 1 */ 43 u32 maccfg2; /* mac configuration reg. 2 */ 44 u32 ipgifg; /* interframe gap reg. */ 45 u32 hafdup; /* half-duplex reg. */ 46 u8 res1[0x10]; 47 u8 miimng[0x18]; /* MII management structure moved to _mii.h */ 48 u32 ifctl; /* interface control reg */ 49 u32 ifstat; /* interface statux reg */ 50 u32 macstnaddr1; /* mac station address part 1 reg */ 51 u32 macstnaddr2; /* mac station address part 2 reg */ 52 u8 res2[0x8]; 53 u32 uempr; /* UCC Ethernet Mac parameter reg */ 54 u32 utbipar; /* UCC tbi address reg */ 55 u16 uescr; /* UCC Ethernet statistics control reg */ 56 u8 res3[0x180 - 0x15A]; 57 u32 tx64; /* Total number of frames (including bad 58 frames) transmitted that were exactly of the 59 minimal length (64 for un tagged, 68 for 60 tagged, or with length exactly equal to the 61 parameter MINLength */ 62 u32 tx127; /* Total number of frames (including bad 63 frames) transmitted that were between 64 MINLength (Including FCS length==4) and 127 65 octets */ 66 u32 tx255; /* Total number of frames (including bad 67 frames) transmitted that were between 128 68 (Including FCS length==4) and 255 octets */ 69 u32 rx64; /* Total number of frames received including 70 bad frames that were exactly of the mninimal 71 length (64 bytes) */ 72 u32 rx127; /* Total number of frames (including bad 73 frames) received that were between MINLength 74 (Including FCS length==4) and 127 octets */ 75 u32 rx255; /* Total number of frames (including bad 76 frames) received that were between 128 77 (Including FCS length==4) and 255 octets */ 78 u32 txok; /* Total number of octets residing in frames 79 that where involved in successful 80 transmission */ 81 u16 txcf; /* Total number of PAUSE control frames 82 transmitted by this MAC */ 83 u8 res4[0x2]; 84 u32 tmca; /* Total number of frames that were transmitted 85 successfully with the group address bit set 86 that are not broadcast frames */ 87 u32 tbca; /* Total number of frames transmitted 88 successfully that had destination address 89 field equal to the broadcast address */ 90 u32 rxfok; /* Total number of frames received OK */ 91 u32 rxbok; /* Total number of octets received OK */ 92 u32 rbyt; /* Total number of octets received including 93 octets in bad frames. Must be implemented in 94 HW because it includes octets in frames that 95 never even reach the UCC */ 96 u32 rmca; /* Total number of frames that were received 97 successfully with the group address bit set 98 that are not broadcast frames */ 99 u32 rbca; /* Total number of frames received successfully 100 that had destination address equal to the 101 broadcast address */ 102 u32 scar; /* Statistics carry register */ 103 u32 scam; /* Statistics caryy mask register */ 104 u8 res5[0x200 - 0x1c4]; 105 } __packed; 106 107 /* UCC GETH TEMODR Register */ 108 #define TEMODER_TX_RMON_STATISTICS_ENABLE 0x0100 /* enable Tx statistics 109 */ 110 #define TEMODER_SCHEDULER_ENABLE 0x2000 /* enable scheduler */ 111 #define TEMODER_IP_CHECKSUM_GENERATE 0x0400 /* generate IPv4 112 checksums */ 113 #define TEMODER_PERFORMANCE_OPTIMIZATION_MODE1 0x0200 /* enable performance 114 optimization 115 enhancement (mode1) */ 116 #define TEMODER_RMON_STATISTICS 0x0100 /* enable tx statistics 117 */ 118 #define TEMODER_NUM_OF_QUEUES_SHIFT (15-15) /* Number of queues << 119 shift */ 120 121 /* UCC GETH TEMODR Register */ 122 #define REMODER_RX_RMON_STATISTICS_ENABLE 0x00001000 /* enable Rx 123 statistics */ 124 #define REMODER_RX_EXTENDED_FEATURES 0x80000000 /* enable 125 extended 126 features */ 127 #define REMODER_VLAN_OPERATION_TAGGED_SHIFT (31-9 ) /* vlan operation 128 tagged << shift */ 129 #define REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT (31-10) /* vlan operation non 130 tagged << shift */ 131 #define REMODER_RX_QOS_MODE_SHIFT (31-15) /* rx QoS mode << shift 132 */ 133 #define REMODER_RMON_STATISTICS 0x00001000 /* enable rx 134 statistics */ 135 #define REMODER_RX_EXTENDED_FILTERING 0x00000800 /* extended 136 filtering 137 vs. 138 mpc82xx-like 139 filtering */ 140 #define REMODER_NUM_OF_QUEUES_SHIFT (31-23) /* Number of queues << 141 shift */ 142 #define REMODER_DYNAMIC_MAX_FRAME_LENGTH 0x00000008 /* enable 143 dynamic max 144 frame length 145 */ 146 #define REMODER_DYNAMIC_MIN_FRAME_LENGTH 0x00000004 /* enable 147 dynamic min 148 frame length 149 */ 150 #define REMODER_IP_CHECKSUM_CHECK 0x00000002 /* check IPv4 151 checksums */ 152 #define REMODER_IP_ADDRESS_ALIGNMENT 0x00000001 /* align ip 153 address to 154 4-byte 155 boundary */ 156 157 /* UCC GETH Event Register */ 158 #define UCCE_TXB (UCC_GETH_UCCE_TXB7 | UCC_GETH_UCCE_TXB6 | \ 159 UCC_GETH_UCCE_TXB5 | UCC_GETH_UCCE_TXB4 | \ 160 UCC_GETH_UCCE_TXB3 | UCC_GETH_UCCE_TXB2 | \ 161 UCC_GETH_UCCE_TXB1 | UCC_GETH_UCCE_TXB0) 162 163 #define UCCE_RXB (UCC_GETH_UCCE_RXB7 | UCC_GETH_UCCE_RXB6 | \ 164 UCC_GETH_UCCE_RXB5 | UCC_GETH_UCCE_RXB4 | \ 165 UCC_GETH_UCCE_RXB3 | UCC_GETH_UCCE_RXB2 | \ 166 UCC_GETH_UCCE_RXB1 | UCC_GETH_UCCE_RXB0) 167 168 #define UCCE_RXF (UCC_GETH_UCCE_RXF7 | UCC_GETH_UCCE_RXF6 | \ 169 UCC_GETH_UCCE_RXF5 | UCC_GETH_UCCE_RXF4 | \ 170 UCC_GETH_UCCE_RXF3 | UCC_GETH_UCCE_RXF2 | \ 171 UCC_GETH_UCCE_RXF1 | UCC_GETH_UCCE_RXF0) 172 173 #define UCCE_OTHER (UCC_GETH_UCCE_SCAR | UCC_GETH_UCCE_GRA | \ 174 UCC_GETH_UCCE_CBPR | UCC_GETH_UCCE_BSY | \ 175 UCC_GETH_UCCE_RXC | UCC_GETH_UCCE_TXC | UCC_GETH_UCCE_TXE) 176 177 #define UCCE_RX_EVENTS (UCCE_RXF | UCC_GETH_UCCE_BSY) 178 #define UCCE_TX_EVENTS (UCCE_TXB | UCC_GETH_UCCE_TXE) 179 180 /* TBI defines */ 181 #define ENET_TBI_MII_CR 0x00 /* Control */ 182 #define ENET_TBI_MII_SR 0x01 /* Status */ 183 #define ENET_TBI_MII_ANA 0x04 /* AN advertisement */ 184 #define ENET_TBI_MII_ANLPBPA 0x05 /* AN link partner base page ability */ 185 #define ENET_TBI_MII_ANEX 0x06 /* AN expansion */ 186 #define ENET_TBI_MII_ANNPT 0x07 /* AN next page transmit */ 187 #define ENET_TBI_MII_ANLPANP 0x08 /* AN link partner ability next page */ 188 #define ENET_TBI_MII_EXST 0x0F /* Extended status */ 189 #define ENET_TBI_MII_JD 0x10 /* Jitter diagnostics */ 190 #define ENET_TBI_MII_TBICON 0x11 /* TBI control */ 191 192 /* TBI MDIO register bit fields*/ 193 #define TBISR_LSTATUS 0x0004 194 #define TBICON_CLK_SELECT 0x0020 195 #define TBIANA_ASYMMETRIC_PAUSE 0x0100 196 #define TBIANA_SYMMETRIC_PAUSE 0x0080 197 #define TBIANA_HALF_DUPLEX 0x0040 198 #define TBIANA_FULL_DUPLEX 0x0020 199 #define TBICR_PHY_RESET 0x8000 200 #define TBICR_ANEG_ENABLE 0x1000 201 #define TBICR_RESTART_ANEG 0x0200 202 #define TBICR_FULL_DUPLEX 0x0100 203 #define TBICR_SPEED1_SET 0x0040 204 205 #define TBIANA_SETTINGS ( \ 206 TBIANA_ASYMMETRIC_PAUSE \ 207 | TBIANA_SYMMETRIC_PAUSE \ 208 | TBIANA_FULL_DUPLEX \ 209 ) 210 #define TBICR_SETTINGS ( \ 211 TBICR_PHY_RESET \ 212 | TBICR_ANEG_ENABLE \ 213 | TBICR_FULL_DUPLEX \ 214 | TBICR_SPEED1_SET \ 215 ) 216 217 /* UCC GETH MACCFG1 (MAC Configuration 1 Register) */ 218 #define MACCFG1_FLOW_RX 0x00000020 /* Flow Control 219 Rx */ 220 #define MACCFG1_FLOW_TX 0x00000010 /* Flow Control 221 Tx */ 222 #define MACCFG1_ENABLE_SYNCHED_RX 0x00000008 /* Rx Enable 223 synchronized 224 to Rx stream 225 */ 226 #define MACCFG1_ENABLE_RX 0x00000004 /* Enable Rx */ 227 #define MACCFG1_ENABLE_SYNCHED_TX 0x00000002 /* Tx Enable 228 synchronized 229 to Tx stream 230 */ 231 #define MACCFG1_ENABLE_TX 0x00000001 /* Enable Tx */ 232 233 /* UCC GETH MACCFG2 (MAC Configuration 2 Register) */ 234 #define MACCFG2_PREL_SHIFT (31 - 19) /* Preamble 235 Length << 236 shift */ 237 #define MACCFG2_PREL_MASK 0x0000f000 /* Preamble 238 Length mask */ 239 #define MACCFG2_SRP 0x00000080 /* Soft Receive 240 Preamble */ 241 #define MACCFG2_STP 0x00000040 /* Soft 242 Transmit 243 Preamble */ 244 #define MACCFG2_RESERVED_1 0x00000020 /* Reserved - 245 must be set 246 to 1 */ 247 #define MACCFG2_LC 0x00000010 /* Length Check 248 */ 249 #define MACCFG2_MPE 0x00000008 /* Magic packet 250 detect */ 251 #define MACCFG2_FDX 0x00000001 /* Full Duplex */ 252 #define MACCFG2_FDX_MASK 0x00000001 /* Full Duplex 253 mask */ 254 #define MACCFG2_PAD_CRC 0x00000004 255 #define MACCFG2_CRC_EN 0x00000002 256 #define MACCFG2_PAD_AND_CRC_MODE_NONE 0x00000000 /* Neither 257 Padding 258 short frames 259 nor CRC */ 260 #define MACCFG2_PAD_AND_CRC_MODE_CRC_ONLY 0x00000002 /* Append CRC 261 only */ 262 #define MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC 0x00000004 263 #define MACCFG2_INTERFACE_MODE_NIBBLE 0x00000100 /* nibble mode 264 (MII/RMII/RGMII 265 10/100bps) */ 266 #define MACCFG2_INTERFACE_MODE_BYTE 0x00000200 /* byte mode 267 (GMII/TBI/RTB/RGMII 268 1000bps ) */ 269 #define MACCFG2_INTERFACE_MODE_MASK 0x00000300 /* mask 270 covering all 271 relevant 272 bits */ 273 274 /* UCC GETH IPGIFG (Inter-frame Gap / Inter-Frame Gap Register) */ 275 #define IPGIFG_NON_BACK_TO_BACK_IFG_PART1_SHIFT (31 - 7) /* Non 276 back-to-back 277 inter frame 278 gap part 1. 279 << shift */ 280 #define IPGIFG_NON_BACK_TO_BACK_IFG_PART2_SHIFT (31 - 15) /* Non 281 back-to-back 282 inter frame 283 gap part 2. 284 << shift */ 285 #define IPGIFG_MINIMUM_IFG_ENFORCEMENT_SHIFT (31 - 23) /* Mimimum IFG 286 Enforcement 287 << shift */ 288 #define IPGIFG_BACK_TO_BACK_IFG_SHIFT (31 - 31) /* back-to-back 289 inter frame 290 gap << shift 291 */ 292 #define IPGIFG_NON_BACK_TO_BACK_IFG_PART1_MAX 127 /* Non back-to-back 293 inter frame gap part 294 1. max val */ 295 #define IPGIFG_NON_BACK_TO_BACK_IFG_PART2_MAX 127 /* Non back-to-back 296 inter frame gap part 297 2. max val */ 298 #define IPGIFG_MINIMUM_IFG_ENFORCEMENT_MAX 255 /* Mimimum IFG 299 Enforcement max val */ 300 #define IPGIFG_BACK_TO_BACK_IFG_MAX 127 /* back-to-back inter 301 frame gap max val */ 302 #define IPGIFG_NBTB_CS_IPG_MASK 0x7F000000 303 #define IPGIFG_NBTB_IPG_MASK 0x007F0000 304 #define IPGIFG_MIN_IFG_MASK 0x0000FF00 305 #define IPGIFG_BTB_IPG_MASK 0x0000007F 306 307 /* UCC GETH HAFDUP (Half Duplex Register) */ 308 #define HALFDUP_ALT_BEB_TRUNCATION_SHIFT (31 - 11) /* Alternate 309 Binary 310 Exponential 311 Backoff 312 Truncation 313 << shift */ 314 #define HALFDUP_ALT_BEB_TRUNCATION_MAX 0xf /* Alternate Binary 315 Exponential Backoff 316 Truncation max val */ 317 #define HALFDUP_ALT_BEB 0x00080000 /* Alternate 318 Binary 319 Exponential 320 Backoff */ 321 #define HALFDUP_BACK_PRESSURE_NO_BACKOFF 0x00040000 /* Back 322 pressure no 323 backoff */ 324 #define HALFDUP_NO_BACKOFF 0x00020000 /* No Backoff */ 325 #define HALFDUP_EXCESSIVE_DEFER 0x00010000 /* Excessive 326 Defer */ 327 #define HALFDUP_MAX_RETRANSMISSION_SHIFT (31 - 19) /* Maximum 328 Retransmission 329 << shift */ 330 #define HALFDUP_MAX_RETRANSMISSION_MAX 0xf /* Maximum 331 Retransmission max 332 val */ 333 #define HALFDUP_COLLISION_WINDOW_SHIFT (31 - 31) /* Collision 334 Window << 335 shift */ 336 #define HALFDUP_COLLISION_WINDOW_MAX 0x3f /* Collision Window max 337 val */ 338 #define HALFDUP_ALT_BEB_TR_MASK 0x00F00000 339 #define HALFDUP_RETRANS_MASK 0x0000F000 340 #define HALFDUP_COL_WINDOW_MASK 0x0000003F 341 342 /* UCC GETH UCCS (Ethernet Status Register) */ 343 #define UCCS_BPR 0x02 /* Back pressure (in 344 half duplex mode) */ 345 #define UCCS_PAU 0x02 /* Pause state (in full 346 duplex mode) */ 347 #define UCCS_MPD 0x01 /* Magic Packet 348 Detected */ 349 350 /* UCC GETH IFSTAT (Interface Status Register) */ 351 #define IFSTAT_EXCESS_DEFER 0x00000200 /* Excessive 352 transmission 353 defer */ 354 355 /* UCC GETH MACSTNADDR1 (Station Address Part 1 Register) */ 356 #define MACSTNADDR1_OCTET_6_SHIFT (31 - 7) /* Station 357 address 6th 358 octet << 359 shift */ 360 #define MACSTNADDR1_OCTET_5_SHIFT (31 - 15) /* Station 361 address 5th 362 octet << 363 shift */ 364 #define MACSTNADDR1_OCTET_4_SHIFT (31 - 23) /* Station 365 address 4th 366 octet << 367 shift */ 368 #define MACSTNADDR1_OCTET_3_SHIFT (31 - 31) /* Station 369 address 3rd 370 octet << 371 shift */ 372 373 /* UCC GETH MACSTNADDR2 (Station Address Part 2 Register) */ 374 #define MACSTNADDR2_OCTET_2_SHIFT (31 - 7) /* Station 375 address 2nd 376 octet << 377 shift */ 378 #define MACSTNADDR2_OCTET_1_SHIFT (31 - 15) /* Station 379 address 1st 380 octet << 381 shift */ 382 383 /* UCC GETH UEMPR (Ethernet Mac Parameter Register) */ 384 #define UEMPR_PAUSE_TIME_VALUE_SHIFT (31 - 15) /* Pause time 385 value << 386 shift */ 387 #define UEMPR_EXTENDED_PAUSE_TIME_VALUE_SHIFT (31 - 31) /* Extended 388 pause time 389 value << 390 shift */ 391 392 /* UCC GETH UTBIPAR (Ten Bit Interface Physical Address Register) */ 393 #define UTBIPAR_PHY_ADDRESS_SHIFT (31 - 31) /* Phy address 394 << shift */ 395 #define UTBIPAR_PHY_ADDRESS_MASK 0x0000001f /* Phy address 396 mask */ 397 398 /* UCC GETH UESCR (Ethernet Statistics Control Register) */ 399 #define UESCR_AUTOZ 0x8000 /* Automatically zero 400 addressed 401 statistical counter 402 values */ 403 #define UESCR_CLRCNT 0x4000 /* Clear all statistics 404 counters */ 405 #define UESCR_MAXCOV_SHIFT (15 - 7) /* Max 406 Coalescing 407 Value << 408 shift */ 409 #define UESCR_SCOV_SHIFT (15 - 15) /* Status 410 Coalescing 411 Value << 412 shift */ 413 414 /* UCC GETH UDSR (Data Synchronization Register) */ 415 #define UDSR_MAGIC 0x067E 416 417 struct ucc_geth_thread_data_tx { 418 u8 res0[104]; 419 } __packed; 420 421 struct ucc_geth_thread_data_rx { 422 u8 res0[40]; 423 } __packed; 424 425 /* Send Queue Queue-Descriptor */ 426 struct ucc_geth_send_queue_qd { 427 u32 bd_ring_base; /* pointer to BD ring base address */ 428 u8 res0[0x8]; 429 u32 last_bd_completed_address;/* initialize to last entry in BD ring */ 430 u8 res1[0x30]; 431 } __packed; 432 433 struct ucc_geth_send_queue_mem_region { 434 struct ucc_geth_send_queue_qd sqqd[NUM_TX_QUEUES]; 435 } __packed; 436 437 struct ucc_geth_thread_tx_pram { 438 u8 res0[64]; 439 } __packed; 440 441 struct ucc_geth_thread_rx_pram { 442 u8 res0[128]; 443 } __packed; 444 445 #define THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING 64 446 #define THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8 64 447 #define THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16 96 448 449 struct ucc_geth_scheduler { 450 u16 cpucount0; /* CPU packet counter */ 451 u16 cpucount1; /* CPU packet counter */ 452 u16 cecount0; /* QE packet counter */ 453 u16 cecount1; /* QE packet counter */ 454 u16 cpucount2; /* CPU packet counter */ 455 u16 cpucount3; /* CPU packet counter */ 456 u16 cecount2; /* QE packet counter */ 457 u16 cecount3; /* QE packet counter */ 458 u16 cpucount4; /* CPU packet counter */ 459 u16 cpucount5; /* CPU packet counter */ 460 u16 cecount4; /* QE packet counter */ 461 u16 cecount5; /* QE packet counter */ 462 u16 cpucount6; /* CPU packet counter */ 463 u16 cpucount7; /* CPU packet counter */ 464 u16 cecount6; /* QE packet counter */ 465 u16 cecount7; /* QE packet counter */ 466 u32 weightstatus[NUM_TX_QUEUES]; /* accumulated weight factor */ 467 u32 rtsrshadow; /* temporary variable handled by QE */ 468 u32 time; /* temporary variable handled by QE */ 469 u32 ttl; /* temporary variable handled by QE */ 470 u32 mblinterval; /* max burst length interval */ 471 u16 nortsrbytetime; /* normalized value of byte time in tsr units */ 472 u8 fracsiz; /* radix 2 log value of denom. of 473 NorTSRByteTime */ 474 u8 res0[1]; 475 u8 strictpriorityq; /* Strict Priority Mask register */ 476 u8 txasap; /* Transmit ASAP register */ 477 u8 extrabw; /* Extra BandWidth register */ 478 u8 oldwfqmask; /* temporary variable handled by QE */ 479 u8 weightfactor[NUM_TX_QUEUES]; 480 /**< weight factor for queues */ 481 u32 minw; /* temporary variable handled by QE */ 482 u8 res1[0x70 - 0x64]; 483 } __packed; 484 485 struct ucc_geth_tx_firmware_statistics_pram { 486 u32 sicoltx; /* single collision */ 487 u32 mulcoltx; /* multiple collision */ 488 u32 latecoltxfr; /* late collision */ 489 u32 frabortduecol; /* frames aborted due to transmit collision */ 490 u32 frlostinmactxer; /* frames lost due to internal MAC error 491 transmission that are not counted on any 492 other counter */ 493 u32 carriersenseertx; /* carrier sense error */ 494 u32 frtxok; /* frames transmitted OK */ 495 u32 txfrexcessivedefer; /* frames with defferal time greater than 496 specified threshold */ 497 u32 txpkts256; /* total packets (including bad) between 256 498 and 511 octets */ 499 u32 txpkts512; /* total packets (including bad) between 512 500 and 1023 octets */ 501 u32 txpkts1024; /* total packets (including bad) between 1024 502 and 1518 octets */ 503 u32 txpktsjumbo; /* total packets (including bad) between 1024 504 and MAXLength octets */ 505 } __packed; 506 507 struct ucc_geth_rx_firmware_statistics_pram { 508 u32 frrxfcser; /* frames with crc error */ 509 u32 fraligner; /* frames with alignment error */ 510 u32 inrangelenrxer; /* in range length error */ 511 u32 outrangelenrxer; /* out of range length error */ 512 u32 frtoolong; /* frame too long */ 513 u32 runt; /* runt */ 514 u32 verylongevent; /* very long event */ 515 u32 symbolerror; /* symbol error */ 516 u32 dropbsy; /* drop because of BD not ready */ 517 u8 res0[0x8]; 518 u32 mismatchdrop; /* drop because of MAC filtering (e.g. address 519 or type mismatch) */ 520 u32 underpkts; /* total frames less than 64 octets */ 521 u32 pkts256; /* total frames (including bad) between 256 and 522 511 octets */ 523 u32 pkts512; /* total frames (including bad) between 512 and 524 1023 octets */ 525 u32 pkts1024; /* total frames (including bad) between 1024 526 and 1518 octets */ 527 u32 pktsjumbo; /* total frames (including bad) between 1024 528 and MAXLength octets */ 529 u32 frlossinmacer; /* frames lost because of internal MAC error 530 that is not counted in any other counter */ 531 u32 pausefr; /* pause frames */ 532 u8 res1[0x4]; 533 u32 removevlan; /* total frames that had their VLAN tag removed 534 */ 535 u32 replacevlan; /* total frames that had their VLAN tag 536 replaced */ 537 u32 insertvlan; /* total frames that had their VLAN tag 538 inserted */ 539 } __packed; 540 541 struct ucc_geth_rx_interrupt_coalescing_entry { 542 u32 interruptcoalescingmaxvalue; /* interrupt coalescing max 543 value */ 544 u32 interruptcoalescingcounter; /* interrupt coalescing counter, 545 initialize to 546 interruptcoalescingmaxvalue */ 547 } __packed; 548 549 struct ucc_geth_rx_interrupt_coalescing_table { 550 struct ucc_geth_rx_interrupt_coalescing_entry coalescingentry[NUM_RX_QUEUES]; 551 /**< interrupt coalescing entry */ 552 } __packed; 553 554 struct ucc_geth_rx_prefetched_bds { 555 struct qe_bd bd[NUM_BDS_IN_PREFETCHED_BDS]; /* prefetched bd */ 556 } __packed; 557 558 struct ucc_geth_rx_bd_queues_entry { 559 u32 bdbaseptr; /* BD base pointer */ 560 u32 bdptr; /* BD pointer */ 561 u32 externalbdbaseptr; /* external BD base pointer */ 562 u32 externalbdptr; /* external BD pointer */ 563 } __packed; 564 565 struct ucc_geth_tx_global_pram { 566 u16 temoder; 567 u8 res0[0x38 - 0x02]; 568 u32 sqptr; /* a base pointer to send queue memory region */ 569 u32 schedulerbasepointer; /* a base pointer to scheduler memory 570 region */ 571 u32 txrmonbaseptr; /* base pointer to Tx RMON statistics counter */ 572 u32 tstate; /* tx internal state. High byte contains 573 function code */ 574 u8 iphoffset[TX_IP_OFFSET_ENTRY_MAX]; 575 u32 vtagtable[0x8]; /* 8 4-byte VLAN tags */ 576 u32 tqptr; /* a base pointer to the Tx Queues Memory 577 Region */ 578 u8 res2[0x78 - 0x74]; 579 u64 snums_en; 580 u32 l2l3baseptr; /* top byte consists of a few other bit fields */ 581 582 u16 mtu[8]; 583 u8 res3[0xa8 - 0x94]; 584 u32 wrrtablebase; /* top byte is reserved */ 585 u8 res4[0xc0 - 0xac]; 586 } __packed; 587 588 /* structure representing Extended Filtering Global Parameters in PRAM */ 589 struct ucc_geth_exf_global_pram { 590 u32 l2pcdptr; /* individual address filter, high */ 591 u8 res0[0x10 - 0x04]; 592 } __packed; 593 594 struct ucc_geth_rx_global_pram { 595 u32 remoder; /* ethernet mode reg. */ 596 u32 rqptr; /* base pointer to the Rx Queues Memory Region*/ 597 u32 res0[0x1]; 598 u8 res1[0x20 - 0xC]; 599 u16 typeorlen; /* cutoff point less than which, type/len field 600 is considered length */ 601 u8 res2[0x1]; 602 u8 rxgstpack; /* acknowledgement on GRACEFUL STOP RX command*/ 603 u32 rxrmonbaseptr; /* base pointer to Rx RMON statistics counter */ 604 u8 res3[0x30 - 0x28]; 605 u32 intcoalescingptr; /* Interrupt coalescing table pointer */ 606 u8 res4[0x36 - 0x34]; 607 u8 rstate; /* rx internal state. High byte contains 608 function code */ 609 u8 res5[0x46 - 0x37]; 610 u16 mrblr; /* max receive buffer length reg. */ 611 u32 rbdqptr; /* base pointer to RxBD parameter table 612 description */ 613 u16 mflr; /* max frame length reg. */ 614 u16 minflr; /* min frame length reg. */ 615 u16 maxd1; /* max dma1 length reg. */ 616 u16 maxd2; /* max dma2 length reg. */ 617 u32 ecamptr; /* external CAM address */ 618 u32 l2qt; /* VLAN priority mapping table. */ 619 u32 l3qt[0x8]; /* IP priority mapping table. */ 620 u16 vlantype; /* vlan type */ 621 u16 vlantci; /* default vlan tci */ 622 u8 addressfiltering[64]; /* address filtering data structure */ 623 u32 exfGlobalParam; /* base address for extended filtering global 624 parameters */ 625 u8 res6[0x100 - 0xC4]; /* Initialize to zero */ 626 } __packed; 627 628 #define GRACEFUL_STOP_ACKNOWLEDGE_RX 0x01 629 630 /* structure representing InitEnet command */ 631 struct ucc_geth_init_pram { 632 u8 resinit1; 633 u8 resinit2; 634 u8 resinit3; 635 u8 resinit4; 636 u16 resinit5; 637 u8 res1[0x1]; 638 u8 largestexternallookupkeysize; 639 u32 rgftgfrxglobal; 640 u32 rxthread[ENET_INIT_PARAM_MAX_ENTRIES_RX]; /* rx threads */ 641 u8 res2[0x38 - 0x30]; 642 u32 txglobal; /* tx global */ 643 u32 txthread[ENET_INIT_PARAM_MAX_ENTRIES_TX]; /* tx threads */ 644 u8 res3[0x1]; 645 } __packed; 646 647 #define ENET_INIT_PARAM_RGF_SHIFT (32 - 4) 648 #define ENET_INIT_PARAM_TGF_SHIFT (32 - 8) 649 650 #define ENET_INIT_PARAM_RISC_MASK 0x0000003f 651 #define ENET_INIT_PARAM_PTR_MASK 0x00ffffc0 652 #define ENET_INIT_PARAM_SNUM_MASK 0xff000000 653 #define ENET_INIT_PARAM_SNUM_SHIFT 24 654 655 #define ENET_INIT_PARAM_MAGIC_RES_INIT1 0x06 656 #define ENET_INIT_PARAM_MAGIC_RES_INIT2 0x30 657 #define ENET_INIT_PARAM_MAGIC_RES_INIT3 0xff 658 #define ENET_INIT_PARAM_MAGIC_RES_INIT4 0x00 659 #define ENET_INIT_PARAM_MAGIC_RES_INIT5 0x0400 660 661 /* structure representing 82xx Address Filtering Enet Address in PRAM */ 662 struct ucc_geth_82xx_enet_address { 663 u8 res1[0x2]; 664 u16 h; /* address (MSB) */ 665 u16 m; /* address */ 666 u16 l; /* address (LSB) */ 667 } __packed; 668 669 /* structure representing 82xx Address Filtering PRAM */ 670 struct ucc_geth_82xx_address_filtering_pram { 671 u32 iaddr_h; /* individual address filter, high */ 672 u32 iaddr_l; /* individual address filter, low */ 673 u32 gaddr_h; /* group address filter, high */ 674 u32 gaddr_l; /* group address filter, low */ 675 struct ucc_geth_82xx_enet_address __iomem taddr; 676 struct ucc_geth_82xx_enet_address __iomem paddr[NUM_OF_PADDRS]; 677 u8 res0[0x40 - 0x38]; 678 } __packed; 679 680 /* GETH Tx firmware statistics structure, used when calling 681 UCC_GETH_GetStatistics. */ 682 struct ucc_geth_tx_firmware_statistics { 683 u32 sicoltx; /* single collision */ 684 u32 mulcoltx; /* multiple collision */ 685 u32 latecoltxfr; /* late collision */ 686 u32 frabortduecol; /* frames aborted due to transmit collision */ 687 u32 frlostinmactxer; /* frames lost due to internal MAC error 688 transmission that are not counted on any 689 other counter */ 690 u32 carriersenseertx; /* carrier sense error */ 691 u32 frtxok; /* frames transmitted OK */ 692 u32 txfrexcessivedefer; /* frames with defferal time greater than 693 specified threshold */ 694 u32 txpkts256; /* total packets (including bad) between 256 695 and 511 octets */ 696 u32 txpkts512; /* total packets (including bad) between 512 697 and 1023 octets */ 698 u32 txpkts1024; /* total packets (including bad) between 1024 699 and 1518 octets */ 700 u32 txpktsjumbo; /* total packets (including bad) between 1024 701 and MAXLength octets */ 702 } __packed; 703 704 /* GETH Rx firmware statistics structure, used when calling 705 UCC_GETH_GetStatistics. */ 706 struct ucc_geth_rx_firmware_statistics { 707 u32 frrxfcser; /* frames with crc error */ 708 u32 fraligner; /* frames with alignment error */ 709 u32 inrangelenrxer; /* in range length error */ 710 u32 outrangelenrxer; /* out of range length error */ 711 u32 frtoolong; /* frame too long */ 712 u32 runt; /* runt */ 713 u32 verylongevent; /* very long event */ 714 u32 symbolerror; /* symbol error */ 715 u32 dropbsy; /* drop because of BD not ready */ 716 u8 res0[0x8]; 717 u32 mismatchdrop; /* drop because of MAC filtering (e.g. address 718 or type mismatch) */ 719 u32 underpkts; /* total frames less than 64 octets */ 720 u32 pkts256; /* total frames (including bad) between 256 and 721 511 octets */ 722 u32 pkts512; /* total frames (including bad) between 512 and 723 1023 octets */ 724 u32 pkts1024; /* total frames (including bad) between 1024 725 and 1518 octets */ 726 u32 pktsjumbo; /* total frames (including bad) between 1024 727 and MAXLength octets */ 728 u32 frlossinmacer; /* frames lost because of internal MAC error 729 that is not counted in any other counter */ 730 u32 pausefr; /* pause frames */ 731 u8 res1[0x4]; 732 u32 removevlan; /* total frames that had their VLAN tag removed 733 */ 734 u32 replacevlan; /* total frames that had their VLAN tag 735 replaced */ 736 u32 insertvlan; /* total frames that had their VLAN tag 737 inserted */ 738 } __packed; 739 740 /* GETH hardware statistics structure, used when calling 741 UCC_GETH_GetStatistics. */ 742 struct ucc_geth_hardware_statistics { 743 u32 tx64; /* Total number of frames (including bad 744 frames) transmitted that were exactly of the 745 minimal length (64 for un tagged, 68 for 746 tagged, or with length exactly equal to the 747 parameter MINLength */ 748 u32 tx127; /* Total number of frames (including bad 749 frames) transmitted that were between 750 MINLength (Including FCS length==4) and 127 751 octets */ 752 u32 tx255; /* Total number of frames (including bad 753 frames) transmitted that were between 128 754 (Including FCS length==4) and 255 octets */ 755 u32 rx64; /* Total number of frames received including 756 bad frames that were exactly of the mninimal 757 length (64 bytes) */ 758 u32 rx127; /* Total number of frames (including bad 759 frames) received that were between MINLength 760 (Including FCS length==4) and 127 octets */ 761 u32 rx255; /* Total number of frames (including bad 762 frames) received that were between 128 763 (Including FCS length==4) and 255 octets */ 764 u32 txok; /* Total number of octets residing in frames 765 that where involved in successful 766 transmission */ 767 u16 txcf; /* Total number of PAUSE control frames 768 transmitted by this MAC */ 769 u32 tmca; /* Total number of frames that were transmitted 770 successfully with the group address bit set 771 that are not broadcast frames */ 772 u32 tbca; /* Total number of frames transmitted 773 successfully that had destination address 774 field equal to the broadcast address */ 775 u32 rxfok; /* Total number of frames received OK */ 776 u32 rxbok; /* Total number of octets received OK */ 777 u32 rbyt; /* Total number of octets received including 778 octets in bad frames. Must be implemented in 779 HW because it includes octets in frames that 780 never even reach the UCC */ 781 u32 rmca; /* Total number of frames that were received 782 successfully with the group address bit set 783 that are not broadcast frames */ 784 u32 rbca; /* Total number of frames received successfully 785 that had destination address equal to the 786 broadcast address */ 787 } __packed; 788 789 /* UCC GETH Tx errors returned via TxConf callback */ 790 #define TX_ERRORS_DEF 0x0200 791 #define TX_ERRORS_EXDEF 0x0100 792 #define TX_ERRORS_LC 0x0080 793 #define TX_ERRORS_RL 0x0040 794 #define TX_ERRORS_RC_MASK 0x003C 795 #define TX_ERRORS_RC_SHIFT 2 796 #define TX_ERRORS_UN 0x0002 797 #define TX_ERRORS_CSL 0x0001 798 799 /* UCC GETH Rx errors returned via RxStore callback */ 800 #define RX_ERRORS_CMR 0x0200 801 #define RX_ERRORS_M 0x0100 802 #define RX_ERRORS_BC 0x0080 803 #define RX_ERRORS_MC 0x0040 804 805 /* Transmit BD. These are in addition to values defined in uccf. */ 806 #define T_VID 0x003c0000 /* insert VLAN id index mask. */ 807 #define T_DEF (((u32) TX_ERRORS_DEF ) << 16) 808 #define T_EXDEF (((u32) TX_ERRORS_EXDEF ) << 16) 809 #define T_LC (((u32) TX_ERRORS_LC ) << 16) 810 #define T_RL (((u32) TX_ERRORS_RL ) << 16) 811 #define T_RC_MASK (((u32) TX_ERRORS_RC_MASK ) << 16) 812 #define T_UN (((u32) TX_ERRORS_UN ) << 16) 813 #define T_CSL (((u32) TX_ERRORS_CSL ) << 16) 814 #define T_ERRORS_REPORT (T_DEF | T_EXDEF | T_LC | T_RL | T_RC_MASK \ 815 | T_UN | T_CSL) /* transmit errors to report */ 816 817 /* Receive BD. These are in addition to values defined in uccf. */ 818 #define R_LG 0x00200000 /* Frame length violation. */ 819 #define R_NO 0x00100000 /* Non-octet aligned frame. */ 820 #define R_SH 0x00080000 /* Short frame. */ 821 #define R_CR 0x00040000 /* CRC error. */ 822 #define R_OV 0x00020000 /* Overrun. */ 823 #define R_IPCH 0x00010000 /* IP checksum check failed. */ 824 #define R_CMR (((u32) RX_ERRORS_CMR ) << 16) 825 #define R_M (((u32) RX_ERRORS_M ) << 16) 826 #define R_BC (((u32) RX_ERRORS_BC ) << 16) 827 #define R_MC (((u32) RX_ERRORS_MC ) << 16) 828 #define R_ERRORS_REPORT (R_CMR | R_M | R_BC | R_MC) /* receive errors to 829 report */ 830 #define R_ERRORS_FATAL (R_LG | R_NO | R_SH | R_CR | \ 831 R_OV | R_IPCH) /* receive errors to discard */ 832 833 /* Alignments */ 834 #define UCC_GETH_RX_GLOBAL_PRAM_ALIGNMENT 256 835 #define UCC_GETH_TX_GLOBAL_PRAM_ALIGNMENT 128 836 #define UCC_GETH_THREAD_RX_PRAM_ALIGNMENT 128 837 #define UCC_GETH_THREAD_TX_PRAM_ALIGNMENT 64 838 #define UCC_GETH_THREAD_DATA_ALIGNMENT 256 /* spec gives values 839 based on num of 840 threads, but always 841 using the maximum is 842 easier */ 843 #define UCC_GETH_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT 32 844 #define UCC_GETH_SCHEDULER_ALIGNMENT 8 /* This is a guess */ 845 #define UCC_GETH_TX_STATISTICS_ALIGNMENT 4 /* This is a guess */ 846 #define UCC_GETH_RX_STATISTICS_ALIGNMENT 4 /* This is a guess */ 847 #define UCC_GETH_RX_INTERRUPT_COALESCING_ALIGNMENT 64 848 #define UCC_GETH_RX_BD_QUEUES_ALIGNMENT 8 /* This is a guess */ 849 #define UCC_GETH_RX_PREFETCHED_BDS_ALIGNMENT 128 /* This is a guess */ 850 #define UCC_GETH_RX_EXTENDED_FILTERING_GLOBAL_PARAMETERS_ALIGNMENT 8 /* This 851 is a 852 guess 853 */ 854 #define UCC_GETH_RX_BD_RING_ALIGNMENT 32 855 #define UCC_GETH_TX_BD_RING_ALIGNMENT 32 856 #define UCC_GETH_MRBLR_ALIGNMENT 128 857 #define UCC_GETH_RX_BD_RING_SIZE_ALIGNMENT 4 858 #define UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT 32 859 #define UCC_GETH_RX_DATA_BUF_ALIGNMENT 64 860 861 #define UCC_GETH_TAD_EF 0x80 862 #define UCC_GETH_TAD_V 0x40 863 #define UCC_GETH_TAD_REJ 0x20 864 #define UCC_GETH_TAD_VTAG_OP_RIGHT_SHIFT 2 865 #define UCC_GETH_TAD_VTAG_OP_SHIFT 6 866 #define UCC_GETH_TAD_V_NON_VTAG_OP 0x20 867 #define UCC_GETH_TAD_RQOS_SHIFT 0 868 #define UCC_GETH_TAD_V_PRIORITY_SHIFT 5 869 #define UCC_GETH_TAD_CFI 0x10 870 871 #define UCC_GETH_VLAN_PRIORITY_MAX 8 872 #define UCC_GETH_IP_PRIORITY_MAX 64 873 #define UCC_GETH_TX_VTAG_TABLE_ENTRY_MAX 8 874 #define UCC_GETH_RX_BD_RING_SIZE_MIN 8 875 #define UCC_GETH_TX_BD_RING_SIZE_MIN 2 876 #define UCC_GETH_BD_RING_SIZE_MAX 0xffff 877 878 #define UCC_GETH_SIZE_OF_BD QE_SIZEOF_BD 879 880 /* Driver definitions */ 881 #define TX_BD_RING_LEN 0x10 882 #define RX_BD_RING_LEN 0x20 883 884 #define TX_RING_MOD_MASK(size) (size-1) 885 #define RX_RING_MOD_MASK(size) (size-1) 886 887 #define ENET_GROUP_ADDR 0x01 /* Group address mask 888 for ethernet 889 addresses */ 890 891 #define TX_TIMEOUT (1*HZ) 892 #define SKB_ALLOC_TIMEOUT 100000 893 #define PHY_INIT_TIMEOUT 100000 894 #define PHY_CHANGE_TIME 2 895 896 /* Fast Ethernet (10/100 Mbps) */ 897 #define UCC_GETH_URFS_INIT 512 /* Rx virtual FIFO size 898 */ 899 #define UCC_GETH_URFET_INIT 256 /* 1/2 urfs */ 900 #define UCC_GETH_URFSET_INIT 384 /* 3/4 urfs */ 901 #define UCC_GETH_UTFS_INIT 512 /* Tx virtual FIFO size 902 */ 903 #define UCC_GETH_UTFET_INIT 256 /* 1/2 utfs */ 904 #define UCC_GETH_UTFTT_INIT 256 /* 1/2 utfs 905 due to errata */ 906 /* Gigabit Ethernet (1000 Mbps) */ 907 #define UCC_GETH_URFS_GIGA_INIT 4096/*2048*/ /* Rx virtual 908 FIFO size */ 909 #define UCC_GETH_URFET_GIGA_INIT 2048/*1024*/ /* 1/2 urfs */ 910 #define UCC_GETH_URFSET_GIGA_INIT 3072/*1536*/ /* 3/4 urfs */ 911 #define UCC_GETH_UTFS_GIGA_INIT 4096/*2048*/ /* Tx virtual 912 FIFO size */ 913 #define UCC_GETH_UTFET_GIGA_INIT 2048/*1024*/ /* 1/2 utfs */ 914 #define UCC_GETH_UTFTT_GIGA_INIT 4096/*0x40*/ /* Tx virtual 915 FIFO size */ 916 917 #define UCC_GETH_REMODER_INIT 0 /* bits that must be 918 set */ 919 #define UCC_GETH_TEMODER_INIT 0xC000 /* bits that must */ 920 921 /* Initial value for UPSMR */ 922 #define UCC_GETH_UPSMR_INIT UCC_GETH_UPSMR_RES1 923 924 #define UCC_GETH_MACCFG1_INIT 0 925 #define UCC_GETH_MACCFG2_INIT (MACCFG2_RESERVED_1) 926 927 /* Ethernet Address Type. */ 928 enum enet_addr_type { 929 ENET_ADDR_TYPE_INDIVIDUAL, 930 ENET_ADDR_TYPE_GROUP, 931 ENET_ADDR_TYPE_BROADCAST 932 }; 933 934 /* UCC GETH 82xx Ethernet Address Recognition Location */ 935 enum ucc_geth_enet_address_recognition_location { 936 UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_STATION_ADDRESS,/* station 937 address */ 938 UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_PADDR_FIRST, /* additional 939 station 940 address 941 paddr1 */ 942 UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_PADDR2, /* additional 943 station 944 address 945 paddr2 */ 946 UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_PADDR3, /* additional 947 station 948 address 949 paddr3 */ 950 UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_PADDR_LAST, /* additional 951 station 952 address 953 paddr4 */ 954 UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_GROUP_HASH, /* group hash */ 955 UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_INDIVIDUAL_HASH /* individual 956 hash */ 957 }; 958 959 /* UCC GETH vlan operation tagged */ 960 enum ucc_geth_vlan_operation_tagged { 961 UCC_GETH_VLAN_OPERATION_TAGGED_NOP = 0x0, /* Tagged - nop */ 962 UCC_GETH_VLAN_OPERATION_TAGGED_REPLACE_VID_PORTION_OF_Q_TAG 963 = 0x1, /* Tagged - replace vid portion of q tag */ 964 UCC_GETH_VLAN_OPERATION_TAGGED_IF_VID0_REPLACE_VID_WITH_DEFAULT_VALUE 965 = 0x2, /* Tagged - if vid0 replace vid with default value */ 966 UCC_GETH_VLAN_OPERATION_TAGGED_EXTRACT_Q_TAG_FROM_FRAME 967 = 0x3 /* Tagged - extract q tag from frame */ 968 }; 969 970 /* UCC GETH vlan operation non-tagged */ 971 enum ucc_geth_vlan_operation_non_tagged { 972 UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP = 0x0, /* Non tagged - nop */ 973 UCC_GETH_VLAN_OPERATION_NON_TAGGED_Q_TAG_INSERT = 0x1 /* Non tagged - 974 q tag insert 975 */ 976 }; 977 978 /* UCC GETH Rx Quality of Service Mode */ 979 enum ucc_geth_qos_mode { 980 UCC_GETH_QOS_MODE_DEFAULT = 0x0, /* default queue */ 981 UCC_GETH_QOS_MODE_QUEUE_NUM_FROM_L2_CRITERIA = 0x1, /* queue 982 determined 983 by L2 984 criteria */ 985 UCC_GETH_QOS_MODE_QUEUE_NUM_FROM_L3_CRITERIA = 0x2 /* queue 986 determined 987 by L3 988 criteria */ 989 }; 990 991 /* UCC GETH Statistics Gathering Mode - These are bit flags, 'or' them together 992 for combined functionality */ 993 enum ucc_geth_statistics_gathering_mode { 994 UCC_GETH_STATISTICS_GATHERING_MODE_NONE = 0x00000000, /* No 995 statistics 996 gathering */ 997 UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE = 0x00000001,/* Enable 998 hardware 999 statistics 1000 gathering 1001 */ 1002 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX = 0x00000004,/*Enable 1003 firmware 1004 tx 1005 statistics 1006 gathering 1007 */ 1008 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX = 0x00000008/* Enable 1009 firmware 1010 rx 1011 statistics 1012 gathering 1013 */ 1014 }; 1015 1016 /* UCC GETH Pad and CRC Mode - Note, Padding without CRC is not possible */ 1017 enum ucc_geth_maccfg2_pad_and_crc_mode { 1018 UCC_GETH_PAD_AND_CRC_MODE_NONE 1019 = MACCFG2_PAD_AND_CRC_MODE_NONE, /* Neither Padding 1020 short frames 1021 nor CRC */ 1022 UCC_GETH_PAD_AND_CRC_MODE_CRC_ONLY 1023 = MACCFG2_PAD_AND_CRC_MODE_CRC_ONLY, /* Append 1024 CRC only */ 1025 UCC_GETH_PAD_AND_CRC_MODE_PAD_AND_CRC = 1026 MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC 1027 }; 1028 1029 /* UCC GETH upsmr Flow Control Mode */ 1030 enum ucc_geth_flow_control_mode { 1031 UPSMR_AUTOMATIC_FLOW_CONTROL_MODE_NONE = 0x00000000, /* No automatic 1032 flow control 1033 */ 1034 UPSMR_AUTOMATIC_FLOW_CONTROL_MODE_PAUSE_WHEN_EMERGENCY 1035 = 0x00004000 /* Send pause frame when RxFIFO reaches its 1036 emergency threshold */ 1037 }; 1038 1039 /* UCC GETH number of threads */ 1040 enum ucc_geth_num_of_threads { 1041 UCC_GETH_NUM_OF_THREADS_1 = 0x1, /* 1 */ 1042 UCC_GETH_NUM_OF_THREADS_2 = 0x2, /* 2 */ 1043 UCC_GETH_NUM_OF_THREADS_4 = 0x0, /* 4 */ 1044 UCC_GETH_NUM_OF_THREADS_6 = 0x3, /* 6 */ 1045 UCC_GETH_NUM_OF_THREADS_8 = 0x4 /* 8 */ 1046 }; 1047 1048 /* UCC GETH number of station addresses */ 1049 enum ucc_geth_num_of_station_addresses { 1050 UCC_GETH_NUM_OF_STATION_ADDRESSES_1, /* 1 */ 1051 UCC_GETH_NUM_OF_STATION_ADDRESSES_5 /* 5 */ 1052 }; 1053 1054 /* UCC GETH 82xx Ethernet Address Container */ 1055 struct enet_addr_container { 1056 u8 address[ETH_ALEN]; /* ethernet address */ 1057 enum ucc_geth_enet_address_recognition_location location; /* location in 1058 82xx address 1059 recognition 1060 hardware */ 1061 struct list_head node; 1062 }; 1063 1064 #define ENET_ADDR_CONT_ENTRY(ptr) list_entry(ptr, struct enet_addr_container, node) 1065 1066 /* UCC GETH Termination Action Descriptor (TAD) structure. */ 1067 struct ucc_geth_tad_params { 1068 int rx_non_dynamic_extended_features_mode; 1069 int reject_frame; 1070 enum ucc_geth_vlan_operation_tagged vtag_op; 1071 enum ucc_geth_vlan_operation_non_tagged vnontag_op; 1072 enum ucc_geth_qos_mode rqos; 1073 u8 vpri; 1074 u16 vid; 1075 }; 1076 1077 /* GETH protocol initialization structure */ 1078 struct ucc_geth_info { 1079 struct ucc_fast_info uf_info; 1080 u8 numQueuesTx; 1081 u8 numQueuesRx; 1082 int ipCheckSumCheck; 1083 int ipCheckSumGenerate; 1084 int rxExtendedFiltering; 1085 u32 extendedFilteringChainPointer; 1086 u16 typeorlen; 1087 int dynamicMaxFrameLength; 1088 int dynamicMinFrameLength; 1089 u8 nonBackToBackIfgPart1; 1090 u8 nonBackToBackIfgPart2; 1091 u8 miminumInterFrameGapEnforcement; 1092 u8 backToBackInterFrameGap; 1093 int ipAddressAlignment; 1094 int lengthCheckRx; 1095 u32 mblinterval; 1096 u16 nortsrbytetime; 1097 u8 fracsiz; 1098 u8 strictpriorityq; 1099 u8 txasap; 1100 u8 extrabw; 1101 int miiPreambleSupress; 1102 u8 altBebTruncation; 1103 int altBeb; 1104 int backPressureNoBackoff; 1105 int noBackoff; 1106 int excessDefer; 1107 u8 maxRetransmission; 1108 u8 collisionWindow; 1109 int pro; 1110 int cap; 1111 int rsh; 1112 int rlpb; 1113 int cam; 1114 int bro; 1115 int ecm; 1116 int receiveFlowControl; 1117 int transmitFlowControl; 1118 u8 maxGroupAddrInHash; 1119 u8 maxIndAddrInHash; 1120 u8 prel; 1121 u16 maxFrameLength; 1122 u16 minFrameLength; 1123 u16 maxD1Length; 1124 u16 maxD2Length; 1125 u16 vlantype; 1126 u16 vlantci; 1127 u32 ecamptr; 1128 u32 eventRegMask; 1129 u16 pausePeriod; 1130 u16 extensionField; 1131 struct device_node *phy_node; 1132 struct device_node *tbi_node; 1133 u8 weightfactor[NUM_TX_QUEUES]; 1134 u8 interruptcoalescingmaxvalue[NUM_RX_QUEUES]; 1135 u8 l2qt[UCC_GETH_VLAN_PRIORITY_MAX]; 1136 u8 l3qt[UCC_GETH_IP_PRIORITY_MAX]; 1137 u32 vtagtable[UCC_GETH_TX_VTAG_TABLE_ENTRY_MAX]; 1138 u8 iphoffset[TX_IP_OFFSET_ENTRY_MAX]; 1139 u16 bdRingLenTx[NUM_TX_QUEUES]; 1140 u16 bdRingLenRx[NUM_RX_QUEUES]; 1141 enum ucc_geth_num_of_station_addresses numStationAddresses; 1142 enum qe_fltr_largest_external_tbl_lookup_key_size 1143 largestexternallookupkeysize; 1144 enum ucc_geth_statistics_gathering_mode statisticsMode; 1145 enum ucc_geth_vlan_operation_tagged vlanOperationTagged; 1146 enum ucc_geth_vlan_operation_non_tagged vlanOperationNonTagged; 1147 enum ucc_geth_qos_mode rxQoSMode; 1148 enum ucc_geth_flow_control_mode aufc; 1149 enum ucc_geth_maccfg2_pad_and_crc_mode padAndCrc; 1150 enum ucc_geth_num_of_threads numThreadsTx; 1151 enum ucc_geth_num_of_threads numThreadsRx; 1152 unsigned int riscTx; 1153 unsigned int riscRx; 1154 }; 1155 1156 /* structure representing UCC GETH */ 1157 struct ucc_geth_private { 1158 struct ucc_geth_info *ug_info; 1159 struct ucc_fast_private *uccf; 1160 struct device *dev; 1161 struct net_device *ndev; 1162 struct napi_struct napi; 1163 struct work_struct timeout_work; 1164 struct ucc_geth __iomem *ug_regs; 1165 struct ucc_geth_init_pram *p_init_enet_param_shadow; 1166 struct ucc_geth_exf_global_pram __iomem *p_exf_glbl_param; 1167 u32 exf_glbl_param_offset; 1168 struct ucc_geth_rx_global_pram __iomem *p_rx_glbl_pram; 1169 u32 rx_glbl_pram_offset; 1170 struct ucc_geth_tx_global_pram __iomem *p_tx_glbl_pram; 1171 u32 tx_glbl_pram_offset; 1172 struct ucc_geth_send_queue_mem_region __iomem *p_send_q_mem_reg; 1173 u32 send_q_mem_reg_offset; 1174 struct ucc_geth_thread_data_tx __iomem *p_thread_data_tx; 1175 u32 thread_dat_tx_offset; 1176 struct ucc_geth_thread_data_rx __iomem *p_thread_data_rx; 1177 u32 thread_dat_rx_offset; 1178 struct ucc_geth_scheduler __iomem *p_scheduler; 1179 u32 scheduler_offset; 1180 struct ucc_geth_tx_firmware_statistics_pram __iomem *p_tx_fw_statistics_pram; 1181 u32 tx_fw_statistics_pram_offset; 1182 struct ucc_geth_rx_firmware_statistics_pram __iomem *p_rx_fw_statistics_pram; 1183 u32 rx_fw_statistics_pram_offset; 1184 struct ucc_geth_rx_interrupt_coalescing_table __iomem *p_rx_irq_coalescing_tbl; 1185 u32 rx_irq_coalescing_tbl_offset; 1186 struct ucc_geth_rx_bd_queues_entry __iomem *p_rx_bd_qs_tbl; 1187 u32 rx_bd_qs_tbl_offset; 1188 u8 __iomem *p_tx_bd_ring[NUM_TX_QUEUES]; 1189 u32 tx_bd_ring_offset[NUM_TX_QUEUES]; 1190 u8 __iomem *p_rx_bd_ring[NUM_RX_QUEUES]; 1191 u32 rx_bd_ring_offset[NUM_RX_QUEUES]; 1192 u8 __iomem *confBd[NUM_TX_QUEUES]; 1193 u8 __iomem *txBd[NUM_TX_QUEUES]; 1194 u8 __iomem *rxBd[NUM_RX_QUEUES]; 1195 int badFrame[NUM_RX_QUEUES]; 1196 u16 cpucount[NUM_TX_QUEUES]; 1197 u16 __iomem *p_cpucount[NUM_TX_QUEUES]; 1198 int indAddrRegUsed[NUM_OF_PADDRS]; 1199 u8 paddr[NUM_OF_PADDRS][ETH_ALEN]; /* ethernet address */ 1200 u8 numGroupAddrInHash; 1201 u8 numIndAddrInHash; 1202 u8 numIndAddrInReg; 1203 int rx_extended_features; 1204 int rx_non_dynamic_extended_features; 1205 struct list_head conf_skbs; 1206 struct list_head group_hash_q; 1207 struct list_head ind_hash_q; 1208 u32 saved_uccm; 1209 spinlock_t lock; 1210 /* pointers to arrays of skbuffs for tx and rx */ 1211 struct sk_buff **tx_skbuff[NUM_TX_QUEUES]; 1212 struct sk_buff **rx_skbuff[NUM_RX_QUEUES]; 1213 /* indices pointing to the next free sbk in skb arrays */ 1214 u16 skb_curtx[NUM_TX_QUEUES]; 1215 u16 skb_currx[NUM_RX_QUEUES]; 1216 /* index of the first skb which hasn't been transmitted yet. */ 1217 u16 skb_dirtytx[NUM_TX_QUEUES]; 1218 1219 struct ugeth_mii_info *mii_info; 1220 struct phy_device *phydev; 1221 phy_interface_t phy_interface; 1222 int max_speed; 1223 uint32_t msg_enable; 1224 int oldspeed; 1225 int oldduplex; 1226 int oldlink; 1227 int wol_en; 1228 1229 struct device_node *node; 1230 }; 1231 1232 void uec_set_ethtool_ops(struct net_device *netdev); 1233 int init_flow_control_params(u32 automatic_flow_control_mode, 1234 int rx_flow_control_enable, int tx_flow_control_enable, 1235 u16 pause_period, u16 extension_field, 1236 u32 __iomem *upsmr_register, u32 __iomem *uempr_register, 1237 u32 __iomem *maccfg1_register); 1238 1239 1240 #endif /* __UCC_GETH_H__ */ 1241