1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 STB0899 Multistandard Frontend driver
4 Copyright (C) Manu Abraham (abraham.manu@gmail.com)
5
6 Copyright (C) ST Microelectronics
7
8 */
9
10 #include <linux/bitops.h>
11 #include "stb0899_drv.h"
12 #include "stb0899_priv.h"
13 #include "stb0899_reg.h"
14
stb0899_do_div(u64 n,u32 d)15 static inline u32 stb0899_do_div(u64 n, u32 d)
16 {
17 /* wrap do_div() for ease of use */
18
19 do_div(n, d);
20 return n;
21 }
22
23 #if 0
24 /* These functions are currently unused */
25 /*
26 * stb0899_calc_srate
27 * Compute symbol rate
28 */
29 static u32 stb0899_calc_srate(u32 master_clk, u8 *sfr)
30 {
31 u64 tmp;
32
33 /* srate = (SFR * master_clk) >> 20 */
34
35 /* sfr is of size 20 bit, stored with an offset of 4 bit */
36 tmp = (((u32)sfr[0]) << 16) | (((u32)sfr[1]) << 8) | sfr[2];
37 tmp &= ~0xf;
38 tmp *= master_clk;
39 tmp >>= 24;
40
41 return tmp;
42 }
43
44 /*
45 * stb0899_get_srate
46 * Get the current symbol rate
47 */
48 static u32 stb0899_get_srate(struct stb0899_state *state)
49 {
50 struct stb0899_internal *internal = &state->internal;
51 u8 sfr[3];
52
53 stb0899_read_regs(state, STB0899_SFRH, sfr, 3);
54
55 return stb0899_calc_srate(internal->master_clk, sfr);
56 }
57 #endif
58
59 /*
60 * stb0899_set_srate
61 * Set symbol frequency
62 * MasterClock: master clock frequency (hz)
63 * SymbolRate: symbol rate (bauds)
64 * return symbol frequency
65 */
stb0899_set_srate(struct stb0899_state * state,u32 master_clk,u32 srate)66 static u32 stb0899_set_srate(struct stb0899_state *state, u32 master_clk, u32 srate)
67 {
68 u32 tmp;
69 u8 sfr[3];
70
71 dprintk(state->verbose, FE_DEBUG, 1, "-->");
72 /*
73 * in order to have the maximum precision, the symbol rate entered into
74 * the chip is computed as the closest value of the "true value".
75 * In this purpose, the symbol rate value is rounded (1 is added on the bit
76 * below the LSB )
77 *
78 * srate = (SFR * master_clk) >> 20
79 * <=>
80 * SFR = srate << 20 / master_clk
81 *
82 * rounded:
83 * SFR = (srate << 21 + master_clk) / (2 * master_clk)
84 *
85 * stored as 20 bit number with an offset of 4 bit:
86 * sfr = SFR << 4;
87 */
88
89 tmp = stb0899_do_div((((u64)srate) << 21) + master_clk, 2 * master_clk);
90 tmp <<= 4;
91
92 sfr[0] = tmp >> 16;
93 sfr[1] = tmp >> 8;
94 sfr[2] = tmp;
95
96 stb0899_write_regs(state, STB0899_SFRH, sfr, 3);
97
98 return srate;
99 }
100
101 /*
102 * stb0899_calc_derot_time
103 * Compute the amount of time needed by the derotator to lock
104 * SymbolRate: Symbol rate
105 * return: derotator time constant (ms)
106 */
stb0899_calc_derot_time(long srate)107 static long stb0899_calc_derot_time(long srate)
108 {
109 if (srate > 0)
110 return (100000 / (srate / 1000));
111 else
112 return 0;
113 }
114
115 /*
116 * stb0899_carr_width
117 * Compute the width of the carrier
118 * return: width of carrier (kHz or Mhz)
119 */
stb0899_carr_width(struct stb0899_state * state)120 long stb0899_carr_width(struct stb0899_state *state)
121 {
122 struct stb0899_internal *internal = &state->internal;
123
124 return (internal->srate + (internal->srate * internal->rolloff) / 100);
125 }
126
127 /*
128 * stb0899_first_subrange
129 * Compute the first subrange of the search
130 */
stb0899_first_subrange(struct stb0899_state * state)131 static void stb0899_first_subrange(struct stb0899_state *state)
132 {
133 struct stb0899_internal *internal = &state->internal;
134 struct stb0899_params *params = &state->params;
135 struct stb0899_config *config = state->config;
136
137 int range = 0;
138 u32 bandwidth = 0;
139
140 if (config->tuner_get_bandwidth) {
141 stb0899_i2c_gate_ctrl(&state->frontend, 1);
142 config->tuner_get_bandwidth(&state->frontend, &bandwidth);
143 stb0899_i2c_gate_ctrl(&state->frontend, 0);
144 range = bandwidth - stb0899_carr_width(state) / 2;
145 }
146
147 if (range > 0)
148 internal->sub_range = min(internal->srch_range, range);
149 else
150 internal->sub_range = 0;
151
152 internal->freq = params->freq;
153 internal->tuner_offst = 0L;
154 internal->sub_dir = 1;
155 }
156
157 /*
158 * stb0899_check_tmg
159 * check for timing lock
160 * internal.Ttiming: time to wait for loop lock
161 */
stb0899_check_tmg(struct stb0899_state * state)162 static enum stb0899_status stb0899_check_tmg(struct stb0899_state *state)
163 {
164 struct stb0899_internal *internal = &state->internal;
165 int lock;
166 u8 reg;
167 s8 timing;
168
169 msleep(internal->t_derot);
170
171 stb0899_write_reg(state, STB0899_RTF, 0xf2);
172 reg = stb0899_read_reg(state, STB0899_TLIR);
173 lock = STB0899_GETFIELD(TLIR_TMG_LOCK_IND, reg);
174 timing = stb0899_read_reg(state, STB0899_RTF);
175
176 if (lock >= 42) {
177 if ((lock > 48) && (abs(timing) >= 110)) {
178 internal->status = ANALOGCARRIER;
179 dprintk(state->verbose, FE_DEBUG, 1, "-->ANALOG Carrier !");
180 } else {
181 internal->status = TIMINGOK;
182 dprintk(state->verbose, FE_DEBUG, 1, "------->TIMING OK !");
183 }
184 } else {
185 internal->status = NOTIMING;
186 dprintk(state->verbose, FE_DEBUG, 1, "-->NO TIMING !");
187 }
188 return internal->status;
189 }
190
191 /*
192 * stb0899_search_tmg
193 * perform a fs/2 zig-zag to find timing
194 */
stb0899_search_tmg(struct stb0899_state * state)195 static enum stb0899_status stb0899_search_tmg(struct stb0899_state *state)
196 {
197 struct stb0899_internal *internal = &state->internal;
198 struct stb0899_params *params = &state->params;
199
200 short int derot_step, derot_freq = 0, derot_limit, next_loop = 3;
201 int index = 0;
202 u8 cfr[2];
203
204 internal->status = NOTIMING;
205
206 /* timing loop computation & symbol rate optimisation */
207 derot_limit = (internal->sub_range / 2L) / internal->mclk;
208 derot_step = (params->srate / 2L) / internal->mclk;
209
210 while ((stb0899_check_tmg(state) != TIMINGOK) && next_loop) {
211 index++;
212 derot_freq += index * internal->direction * derot_step; /* next derot zig zag position */
213
214 if (abs(derot_freq) > derot_limit)
215 next_loop--;
216
217 if (next_loop) {
218 STB0899_SETFIELD_VAL(CFRM, cfr[0], MSB(internal->inversion * derot_freq));
219 STB0899_SETFIELD_VAL(CFRL, cfr[1], LSB(internal->inversion * derot_freq));
220 stb0899_write_regs(state, STB0899_CFRM, cfr, 2); /* derotator frequency */
221 }
222 internal->direction = -internal->direction; /* Change zigzag direction */
223 }
224
225 if (internal->status == TIMINGOK) {
226 stb0899_read_regs(state, STB0899_CFRM, cfr, 2); /* get derotator frequency */
227 internal->derot_freq = internal->inversion * MAKEWORD16(cfr[0], cfr[1]);
228 dprintk(state->verbose, FE_DEBUG, 1, "------->TIMING OK ! Derot Freq = %d", internal->derot_freq);
229 }
230
231 return internal->status;
232 }
233
234 /*
235 * stb0899_check_carrier
236 * Check for carrier found
237 */
stb0899_check_carrier(struct stb0899_state * state)238 static enum stb0899_status stb0899_check_carrier(struct stb0899_state *state)
239 {
240 struct stb0899_internal *internal = &state->internal;
241 u8 reg;
242
243 msleep(internal->t_derot); /* wait for derotator ok */
244
245 reg = stb0899_read_reg(state, STB0899_CFD);
246 STB0899_SETFIELD_VAL(CFD_ON, reg, 1);
247 stb0899_write_reg(state, STB0899_CFD, reg);
248
249 reg = stb0899_read_reg(state, STB0899_DSTATUS);
250 dprintk(state->verbose, FE_DEBUG, 1, "--------------------> STB0899_DSTATUS=[0x%02x]", reg);
251 if (STB0899_GETFIELD(CARRIER_FOUND, reg)) {
252 internal->status = CARRIEROK;
253 dprintk(state->verbose, FE_DEBUG, 1, "-------------> CARRIEROK !");
254 } else {
255 internal->status = NOCARRIER;
256 dprintk(state->verbose, FE_DEBUG, 1, "-------------> NOCARRIER !");
257 }
258
259 return internal->status;
260 }
261
262 /*
263 * stb0899_search_carrier
264 * Search for a QPSK carrier with the derotator
265 */
stb0899_search_carrier(struct stb0899_state * state)266 static enum stb0899_status stb0899_search_carrier(struct stb0899_state *state)
267 {
268 struct stb0899_internal *internal = &state->internal;
269
270 short int derot_freq = 0, last_derot_freq = 0, derot_limit, next_loop = 3;
271 int index = 0;
272 u8 cfr[2];
273 u8 reg;
274
275 internal->status = NOCARRIER;
276 derot_limit = (internal->sub_range / 2L) / internal->mclk;
277 derot_freq = internal->derot_freq;
278
279 reg = stb0899_read_reg(state, STB0899_CFD);
280 STB0899_SETFIELD_VAL(CFD_ON, reg, 1);
281 stb0899_write_reg(state, STB0899_CFD, reg);
282
283 do {
284 dprintk(state->verbose, FE_DEBUG, 1, "Derot Freq=%d, mclk=%d", derot_freq, internal->mclk);
285 if (stb0899_check_carrier(state) == NOCARRIER) {
286 index++;
287 last_derot_freq = derot_freq;
288 derot_freq += index * internal->direction * internal->derot_step; /* next zig zag derotator position */
289
290 if(abs(derot_freq) > derot_limit)
291 next_loop--;
292
293 if (next_loop) {
294 reg = stb0899_read_reg(state, STB0899_CFD);
295 STB0899_SETFIELD_VAL(CFD_ON, reg, 1);
296 stb0899_write_reg(state, STB0899_CFD, reg);
297
298 STB0899_SETFIELD_VAL(CFRM, cfr[0], MSB(internal->inversion * derot_freq));
299 STB0899_SETFIELD_VAL(CFRL, cfr[1], LSB(internal->inversion * derot_freq));
300 stb0899_write_regs(state, STB0899_CFRM, cfr, 2); /* derotator frequency */
301 }
302 }
303
304 internal->direction = -internal->direction; /* Change zigzag direction */
305 } while ((internal->status != CARRIEROK) && next_loop);
306
307 if (internal->status == CARRIEROK) {
308 stb0899_read_regs(state, STB0899_CFRM, cfr, 2); /* get derotator frequency */
309 internal->derot_freq = internal->inversion * MAKEWORD16(cfr[0], cfr[1]);
310 dprintk(state->verbose, FE_DEBUG, 1, "----> CARRIER OK !, Derot Freq=%d", internal->derot_freq);
311 } else {
312 internal->derot_freq = last_derot_freq;
313 }
314
315 return internal->status;
316 }
317
318 /*
319 * stb0899_check_data
320 * Check for data found
321 */
stb0899_check_data(struct stb0899_state * state)322 static enum stb0899_status stb0899_check_data(struct stb0899_state *state)
323 {
324 struct stb0899_internal *internal = &state->internal;
325 struct stb0899_params *params = &state->params;
326
327 int lock = 0, index = 0, dataTime = 500, loop;
328 u8 reg;
329
330 internal->status = NODATA;
331
332 /* RESET FEC */
333 reg = stb0899_read_reg(state, STB0899_TSTRES);
334 STB0899_SETFIELD_VAL(FRESACS, reg, 1);
335 stb0899_write_reg(state, STB0899_TSTRES, reg);
336 msleep(1);
337 reg = stb0899_read_reg(state, STB0899_TSTRES);
338 STB0899_SETFIELD_VAL(FRESACS, reg, 0);
339 stb0899_write_reg(state, STB0899_TSTRES, reg);
340
341 if (params->srate <= 2000000)
342 dataTime = 2000;
343 else if (params->srate <= 5000000)
344 dataTime = 1500;
345 else if (params->srate <= 15000000)
346 dataTime = 1000;
347 else
348 dataTime = 500;
349
350 /* clear previous failed END_LOOPVIT */
351 stb0899_read_reg(state, STB0899_VSTATUS);
352
353 stb0899_write_reg(state, STB0899_DSTATUS2, 0x00); /* force search loop */
354 while (1) {
355 /* WARNING! VIT LOCKED has to be tested before VIT_END_LOOOP */
356 reg = stb0899_read_reg(state, STB0899_VSTATUS);
357 lock = STB0899_GETFIELD(VSTATUS_LOCKEDVIT, reg);
358 loop = STB0899_GETFIELD(VSTATUS_END_LOOPVIT, reg);
359
360 if (lock || loop || (index > dataTime))
361 break;
362 index++;
363 }
364
365 if (lock) { /* DATA LOCK indicator */
366 internal->status = DATAOK;
367 dprintk(state->verbose, FE_DEBUG, 1, "-----------------> DATA OK !");
368 }
369
370 return internal->status;
371 }
372
373 /*
374 * stb0899_search_data
375 * Search for a QPSK carrier with the derotator
376 */
stb0899_search_data(struct stb0899_state * state)377 static enum stb0899_status stb0899_search_data(struct stb0899_state *state)
378 {
379 short int derot_freq, derot_step, derot_limit, next_loop = 3;
380 u8 cfr[2];
381 u8 reg;
382 int index = 1;
383
384 struct stb0899_internal *internal = &state->internal;
385 struct stb0899_params *params = &state->params;
386
387 derot_step = (params->srate / 4L) / internal->mclk;
388 derot_limit = (internal->sub_range / 2L) / internal->mclk;
389 derot_freq = internal->derot_freq;
390
391 do {
392 if ((internal->status != CARRIEROK) || (stb0899_check_data(state) != DATAOK)) {
393
394 derot_freq += index * internal->direction * derot_step; /* next zig zag derotator position */
395 if (abs(derot_freq) > derot_limit)
396 next_loop--;
397
398 if (next_loop) {
399 dprintk(state->verbose, FE_DEBUG, 1, "Derot freq=%d, mclk=%d", derot_freq, internal->mclk);
400 reg = stb0899_read_reg(state, STB0899_CFD);
401 STB0899_SETFIELD_VAL(CFD_ON, reg, 1);
402 stb0899_write_reg(state, STB0899_CFD, reg);
403
404 STB0899_SETFIELD_VAL(CFRM, cfr[0], MSB(internal->inversion * derot_freq));
405 STB0899_SETFIELD_VAL(CFRL, cfr[1], LSB(internal->inversion * derot_freq));
406 stb0899_write_regs(state, STB0899_CFRM, cfr, 2); /* derotator frequency */
407
408 stb0899_check_carrier(state);
409 index++;
410 }
411 }
412 internal->direction = -internal->direction; /* change zig zag direction */
413 } while ((internal->status != DATAOK) && next_loop);
414
415 if (internal->status == DATAOK) {
416 stb0899_read_regs(state, STB0899_CFRM, cfr, 2); /* get derotator frequency */
417
418 /* store autodetected IQ swapping as default for DVB-S2 tuning */
419 reg = stb0899_read_reg(state, STB0899_IQSWAP);
420 if (STB0899_GETFIELD(SYM, reg))
421 internal->inversion = IQ_SWAP_ON;
422 else
423 internal->inversion = IQ_SWAP_OFF;
424
425 internal->derot_freq = internal->inversion * MAKEWORD16(cfr[0], cfr[1]);
426 dprintk(state->verbose, FE_DEBUG, 1, "------> DATAOK ! Derot Freq=%d", internal->derot_freq);
427 }
428
429 return internal->status;
430 }
431
432 /*
433 * stb0899_check_range
434 * check if the found frequency is in the correct range
435 */
stb0899_check_range(struct stb0899_state * state)436 static enum stb0899_status stb0899_check_range(struct stb0899_state *state)
437 {
438 struct stb0899_internal *internal = &state->internal;
439 struct stb0899_params *params = &state->params;
440
441 int range_offst, tp_freq;
442
443 range_offst = internal->srch_range / 2000;
444 tp_freq = internal->freq - (internal->derot_freq * internal->mclk) / 1000;
445
446 if ((tp_freq >= params->freq - range_offst) && (tp_freq <= params->freq + range_offst)) {
447 internal->status = RANGEOK;
448 dprintk(state->verbose, FE_DEBUG, 1, "----> RANGEOK !");
449 } else {
450 internal->status = OUTOFRANGE;
451 dprintk(state->verbose, FE_DEBUG, 1, "----> OUT OF RANGE !");
452 }
453
454 return internal->status;
455 }
456
457 /*
458 * NextSubRange
459 * Compute the next subrange of the search
460 */
next_sub_range(struct stb0899_state * state)461 static void next_sub_range(struct stb0899_state *state)
462 {
463 struct stb0899_internal *internal = &state->internal;
464 struct stb0899_params *params = &state->params;
465
466 long old_sub_range;
467
468 if (internal->sub_dir > 0) {
469 old_sub_range = internal->sub_range;
470 internal->sub_range = min((internal->srch_range / 2) -
471 (internal->tuner_offst + internal->sub_range / 2),
472 internal->sub_range);
473
474 if (internal->sub_range < 0)
475 internal->sub_range = 0;
476
477 internal->tuner_offst += (old_sub_range + internal->sub_range) / 2;
478 }
479
480 internal->freq = params->freq + (internal->sub_dir * internal->tuner_offst) / 1000;
481 internal->sub_dir = -internal->sub_dir;
482 }
483
484 /*
485 * stb0899_dvbs_algo
486 * Search for a signal, timing, carrier and data for a
487 * given frequency in a given range
488 */
stb0899_dvbs_algo(struct stb0899_state * state)489 enum stb0899_status stb0899_dvbs_algo(struct stb0899_state *state)
490 {
491 struct stb0899_params *params = &state->params;
492 struct stb0899_internal *internal = &state->internal;
493 struct stb0899_config *config = state->config;
494
495 u8 bclc, reg;
496 u8 cfr[2];
497 u8 eq_const[10];
498 s32 clnI = 3;
499 u32 bandwidth = 0;
500
501 /* BETA values rated @ 99MHz */
502 s32 betaTab[5][4] = {
503 /* 5 10 20 30MBps */
504 { 37, 34, 32, 31 }, /* QPSK 1/2 */
505 { 37, 35, 33, 31 }, /* QPSK 2/3 */
506 { 37, 35, 33, 31 }, /* QPSK 3/4 */
507 { 37, 36, 33, 32 }, /* QPSK 5/6 */
508 { 37, 36, 33, 32 } /* QPSK 7/8 */
509 };
510
511 internal->direction = 1;
512
513 stb0899_set_srate(state, internal->master_clk, params->srate);
514 /* Carrier loop optimization versus symbol rate for acquisition*/
515 if (params->srate <= 5000000) {
516 stb0899_write_reg(state, STB0899_ACLC, 0x89);
517 bclc = stb0899_read_reg(state, STB0899_BCLC);
518 STB0899_SETFIELD_VAL(BETA, bclc, 0x1c);
519 stb0899_write_reg(state, STB0899_BCLC, bclc);
520 clnI = 0;
521 } else if (params->srate <= 15000000) {
522 stb0899_write_reg(state, STB0899_ACLC, 0xc9);
523 bclc = stb0899_read_reg(state, STB0899_BCLC);
524 STB0899_SETFIELD_VAL(BETA, bclc, 0x22);
525 stb0899_write_reg(state, STB0899_BCLC, bclc);
526 clnI = 1;
527 } else if(params->srate <= 25000000) {
528 stb0899_write_reg(state, STB0899_ACLC, 0x89);
529 bclc = stb0899_read_reg(state, STB0899_BCLC);
530 STB0899_SETFIELD_VAL(BETA, bclc, 0x27);
531 stb0899_write_reg(state, STB0899_BCLC, bclc);
532 clnI = 2;
533 } else {
534 stb0899_write_reg(state, STB0899_ACLC, 0xc8);
535 bclc = stb0899_read_reg(state, STB0899_BCLC);
536 STB0899_SETFIELD_VAL(BETA, bclc, 0x29);
537 stb0899_write_reg(state, STB0899_BCLC, bclc);
538 clnI = 3;
539 }
540
541 dprintk(state->verbose, FE_DEBUG, 1, "Set the timing loop to acquisition");
542 /* Set the timing loop to acquisition */
543 stb0899_write_reg(state, STB0899_RTC, 0x46);
544 stb0899_write_reg(state, STB0899_CFD, 0xee);
545
546 /* !! WARNING !!
547 * Do not read any status variables while acquisition,
548 * If any needed, read before the acquisition starts
549 * querying status while acquiring causes the
550 * acquisition to go bad and hence no locks.
551 */
552 dprintk(state->verbose, FE_DEBUG, 1, "Derot Percent=%d Srate=%d mclk=%d",
553 internal->derot_percent, params->srate, internal->mclk);
554
555 /* Initial calculations */
556 internal->derot_step = internal->derot_percent * (params->srate / 1000L) / internal->mclk; /* DerotStep/1000 * Fsymbol */
557 internal->t_derot = stb0899_calc_derot_time(params->srate);
558 internal->t_data = 500;
559
560 dprintk(state->verbose, FE_DEBUG, 1, "RESET stream merger");
561 /* RESET Stream merger */
562 reg = stb0899_read_reg(state, STB0899_TSTRES);
563 STB0899_SETFIELD_VAL(FRESRS, reg, 1);
564 stb0899_write_reg(state, STB0899_TSTRES, reg);
565
566 /*
567 * Set KDIVIDER to an intermediate value between
568 * 1/2 and 7/8 for acquisition
569 */
570 reg = stb0899_read_reg(state, STB0899_DEMAPVIT);
571 STB0899_SETFIELD_VAL(DEMAPVIT_KDIVIDER, reg, 60);
572 stb0899_write_reg(state, STB0899_DEMAPVIT, reg);
573
574 stb0899_write_reg(state, STB0899_EQON, 0x01); /* Equalizer OFF while acquiring */
575 stb0899_write_reg(state, STB0899_VITSYNC, 0x19);
576
577 stb0899_first_subrange(state);
578 do {
579 /* Initialisations */
580 cfr[0] = cfr[1] = 0;
581 stb0899_write_regs(state, STB0899_CFRM, cfr, 2); /* RESET derotator frequency */
582
583 stb0899_write_reg(state, STB0899_RTF, 0);
584 reg = stb0899_read_reg(state, STB0899_CFD);
585 STB0899_SETFIELD_VAL(CFD_ON, reg, 1);
586 stb0899_write_reg(state, STB0899_CFD, reg);
587
588 internal->derot_freq = 0;
589 internal->status = NOAGC1;
590
591 /* enable tuner I/O */
592 stb0899_i2c_gate_ctrl(&state->frontend, 1);
593
594 /* Move tuner to frequency */
595 dprintk(state->verbose, FE_DEBUG, 1, "Tuner set frequency");
596 if (state->config->tuner_set_frequency)
597 state->config->tuner_set_frequency(&state->frontend, internal->freq);
598
599 if (state->config->tuner_get_frequency)
600 state->config->tuner_get_frequency(&state->frontend, &internal->freq);
601
602 msleep(internal->t_agc1 + internal->t_agc2 + internal->t_derot); /* AGC1, AGC2 and timing loop */
603 dprintk(state->verbose, FE_DEBUG, 1, "current derot freq=%d", internal->derot_freq);
604 internal->status = AGC1OK;
605
606 /* There is signal in the band */
607 if (config->tuner_get_bandwidth)
608 config->tuner_get_bandwidth(&state->frontend, &bandwidth);
609
610 /* disable tuner I/O */
611 stb0899_i2c_gate_ctrl(&state->frontend, 0);
612
613 if (params->srate <= bandwidth / 2)
614 stb0899_search_tmg(state); /* For low rates (SCPC) */
615 else
616 stb0899_check_tmg(state); /* For high rates (MCPC) */
617
618 if (internal->status == TIMINGOK) {
619 dprintk(state->verbose, FE_DEBUG, 1,
620 "TIMING OK ! Derot freq=%d, mclk=%d",
621 internal->derot_freq, internal->mclk);
622
623 if (stb0899_search_carrier(state) == CARRIEROK) { /* Search for carrier */
624 dprintk(state->verbose, FE_DEBUG, 1,
625 "CARRIER OK ! Derot freq=%d, mclk=%d",
626 internal->derot_freq, internal->mclk);
627
628 if (stb0899_search_data(state) == DATAOK) { /* Check for data */
629 dprintk(state->verbose, FE_DEBUG, 1,
630 "DATA OK ! Derot freq=%d, mclk=%d",
631 internal->derot_freq, internal->mclk);
632
633 if (stb0899_check_range(state) == RANGEOK) {
634 dprintk(state->verbose, FE_DEBUG, 1,
635 "RANGE OK ! derot freq=%d, mclk=%d",
636 internal->derot_freq, internal->mclk);
637
638 internal->freq = params->freq - ((internal->derot_freq * internal->mclk) / 1000);
639 reg = stb0899_read_reg(state, STB0899_PLPARM);
640 internal->fecrate = STB0899_GETFIELD(VITCURPUN, reg);
641 dprintk(state->verbose, FE_DEBUG, 1,
642 "freq=%d, internal resultant freq=%d",
643 params->freq, internal->freq);
644
645 dprintk(state->verbose, FE_DEBUG, 1,
646 "internal puncture rate=%d",
647 internal->fecrate);
648 }
649 }
650 }
651 }
652 if (internal->status != RANGEOK)
653 next_sub_range(state);
654
655 } while (internal->sub_range && internal->status != RANGEOK);
656
657 /* Set the timing loop to tracking */
658 stb0899_write_reg(state, STB0899_RTC, 0x33);
659 stb0899_write_reg(state, STB0899_CFD, 0xf7);
660 /* if locked and range ok, set Kdiv */
661 if (internal->status == RANGEOK) {
662 dprintk(state->verbose, FE_DEBUG, 1, "Locked & Range OK !");
663 stb0899_write_reg(state, STB0899_EQON, 0x41); /* Equalizer OFF while acquiring */
664 stb0899_write_reg(state, STB0899_VITSYNC, 0x39); /* SN to b'11 for acquisition */
665
666 /*
667 * Carrier loop optimization versus
668 * symbol Rate/Puncture Rate for Tracking
669 */
670 reg = stb0899_read_reg(state, STB0899_BCLC);
671 switch (internal->fecrate) {
672 case STB0899_FEC_1_2: /* 13 */
673 stb0899_write_reg(state, STB0899_DEMAPVIT, 0x1a);
674 STB0899_SETFIELD_VAL(BETA, reg, betaTab[0][clnI]);
675 stb0899_write_reg(state, STB0899_BCLC, reg);
676 break;
677 case STB0899_FEC_2_3: /* 18 */
678 stb0899_write_reg(state, STB0899_DEMAPVIT, 44);
679 STB0899_SETFIELD_VAL(BETA, reg, betaTab[1][clnI]);
680 stb0899_write_reg(state, STB0899_BCLC, reg);
681 break;
682 case STB0899_FEC_3_4: /* 21 */
683 stb0899_write_reg(state, STB0899_DEMAPVIT, 60);
684 STB0899_SETFIELD_VAL(BETA, reg, betaTab[2][clnI]);
685 stb0899_write_reg(state, STB0899_BCLC, reg);
686 break;
687 case STB0899_FEC_5_6: /* 24 */
688 stb0899_write_reg(state, STB0899_DEMAPVIT, 75);
689 STB0899_SETFIELD_VAL(BETA, reg, betaTab[3][clnI]);
690 stb0899_write_reg(state, STB0899_BCLC, reg);
691 break;
692 case STB0899_FEC_6_7: /* 25 */
693 stb0899_write_reg(state, STB0899_DEMAPVIT, 88);
694 stb0899_write_reg(state, STB0899_ACLC, 0x88);
695 stb0899_write_reg(state, STB0899_BCLC, 0x9a);
696 break;
697 case STB0899_FEC_7_8: /* 26 */
698 stb0899_write_reg(state, STB0899_DEMAPVIT, 94);
699 STB0899_SETFIELD_VAL(BETA, reg, betaTab[4][clnI]);
700 stb0899_write_reg(state, STB0899_BCLC, reg);
701 break;
702 default:
703 dprintk(state->verbose, FE_DEBUG, 1, "Unsupported Puncture Rate");
704 break;
705 }
706 /* release stream merger RESET */
707 reg = stb0899_read_reg(state, STB0899_TSTRES);
708 STB0899_SETFIELD_VAL(FRESRS, reg, 0);
709 stb0899_write_reg(state, STB0899_TSTRES, reg);
710
711 /* disable carrier detector */
712 reg = stb0899_read_reg(state, STB0899_CFD);
713 STB0899_SETFIELD_VAL(CFD_ON, reg, 0);
714 stb0899_write_reg(state, STB0899_CFD, reg);
715
716 stb0899_read_regs(state, STB0899_EQUAI1, eq_const, 10);
717 }
718
719 return internal->status;
720 }
721
722 /*
723 * stb0899_dvbs2_config_uwp
724 * Configure UWP state machine
725 */
stb0899_dvbs2_config_uwp(struct stb0899_state * state)726 static void stb0899_dvbs2_config_uwp(struct stb0899_state *state)
727 {
728 struct stb0899_internal *internal = &state->internal;
729 struct stb0899_config *config = state->config;
730 u32 uwp1, uwp2, uwp3, reg;
731
732 uwp1 = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_CNTRL1);
733 uwp2 = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_CNTRL2);
734 uwp3 = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_CNTRL3);
735
736 STB0899_SETFIELD_VAL(UWP_ESN0_AVE, uwp1, config->esno_ave);
737 STB0899_SETFIELD_VAL(UWP_ESN0_QUANT, uwp1, config->esno_quant);
738 STB0899_SETFIELD_VAL(UWP_TH_SOF, uwp1, config->uwp_threshold_sof);
739
740 STB0899_SETFIELD_VAL(FE_COARSE_TRK, uwp2, internal->av_frame_coarse);
741 STB0899_SETFIELD_VAL(FE_FINE_TRK, uwp2, internal->av_frame_fine);
742 STB0899_SETFIELD_VAL(UWP_MISS_TH, uwp2, config->miss_threshold);
743
744 STB0899_SETFIELD_VAL(UWP_TH_ACQ, uwp3, config->uwp_threshold_acq);
745 STB0899_SETFIELD_VAL(UWP_TH_TRACK, uwp3, config->uwp_threshold_track);
746
747 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_UWP_CNTRL1, STB0899_OFF0_UWP_CNTRL1, uwp1);
748 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_UWP_CNTRL2, STB0899_OFF0_UWP_CNTRL2, uwp2);
749 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_UWP_CNTRL3, STB0899_OFF0_UWP_CNTRL3, uwp3);
750
751 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, SOF_SRCH_TO);
752 STB0899_SETFIELD_VAL(SOF_SEARCH_TIMEOUT, reg, config->sof_search_timeout);
753 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_SOF_SRCH_TO, STB0899_OFF0_SOF_SRCH_TO, reg);
754 }
755
756 /*
757 * stb0899_dvbs2_config_csm_auto
758 * Set CSM to AUTO mode
759 */
stb0899_dvbs2_config_csm_auto(struct stb0899_state * state)760 static void stb0899_dvbs2_config_csm_auto(struct stb0899_state *state)
761 {
762 u32 reg;
763
764 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL1);
765 STB0899_SETFIELD_VAL(CSM_AUTO_PARAM, reg, 1);
766 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL1, STB0899_OFF0_CSM_CNTRL1, reg);
767 }
768
Log2Int(int number)769 static long Log2Int(int number)
770 {
771 int i;
772
773 i = 0;
774 while ((1 << i) <= abs(number))
775 i++;
776
777 if (number == 0)
778 i = 1;
779
780 return i - 1;
781 }
782
783 /*
784 * stb0899_dvbs2_calc_srate
785 * compute BTR_NOM_FREQ for the symbol rate
786 */
stb0899_dvbs2_calc_srate(struct stb0899_state * state)787 static u32 stb0899_dvbs2_calc_srate(struct stb0899_state *state)
788 {
789 struct stb0899_internal *internal = &state->internal;
790 struct stb0899_config *config = state->config;
791
792 u32 dec_ratio, dec_rate, decim, remain, intval, btr_nom_freq;
793 u32 master_clk, srate;
794
795 dec_ratio = (internal->master_clk * 2) / (5 * internal->srate);
796 dec_ratio = (dec_ratio == 0) ? 1 : dec_ratio;
797 dec_rate = Log2Int(dec_ratio);
798 decim = 1 << dec_rate;
799 master_clk = internal->master_clk / 1000;
800 srate = internal->srate / 1000;
801
802 if (decim <= 4) {
803 intval = (decim * (1 << (config->btr_nco_bits - 1))) / master_clk;
804 remain = (decim * (1 << (config->btr_nco_bits - 1))) % master_clk;
805 } else {
806 intval = (1 << (config->btr_nco_bits - 1)) / (master_clk / 100) * decim / 100;
807 remain = (decim * (1 << (config->btr_nco_bits - 1))) % master_clk;
808 }
809 btr_nom_freq = (intval * srate) + ((remain * srate) / master_clk);
810
811 return btr_nom_freq;
812 }
813
814 /*
815 * stb0899_dvbs2_calc_dev
816 * compute the correction to be applied to symbol rate
817 */
stb0899_dvbs2_calc_dev(struct stb0899_state * state)818 static u32 stb0899_dvbs2_calc_dev(struct stb0899_state *state)
819 {
820 struct stb0899_internal *internal = &state->internal;
821 u32 dec_ratio, correction, master_clk, srate;
822
823 dec_ratio = (internal->master_clk * 2) / (5 * internal->srate);
824 dec_ratio = (dec_ratio == 0) ? 1 : dec_ratio;
825
826 master_clk = internal->master_clk / 1000; /* for integer Calculation*/
827 srate = internal->srate / 1000; /* for integer Calculation*/
828 correction = (512 * master_clk) / (2 * dec_ratio * srate);
829
830 return correction;
831 }
832
833 /*
834 * stb0899_dvbs2_set_srate
835 * Set DVBS2 symbol rate
836 */
stb0899_dvbs2_set_srate(struct stb0899_state * state)837 static void stb0899_dvbs2_set_srate(struct stb0899_state *state)
838 {
839 struct stb0899_internal *internal = &state->internal;
840
841 u32 dec_ratio, dec_rate, win_sel, decim, f_sym, btr_nom_freq;
842 u32 correction, freq_adj, band_lim, decim_cntrl, reg;
843 u8 anti_alias;
844
845 /*set decimation to 1*/
846 dec_ratio = (internal->master_clk * 2) / (5 * internal->srate);
847 dec_ratio = (dec_ratio == 0) ? 1 : dec_ratio;
848 dec_rate = Log2Int(dec_ratio);
849
850 win_sel = 0;
851 if (dec_rate >= 5)
852 win_sel = dec_rate - 4;
853
854 decim = (1 << dec_rate);
855 /* (FSamp/Fsymbol *100) for integer Calculation */
856 f_sym = internal->master_clk / ((decim * internal->srate) / 1000);
857
858 if (f_sym <= 2250) /* don't band limit signal going into btr block*/
859 band_lim = 1;
860 else
861 band_lim = 0; /* band limit signal going into btr block*/
862
863 decim_cntrl = ((win_sel << 3) & 0x18) + ((band_lim << 5) & 0x20) + (dec_rate & 0x7);
864 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_DECIM_CNTRL, STB0899_OFF0_DECIM_CNTRL, decim_cntrl);
865
866 if (f_sym <= 3450)
867 anti_alias = 0;
868 else if (f_sym <= 4250)
869 anti_alias = 1;
870 else
871 anti_alias = 2;
872
873 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_ANTI_ALIAS_SEL, STB0899_OFF0_ANTI_ALIAS_SEL, anti_alias);
874 btr_nom_freq = stb0899_dvbs2_calc_srate(state);
875 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_NOM_FREQ, STB0899_OFF0_BTR_NOM_FREQ, btr_nom_freq);
876
877 correction = stb0899_dvbs2_calc_dev(state);
878 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, BTR_CNTRL);
879 STB0899_SETFIELD_VAL(BTR_FREQ_CORR, reg, correction);
880 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_CNTRL, STB0899_OFF0_BTR_CNTRL, reg);
881
882 /* scale UWP+CSM frequency to sample rate*/
883 freq_adj = internal->srate / (internal->master_clk / 4096);
884 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_FREQ_ADJ_SCALE, STB0899_OFF0_FREQ_ADJ_SCALE, freq_adj);
885 }
886
887 /*
888 * stb0899_dvbs2_set_btr_loopbw
889 * set bit timing loop bandwidth as a percentage of the symbol rate
890 */
stb0899_dvbs2_set_btr_loopbw(struct stb0899_state * state)891 static void stb0899_dvbs2_set_btr_loopbw(struct stb0899_state *state)
892 {
893 struct stb0899_internal *internal = &state->internal;
894 struct stb0899_config *config = state->config;
895
896 u32 sym_peak = 23, zeta = 707, loopbw_percent = 60;
897 s32 dec_ratio, dec_rate, k_btr1_rshft, k_btr1, k_btr0_rshft;
898 s32 k_btr0, k_btr2_rshft, k_direct_shift, k_indirect_shift;
899 u32 decim, K, wn, k_direct, k_indirect;
900 u32 reg;
901
902 dec_ratio = (internal->master_clk * 2) / (5 * internal->srate);
903 dec_ratio = (dec_ratio == 0) ? 1 : dec_ratio;
904 dec_rate = Log2Int(dec_ratio);
905 decim = (1 << dec_rate);
906
907 sym_peak *= 576000;
908 K = (1 << config->btr_nco_bits) / (internal->master_clk / 1000);
909 K *= (internal->srate / 1000000) * decim; /*k=k 10^-8*/
910
911 if (K != 0) {
912 K = sym_peak / K;
913 wn = (4 * zeta * zeta) + 1000000;
914 wn = (2 * (loopbw_percent * 1000) * 40 * zeta) /wn; /*wn =wn 10^-8*/
915
916 k_indirect = (wn * wn) / K; /*kindirect = kindirect 10^-6*/
917 k_direct = (2 * wn * zeta) / K; /*kDirect = kDirect 10^-2*/
918 k_direct *= 100;
919
920 k_direct_shift = Log2Int(k_direct) - Log2Int(10000) - 2;
921 k_btr1_rshft = (-1 * k_direct_shift) + config->btr_gain_shift_offset;
922 k_btr1 = k_direct / (1 << k_direct_shift);
923 k_btr1 /= 10000;
924
925 k_indirect_shift = Log2Int(k_indirect + 15) - 20 /*- 2*/;
926 k_btr0_rshft = (-1 * k_indirect_shift) + config->btr_gain_shift_offset;
927 k_btr0 = k_indirect * (1 << (-k_indirect_shift));
928 k_btr0 /= 1000000;
929
930 k_btr2_rshft = 0;
931 if (k_btr0_rshft > 15) {
932 k_btr2_rshft = k_btr0_rshft - 15;
933 k_btr0_rshft = 15;
934 }
935 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, BTR_LOOP_GAIN);
936 STB0899_SETFIELD_VAL(KBTR0_RSHFT, reg, k_btr0_rshft);
937 STB0899_SETFIELD_VAL(KBTR0, reg, k_btr0);
938 STB0899_SETFIELD_VAL(KBTR1_RSHFT, reg, k_btr1_rshft);
939 STB0899_SETFIELD_VAL(KBTR1, reg, k_btr1);
940 STB0899_SETFIELD_VAL(KBTR2_RSHFT, reg, k_btr2_rshft);
941 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_LOOP_GAIN, STB0899_OFF0_BTR_LOOP_GAIN, reg);
942 } else
943 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_LOOP_GAIN, STB0899_OFF0_BTR_LOOP_GAIN, 0xc4c4f);
944 }
945
946 /*
947 * stb0899_dvbs2_set_carr_freq
948 * set nominal frequency for carrier search
949 */
stb0899_dvbs2_set_carr_freq(struct stb0899_state * state,s32 carr_freq,u32 master_clk)950 static void stb0899_dvbs2_set_carr_freq(struct stb0899_state *state, s32 carr_freq, u32 master_clk)
951 {
952 struct stb0899_config *config = state->config;
953 s32 crl_nom_freq;
954 u32 reg;
955
956 crl_nom_freq = (1 << config->crl_nco_bits) / master_clk;
957 crl_nom_freq *= carr_freq;
958 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_NOM_FREQ);
959 STB0899_SETFIELD_VAL(CRL_NOM_FREQ, reg, crl_nom_freq);
960 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_NOM_FREQ, STB0899_OFF0_CRL_NOM_FREQ, reg);
961 }
962
963 /*
964 * stb0899_dvbs2_init_calc
965 * Initialize DVBS2 UWP, CSM, carrier and timing loops
966 */
stb0899_dvbs2_init_calc(struct stb0899_state * state)967 static void stb0899_dvbs2_init_calc(struct stb0899_state *state)
968 {
969 struct stb0899_internal *internal = &state->internal;
970 s32 steps, step_size;
971 u32 range, reg;
972
973 /* config uwp and csm */
974 stb0899_dvbs2_config_uwp(state);
975 stb0899_dvbs2_config_csm_auto(state);
976
977 /* initialize BTR */
978 stb0899_dvbs2_set_srate(state);
979 stb0899_dvbs2_set_btr_loopbw(state);
980
981 if (internal->srate / 1000000 >= 15)
982 step_size = (1 << 17) / 5;
983 else if (internal->srate / 1000000 >= 10)
984 step_size = (1 << 17) / 7;
985 else if (internal->srate / 1000000 >= 5)
986 step_size = (1 << 17) / 10;
987 else
988 step_size = (1 << 17) / 4;
989
990 range = internal->srch_range / 1000000;
991 steps = (10 * range * (1 << 17)) / (step_size * (internal->srate / 1000000));
992 steps = (steps + 6) / 10;
993 steps = (steps == 0) ? 1 : steps;
994 if (steps % 2 == 0)
995 stb0899_dvbs2_set_carr_freq(state, internal->center_freq -
996 (internal->step_size * (internal->srate / 20000000)),
997 (internal->master_clk) / 1000000);
998 else
999 stb0899_dvbs2_set_carr_freq(state, internal->center_freq, (internal->master_clk) / 1000000);
1000
1001 /*Set Carrier Search params (zigzag, num steps and freq step size*/
1002 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, ACQ_CNTRL2);
1003 STB0899_SETFIELD_VAL(ZIGZAG, reg, 1);
1004 STB0899_SETFIELD_VAL(NUM_STEPS, reg, steps);
1005 STB0899_SETFIELD_VAL(FREQ_STEPSIZE, reg, step_size);
1006 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_ACQ_CNTRL2, STB0899_OFF0_ACQ_CNTRL2, reg);
1007 }
1008
1009 /*
1010 * stb0899_dvbs2_btr_init
1011 * initialize the timing loop
1012 */
stb0899_dvbs2_btr_init(struct stb0899_state * state)1013 static void stb0899_dvbs2_btr_init(struct stb0899_state *state)
1014 {
1015 u32 reg;
1016
1017 /* set enable BTR loopback */
1018 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, BTR_CNTRL);
1019 STB0899_SETFIELD_VAL(INTRP_PHS_SENSE, reg, 1);
1020 STB0899_SETFIELD_VAL(BTR_ERR_ENA, reg, 1);
1021 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_CNTRL, STB0899_OFF0_BTR_CNTRL, reg);
1022
1023 /* fix btr freq accum at 0 */
1024 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_FREQ_INIT, STB0899_OFF0_BTR_FREQ_INIT, 0x10000000);
1025 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_FREQ_INIT, STB0899_OFF0_BTR_FREQ_INIT, 0x00000000);
1026
1027 /* fix btr freq accum at 0 */
1028 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_PHS_INIT, STB0899_OFF0_BTR_PHS_INIT, 0x10000000);
1029 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_PHS_INIT, STB0899_OFF0_BTR_PHS_INIT, 0x00000000);
1030 }
1031
1032 /*
1033 * stb0899_dvbs2_reacquire
1034 * trigger a DVB-S2 acquisition
1035 */
stb0899_dvbs2_reacquire(struct stb0899_state * state)1036 static void stb0899_dvbs2_reacquire(struct stb0899_state *state)
1037 {
1038 u32 reg = 0;
1039
1040 /* demod soft reset */
1041 STB0899_SETFIELD_VAL(DVBS2_RESET, reg, 1);
1042 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_RESET_CNTRL, STB0899_OFF0_RESET_CNTRL, reg);
1043
1044 /*Reset Timing Loop */
1045 stb0899_dvbs2_btr_init(state);
1046
1047 /* reset Carrier loop */
1048 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_FREQ_INIT, STB0899_OFF0_CRL_FREQ_INIT, (1 << 30));
1049 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_FREQ_INIT, STB0899_OFF0_CRL_FREQ_INIT, 0);
1050 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_LOOP_GAIN, STB0899_OFF0_CRL_LOOP_GAIN, 0);
1051 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_PHS_INIT, STB0899_OFF0_CRL_PHS_INIT, (1 << 30));
1052 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_PHS_INIT, STB0899_OFF0_CRL_PHS_INIT, 0);
1053
1054 /*release demod soft reset */
1055 reg = 0;
1056 STB0899_SETFIELD_VAL(DVBS2_RESET, reg, 0);
1057 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_RESET_CNTRL, STB0899_OFF0_RESET_CNTRL, reg);
1058
1059 /* start acquisition process */
1060 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_ACQUIRE_TRIG, STB0899_OFF0_ACQUIRE_TRIG, 1);
1061 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_LOCK_LOST, STB0899_OFF0_LOCK_LOST, 0);
1062
1063 /* equalizer Init */
1064 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_EQUALIZER_INIT, STB0899_OFF0_EQUALIZER_INIT, 1);
1065
1066 /*Start equilizer */
1067 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_EQUALIZER_INIT, STB0899_OFF0_EQUALIZER_INIT, 0);
1068
1069 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, EQ_CNTRL);
1070 STB0899_SETFIELD_VAL(EQ_SHIFT, reg, 0);
1071 STB0899_SETFIELD_VAL(EQ_DISABLE_UPDATE, reg, 0);
1072 STB0899_SETFIELD_VAL(EQ_DELAY, reg, 0x05);
1073 STB0899_SETFIELD_VAL(EQ_ADAPT_MODE, reg, 0x01);
1074 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_EQ_CNTRL, STB0899_OFF0_EQ_CNTRL, reg);
1075
1076 /* RESET Packet delineator */
1077 stb0899_write_reg(state, STB0899_PDELCTRL, 0x4a);
1078 }
1079
1080 /*
1081 * stb0899_dvbs2_get_dmd_status
1082 * get DVB-S2 Demod LOCK status
1083 */
stb0899_dvbs2_get_dmd_status(struct stb0899_state * state,int timeout)1084 static enum stb0899_status stb0899_dvbs2_get_dmd_status(struct stb0899_state *state, int timeout)
1085 {
1086 int time = -10, lock = 0, uwp, csm;
1087 u32 reg;
1088
1089 do {
1090 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_STATUS);
1091 dprintk(state->verbose, FE_DEBUG, 1, "DMD_STATUS=[0x%02x]", reg);
1092 if (STB0899_GETFIELD(IF_AGC_LOCK, reg))
1093 dprintk(state->verbose, FE_DEBUG, 1, "------------->IF AGC LOCKED !");
1094 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_STAT2);
1095 dprintk(state->verbose, FE_DEBUG, 1, "----------->DMD STAT2=[0x%02x]", reg);
1096 uwp = STB0899_GETFIELD(UWP_LOCK, reg);
1097 csm = STB0899_GETFIELD(CSM_LOCK, reg);
1098 if (uwp && csm)
1099 lock = 1;
1100
1101 time += 10;
1102 msleep(10);
1103
1104 } while ((!lock) && (time <= timeout));
1105
1106 if (lock) {
1107 dprintk(state->verbose, FE_DEBUG, 1, "----------------> DVB-S2 LOCK !");
1108 return DVBS2_DEMOD_LOCK;
1109 } else {
1110 return DVBS2_DEMOD_NOLOCK;
1111 }
1112 }
1113
1114 /*
1115 * stb0899_dvbs2_get_data_lock
1116 * get FEC status
1117 */
stb0899_dvbs2_get_data_lock(struct stb0899_state * state,int timeout)1118 static int stb0899_dvbs2_get_data_lock(struct stb0899_state *state, int timeout)
1119 {
1120 int time = 0, lock = 0;
1121 u8 reg;
1122
1123 while ((!lock) && (time < timeout)) {
1124 reg = stb0899_read_reg(state, STB0899_CFGPDELSTATUS1);
1125 dprintk(state->verbose, FE_DEBUG, 1, "---------> CFGPDELSTATUS=[0x%02x]", reg);
1126 lock = STB0899_GETFIELD(CFGPDELSTATUS_LOCK, reg);
1127 time++;
1128 }
1129
1130 return lock;
1131 }
1132
1133 /*
1134 * stb0899_dvbs2_get_fec_status
1135 * get DVB-S2 FEC LOCK status
1136 */
stb0899_dvbs2_get_fec_status(struct stb0899_state * state,int timeout)1137 static enum stb0899_status stb0899_dvbs2_get_fec_status(struct stb0899_state *state, int timeout)
1138 {
1139 int time = 0, Locked;
1140
1141 do {
1142 Locked = stb0899_dvbs2_get_data_lock(state, 1);
1143 time++;
1144 msleep(1);
1145
1146 } while ((!Locked) && (time < timeout));
1147
1148 if (Locked) {
1149 dprintk(state->verbose, FE_DEBUG, 1, "---------->DVB-S2 FEC LOCK !");
1150 return DVBS2_FEC_LOCK;
1151 } else {
1152 return DVBS2_FEC_NOLOCK;
1153 }
1154 }
1155
1156
1157 /*
1158 * stb0899_dvbs2_init_csm
1159 * set parameters for manual mode
1160 */
stb0899_dvbs2_init_csm(struct stb0899_state * state,int pilots,enum stb0899_modcod modcod)1161 static void stb0899_dvbs2_init_csm(struct stb0899_state *state, int pilots, enum stb0899_modcod modcod)
1162 {
1163 struct stb0899_internal *internal = &state->internal;
1164
1165 s32 dvt_tbl = 1, two_pass = 0, agc_gain = 6, agc_shift = 0, loop_shift = 0, phs_diff_thr = 0x80;
1166 s32 gamma_acq, gamma_rho_acq, gamma_trk, gamma_rho_trk, lock_count_thr;
1167 u32 csm1, csm2, csm3, csm4;
1168
1169 if (((internal->master_clk / internal->srate) <= 4) && (modcod <= 11) && (pilots == 1)) {
1170 switch (modcod) {
1171 case STB0899_QPSK_12:
1172 gamma_acq = 25;
1173 gamma_rho_acq = 2700;
1174 gamma_trk = 12;
1175 gamma_rho_trk = 180;
1176 lock_count_thr = 8;
1177 break;
1178 case STB0899_QPSK_35:
1179 gamma_acq = 38;
1180 gamma_rho_acq = 7182;
1181 gamma_trk = 14;
1182 gamma_rho_trk = 308;
1183 lock_count_thr = 8;
1184 break;
1185 case STB0899_QPSK_23:
1186 gamma_acq = 42;
1187 gamma_rho_acq = 9408;
1188 gamma_trk = 17;
1189 gamma_rho_trk = 476;
1190 lock_count_thr = 8;
1191 break;
1192 case STB0899_QPSK_34:
1193 gamma_acq = 53;
1194 gamma_rho_acq = 16642;
1195 gamma_trk = 19;
1196 gamma_rho_trk = 646;
1197 lock_count_thr = 8;
1198 break;
1199 case STB0899_QPSK_45:
1200 gamma_acq = 53;
1201 gamma_rho_acq = 17119;
1202 gamma_trk = 22;
1203 gamma_rho_trk = 880;
1204 lock_count_thr = 8;
1205 break;
1206 case STB0899_QPSK_56:
1207 gamma_acq = 55;
1208 gamma_rho_acq = 19250;
1209 gamma_trk = 23;
1210 gamma_rho_trk = 989;
1211 lock_count_thr = 8;
1212 break;
1213 case STB0899_QPSK_89:
1214 gamma_acq = 60;
1215 gamma_rho_acq = 24240;
1216 gamma_trk = 24;
1217 gamma_rho_trk = 1176;
1218 lock_count_thr = 8;
1219 break;
1220 case STB0899_QPSK_910:
1221 gamma_acq = 66;
1222 gamma_rho_acq = 29634;
1223 gamma_trk = 24;
1224 gamma_rho_trk = 1176;
1225 lock_count_thr = 8;
1226 break;
1227 default:
1228 gamma_acq = 66;
1229 gamma_rho_acq = 29634;
1230 gamma_trk = 24;
1231 gamma_rho_trk = 1176;
1232 lock_count_thr = 8;
1233 break;
1234 }
1235
1236 csm1 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL1);
1237 STB0899_SETFIELD_VAL(CSM_AUTO_PARAM, csm1, 0);
1238 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL1, STB0899_OFF0_CSM_CNTRL1, csm1);
1239
1240 csm1 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL1);
1241 csm2 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL2);
1242 csm3 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL3);
1243 csm4 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL4);
1244
1245 STB0899_SETFIELD_VAL(CSM_DVT_TABLE, csm1, dvt_tbl);
1246 STB0899_SETFIELD_VAL(CSM_TWO_PASS, csm1, two_pass);
1247 STB0899_SETFIELD_VAL(CSM_AGC_GAIN, csm1, agc_gain);
1248 STB0899_SETFIELD_VAL(CSM_AGC_SHIFT, csm1, agc_shift);
1249 STB0899_SETFIELD_VAL(FE_LOOP_SHIFT, csm1, loop_shift);
1250 STB0899_SETFIELD_VAL(CSM_GAMMA_ACQ, csm2, gamma_acq);
1251 STB0899_SETFIELD_VAL(CSM_GAMMA_RHOACQ, csm2, gamma_rho_acq);
1252 STB0899_SETFIELD_VAL(CSM_GAMMA_TRACK, csm3, gamma_trk);
1253 STB0899_SETFIELD_VAL(CSM_GAMMA_RHOTRACK, csm3, gamma_rho_trk);
1254 STB0899_SETFIELD_VAL(CSM_LOCKCOUNT_THRESH, csm4, lock_count_thr);
1255 STB0899_SETFIELD_VAL(CSM_PHASEDIFF_THRESH, csm4, phs_diff_thr);
1256
1257 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL1, STB0899_OFF0_CSM_CNTRL1, csm1);
1258 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL2, STB0899_OFF0_CSM_CNTRL2, csm2);
1259 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL3, STB0899_OFF0_CSM_CNTRL3, csm3);
1260 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL4, STB0899_OFF0_CSM_CNTRL4, csm4);
1261 }
1262 }
1263
1264 /*
1265 * stb0899_dvbs2_get_srate
1266 * get DVB-S2 Symbol Rate
1267 */
stb0899_dvbs2_get_srate(struct stb0899_state * state)1268 static u32 stb0899_dvbs2_get_srate(struct stb0899_state *state)
1269 {
1270 struct stb0899_internal *internal = &state->internal;
1271 struct stb0899_config *config = state->config;
1272
1273 u32 bTrNomFreq, srate, decimRate, intval1, intval2, reg;
1274 int div1, div2, rem1, rem2;
1275
1276 div1 = config->btr_nco_bits / 2;
1277 div2 = config->btr_nco_bits - div1 - 1;
1278
1279 bTrNomFreq = STB0899_READ_S2REG(STB0899_S2DEMOD, BTR_NOM_FREQ);
1280
1281 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DECIM_CNTRL);
1282 decimRate = STB0899_GETFIELD(DECIM_RATE, reg);
1283 decimRate = (1 << decimRate);
1284
1285 intval1 = internal->master_clk / (1 << div1);
1286 intval2 = bTrNomFreq / (1 << div2);
1287
1288 rem1 = internal->master_clk % (1 << div1);
1289 rem2 = bTrNomFreq % (1 << div2);
1290 /* only for integer calculation */
1291 srate = (intval1 * intval2) + ((intval1 * rem2) / (1 << div2)) + ((intval2 * rem1) / (1 << div1));
1292 srate /= decimRate; /*symbrate = (btrnomfreq_register_val*MasterClock)/2^(27+decim_rate_field) */
1293
1294 return srate;
1295 }
1296
1297 /*
1298 * stb0899_dvbs2_algo
1299 * Search for signal, timing, carrier and data for a given
1300 * frequency in a given range
1301 */
stb0899_dvbs2_algo(struct stb0899_state * state)1302 enum stb0899_status stb0899_dvbs2_algo(struct stb0899_state *state)
1303 {
1304 struct stb0899_internal *internal = &state->internal;
1305 enum stb0899_modcod modcod;
1306
1307 s32 offsetfreq, searchTime, FecLockTime, pilots, iqSpectrum;
1308 int i = 0;
1309 u32 reg, csm1;
1310
1311 if (internal->srate <= 2000000) {
1312 searchTime = 5000; /* 5000 ms max time to lock UWP and CSM, SYMB <= 2Mbs */
1313 FecLockTime = 350; /* 350 ms max time to lock FEC, SYMB <= 2Mbs */
1314 } else if (internal->srate <= 5000000) {
1315 searchTime = 2500; /* 2500 ms max time to lock UWP and CSM, 2Mbs < SYMB <= 5Mbs */
1316 FecLockTime = 170; /* 170 ms max time to lock FEC, 2Mbs< SYMB <= 5Mbs */
1317 } else if (internal->srate <= 10000000) {
1318 searchTime = 1500; /* 1500 ms max time to lock UWP and CSM, 5Mbs <SYMB <= 10Mbs */
1319 FecLockTime = 80; /* 80 ms max time to lock FEC, 5Mbs< SYMB <= 10Mbs */
1320 } else if (internal->srate <= 15000000) {
1321 searchTime = 500; /* 500 ms max time to lock UWP and CSM, 10Mbs <SYMB <= 15Mbs */
1322 FecLockTime = 50; /* 50 ms max time to lock FEC, 10Mbs< SYMB <= 15Mbs */
1323 } else if (internal->srate <= 20000000) {
1324 searchTime = 300; /* 300 ms max time to lock UWP and CSM, 15Mbs < SYMB <= 20Mbs */
1325 FecLockTime = 30; /* 50 ms max time to lock FEC, 15Mbs< SYMB <= 20Mbs */
1326 } else if (internal->srate <= 25000000) {
1327 searchTime = 250; /* 250 ms max time to lock UWP and CSM, 20 Mbs < SYMB <= 25Mbs */
1328 FecLockTime = 25; /* 25 ms max time to lock FEC, 20Mbs< SYMB <= 25Mbs */
1329 } else {
1330 searchTime = 150; /* 150 ms max time to lock UWP and CSM, SYMB > 25Mbs */
1331 FecLockTime = 20; /* 20 ms max time to lock FEC, 20Mbs< SYMB <= 25Mbs */
1332 }
1333
1334 /* Maintain Stream Merger in reset during acquisition */
1335 reg = stb0899_read_reg(state, STB0899_TSTRES);
1336 STB0899_SETFIELD_VAL(FRESRS, reg, 1);
1337 stb0899_write_reg(state, STB0899_TSTRES, reg);
1338
1339 /* enable tuner I/O */
1340 stb0899_i2c_gate_ctrl(&state->frontend, 1);
1341
1342 /* Move tuner to frequency */
1343 if (state->config->tuner_set_frequency)
1344 state->config->tuner_set_frequency(&state->frontend, internal->freq);
1345 if (state->config->tuner_get_frequency)
1346 state->config->tuner_get_frequency(&state->frontend, &internal->freq);
1347
1348 /* disable tuner I/O */
1349 stb0899_i2c_gate_ctrl(&state->frontend, 0);
1350
1351 /* Set IF AGC to acquisition */
1352 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, IF_AGC_CNTRL);
1353 STB0899_SETFIELD_VAL(IF_LOOP_GAIN, reg, 4);
1354 STB0899_SETFIELD_VAL(IF_AGC_REF, reg, 32);
1355 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_IF_AGC_CNTRL, STB0899_OFF0_IF_AGC_CNTRL, reg);
1356
1357 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, IF_AGC_CNTRL2);
1358 STB0899_SETFIELD_VAL(IF_AGC_DUMP_PER, reg, 0);
1359 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_IF_AGC_CNTRL2, STB0899_OFF0_IF_AGC_CNTRL2, reg);
1360
1361 /* Initialisation */
1362 stb0899_dvbs2_init_calc(state);
1363
1364 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_CNTRL2);
1365 switch (internal->inversion) {
1366 case IQ_SWAP_OFF:
1367 STB0899_SETFIELD_VAL(SPECTRUM_INVERT, reg, 0);
1368 break;
1369 case IQ_SWAP_ON:
1370 STB0899_SETFIELD_VAL(SPECTRUM_INVERT, reg, 1);
1371 break;
1372 }
1373 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_DMD_CNTRL2, STB0899_OFF0_DMD_CNTRL2, reg);
1374 stb0899_dvbs2_reacquire(state);
1375
1376 /* Wait for demod lock (UWP and CSM) */
1377 internal->status = stb0899_dvbs2_get_dmd_status(state, searchTime);
1378
1379 if (internal->status == DVBS2_DEMOD_LOCK) {
1380 dprintk(state->verbose, FE_DEBUG, 1, "------------> DVB-S2 DEMOD LOCK !");
1381 i = 0;
1382 /* Demod Locked, check FEC status */
1383 internal->status = stb0899_dvbs2_get_fec_status(state, FecLockTime);
1384
1385 /*If false lock (UWP and CSM Locked but no FEC) try 3 time max*/
1386 while ((internal->status != DVBS2_FEC_LOCK) && (i < 3)) {
1387 /* Read the frequency offset*/
1388 offsetfreq = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_FREQ);
1389
1390 /* Set the Nominal frequency to the found frequency offset for the next reacquire*/
1391 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_NOM_FREQ);
1392 STB0899_SETFIELD_VAL(CRL_NOM_FREQ, reg, offsetfreq);
1393 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_NOM_FREQ, STB0899_OFF0_CRL_NOM_FREQ, reg);
1394 stb0899_dvbs2_reacquire(state);
1395 internal->status = stb0899_dvbs2_get_fec_status(state, searchTime);
1396 i++;
1397 }
1398 }
1399
1400 if (internal->status != DVBS2_FEC_LOCK) {
1401 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_CNTRL2);
1402 iqSpectrum = STB0899_GETFIELD(SPECTRUM_INVERT, reg);
1403 /* IQ Spectrum Inversion */
1404 STB0899_SETFIELD_VAL(SPECTRUM_INVERT, reg, !iqSpectrum);
1405 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_DMD_CNTRL2, STB0899_OFF0_DMD_CNTRL2, reg);
1406 /* start acquistion process */
1407 stb0899_dvbs2_reacquire(state);
1408
1409 /* Wait for demod lock (UWP and CSM) */
1410 internal->status = stb0899_dvbs2_get_dmd_status(state, searchTime);
1411 if (internal->status == DVBS2_DEMOD_LOCK) {
1412 i = 0;
1413 /* Demod Locked, check FEC */
1414 internal->status = stb0899_dvbs2_get_fec_status(state, FecLockTime);
1415 /*try thrice for false locks, (UWP and CSM Locked but no FEC) */
1416 while ((internal->status != DVBS2_FEC_LOCK) && (i < 3)) {
1417 /* Read the frequency offset*/
1418 offsetfreq = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_FREQ);
1419
1420 /* Set the Nominal frequency to the found frequency offset for the next reacquire*/
1421 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_NOM_FREQ);
1422 STB0899_SETFIELD_VAL(CRL_NOM_FREQ, reg, offsetfreq);
1423 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_NOM_FREQ, STB0899_OFF0_CRL_NOM_FREQ, reg);
1424
1425 stb0899_dvbs2_reacquire(state);
1426 internal->status = stb0899_dvbs2_get_fec_status(state, searchTime);
1427 i++;
1428 }
1429 }
1430 /*
1431 if (pParams->DVBS2State == FE_DVBS2_FEC_LOCKED)
1432 pParams->IQLocked = !iqSpectrum;
1433 */
1434 }
1435 if (internal->status == DVBS2_FEC_LOCK) {
1436 dprintk(state->verbose, FE_DEBUG, 1, "----------------> DVB-S2 FEC Lock !");
1437 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_STAT2);
1438 modcod = STB0899_GETFIELD(UWP_DECODE_MOD, reg) >> 2;
1439 pilots = STB0899_GETFIELD(UWP_DECODE_MOD, reg) & 0x01;
1440
1441 if ((((10 * internal->master_clk) / (internal->srate / 10)) <= 410) &&
1442 (INRANGE(STB0899_QPSK_23, modcod, STB0899_QPSK_910)) &&
1443 (pilots == 1)) {
1444
1445 stb0899_dvbs2_init_csm(state, pilots, modcod);
1446 /* Wait for UWP,CSM and data LOCK 20ms max */
1447 internal->status = stb0899_dvbs2_get_fec_status(state, FecLockTime);
1448
1449 i = 0;
1450 while ((internal->status != DVBS2_FEC_LOCK) && (i < 3)) {
1451 csm1 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL1);
1452 STB0899_SETFIELD_VAL(CSM_TWO_PASS, csm1, 1);
1453 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL1, STB0899_OFF0_CSM_CNTRL1, csm1);
1454 csm1 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL1);
1455 STB0899_SETFIELD_VAL(CSM_TWO_PASS, csm1, 0);
1456 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL1, STB0899_OFF0_CSM_CNTRL1, csm1);
1457
1458 internal->status = stb0899_dvbs2_get_fec_status(state, FecLockTime);
1459 i++;
1460 }
1461 }
1462
1463 if ((((10 * internal->master_clk) / (internal->srate / 10)) <= 410) &&
1464 (INRANGE(STB0899_QPSK_12, modcod, STB0899_QPSK_35)) &&
1465 (pilots == 1)) {
1466
1467 /* Equalizer Disable update */
1468 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, EQ_CNTRL);
1469 STB0899_SETFIELD_VAL(EQ_DISABLE_UPDATE, reg, 1);
1470 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_EQ_CNTRL, STB0899_OFF0_EQ_CNTRL, reg);
1471 }
1472
1473 /* slow down the Equalizer once locked */
1474 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, EQ_CNTRL);
1475 STB0899_SETFIELD_VAL(EQ_SHIFT, reg, 0x02);
1476 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_EQ_CNTRL, STB0899_OFF0_EQ_CNTRL, reg);
1477
1478 /* Store signal parameters */
1479 offsetfreq = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_FREQ);
1480
1481 offsetfreq = sign_extend32(offsetfreq, 29);
1482
1483 offsetfreq = offsetfreq / ((1 << 30) / 1000);
1484 offsetfreq *= (internal->master_clk / 1000000);
1485
1486 /* store current inversion for next run */
1487 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_CNTRL2);
1488 if (STB0899_GETFIELD(SPECTRUM_INVERT, reg))
1489 internal->inversion = IQ_SWAP_ON;
1490 else
1491 internal->inversion = IQ_SWAP_OFF;
1492
1493 internal->freq = internal->freq + offsetfreq;
1494 internal->srate = stb0899_dvbs2_get_srate(state);
1495
1496 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_STAT2);
1497 internal->modcod = STB0899_GETFIELD(UWP_DECODE_MOD, reg) >> 2;
1498 internal->pilots = STB0899_GETFIELD(UWP_DECODE_MOD, reg) & 0x01;
1499 internal->frame_length = (STB0899_GETFIELD(UWP_DECODE_MOD, reg) >> 1) & 0x01;
1500
1501 /* Set IF AGC to tracking */
1502 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, IF_AGC_CNTRL);
1503 STB0899_SETFIELD_VAL(IF_LOOP_GAIN, reg, 3);
1504
1505 /* if QPSK 1/2,QPSK 3/5 or QPSK 2/3 set IF AGC reference to 16 otherwise 32*/
1506 if (INRANGE(STB0899_QPSK_12, internal->modcod, STB0899_QPSK_23))
1507 STB0899_SETFIELD_VAL(IF_AGC_REF, reg, 16);
1508
1509 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_IF_AGC_CNTRL, STB0899_OFF0_IF_AGC_CNTRL, reg);
1510
1511 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, IF_AGC_CNTRL2);
1512 STB0899_SETFIELD_VAL(IF_AGC_DUMP_PER, reg, 7);
1513 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_IF_AGC_CNTRL2, STB0899_OFF0_IF_AGC_CNTRL2, reg);
1514 }
1515
1516 /* Release Stream Merger Reset */
1517 reg = stb0899_read_reg(state, STB0899_TSTRES);
1518 STB0899_SETFIELD_VAL(FRESRS, reg, 0);
1519 stb0899_write_reg(state, STB0899_TSTRES, reg);
1520
1521 return internal->status;
1522 }
1523