1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2016 MediaTek Inc.
4 * Author: Jungchang Tsao <jungchang.tsao@mediatek.com>
5 * Daniel Hsiao <daniel.hsiao@mediatek.com>
6 * PoChun Lin <pochun.lin@mediatek.com>
7 */
8
9 #include <linux/interrupt.h>
10 #include <linux/kernel.h>
11 #include <linux/slab.h>
12
13 #include "../mtk_vcodec_drv.h"
14 #include "../mtk_vcodec_util.h"
15 #include "../mtk_vcodec_intr.h"
16 #include "../mtk_vcodec_enc.h"
17 #include "../mtk_vcodec_enc_pm.h"
18 #include "../venc_drv_base.h"
19 #include "../venc_ipi_msg.h"
20 #include "../venc_vpu_if.h"
21
22 static const char h264_filler_marker[] = {0x0, 0x0, 0x0, 0x1, 0xc};
23
24 #define H264_FILLER_MARKER_SIZE ARRAY_SIZE(h264_filler_marker)
25 #define VENC_PIC_BITSTREAM_BYTE_CNT 0x0098
26
27 /*
28 * enum venc_h264_frame_type - h264 encoder output bitstream frame type
29 */
30 enum venc_h264_frame_type {
31 VENC_H264_IDR_FRM,
32 VENC_H264_I_FRM,
33 VENC_H264_P_FRM,
34 VENC_H264_B_FRM,
35 };
36
37 /*
38 * enum venc_h264_vpu_work_buf - h264 encoder buffer index
39 */
40 enum venc_h264_vpu_work_buf {
41 VENC_H264_VPU_WORK_BUF_RC_INFO,
42 VENC_H264_VPU_WORK_BUF_RC_CODE,
43 VENC_H264_VPU_WORK_BUF_REC_LUMA,
44 VENC_H264_VPU_WORK_BUF_REC_CHROMA,
45 VENC_H264_VPU_WORK_BUF_REF_LUMA,
46 VENC_H264_VPU_WORK_BUF_REF_CHROMA,
47 VENC_H264_VPU_WORK_BUF_MV_INFO_1,
48 VENC_H264_VPU_WORK_BUF_MV_INFO_2,
49 VENC_H264_VPU_WORK_BUF_SKIP_FRAME,
50 VENC_H264_VPU_WORK_BUF_MAX,
51 };
52
53 /*
54 * enum venc_h264_bs_mode - for bs_mode argument in h264_enc_vpu_encode
55 */
56 enum venc_h264_bs_mode {
57 H264_BS_MODE_SPS,
58 H264_BS_MODE_PPS,
59 H264_BS_MODE_FRAME,
60 };
61
62 /*
63 * struct venc_h264_vpu_config - Structure for h264 encoder configuration
64 * AP-W/R : AP is writer/reader on this item
65 * VPU-W/R: VPU is write/reader on this item
66 * @input_fourcc: input fourcc
67 * @bitrate: target bitrate (in bps)
68 * @pic_w: picture width. Picture size is visible stream resolution, in pixels,
69 * to be used for display purposes; must be smaller or equal to buffer
70 * size.
71 * @pic_h: picture height
72 * @buf_w: buffer width. Buffer size is stream resolution in pixels aligned to
73 * hardware requirements.
74 * @buf_h: buffer height
75 * @gop_size: group of picture size (idr frame)
76 * @intra_period: intra frame period
77 * @framerate: frame rate in fps
78 * @profile: as specified in standard
79 * @level: as specified in standard
80 * @wfd: WFD mode 1:on, 0:off
81 */
82 struct venc_h264_vpu_config {
83 u32 input_fourcc;
84 u32 bitrate;
85 u32 pic_w;
86 u32 pic_h;
87 u32 buf_w;
88 u32 buf_h;
89 u32 gop_size;
90 u32 intra_period;
91 u32 framerate;
92 u32 profile;
93 u32 level;
94 u32 wfd;
95 };
96
97 /*
98 * struct venc_h264_vpu_buf - Structure for buffer information
99 * AP-W/R : AP is writer/reader on this item
100 * VPU-W/R: VPU is write/reader on this item
101 * @iova: IO virtual address
102 * @vpua: VPU side memory addr which is used by RC_CODE
103 * @size: buffer size (in bytes)
104 */
105 struct venc_h264_vpu_buf {
106 u32 iova;
107 u32 vpua;
108 u32 size;
109 };
110
111 /*
112 * struct venc_h264_vsi - Structure for VPU driver control and info share
113 * AP-W/R : AP is writer/reader on this item
114 * VPU-W/R: VPU is write/reader on this item
115 * This structure is allocated in VPU side and shared to AP side.
116 * @config: h264 encoder configuration
117 * @work_bufs: working buffer information in VPU side
118 * The work_bufs here is for storing the 'size' info shared to AP side.
119 * The similar item in struct venc_h264_inst is for memory allocation
120 * in AP side. The AP driver will copy the 'size' from here to the one in
121 * struct mtk_vcodec_mem, then invoke mtk_vcodec_mem_alloc to allocate
122 * the buffer. After that, bypass the 'dma_addr' to the 'iova' field here for
123 * register setting in VPU side.
124 */
125 struct venc_h264_vsi {
126 struct venc_h264_vpu_config config;
127 struct venc_h264_vpu_buf work_bufs[VENC_H264_VPU_WORK_BUF_MAX];
128 };
129
130 /*
131 * struct venc_h264_inst - h264 encoder AP driver instance
132 * @hw_base: h264 encoder hardware register base
133 * @work_bufs: working buffer
134 * @pps_buf: buffer to store the pps bitstream
135 * @work_buf_allocated: working buffer allocated flag
136 * @frm_cnt: encoded frame count
137 * @prepend_hdr: when the v4l2 layer send VENC_SET_PARAM_PREPEND_HEADER cmd
138 * through h264_enc_set_param interface, it will set this flag and prepend the
139 * sps/pps in h264_enc_encode function.
140 * @vpu_inst: VPU instance to exchange information between AP and VPU
141 * @vsi: driver structure allocated by VPU side and shared to AP side for
142 * control and info share
143 * @ctx: context for v4l2 layer integration
144 */
145 struct venc_h264_inst {
146 void __iomem *hw_base;
147 struct mtk_vcodec_mem work_bufs[VENC_H264_VPU_WORK_BUF_MAX];
148 struct mtk_vcodec_mem pps_buf;
149 bool work_buf_allocated;
150 unsigned int frm_cnt;
151 unsigned int skip_frm_cnt;
152 unsigned int prepend_hdr;
153 struct venc_vpu_inst vpu_inst;
154 struct venc_h264_vsi *vsi;
155 struct mtk_vcodec_ctx *ctx;
156 };
157
h264_read_reg(struct venc_h264_inst * inst,u32 addr)158 static inline u32 h264_read_reg(struct venc_h264_inst *inst, u32 addr)
159 {
160 return readl(inst->hw_base + addr);
161 }
162
h264_get_profile(struct venc_h264_inst * inst,unsigned int profile)163 static unsigned int h264_get_profile(struct venc_h264_inst *inst,
164 unsigned int profile)
165 {
166 switch (profile) {
167 case V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE:
168 return 66;
169 case V4L2_MPEG_VIDEO_H264_PROFILE_MAIN:
170 return 77;
171 case V4L2_MPEG_VIDEO_H264_PROFILE_HIGH:
172 return 100;
173 case V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE:
174 mtk_vcodec_err(inst, "unsupported CONSTRAINED_BASELINE");
175 return 0;
176 case V4L2_MPEG_VIDEO_H264_PROFILE_EXTENDED:
177 mtk_vcodec_err(inst, "unsupported EXTENDED");
178 return 0;
179 default:
180 mtk_vcodec_debug(inst, "unsupported profile %d", profile);
181 return 100;
182 }
183 }
184
h264_get_level(struct venc_h264_inst * inst,unsigned int level)185 static unsigned int h264_get_level(struct venc_h264_inst *inst,
186 unsigned int level)
187 {
188 switch (level) {
189 case V4L2_MPEG_VIDEO_H264_LEVEL_1B:
190 mtk_vcodec_err(inst, "unsupported 1B");
191 return 0;
192 case V4L2_MPEG_VIDEO_H264_LEVEL_1_0:
193 return 10;
194 case V4L2_MPEG_VIDEO_H264_LEVEL_1_1:
195 return 11;
196 case V4L2_MPEG_VIDEO_H264_LEVEL_1_2:
197 return 12;
198 case V4L2_MPEG_VIDEO_H264_LEVEL_1_3:
199 return 13;
200 case V4L2_MPEG_VIDEO_H264_LEVEL_2_0:
201 return 20;
202 case V4L2_MPEG_VIDEO_H264_LEVEL_2_1:
203 return 21;
204 case V4L2_MPEG_VIDEO_H264_LEVEL_2_2:
205 return 22;
206 case V4L2_MPEG_VIDEO_H264_LEVEL_3_0:
207 return 30;
208 case V4L2_MPEG_VIDEO_H264_LEVEL_3_1:
209 return 31;
210 case V4L2_MPEG_VIDEO_H264_LEVEL_3_2:
211 return 32;
212 case V4L2_MPEG_VIDEO_H264_LEVEL_4_0:
213 return 40;
214 case V4L2_MPEG_VIDEO_H264_LEVEL_4_1:
215 return 41;
216 case V4L2_MPEG_VIDEO_H264_LEVEL_4_2:
217 return 42;
218 default:
219 mtk_vcodec_debug(inst, "unsupported level %d", level);
220 return 31;
221 }
222 }
223
h264_enc_free_work_buf(struct venc_h264_inst * inst)224 static void h264_enc_free_work_buf(struct venc_h264_inst *inst)
225 {
226 int i;
227
228 mtk_vcodec_debug_enter(inst);
229
230 /* Except the SKIP_FRAME buffers,
231 * other buffers need to be freed by AP.
232 */
233 for (i = 0; i < VENC_H264_VPU_WORK_BUF_MAX; i++) {
234 if (i != VENC_H264_VPU_WORK_BUF_SKIP_FRAME)
235 mtk_vcodec_mem_free(inst->ctx, &inst->work_bufs[i]);
236 }
237
238 mtk_vcodec_mem_free(inst->ctx, &inst->pps_buf);
239
240 mtk_vcodec_debug_leave(inst);
241 }
242
h264_enc_alloc_work_buf(struct venc_h264_inst * inst)243 static int h264_enc_alloc_work_buf(struct venc_h264_inst *inst)
244 {
245 int i;
246 int ret = 0;
247 struct venc_h264_vpu_buf *wb = inst->vsi->work_bufs;
248
249 mtk_vcodec_debug_enter(inst);
250
251 for (i = 0; i < VENC_H264_VPU_WORK_BUF_MAX; i++) {
252 /*
253 * This 'wb' structure is set by VPU side and shared to AP for
254 * buffer allocation and IO virtual addr mapping. For most of
255 * the buffers, AP will allocate the buffer according to 'size'
256 * field and store the IO virtual addr in 'iova' field. There
257 * are two exceptions:
258 * (1) RC_CODE buffer, it's pre-allocated in the VPU side, and
259 * save the VPU addr in the 'vpua' field. The AP will translate
260 * the VPU addr to the corresponding IO virtual addr and store
261 * in 'iova' field for reg setting in VPU side.
262 * (2) SKIP_FRAME buffer, it's pre-allocated in the VPU side,
263 * and save the VPU addr in the 'vpua' field. The AP will
264 * translate the VPU addr to the corresponding AP side virtual
265 * address and do some memcpy access to move to bitstream buffer
266 * assigned by v4l2 layer.
267 */
268 inst->work_bufs[i].size = wb[i].size;
269 if (i == VENC_H264_VPU_WORK_BUF_SKIP_FRAME) {
270 struct mtk_vcodec_fw *handler;
271
272 handler = inst->vpu_inst.ctx->dev->fw_handler;
273 inst->work_bufs[i].va =
274 mtk_vcodec_fw_map_dm_addr(handler, wb[i].vpua);
275 inst->work_bufs[i].dma_addr = 0;
276 } else {
277 ret = mtk_vcodec_mem_alloc(inst->ctx,
278 &inst->work_bufs[i]);
279 if (ret) {
280 mtk_vcodec_err(inst,
281 "cannot allocate buf %d", i);
282 goto err_alloc;
283 }
284 /*
285 * This RC_CODE is pre-allocated by VPU and saved in VPU
286 * addr. So we need use memcpy to copy RC_CODE from VPU
287 * addr into IO virtual addr in 'iova' field for reg
288 * setting in VPU side.
289 */
290 if (i == VENC_H264_VPU_WORK_BUF_RC_CODE) {
291 struct mtk_vcodec_fw *handler;
292 void *tmp_va;
293
294 handler = inst->vpu_inst.ctx->dev->fw_handler;
295 tmp_va = mtk_vcodec_fw_map_dm_addr(handler,
296 wb[i].vpua);
297 memcpy(inst->work_bufs[i].va, tmp_va,
298 wb[i].size);
299 }
300 }
301 wb[i].iova = inst->work_bufs[i].dma_addr;
302
303 mtk_vcodec_debug(inst,
304 "work_buf[%d] va=0x%p iova=%pad size=%zu",
305 i, inst->work_bufs[i].va,
306 &inst->work_bufs[i].dma_addr,
307 inst->work_bufs[i].size);
308 }
309
310 /* the pps_buf is used by AP side only */
311 inst->pps_buf.size = 128;
312 ret = mtk_vcodec_mem_alloc(inst->ctx, &inst->pps_buf);
313 if (ret) {
314 mtk_vcodec_err(inst, "cannot allocate pps_buf");
315 goto err_alloc;
316 }
317
318 mtk_vcodec_debug_leave(inst);
319
320 return ret;
321
322 err_alloc:
323 h264_enc_free_work_buf(inst);
324
325 return ret;
326 }
327
h264_enc_wait_venc_done(struct venc_h264_inst * inst)328 static unsigned int h264_enc_wait_venc_done(struct venc_h264_inst *inst)
329 {
330 unsigned int irq_status = 0;
331 struct mtk_vcodec_ctx *ctx = (struct mtk_vcodec_ctx *)inst->ctx;
332
333 if (!mtk_vcodec_wait_for_done_ctx(ctx, MTK_INST_IRQ_RECEIVED,
334 WAIT_INTR_TIMEOUT_MS)) {
335 irq_status = ctx->irq_status;
336 mtk_vcodec_debug(inst, "irq_status %x <-", irq_status);
337 }
338 return irq_status;
339 }
340
h264_frame_type(struct venc_h264_inst * inst)341 static int h264_frame_type(struct venc_h264_inst *inst)
342 {
343 if ((inst->vsi->config.gop_size != 0 &&
344 (inst->frm_cnt % inst->vsi->config.gop_size) == 0) ||
345 (inst->frm_cnt == 0 && inst->vsi->config.gop_size == 0)) {
346 /* IDR frame */
347 return VENC_H264_IDR_FRM;
348 } else if ((inst->vsi->config.intra_period != 0 &&
349 (inst->frm_cnt % inst->vsi->config.intra_period) == 0) ||
350 (inst->frm_cnt == 0 && inst->vsi->config.intra_period == 0)) {
351 /* I frame */
352 return VENC_H264_I_FRM;
353 } else {
354 return VENC_H264_P_FRM; /* Note: B frames are not supported */
355 }
356 }
h264_encode_sps(struct venc_h264_inst * inst,struct mtk_vcodec_mem * bs_buf,unsigned int * bs_size)357 static int h264_encode_sps(struct venc_h264_inst *inst,
358 struct mtk_vcodec_mem *bs_buf,
359 unsigned int *bs_size)
360 {
361 int ret = 0;
362 unsigned int irq_status;
363
364 mtk_vcodec_debug_enter(inst);
365
366 ret = vpu_enc_encode(&inst->vpu_inst, H264_BS_MODE_SPS, NULL,
367 bs_buf, bs_size, NULL);
368 if (ret)
369 return ret;
370
371 irq_status = h264_enc_wait_venc_done(inst);
372 if (irq_status != MTK_VENC_IRQ_STATUS_SPS) {
373 mtk_vcodec_err(inst, "expect irq status %d",
374 MTK_VENC_IRQ_STATUS_SPS);
375 return -EINVAL;
376 }
377
378 *bs_size = h264_read_reg(inst, VENC_PIC_BITSTREAM_BYTE_CNT);
379 mtk_vcodec_debug(inst, "bs size %d <-", *bs_size);
380
381 return ret;
382 }
383
h264_encode_pps(struct venc_h264_inst * inst,struct mtk_vcodec_mem * bs_buf,unsigned int * bs_size)384 static int h264_encode_pps(struct venc_h264_inst *inst,
385 struct mtk_vcodec_mem *bs_buf,
386 unsigned int *bs_size)
387 {
388 int ret = 0;
389 unsigned int irq_status;
390
391 mtk_vcodec_debug_enter(inst);
392
393 ret = vpu_enc_encode(&inst->vpu_inst, H264_BS_MODE_PPS, NULL,
394 bs_buf, bs_size, NULL);
395 if (ret)
396 return ret;
397
398 irq_status = h264_enc_wait_venc_done(inst);
399 if (irq_status != MTK_VENC_IRQ_STATUS_PPS) {
400 mtk_vcodec_err(inst, "expect irq status %d",
401 MTK_VENC_IRQ_STATUS_PPS);
402 return -EINVAL;
403 }
404
405 *bs_size = h264_read_reg(inst, VENC_PIC_BITSTREAM_BYTE_CNT);
406 mtk_vcodec_debug(inst, "bs size %d <-", *bs_size);
407
408 return ret;
409 }
410
h264_encode_header(struct venc_h264_inst * inst,struct mtk_vcodec_mem * bs_buf,unsigned int * bs_size)411 static int h264_encode_header(struct venc_h264_inst *inst,
412 struct mtk_vcodec_mem *bs_buf,
413 unsigned int *bs_size)
414 {
415 int ret = 0;
416 unsigned int bs_size_sps;
417 unsigned int bs_size_pps;
418
419 ret = h264_encode_sps(inst, bs_buf, &bs_size_sps);
420 if (ret)
421 return ret;
422
423 ret = h264_encode_pps(inst, &inst->pps_buf, &bs_size_pps);
424 if (ret)
425 return ret;
426
427 memcpy(bs_buf->va + bs_size_sps, inst->pps_buf.va, bs_size_pps);
428 *bs_size = bs_size_sps + bs_size_pps;
429
430 return ret;
431 }
432
h264_encode_frame(struct venc_h264_inst * inst,struct venc_frm_buf * frm_buf,struct mtk_vcodec_mem * bs_buf,unsigned int * bs_size)433 static int h264_encode_frame(struct venc_h264_inst *inst,
434 struct venc_frm_buf *frm_buf,
435 struct mtk_vcodec_mem *bs_buf,
436 unsigned int *bs_size)
437 {
438 int ret = 0;
439 unsigned int irq_status;
440 struct venc_frame_info frame_info;
441
442 mtk_vcodec_debug_enter(inst);
443 mtk_vcodec_debug(inst, "frm_cnt = %d\n ", inst->frm_cnt);
444 frame_info.frm_count = inst->frm_cnt;
445 frame_info.skip_frm_count = inst->skip_frm_cnt;
446 frame_info.frm_type = h264_frame_type(inst);
447 mtk_vcodec_debug(inst, "frm_count = %d,skip_frm_count =%d,frm_type=%d.\n",
448 frame_info.frm_count, frame_info.skip_frm_count,
449 frame_info.frm_type);
450 ret = vpu_enc_encode(&inst->vpu_inst, H264_BS_MODE_FRAME, frm_buf,
451 bs_buf, bs_size, &frame_info);
452 if (ret)
453 return ret;
454
455 /*
456 * skip frame case: The skip frame buffer is composed by vpu side only,
457 * it does not trigger the hw, so skip the wait interrupt operation.
458 */
459 if (inst->vpu_inst.state == VEN_IPI_MSG_ENC_STATE_SKIP) {
460 *bs_size = inst->vpu_inst.bs_size;
461 memcpy(bs_buf->va,
462 inst->work_bufs[VENC_H264_VPU_WORK_BUF_SKIP_FRAME].va,
463 *bs_size);
464 ++inst->frm_cnt;
465 ++inst->skip_frm_cnt;
466 return ret;
467 }
468
469 irq_status = h264_enc_wait_venc_done(inst);
470 if (irq_status != MTK_VENC_IRQ_STATUS_FRM) {
471 mtk_vcodec_err(inst, "irq_status=%d failed", irq_status);
472 return -EIO;
473 }
474
475 *bs_size = h264_read_reg(inst, VENC_PIC_BITSTREAM_BYTE_CNT);
476
477 ++inst->frm_cnt;
478 mtk_vcodec_debug(inst, "frm %d bs_size %d key_frm %d <-",
479 inst->frm_cnt, *bs_size, inst->vpu_inst.is_key_frm);
480
481 return ret;
482 }
483
h264_encode_filler(struct venc_h264_inst * inst,void * buf,int size)484 static void h264_encode_filler(struct venc_h264_inst *inst, void *buf,
485 int size)
486 {
487 unsigned char *p = buf;
488
489 if (size < H264_FILLER_MARKER_SIZE) {
490 mtk_vcodec_err(inst, "filler size too small %d", size);
491 return;
492 }
493
494 memcpy(p, h264_filler_marker, ARRAY_SIZE(h264_filler_marker));
495 size -= H264_FILLER_MARKER_SIZE;
496 p += H264_FILLER_MARKER_SIZE;
497 memset(p, 0xff, size);
498 }
499
h264_enc_init(struct mtk_vcodec_ctx * ctx)500 static int h264_enc_init(struct mtk_vcodec_ctx *ctx)
501 {
502 const bool is_ext = MTK_ENC_CTX_IS_EXT(ctx);
503 int ret = 0;
504 struct venc_h264_inst *inst;
505
506 inst = kzalloc(sizeof(*inst), GFP_KERNEL);
507 if (!inst)
508 return -ENOMEM;
509
510 inst->ctx = ctx;
511 inst->vpu_inst.ctx = ctx;
512 inst->vpu_inst.id = is_ext ? SCP_IPI_VENC_H264 : IPI_VENC_H264;
513 inst->hw_base = mtk_vcodec_get_reg_addr(inst->ctx, VENC_SYS);
514
515 mtk_vcodec_debug_enter(inst);
516
517 ret = vpu_enc_init(&inst->vpu_inst);
518
519 inst->vsi = (struct venc_h264_vsi *)inst->vpu_inst.vsi;
520
521 mtk_vcodec_debug_leave(inst);
522
523 if (ret)
524 kfree(inst);
525 else
526 ctx->drv_handle = inst;
527
528 return ret;
529 }
530
h264_enc_encode(void * handle,enum venc_start_opt opt,struct venc_frm_buf * frm_buf,struct mtk_vcodec_mem * bs_buf,struct venc_done_result * result)531 static int h264_enc_encode(void *handle,
532 enum venc_start_opt opt,
533 struct venc_frm_buf *frm_buf,
534 struct mtk_vcodec_mem *bs_buf,
535 struct venc_done_result *result)
536 {
537 int ret = 0;
538 struct venc_h264_inst *inst = (struct venc_h264_inst *)handle;
539 struct mtk_vcodec_ctx *ctx = inst->ctx;
540
541 mtk_vcodec_debug(inst, "opt %d ->", opt);
542
543 enable_irq(ctx->dev->enc_irq);
544
545 switch (opt) {
546 case VENC_START_OPT_ENCODE_SEQUENCE_HEADER: {
547 unsigned int bs_size_hdr;
548
549 ret = h264_encode_header(inst, bs_buf, &bs_size_hdr);
550 if (ret)
551 goto encode_err;
552
553 result->bs_size = bs_size_hdr;
554 result->is_key_frm = false;
555 break;
556 }
557
558 case VENC_START_OPT_ENCODE_FRAME: {
559 int hdr_sz;
560 int hdr_sz_ext;
561 int filler_sz = 0;
562 const int bs_alignment = 128;
563 struct mtk_vcodec_mem tmp_bs_buf;
564 unsigned int bs_size_hdr;
565 unsigned int bs_size_frm;
566
567 if (!inst->prepend_hdr) {
568 ret = h264_encode_frame(inst, frm_buf, bs_buf,
569 &result->bs_size);
570 if (ret)
571 goto encode_err;
572 result->is_key_frm = inst->vpu_inst.is_key_frm;
573 break;
574 }
575
576 mtk_vcodec_debug(inst, "h264_encode_frame prepend SPS/PPS");
577
578 ret = h264_encode_header(inst, bs_buf, &bs_size_hdr);
579 if (ret)
580 goto encode_err;
581
582 hdr_sz = bs_size_hdr;
583 hdr_sz_ext = (hdr_sz & (bs_alignment - 1));
584 if (hdr_sz_ext) {
585 filler_sz = bs_alignment - hdr_sz_ext;
586 if (hdr_sz_ext + H264_FILLER_MARKER_SIZE > bs_alignment)
587 filler_sz += bs_alignment;
588 h264_encode_filler(inst, bs_buf->va + hdr_sz,
589 filler_sz);
590 }
591
592 tmp_bs_buf.va = bs_buf->va + hdr_sz + filler_sz;
593 tmp_bs_buf.dma_addr = bs_buf->dma_addr + hdr_sz + filler_sz;
594 tmp_bs_buf.size = bs_buf->size - (hdr_sz + filler_sz);
595
596 ret = h264_encode_frame(inst, frm_buf, &tmp_bs_buf,
597 &bs_size_frm);
598 if (ret)
599 goto encode_err;
600
601 result->bs_size = hdr_sz + filler_sz + bs_size_frm;
602
603 mtk_vcodec_debug(inst, "hdr %d filler %d frame %d bs %d",
604 hdr_sz, filler_sz, bs_size_frm,
605 result->bs_size);
606
607 inst->prepend_hdr = 0;
608 result->is_key_frm = inst->vpu_inst.is_key_frm;
609 break;
610 }
611
612 default:
613 mtk_vcodec_err(inst, "venc_start_opt %d not supported", opt);
614 ret = -EINVAL;
615 break;
616 }
617
618 encode_err:
619
620 disable_irq(ctx->dev->enc_irq);
621 mtk_vcodec_debug(inst, "opt %d <-", opt);
622
623 return ret;
624 }
625
h264_enc_set_param(void * handle,enum venc_set_param_type type,struct venc_enc_param * enc_prm)626 static int h264_enc_set_param(void *handle,
627 enum venc_set_param_type type,
628 struct venc_enc_param *enc_prm)
629 {
630 int ret = 0;
631 struct venc_h264_inst *inst = (struct venc_h264_inst *)handle;
632
633 mtk_vcodec_debug(inst, "->type=%d", type);
634
635 switch (type) {
636 case VENC_SET_PARAM_ENC:
637 inst->vsi->config.input_fourcc = enc_prm->input_yuv_fmt;
638 inst->vsi->config.bitrate = enc_prm->bitrate;
639 inst->vsi->config.pic_w = enc_prm->width;
640 inst->vsi->config.pic_h = enc_prm->height;
641 inst->vsi->config.buf_w = enc_prm->buf_width;
642 inst->vsi->config.buf_h = enc_prm->buf_height;
643 inst->vsi->config.gop_size = enc_prm->gop_size;
644 inst->vsi->config.framerate = enc_prm->frm_rate;
645 inst->vsi->config.intra_period = enc_prm->intra_period;
646 inst->vsi->config.profile =
647 h264_get_profile(inst, enc_prm->h264_profile);
648 inst->vsi->config.level =
649 h264_get_level(inst, enc_prm->h264_level);
650 inst->vsi->config.wfd = 0;
651 ret = vpu_enc_set_param(&inst->vpu_inst, type, enc_prm);
652 if (ret)
653 break;
654 if (inst->work_buf_allocated) {
655 h264_enc_free_work_buf(inst);
656 inst->work_buf_allocated = false;
657 }
658 ret = h264_enc_alloc_work_buf(inst);
659 if (ret)
660 break;
661 inst->work_buf_allocated = true;
662 break;
663
664 case VENC_SET_PARAM_PREPEND_HEADER:
665 inst->prepend_hdr = 1;
666 mtk_vcodec_debug(inst, "set prepend header mode");
667 break;
668 case VENC_SET_PARAM_FORCE_INTRA:
669 case VENC_SET_PARAM_GOP_SIZE:
670 case VENC_SET_PARAM_INTRA_PERIOD:
671 inst->frm_cnt = 0;
672 inst->skip_frm_cnt = 0;
673 fallthrough;
674 default:
675 ret = vpu_enc_set_param(&inst->vpu_inst, type, enc_prm);
676 break;
677 }
678
679 mtk_vcodec_debug_leave(inst);
680
681 return ret;
682 }
683
h264_enc_deinit(void * handle)684 static int h264_enc_deinit(void *handle)
685 {
686 int ret = 0;
687 struct venc_h264_inst *inst = (struct venc_h264_inst *)handle;
688
689 mtk_vcodec_debug_enter(inst);
690
691 ret = vpu_enc_deinit(&inst->vpu_inst);
692
693 if (inst->work_buf_allocated)
694 h264_enc_free_work_buf(inst);
695
696 mtk_vcodec_debug_leave(inst);
697 kfree(inst);
698
699 return ret;
700 }
701
702 const struct venc_common_if venc_h264_if = {
703 .init = h264_enc_init,
704 .encode = h264_enc_encode,
705 .set_param = h264_enc_set_param,
706 .deinit = h264_enc_deinit,
707 };
708