1 /* SPDX-License-Identifier: MIT 2 * 3 * Copyright © 2019 Intel Corporation 4 */ 5 6 #ifndef _INTEL_DSB_H 7 #define _INTEL_DSB_H 8 9 #include <linux/types.h> 10 11 #include "i915_reg.h" 12 13 struct intel_crtc_state; 14 struct i915_vma; 15 16 enum dsb_id { 17 INVALID_DSB = -1, 18 DSB1, 19 DSB2, 20 DSB3, 21 MAX_DSB_PER_PIPE 22 }; 23 24 struct intel_dsb { 25 enum dsb_id id; 26 u32 *cmd_buf; 27 struct i915_vma *vma; 28 29 /* 30 * free_pos will point the first free entry position 31 * and help in calculating tail of command buffer. 32 */ 33 int free_pos; 34 35 /* 36 * ins_start_offset will help to store start address of the dsb 37 * instuction and help in identifying the batch of auto-increment 38 * register. 39 */ 40 u32 ins_start_offset; 41 }; 42 43 void intel_dsb_prepare(struct intel_crtc_state *crtc_state); 44 void intel_dsb_cleanup(struct intel_crtc_state *crtc_state); 45 void intel_dsb_reg_write(const struct intel_crtc_state *crtc_state, 46 i915_reg_t reg, u32 val); 47 void intel_dsb_indexed_reg_write(const struct intel_crtc_state *crtc_state, 48 i915_reg_t reg, u32 val); 49 void intel_dsb_commit(const struct intel_crtc_state *crtc_state); 50 51 #endif 52