1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2018 BayLibre, SAS 4 * Author: Maxime Jourdan <mjourdan@baylibre.com> 5 */ 6 7 #ifndef __MESON_VDEC_DOS_REGS_H_ 8 #define __MESON_VDEC_DOS_REGS_H_ 9 10 /* DOS registers */ 11 #define VDEC_ASSIST_AMR1_INT8 0x00b4 12 13 #define ASSIST_MBOX1_CLR_REG 0x01d4 14 #define ASSIST_MBOX1_MASK 0x01d8 15 16 #define MPSR 0x0c04 17 #define MCPU_INTR_MSK 0x0c10 18 #define CPSR 0x0c84 19 20 #define IMEM_DMA_CTRL 0x0d00 21 #define IMEM_DMA_ADR 0x0d04 22 #define IMEM_DMA_COUNT 0x0d08 23 #define LMEM_DMA_CTRL 0x0d40 24 25 #define MC_STATUS0 0x2424 26 #define MC_CTRL1 0x242c 27 28 #define PSCALE_RST 0x2440 29 #define PSCALE_CTRL 0x2444 30 #define PSCALE_BMEM_ADDR 0x247c 31 #define PSCALE_BMEM_DAT 0x2480 32 33 #define DBLK_CTRL 0x2544 34 #define DBLK_STATUS 0x254c 35 36 #define GCLK_EN 0x260c 37 #define MDEC_PIC_DC_CTRL 0x2638 38 #define MDEC_PIC_DC_STATUS 0x263c 39 #define ANC0_CANVAS_ADDR 0x2640 40 #define MDEC_PIC_DC_THRESH 0x26e0 41 42 /* Firmware interface registers */ 43 #define AV_SCRATCH_0 0x2700 44 #define AV_SCRATCH_1 0x2704 45 #define AV_SCRATCH_2 0x2708 46 #define AV_SCRATCH_3 0x270c 47 #define AV_SCRATCH_4 0x2710 48 #define AV_SCRATCH_5 0x2714 49 #define AV_SCRATCH_6 0x2718 50 #define AV_SCRATCH_7 0x271c 51 #define AV_SCRATCH_8 0x2720 52 #define AV_SCRATCH_9 0x2724 53 #define AV_SCRATCH_A 0x2728 54 #define AV_SCRATCH_B 0x272c 55 #define AV_SCRATCH_C 0x2730 56 #define AV_SCRATCH_D 0x2734 57 #define AV_SCRATCH_E 0x2738 58 #define AV_SCRATCH_F 0x273c 59 #define AV_SCRATCH_G 0x2740 60 #define AV_SCRATCH_H 0x2744 61 #define AV_SCRATCH_I 0x2748 62 #define AV_SCRATCH_J 0x274c 63 #define AV_SCRATCH_K 0x2750 64 #define AV_SCRATCH_L 0x2754 65 66 #define MPEG1_2_REG 0x3004 67 #define PIC_HEAD_INFO 0x300c 68 #define POWER_CTL_VLD 0x3020 69 #define M4_CONTROL_REG 0x30a4 70 71 /* Stream Buffer (stbuf) regs */ 72 #define VLD_MEM_VIFIFO_START_PTR 0x3100 73 #define VLD_MEM_VIFIFO_CURR_PTR 0x3104 74 #define VLD_MEM_VIFIFO_END_PTR 0x3108 75 #define VLD_MEM_VIFIFO_CONTROL 0x3110 76 #define MEM_FIFO_CNT_BIT 16 77 #define MEM_FILL_ON_LEVEL BIT(10) 78 #define MEM_CTRL_EMPTY_EN BIT(2) 79 #define MEM_CTRL_FILL_EN BIT(1) 80 #define VLD_MEM_VIFIFO_WP 0x3114 81 #define VLD_MEM_VIFIFO_RP 0x3118 82 #define VLD_MEM_VIFIFO_LEVEL 0x311c 83 #define VLD_MEM_VIFIFO_BUF_CNTL 0x3120 84 #define MEM_BUFCTRL_MANUAL BIT(1) 85 #define VLD_MEM_VIFIFO_WRAP_COUNT 0x3144 86 87 #define DCAC_DMA_CTRL 0x3848 88 89 #define DOS_SW_RESET0 0xfc00 90 #define DOS_GCLK_EN0 0xfc04 91 #define DOS_GEN_CTRL0 0xfc08 92 #define DOS_MEM_PD_VDEC 0xfcc0 93 #define DOS_MEM_PD_HEVC 0xfccc 94 #define DOS_SW_RESET3 0xfcd0 95 #define DOS_GCLK_EN3 0xfcd4 96 #define DOS_VDEC_MCRCC_STALL_CTRL 0xfd00 97 98 #endif 99