1 /* 2 * GMC_8_2 Register documentation 3 * 4 * Copyright (C) 2014 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included 14 * in all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24 #ifndef GMC_8_2_SH_MASK_H 25 #define GMC_8_2_SH_MASK_H 26 27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1 28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0 29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2 30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1 31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4 32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2 33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8 34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3 35 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10 36 #define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4 37 #define MC_CONFIG__MCDT_WR_ENABLE_MASK 0x20 38 #define MC_CONFIG__MCDT_WR_ENABLE__SHIFT 0x5 39 #define MC_CONFIG__MCDU_WR_ENABLE_MASK 0x40 40 #define MC_CONFIG__MCDU_WR_ENABLE__SHIFT 0x6 41 #define MC_CONFIG__MCDV_WR_ENABLE_MASK 0x80 42 #define MC_CONFIG__MCDV_WR_ENABLE__SHIFT 0x7 43 #define MC_CONFIG__MC_RD_ENABLE_MASK 0x700 44 #define MC_CONFIG__MC_RD_ENABLE__SHIFT 0x8 45 #define MC_CONFIG__MCC_INDEX_MODE_ENABLE_MASK 0x80000000 46 #define MC_CONFIG__MCC_INDEX_MODE_ENABLE__SHIFT 0x1f 47 #define MC_ARB_ATOMIC__TC_GRP_MASK 0x7 48 #define MC_ARB_ATOMIC__TC_GRP__SHIFT 0x0 49 #define MC_ARB_ATOMIC__TC_GRP_EN_MASK 0x8 50 #define MC_ARB_ATOMIC__TC_GRP_EN__SHIFT 0x3 51 #define MC_ARB_ATOMIC__SDMA_GRP_MASK 0x70 52 #define MC_ARB_ATOMIC__SDMA_GRP__SHIFT 0x4 53 #define MC_ARB_ATOMIC__SDMA_GRP_EN_MASK 0x80 54 #define MC_ARB_ATOMIC__SDMA_GRP_EN__SHIFT 0x7 55 #define MC_ARB_ATOMIC__OUTSTANDING_MASK 0xff00 56 #define MC_ARB_ATOMIC__OUTSTANDING__SHIFT 0x8 57 #define MC_ARB_ATOMIC__ATOMIC_RTN_GRP_MASK 0xff0000 58 #define MC_ARB_ATOMIC__ATOMIC_RTN_GRP__SHIFT 0x10 59 #define MC_ARB_AGE_CNTL__RESET_RD_GROUP0_MASK 0x1 60 #define MC_ARB_AGE_CNTL__RESET_RD_GROUP0__SHIFT 0x0 61 #define MC_ARB_AGE_CNTL__RESET_RD_GROUP1_MASK 0x2 62 #define MC_ARB_AGE_CNTL__RESET_RD_GROUP1__SHIFT 0x1 63 #define MC_ARB_AGE_CNTL__RESET_RD_GROUP2_MASK 0x4 64 #define MC_ARB_AGE_CNTL__RESET_RD_GROUP2__SHIFT 0x2 65 #define MC_ARB_AGE_CNTL__RESET_RD_GROUP3_MASK 0x8 66 #define MC_ARB_AGE_CNTL__RESET_RD_GROUP3__SHIFT 0x3 67 #define MC_ARB_AGE_CNTL__RESET_RD_GROUP4_MASK 0x10 68 #define MC_ARB_AGE_CNTL__RESET_RD_GROUP4__SHIFT 0x4 69 #define MC_ARB_AGE_CNTL__RESET_RD_GROUP5_MASK 0x20 70 #define MC_ARB_AGE_CNTL__RESET_RD_GROUP5__SHIFT 0x5 71 #define MC_ARB_AGE_CNTL__RESET_RD_GROUP6_MASK 0x40 72 #define MC_ARB_AGE_CNTL__RESET_RD_GROUP6__SHIFT 0x6 73 #define MC_ARB_AGE_CNTL__RESET_RD_GROUP7_MASK 0x80 74 #define MC_ARB_AGE_CNTL__RESET_RD_GROUP7__SHIFT 0x7 75 #define MC_ARB_AGE_CNTL__RESET_WR_GROUP0_MASK 0x100 76 #define MC_ARB_AGE_CNTL__RESET_WR_GROUP0__SHIFT 0x8 77 #define MC_ARB_AGE_CNTL__RESET_WR_GROUP1_MASK 0x200 78 #define MC_ARB_AGE_CNTL__RESET_WR_GROUP1__SHIFT 0x9 79 #define MC_ARB_AGE_CNTL__RESET_WR_GROUP2_MASK 0x400 80 #define MC_ARB_AGE_CNTL__RESET_WR_GROUP2__SHIFT 0xa 81 #define MC_ARB_AGE_CNTL__RESET_WR_GROUP3_MASK 0x800 82 #define MC_ARB_AGE_CNTL__RESET_WR_GROUP3__SHIFT 0xb 83 #define MC_ARB_AGE_CNTL__RESET_WR_GROUP4_MASK 0x1000 84 #define MC_ARB_AGE_CNTL__RESET_WR_GROUP4__SHIFT 0xc 85 #define MC_ARB_AGE_CNTL__RESET_WR_GROUP5_MASK 0x2000 86 #define MC_ARB_AGE_CNTL__RESET_WR_GROUP5__SHIFT 0xd 87 #define MC_ARB_AGE_CNTL__RESET_WR_GROUP6_MASK 0x4000 88 #define MC_ARB_AGE_CNTL__RESET_WR_GROUP6__SHIFT 0xe 89 #define MC_ARB_AGE_CNTL__RESET_WR_GROUP7_MASK 0x8000 90 #define MC_ARB_AGE_CNTL__RESET_WR_GROUP7__SHIFT 0xf 91 #define MC_ARB_AGE_CNTL__AGE_LOW_RATE_RD_MASK 0x70000 92 #define MC_ARB_AGE_CNTL__AGE_LOW_RATE_RD__SHIFT 0x10 93 #define MC_ARB_AGE_CNTL__AGE_LOW_RATE_WR_MASK 0x380000 94 #define MC_ARB_AGE_CNTL__AGE_LOW_RATE_WR__SHIFT 0x13 95 #define MC_ARB_AGE_CNTL__TIMER_STALL_RD_MASK 0x400000 96 #define MC_ARB_AGE_CNTL__TIMER_STALL_RD__SHIFT 0x16 97 #define MC_ARB_AGE_CNTL__TIMER_STALL_WR_MASK 0x800000 98 #define MC_ARB_AGE_CNTL__TIMER_STALL_WR__SHIFT 0x17 99 #define MC_ARB_AGE_CNTL__EXTEND_WEIGHT_RD_MASK 0x1000000 100 #define MC_ARB_AGE_CNTL__EXTEND_WEIGHT_RD__SHIFT 0x18 101 #define MC_ARB_AGE_CNTL__EXTEND_WEIGHT_WR_MASK 0x2000000 102 #define MC_ARB_AGE_CNTL__EXTEND_WEIGHT_WR__SHIFT 0x19 103 #define MC_ARB_RET_CREDITS2__ACP_WR_MASK 0xff 104 #define MC_ARB_RET_CREDITS2__ACP_WR__SHIFT 0x0 105 #define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_EN_RD_MASK 0x100 106 #define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_EN_RD__SHIFT 0x8 107 #define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_EN_WR_MASK 0x200 108 #define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_EN_WR__SHIFT 0x9 109 #define MC_ARB_RET_CREDITS2__ACP_RDRET_URG_MASK 0x400 110 #define MC_ARB_RET_CREDITS2__ACP_RDRET_URG__SHIFT 0xa 111 #define MC_ARB_RET_CREDITS2__HDP_RDRET_URG_MASK 0x800 112 #define MC_ARB_RET_CREDITS2__HDP_RDRET_URG__SHIFT 0xb 113 #define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_MONITOR_RD_MASK 0x1000 114 #define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_MONITOR_RD__SHIFT 0xc 115 #define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_MONITOR_WR_MASK 0x2000 116 #define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_MONITOR_WR__SHIFT 0xd 117 #define MC_ARB_RET_CREDITS2__DISABLE_DISP_RDY_RD_MASK 0x4000 118 #define MC_ARB_RET_CREDITS2__DISABLE_DISP_RDY_RD__SHIFT 0xe 119 #define MC_ARB_RET_CREDITS2__DISABLE_ACP_RDY_WR_MASK 0x8000 120 #define MC_ARB_RET_CREDITS2__DISABLE_ACP_RDY_WR__SHIFT 0xf 121 #define MC_ARB_RET_CREDITS2__RDRET_CREDIT_MED_MASK 0xff0000 122 #define MC_ARB_RET_CREDITS2__RDRET_CREDIT_MED__SHIFT 0x10 123 #define MC_ARB_FED_CNTL__MODE_MASK 0x3 124 #define MC_ARB_FED_CNTL__MODE__SHIFT 0x0 125 #define MC_ARB_FED_CNTL__WR_ERR_MASK 0xc 126 #define MC_ARB_FED_CNTL__WR_ERR__SHIFT 0x2 127 #define MC_ARB_FED_CNTL__KEEP_POISON_IN_PAGE_MASK 0x10 128 #define MC_ARB_FED_CNTL__KEEP_POISON_IN_PAGE__SHIFT 0x4 129 #define MC_ARB_FED_CNTL__RDRET_PARITY_NACK_MASK 0x20 130 #define MC_ARB_FED_CNTL__RDRET_PARITY_NACK__SHIFT 0x5 131 #define MC_ARB_FED_CNTL__USE_LEGACY_NACK_MASK 0x40 132 #define MC_ARB_FED_CNTL__USE_LEGACY_NACK__SHIFT 0x6 133 #define MC_ARB_FED_CNTL__DEBUG_RSV_MASK 0xffffff80 134 #define MC_ARB_FED_CNTL__DEBUG_RSV__SHIFT 0x7 135 #define MC_ARB_GECC2_STATUS__CORR_STS0_MASK 0x1 136 #define MC_ARB_GECC2_STATUS__CORR_STS0__SHIFT 0x0 137 #define MC_ARB_GECC2_STATUS__UNCORR_STS0_MASK 0x2 138 #define MC_ARB_GECC2_STATUS__UNCORR_STS0__SHIFT 0x1 139 #define MC_ARB_GECC2_STATUS__FED_STS0_MASK 0x4 140 #define MC_ARB_GECC2_STATUS__FED_STS0__SHIFT 0x2 141 #define MC_ARB_GECC2_STATUS__RSVD0_MASK 0x8 142 #define MC_ARB_GECC2_STATUS__RSVD0__SHIFT 0x3 143 #define MC_ARB_GECC2_STATUS__CORR_STS1_MASK 0x10 144 #define MC_ARB_GECC2_STATUS__CORR_STS1__SHIFT 0x4 145 #define MC_ARB_GECC2_STATUS__UNCORR_STS1_MASK 0x20 146 #define MC_ARB_GECC2_STATUS__UNCORR_STS1__SHIFT 0x5 147 #define MC_ARB_GECC2_STATUS__FED_STS1_MASK 0x40 148 #define MC_ARB_GECC2_STATUS__FED_STS1__SHIFT 0x6 149 #define MC_ARB_GECC2_STATUS__RSVD1_MASK 0x80 150 #define MC_ARB_GECC2_STATUS__RSVD1__SHIFT 0x7 151 #define MC_ARB_GECC2_STATUS__CORR_CLEAR0_MASK 0x100 152 #define MC_ARB_GECC2_STATUS__CORR_CLEAR0__SHIFT 0x8 153 #define MC_ARB_GECC2_STATUS__UNCORR_CLEAR0_MASK 0x200 154 #define MC_ARB_GECC2_STATUS__UNCORR_CLEAR0__SHIFT 0x9 155 #define MC_ARB_GECC2_STATUS__FED_CLEAR0_MASK 0x400 156 #define MC_ARB_GECC2_STATUS__FED_CLEAR0__SHIFT 0xa 157 #define MC_ARB_GECC2_STATUS__RSVD2_MASK 0x800 158 #define MC_ARB_GECC2_STATUS__RSVD2__SHIFT 0xb 159 #define MC_ARB_GECC2_STATUS__CORR_CLEAR1_MASK 0x1000 160 #define MC_ARB_GECC2_STATUS__CORR_CLEAR1__SHIFT 0xc 161 #define MC_ARB_GECC2_STATUS__UNCORR_CLEAR1_MASK 0x2000 162 #define MC_ARB_GECC2_STATUS__UNCORR_CLEAR1__SHIFT 0xd 163 #define MC_ARB_GECC2_STATUS__FED_CLEAR1_MASK 0x4000 164 #define MC_ARB_GECC2_STATUS__FED_CLEAR1__SHIFT 0xe 165 #define MC_ARB_GECC2_STATUS__RSVD3_MASK 0x8000 166 #define MC_ARB_GECC2_STATUS__RSVD3__SHIFT 0xf 167 #define MC_ARB_GECC2_STATUS__RMWRD_CORR_STS0_MASK 0x10000 168 #define MC_ARB_GECC2_STATUS__RMWRD_CORR_STS0__SHIFT 0x10 169 #define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_STS0_MASK 0x20000 170 #define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_STS0__SHIFT 0x11 171 #define MC_ARB_GECC2_STATUS__RSVD4_MASK 0xc0000 172 #define MC_ARB_GECC2_STATUS__RSVD4__SHIFT 0x12 173 #define MC_ARB_GECC2_STATUS__RMWRD_CORR_STS1_MASK 0x100000 174 #define MC_ARB_GECC2_STATUS__RMWRD_CORR_STS1__SHIFT 0x14 175 #define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_STS1_MASK 0x200000 176 #define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_STS1__SHIFT 0x15 177 #define MC_ARB_GECC2_STATUS__RSVD5_MASK 0xc00000 178 #define MC_ARB_GECC2_STATUS__RSVD5__SHIFT 0x16 179 #define MC_ARB_GECC2_STATUS__RMWRD_CORR_CLEAR0_MASK 0x1000000 180 #define MC_ARB_GECC2_STATUS__RMWRD_CORR_CLEAR0__SHIFT 0x18 181 #define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_CLEAR0_MASK 0x2000000 182 #define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_CLEAR0__SHIFT 0x19 183 #define MC_ARB_GECC2_STATUS__RSVD6_MASK 0xc000000 184 #define MC_ARB_GECC2_STATUS__RSVD6__SHIFT 0x1a 185 #define MC_ARB_GECC2_STATUS__RMWRD_CORR_CLEAR1_MASK 0x10000000 186 #define MC_ARB_GECC2_STATUS__RMWRD_CORR_CLEAR1__SHIFT 0x1c 187 #define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_CLEAR1_MASK 0x20000000 188 #define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_CLEAR1__SHIFT 0x1d 189 #define MC_ARB_GECC2_MISC__STREAK_BREAK_MASK 0xf 190 #define MC_ARB_GECC2_MISC__STREAK_BREAK__SHIFT 0x0 191 #define MC_ARB_GECC2_MISC__COL10_HACK_MASK 0x10 192 #define MC_ARB_GECC2_MISC__COL10_HACK__SHIFT 0x4 193 #define MC_ARB_GECC2_MISC__CWRD_IN_REPLAY_MASK 0x20 194 #define MC_ARB_GECC2_MISC__CWRD_IN_REPLAY__SHIFT 0x5 195 #define MC_ARB_GECC2_MISC__NO_EOB_ALL_WR_IN_REPLAY_MASK 0x40 196 #define MC_ARB_GECC2_MISC__NO_EOB_ALL_WR_IN_REPLAY__SHIFT 0x6 197 #define MC_ARB_GECC2_MISC__RMW_LM_WR_STALL_MASK 0x80 198 #define MC_ARB_GECC2_MISC__RMW_LM_WR_STALL__SHIFT 0x7 199 #define MC_ARB_GECC2_MISC__RMW_STALL_RELEASE_MASK 0x100 200 #define MC_ARB_GECC2_MISC__RMW_STALL_RELEASE__SHIFT 0x8 201 #define MC_ARB_GECC2_MISC__WR_EDC_MASK_REPLAY_MASK 0x200 202 #define MC_ARB_GECC2_MISC__WR_EDC_MASK_REPLAY__SHIFT 0x9 203 #define MC_ARB_GECC2_MISC__CWRD_REPLAY_AGAIN_MASK 0x400 204 #define MC_ARB_GECC2_MISC__CWRD_REPLAY_AGAIN__SHIFT 0xa 205 #define MC_ARB_GECC2_MISC__WRRDWR_REPLAY_AGAIN_MASK 0x800 206 #define MC_ARB_GECC2_MISC__WRRDWR_REPLAY_AGAIN__SHIFT 0xb 207 #define MC_ARB_GECC2_MISC__ALLOW_RMW_ERR_AFTER_REPLAY_MASK 0x1000 208 #define MC_ARB_GECC2_MISC__ALLOW_RMW_ERR_AFTER_REPLAY__SHIFT 0xc 209 #define MC_ARB_GECC2_MISC__DEBUG_RSV_MASK 0xffffe000 210 #define MC_ARB_GECC2_MISC__DEBUG_RSV__SHIFT 0xd 211 #define MC_ARB_GECC2_DEBUG__NUM_ERR_BITS_MASK 0x3 212 #define MC_ARB_GECC2_DEBUG__NUM_ERR_BITS__SHIFT 0x0 213 #define MC_ARB_GECC2_DEBUG__DIRECTION_MASK 0x4 214 #define MC_ARB_GECC2_DEBUG__DIRECTION__SHIFT 0x2 215 #define MC_ARB_GECC2_DEBUG__DATA_FIELD_MASK 0x18 216 #define MC_ARB_GECC2_DEBUG__DATA_FIELD__SHIFT 0x3 217 #define MC_ARB_GECC2_DEBUG__SW_INJECTION_MASK 0x20 218 #define MC_ARB_GECC2_DEBUG__SW_INJECTION__SHIFT 0x5 219 #define MC_ARB_GECC2_DEBUG2__PERIOD_MASK 0xff 220 #define MC_ARB_GECC2_DEBUG2__PERIOD__SHIFT 0x0 221 #define MC_ARB_GECC2_DEBUG2__ERR0_START_MASK 0xff00 222 #define MC_ARB_GECC2_DEBUG2__ERR0_START__SHIFT 0x8 223 #define MC_ARB_GECC2_DEBUG2__ERR1_START_MASK 0xff0000 224 #define MC_ARB_GECC2_DEBUG2__ERR1_START__SHIFT 0x10 225 #define MC_ARB_GECC2_DEBUG2__ERR2_START_MASK 0xff000000 226 #define MC_ARB_GECC2_DEBUG2__ERR2_START__SHIFT 0x18 227 #define MC_ARB_PERF_CID__CH0_MASK 0xff 228 #define MC_ARB_PERF_CID__CH0__SHIFT 0x0 229 #define MC_ARB_PERF_CID__CH1_MASK 0xff00 230 #define MC_ARB_PERF_CID__CH1__SHIFT 0x8 231 #define MC_ARB_PERF_CID__CH0_EN_MASK 0x10000 232 #define MC_ARB_PERF_CID__CH0_EN__SHIFT 0x10 233 #define MC_ARB_PERF_CID__CH1_EN_MASK 0x20000 234 #define MC_ARB_PERF_CID__CH1_EN__SHIFT 0x11 235 #define MC_ARB_SNOOP__TC_GRP_RD_MASK 0x7 236 #define MC_ARB_SNOOP__TC_GRP_RD__SHIFT 0x0 237 #define MC_ARB_SNOOP__TC_GRP_RD_EN_MASK 0x8 238 #define MC_ARB_SNOOP__TC_GRP_RD_EN__SHIFT 0x3 239 #define MC_ARB_SNOOP__TC_GRP_WR_MASK 0x70 240 #define MC_ARB_SNOOP__TC_GRP_WR__SHIFT 0x4 241 #define MC_ARB_SNOOP__TC_GRP_WR_EN_MASK 0x80 242 #define MC_ARB_SNOOP__TC_GRP_WR_EN__SHIFT 0x7 243 #define MC_ARB_SNOOP__SDMA_GRP_RD_MASK 0x700 244 #define MC_ARB_SNOOP__SDMA_GRP_RD__SHIFT 0x8 245 #define MC_ARB_SNOOP__SDMA_GRP_RD_EN_MASK 0x800 246 #define MC_ARB_SNOOP__SDMA_GRP_RD_EN__SHIFT 0xb 247 #define MC_ARB_SNOOP__SDMA_GRP_WR_MASK 0x7000 248 #define MC_ARB_SNOOP__SDMA_GRP_WR__SHIFT 0xc 249 #define MC_ARB_SNOOP__SDMA_GRP_WR_EN_MASK 0x8000 250 #define MC_ARB_SNOOP__SDMA_GRP_WR_EN__SHIFT 0xf 251 #define MC_ARB_SNOOP__OUTSTANDING_RD_MASK 0xff0000 252 #define MC_ARB_SNOOP__OUTSTANDING_RD__SHIFT 0x10 253 #define MC_ARB_SNOOP__OUTSTANDING_WR_MASK 0xff000000 254 #define MC_ARB_SNOOP__OUTSTANDING_WR__SHIFT 0x18 255 #define MC_ARB_GRUB__GRUB_WATERMARK_MASK 0xff 256 #define MC_ARB_GRUB__GRUB_WATERMARK__SHIFT 0x0 257 #define MC_ARB_GRUB__GRUB_WATERMARK_PRI_MASK 0xff00 258 #define MC_ARB_GRUB__GRUB_WATERMARK_PRI__SHIFT 0x8 259 #define MC_ARB_GRUB__GRUB_WATERMARK_MED_MASK 0xff0000 260 #define MC_ARB_GRUB__GRUB_WATERMARK_MED__SHIFT 0x10 261 #define MC_ARB_GRUB__REG_WR_EN_MASK 0x3000000 262 #define MC_ARB_GRUB__REG_WR_EN__SHIFT 0x18 263 #define MC_ARB_GRUB__REG_RD_SEL_MASK 0x4000000 264 #define MC_ARB_GRUB__REG_RD_SEL__SHIFT 0x1a 265 #define MC_ARB_GECC2__ENABLE_MASK 0x1 266 #define MC_ARB_GECC2__ENABLE__SHIFT 0x0 267 #define MC_ARB_GECC2__ECC_MODE_MASK 0x6 268 #define MC_ARB_GECC2__ECC_MODE__SHIFT 0x1 269 #define MC_ARB_GECC2__PAGE_BIT0_MASK 0x18 270 #define MC_ARB_GECC2__PAGE_BIT0__SHIFT 0x3 271 #define MC_ARB_GECC2__EXOR_BANK_SEL_MASK 0x60 272 #define MC_ARB_GECC2__EXOR_BANK_SEL__SHIFT 0x5 273 #define MC_ARB_GECC2__NO_GECC_CLI_MASK 0x780 274 #define MC_ARB_GECC2__NO_GECC_CLI__SHIFT 0x7 275 #define MC_ARB_GECC2__READ_ERR_MASK 0x3800 276 #define MC_ARB_GECC2__READ_ERR__SHIFT 0xb 277 #define MC_ARB_GECC2__CLOSE_BANK_RMW_MASK 0x4000 278 #define MC_ARB_GECC2__CLOSE_BANK_RMW__SHIFT 0xe 279 #define MC_ARB_GECC2__COLFIFO_WATER_MASK 0x1f8000 280 #define MC_ARB_GECC2__COLFIFO_WATER__SHIFT 0xf 281 #define MC_ARB_GECC2__WRADDR_CONV_MASK 0x200000 282 #define MC_ARB_GECC2__WRADDR_CONV__SHIFT 0x15 283 #define MC_ARB_GECC2__RMWRD_UNCOR_POISON_MASK 0x400000 284 #define MC_ARB_GECC2__RMWRD_UNCOR_POISON__SHIFT 0x16 285 #define MC_ARB_GECC2_CLI__NO_GECC_CLI0_MASK 0xff 286 #define MC_ARB_GECC2_CLI__NO_GECC_CLI0__SHIFT 0x0 287 #define MC_ARB_GECC2_CLI__NO_GECC_CLI1_MASK 0xff00 288 #define MC_ARB_GECC2_CLI__NO_GECC_CLI1__SHIFT 0x8 289 #define MC_ARB_GECC2_CLI__NO_GECC_CLI2_MASK 0xff0000 290 #define MC_ARB_GECC2_CLI__NO_GECC_CLI2__SHIFT 0x10 291 #define MC_ARB_GECC2_CLI__NO_GECC_CLI3_MASK 0xff000000 292 #define MC_ARB_GECC2_CLI__NO_GECC_CLI3__SHIFT 0x18 293 #define MC_ARB_ADDR_SWIZ0__A8_MASK 0xf 294 #define MC_ARB_ADDR_SWIZ0__A8__SHIFT 0x0 295 #define MC_ARB_ADDR_SWIZ0__A9_MASK 0xf0 296 #define MC_ARB_ADDR_SWIZ0__A9__SHIFT 0x4 297 #define MC_ARB_ADDR_SWIZ0__A10_MASK 0xf00 298 #define MC_ARB_ADDR_SWIZ0__A10__SHIFT 0x8 299 #define MC_ARB_ADDR_SWIZ0__A11_MASK 0xf000 300 #define MC_ARB_ADDR_SWIZ0__A11__SHIFT 0xc 301 #define MC_ARB_ADDR_SWIZ0__A12_MASK 0xf0000 302 #define MC_ARB_ADDR_SWIZ0__A12__SHIFT 0x10 303 #define MC_ARB_ADDR_SWIZ0__A13_MASK 0xf00000 304 #define MC_ARB_ADDR_SWIZ0__A13__SHIFT 0x14 305 #define MC_ARB_ADDR_SWIZ0__A14_MASK 0xf000000 306 #define MC_ARB_ADDR_SWIZ0__A14__SHIFT 0x18 307 #define MC_ARB_ADDR_SWIZ0__A15_MASK 0xf0000000 308 #define MC_ARB_ADDR_SWIZ0__A15__SHIFT 0x1c 309 #define MC_ARB_ADDR_SWIZ1__A16_MASK 0xf 310 #define MC_ARB_ADDR_SWIZ1__A16__SHIFT 0x0 311 #define MC_ARB_ADDR_SWIZ1__A17_MASK 0xf0 312 #define MC_ARB_ADDR_SWIZ1__A17__SHIFT 0x4 313 #define MC_ARB_ADDR_SWIZ1__A18_MASK 0xf00 314 #define MC_ARB_ADDR_SWIZ1__A18__SHIFT 0x8 315 #define MC_ARB_ADDR_SWIZ1__A19_MASK 0xf000 316 #define MC_ARB_ADDR_SWIZ1__A19__SHIFT 0xc 317 #define MC_ARB_MISC3__NO_GECC_EXT_EOB_MASK 0x1 318 #define MC_ARB_MISC3__NO_GECC_EXT_EOB__SHIFT 0x0 319 #define MC_ARB_MISC3__CHAN4_EN_MASK 0x2 320 #define MC_ARB_MISC3__CHAN4_EN__SHIFT 0x1 321 #define MC_ARB_MISC3__CHAN4_ARB_SEL_MASK 0x4 322 #define MC_ARB_MISC3__CHAN4_ARB_SEL__SHIFT 0x2 323 #define MC_ARB_MISC3__UVD_URG_MODE_MASK 0x8 324 #define MC_ARB_MISC3__UVD_URG_MODE__SHIFT 0x3 325 #define MC_ARB_MISC3__UVD_DMIF_HARSH_WT_EN_MASK 0x10 326 #define MC_ARB_MISC3__UVD_DMIF_HARSH_WT_EN__SHIFT 0x4 327 #define MC_ARB_MISC3__TBD_FIELD_MASK 0xffffffe0 328 #define MC_ARB_MISC3__TBD_FIELD__SHIFT 0x5 329 #define MC_ARB_GRUB_PROMOTE__URGENT_RD_MASK 0xff 330 #define MC_ARB_GRUB_PROMOTE__URGENT_RD__SHIFT 0x0 331 #define MC_ARB_GRUB_PROMOTE__URGENT_WR_MASK 0xff00 332 #define MC_ARB_GRUB_PROMOTE__URGENT_WR__SHIFT 0x8 333 #define MC_ARB_GRUB_PROMOTE__PROMOTE_RD_MASK 0xff0000 334 #define MC_ARB_GRUB_PROMOTE__PROMOTE_RD__SHIFT 0x10 335 #define MC_ARB_GRUB_PROMOTE__PROMOTE_WR_MASK 0xff000000 336 #define MC_ARB_GRUB_PROMOTE__PROMOTE_WR__SHIFT 0x18 337 #define MC_ARB_RTT_DATA__PATTERN_MASK 0xff 338 #define MC_ARB_RTT_DATA__PATTERN__SHIFT 0x0 339 #define MC_ARB_RTT_CNTL0__ENABLE_MASK 0x1 340 #define MC_ARB_RTT_CNTL0__ENABLE__SHIFT 0x0 341 #define MC_ARB_RTT_CNTL0__START_IDLE_MASK 0x2 342 #define MC_ARB_RTT_CNTL0__START_IDLE__SHIFT 0x1 343 #define MC_ARB_RTT_CNTL0__START_R2W_MASK 0xc 344 #define MC_ARB_RTT_CNTL0__START_R2W__SHIFT 0x2 345 #define MC_ARB_RTT_CNTL0__FLUSH_ON_ENTER_MASK 0x10 346 #define MC_ARB_RTT_CNTL0__FLUSH_ON_ENTER__SHIFT 0x4 347 #define MC_ARB_RTT_CNTL0__HARSH_START_MASK 0x20 348 #define MC_ARB_RTT_CNTL0__HARSH_START__SHIFT 0x5 349 #define MC_ARB_RTT_CNTL0__TPS_HARSH_PRIORITY_MASK 0x40 350 #define MC_ARB_RTT_CNTL0__TPS_HARSH_PRIORITY__SHIFT 0x6 351 #define MC_ARB_RTT_CNTL0__TWRT_HARSH_PRIORITY_MASK 0x80 352 #define MC_ARB_RTT_CNTL0__TWRT_HARSH_PRIORITY__SHIFT 0x7 353 #define MC_ARB_RTT_CNTL0__BREAK_ON_HARSH_MASK 0x100 354 #define MC_ARB_RTT_CNTL0__BREAK_ON_HARSH__SHIFT 0x8 355 #define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTRD_MASK 0x200 356 #define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTRD__SHIFT 0x9 357 #define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTWR_MASK 0x400 358 #define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTWR__SHIFT 0xa 359 #define MC_ARB_RTT_CNTL0__TRAIN_PERIOD_MASK 0x3800 360 #define MC_ARB_RTT_CNTL0__TRAIN_PERIOD__SHIFT 0xb 361 #define MC_ARB_RTT_CNTL0__START_R2W_RFSH_MASK 0x4000 362 #define MC_ARB_RTT_CNTL0__START_R2W_RFSH__SHIFT 0xe 363 #define MC_ARB_RTT_CNTL0__DEBUG_RSV_0_MASK 0x8000 364 #define MC_ARB_RTT_CNTL0__DEBUG_RSV_0__SHIFT 0xf 365 #define MC_ARB_RTT_CNTL0__DEBUG_RSV_1_MASK 0x10000 366 #define MC_ARB_RTT_CNTL0__DEBUG_RSV_1__SHIFT 0x10 367 #define MC_ARB_RTT_CNTL0__DEBUG_RSV_2_MASK 0x20000 368 #define MC_ARB_RTT_CNTL0__DEBUG_RSV_2__SHIFT 0x11 369 #define MC_ARB_RTT_CNTL0__DEBUG_RSV_3_MASK 0x40000 370 #define MC_ARB_RTT_CNTL0__DEBUG_RSV_3__SHIFT 0x12 371 #define MC_ARB_RTT_CNTL0__DEBUG_RSV_4_MASK 0x80000 372 #define MC_ARB_RTT_CNTL0__DEBUG_RSV_4__SHIFT 0x13 373 #define MC_ARB_RTT_CNTL0__DEBUG_RSV_5_MASK 0x100000 374 #define MC_ARB_RTT_CNTL0__DEBUG_RSV_5__SHIFT 0x14 375 #define MC_ARB_RTT_CNTL0__DEBUG_RSV_6_MASK 0x200000 376 #define MC_ARB_RTT_CNTL0__DEBUG_RSV_6__SHIFT 0x15 377 #define MC_ARB_RTT_CNTL0__DEBUG_RSV_7_MASK 0x400000 378 #define MC_ARB_RTT_CNTL0__DEBUG_RSV_7__SHIFT 0x16 379 #define MC_ARB_RTT_CNTL0__DEBUG_RSV_8_MASK 0x800000 380 #define MC_ARB_RTT_CNTL0__DEBUG_RSV_8__SHIFT 0x17 381 #define MC_ARB_RTT_CNTL0__DATA_CNTL_MASK 0x1000000 382 #define MC_ARB_RTT_CNTL0__DATA_CNTL__SHIFT 0x18 383 #define MC_ARB_RTT_CNTL0__NEIGHBOR_BIT_MASK 0x2000000 384 #define MC_ARB_RTT_CNTL0__NEIGHBOR_BIT__SHIFT 0x19 385 #define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MASK 0x1f 386 #define MC_ARB_RTT_CNTL1__WINDOW_SIZE__SHIFT 0x0 387 #define MC_ARB_RTT_CNTL1__WINDOW_UPDATE_MASK 0x20 388 #define MC_ARB_RTT_CNTL1__WINDOW_UPDATE__SHIFT 0x5 389 #define MC_ARB_RTT_CNTL1__WINDOW_INC_THRESHOLD_MASK 0x1fc0 390 #define MC_ARB_RTT_CNTL1__WINDOW_INC_THRESHOLD__SHIFT 0x6 391 #define MC_ARB_RTT_CNTL1__WINDOW_DEC_THRESHOLD_MASK 0xfe000 392 #define MC_ARB_RTT_CNTL1__WINDOW_DEC_THRESHOLD__SHIFT 0xd 393 #define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MAX_MASK 0x1f00000 394 #define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MAX__SHIFT 0x14 395 #define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MIN_MASK 0x3e000000 396 #define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MIN__SHIFT 0x19 397 #define MC_ARB_RTT_CNTL1__WINDOW_UPDATE_COUNT_MASK 0xc0000000 398 #define MC_ARB_RTT_CNTL1__WINDOW_UPDATE_COUNT__SHIFT 0x1e 399 #define MC_ARB_RTT_CNTL2__SAMPLE_CNT_MASK 0x3f 400 #define MC_ARB_RTT_CNTL2__SAMPLE_CNT__SHIFT 0x0 401 #define MC_ARB_RTT_CNTL2__PHASE_ADJUST_THRESHOLD_MASK 0xfc0 402 #define MC_ARB_RTT_CNTL2__PHASE_ADJUST_THRESHOLD__SHIFT 0x6 403 #define MC_ARB_RTT_CNTL2__PHASE_ADJUST_SIZE_MASK 0x1000 404 #define MC_ARB_RTT_CNTL2__PHASE_ADJUST_SIZE__SHIFT 0xc 405 #define MC_ARB_RTT_CNTL2__FILTER_CNTL_MASK 0x2000 406 #define MC_ARB_RTT_CNTL2__FILTER_CNTL__SHIFT 0xd 407 #define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH0_MASK 0x3 408 #define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH0__SHIFT 0x0 409 #define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH1_MASK 0xc 410 #define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH1__SHIFT 0x2 411 #define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH0_MASK 0xff0 412 #define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH0__SHIFT 0x4 413 #define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH0_MASK 0x1f000 414 #define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH0__SHIFT 0xc 415 #define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH1_MASK 0x1fe0000 416 #define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH1__SHIFT 0x11 417 #define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH1_MASK 0x3e000000 418 #define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH1__SHIFT 0x19 419 #define MC_ARB_CAC_CNTL__ENABLE_MASK 0x1 420 #define MC_ARB_CAC_CNTL__ENABLE__SHIFT 0x0 421 #define MC_ARB_CAC_CNTL__READ_WEIGHT_MASK 0x7e 422 #define MC_ARB_CAC_CNTL__READ_WEIGHT__SHIFT 0x1 423 #define MC_ARB_CAC_CNTL__WRITE_WEIGHT_MASK 0x1f80 424 #define MC_ARB_CAC_CNTL__WRITE_WEIGHT__SHIFT 0x7 425 #define MC_ARB_CAC_CNTL__ALLOW_OVERFLOW_MASK 0x2000 426 #define MC_ARB_CAC_CNTL__ALLOW_OVERFLOW__SHIFT 0xd 427 #define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_ENABLE_MASK 0x20 428 #define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_ENABLE__SHIFT 0x5 429 #define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT4_MASK 0x40 430 #define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT4__SHIFT 0x6 431 #define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT5_MASK 0x80 432 #define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT5__SHIFT 0x7 433 #define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT6_MASK 0x100 434 #define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT6__SHIFT 0x8 435 #define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT7_MASK 0x200 436 #define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT7__SHIFT 0x9 437 #define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT8_MASK 0x400 438 #define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT8__SHIFT 0xa 439 #define MC_ARB_MISC2__POP_IDLE_REPLAY_MASK 0x800 440 #define MC_ARB_MISC2__POP_IDLE_REPLAY__SHIFT 0xb 441 #define MC_ARB_MISC2__RDRET_NO_REORDERING_MASK 0x1000 442 #define MC_ARB_MISC2__RDRET_NO_REORDERING__SHIFT 0xc 443 #define MC_ARB_MISC2__RDRET_NO_BP_MASK 0x2000 444 #define MC_ARB_MISC2__RDRET_NO_BP__SHIFT 0xd 445 #define MC_ARB_MISC2__RDRET_SEQ_SKID_MASK 0x3c000 446 #define MC_ARB_MISC2__RDRET_SEQ_SKID__SHIFT 0xe 447 #define MC_ARB_MISC2__GECC_MASK 0x40000 448 #define MC_ARB_MISC2__GECC__SHIFT 0x12 449 #define MC_ARB_MISC2__GECC_RST_MASK 0x80000 450 #define MC_ARB_MISC2__GECC_RST__SHIFT 0x13 451 #define MC_ARB_MISC2__GECC_STATUS_MASK 0x100000 452 #define MC_ARB_MISC2__GECC_STATUS__SHIFT 0x14 453 #define MC_ARB_MISC2__TAGFIFO_THRESHOLD_MASK 0x1e00000 454 #define MC_ARB_MISC2__TAGFIFO_THRESHOLD__SHIFT 0x15 455 #define MC_ARB_MISC2__WCDR_REPLAY_MASKCNT_MASK 0xe000000 456 #define MC_ARB_MISC2__WCDR_REPLAY_MASKCNT__SHIFT 0x19 457 #define MC_ARB_MISC2__REPLAY_DEBUG_MASK 0x10000000 458 #define MC_ARB_MISC2__REPLAY_DEBUG__SHIFT 0x1c 459 #define MC_ARB_MISC2__ARB_DEBUG29_MASK 0x20000000 460 #define MC_ARB_MISC2__ARB_DEBUG29__SHIFT 0x1d 461 #define MC_ARB_MISC2__SEQ_RDY_POP_IDLE_MASK 0x40000000 462 #define MC_ARB_MISC2__SEQ_RDY_POP_IDLE__SHIFT 0x1e 463 #define MC_ARB_MISC2__TCCDL4_REPLAY_EOB_MASK 0x80000000 464 #define MC_ARB_MISC2__TCCDL4_REPLAY_EOB__SHIFT 0x1f 465 #define MC_ARB_MISC__STICKY_RFSH_MASK 0x1 466 #define MC_ARB_MISC__STICKY_RFSH__SHIFT 0x0 467 #define MC_ARB_MISC__IDLE_RFSH_MASK 0x2 468 #define MC_ARB_MISC__IDLE_RFSH__SHIFT 0x1 469 #define MC_ARB_MISC__STUTTER_RFSH_MASK 0x4 470 #define MC_ARB_MISC__STUTTER_RFSH__SHIFT 0x2 471 #define MC_ARB_MISC__CHAN_COUPLE_MASK 0x7f8 472 #define MC_ARB_MISC__CHAN_COUPLE__SHIFT 0x3 473 #define MC_ARB_MISC__HARSHNESS_MASK 0x7f800 474 #define MC_ARB_MISC__HARSHNESS__SHIFT 0xb 475 #define MC_ARB_MISC__SMART_RDWR_SW_MASK 0x80000 476 #define MC_ARB_MISC__SMART_RDWR_SW__SHIFT 0x13 477 #define MC_ARB_MISC__CALI_ENABLE_MASK 0x100000 478 #define MC_ARB_MISC__CALI_ENABLE__SHIFT 0x14 479 #define MC_ARB_MISC__CALI_RATES_MASK 0x600000 480 #define MC_ARB_MISC__CALI_RATES__SHIFT 0x15 481 #define MC_ARB_MISC__DISPURGVLD_NOWRT_MASK 0x800000 482 #define MC_ARB_MISC__DISPURGVLD_NOWRT__SHIFT 0x17 483 #define MC_ARB_MISC__DISPURG_NOSW2WR_MASK 0x1000000 484 #define MC_ARB_MISC__DISPURG_NOSW2WR__SHIFT 0x18 485 #define MC_ARB_MISC__DISPURG_STALL_MASK 0x2000000 486 #define MC_ARB_MISC__DISPURG_STALL__SHIFT 0x19 487 #define MC_ARB_MISC__DISPURG_THROTTLE_MASK 0x3c000000 488 #define MC_ARB_MISC__DISPURG_THROTTLE__SHIFT 0x1a 489 #define MC_ARB_MISC__EXTEND_WEIGHT_MASK 0x40000000 490 #define MC_ARB_MISC__EXTEND_WEIGHT__SHIFT 0x1e 491 #define MC_ARB_MISC__ACPURG_STALL_MASK 0x80000000 492 #define MC_ARB_MISC__ACPURG_STALL__SHIFT 0x1f 493 #define MC_ARB_BANKMAP__BANK0_MASK 0xf 494 #define MC_ARB_BANKMAP__BANK0__SHIFT 0x0 495 #define MC_ARB_BANKMAP__BANK1_MASK 0xf0 496 #define MC_ARB_BANKMAP__BANK1__SHIFT 0x4 497 #define MC_ARB_BANKMAP__BANK2_MASK 0xf00 498 #define MC_ARB_BANKMAP__BANK2__SHIFT 0x8 499 #define MC_ARB_BANKMAP__BANK3_MASK 0xf000 500 #define MC_ARB_BANKMAP__BANK3__SHIFT 0xc 501 #define MC_ARB_BANKMAP__RANK_MASK 0xf0000 502 #define MC_ARB_BANKMAP__RANK__SHIFT 0x10 503 #define MC_ARB_RAMCFG__NOOFBANK_MASK 0x3 504 #define MC_ARB_RAMCFG__NOOFBANK__SHIFT 0x0 505 #define MC_ARB_RAMCFG__NOOFRANKS_MASK 0x4 506 #define MC_ARB_RAMCFG__NOOFRANKS__SHIFT 0x2 507 #define MC_ARB_RAMCFG__NOOFROWS_MASK 0x38 508 #define MC_ARB_RAMCFG__NOOFROWS__SHIFT 0x3 509 #define MC_ARB_RAMCFG__NOOFCOLS_MASK 0xc0 510 #define MC_ARB_RAMCFG__NOOFCOLS__SHIFT 0x6 511 #define MC_ARB_RAMCFG__CHANSIZE_MASK 0x100 512 #define MC_ARB_RAMCFG__CHANSIZE__SHIFT 0x8 513 #define MC_ARB_RAMCFG__RSV_1_MASK 0x200 514 #define MC_ARB_RAMCFG__RSV_1__SHIFT 0x9 515 #define MC_ARB_RAMCFG__RSV_2_MASK 0x400 516 #define MC_ARB_RAMCFG__RSV_2__SHIFT 0xa 517 #define MC_ARB_RAMCFG__RSV_3_MASK 0x800 518 #define MC_ARB_RAMCFG__RSV_3__SHIFT 0xb 519 #define MC_ARB_RAMCFG__NOOFGROUPS_MASK 0x1000 520 #define MC_ARB_RAMCFG__NOOFGROUPS__SHIFT 0xc 521 #define MC_ARB_RAMCFG__RSV_4_MASK 0x3e000 522 #define MC_ARB_RAMCFG__RSV_4__SHIFT 0xd 523 #define MC_ARB_POP__ENABLE_ARB_MASK 0x1 524 #define MC_ARB_POP__ENABLE_ARB__SHIFT 0x0 525 #define MC_ARB_POP__SPEC_OPEN_MASK 0x2 526 #define MC_ARB_POP__SPEC_OPEN__SHIFT 0x1 527 #define MC_ARB_POP__POP_DEPTH_MASK 0x3c 528 #define MC_ARB_POP__POP_DEPTH__SHIFT 0x2 529 #define MC_ARB_POP__WRDATAINDEX_DEPTH_MASK 0xfc0 530 #define MC_ARB_POP__WRDATAINDEX_DEPTH__SHIFT 0x6 531 #define MC_ARB_POP__SKID_DEPTH_MASK 0x7000 532 #define MC_ARB_POP__SKID_DEPTH__SHIFT 0xc 533 #define MC_ARB_POP__WAIT_AFTER_RFSH_MASK 0x18000 534 #define MC_ARB_POP__WAIT_AFTER_RFSH__SHIFT 0xf 535 #define MC_ARB_POP__QUICK_STOP_MASK 0x20000 536 #define MC_ARB_POP__QUICK_STOP__SHIFT 0x11 537 #define MC_ARB_POP__ENABLE_TWO_PAGE_MASK 0x40000 538 #define MC_ARB_POP__ENABLE_TWO_PAGE__SHIFT 0x12 539 #define MC_ARB_POP__ALLOW_EOB_BY_WRRET_STALL_MASK 0x80000 540 #define MC_ARB_POP__ALLOW_EOB_BY_WRRET_STALL__SHIFT 0x13 541 #define MC_ARB_MINCLKS__READ_CLKS_MASK 0xff 542 #define MC_ARB_MINCLKS__READ_CLKS__SHIFT 0x0 543 #define MC_ARB_MINCLKS__WRITE_CLKS_MASK 0xff00 544 #define MC_ARB_MINCLKS__WRITE_CLKS__SHIFT 0x8 545 #define MC_ARB_MINCLKS__ARB_RW_SWITCH_MASK 0x10000 546 #define MC_ARB_MINCLKS__ARB_RW_SWITCH__SHIFT 0x10 547 #define MC_ARB_MINCLKS__RW_SWITCH_HARSH_MASK 0x60000 548 #define MC_ARB_MINCLKS__RW_SWITCH_HARSH__SHIFT 0x11 549 #define MC_ARB_SQM_CNTL__MIN_PENAL_MASK 0xff 550 #define MC_ARB_SQM_CNTL__MIN_PENAL__SHIFT 0x0 551 #define MC_ARB_SQM_CNTL__DYN_SQM_ENABLE_MASK 0x100 552 #define MC_ARB_SQM_CNTL__DYN_SQM_ENABLE__SHIFT 0x8 553 #define MC_ARB_SQM_CNTL__SQM_RDY16_MASK 0x200 554 #define MC_ARB_SQM_CNTL__SQM_RDY16__SHIFT 0x9 555 #define MC_ARB_SQM_CNTL__SQM_RESERVE_MASK 0xfc00 556 #define MC_ARB_SQM_CNTL__SQM_RESERVE__SHIFT 0xa 557 #define MC_ARB_SQM_CNTL__RATIO_MASK 0xff0000 558 #define MC_ARB_SQM_CNTL__RATIO__SHIFT 0x10 559 #define MC_ARB_SQM_CNTL__RATIO_DEBUG_MASK 0xff000000 560 #define MC_ARB_SQM_CNTL__RATIO_DEBUG__SHIFT 0x18 561 #define MC_ARB_ADDR_HASH__BANK_XOR_ENABLE_MASK 0xf 562 #define MC_ARB_ADDR_HASH__BANK_XOR_ENABLE__SHIFT 0x0 563 #define MC_ARB_ADDR_HASH__COL_XOR_MASK 0xff0 564 #define MC_ARB_ADDR_HASH__COL_XOR__SHIFT 0x4 565 #define MC_ARB_ADDR_HASH__ROW_XOR_MASK 0xffff000 566 #define MC_ARB_ADDR_HASH__ROW_XOR__SHIFT 0xc 567 #define MC_ARB_DRAM_TIMING__ACTRD_MASK 0xff 568 #define MC_ARB_DRAM_TIMING__ACTRD__SHIFT 0x0 569 #define MC_ARB_DRAM_TIMING__ACTWR_MASK 0xff00 570 #define MC_ARB_DRAM_TIMING__ACTWR__SHIFT 0x8 571 #define MC_ARB_DRAM_TIMING__RASMACTRD_MASK 0xff0000 572 #define MC_ARB_DRAM_TIMING__RASMACTRD__SHIFT 0x10 573 #define MC_ARB_DRAM_TIMING__RASMACTWR_MASK 0xff000000 574 #define MC_ARB_DRAM_TIMING__RASMACTWR__SHIFT 0x18 575 #define MC_ARB_DRAM_TIMING2__RAS2RAS_MASK 0xff 576 #define MC_ARB_DRAM_TIMING2__RAS2RAS__SHIFT 0x0 577 #define MC_ARB_DRAM_TIMING2__RP_MASK 0xff00 578 #define MC_ARB_DRAM_TIMING2__RP__SHIFT 0x8 579 #define MC_ARB_DRAM_TIMING2__WRPLUSRP_MASK 0xff0000 580 #define MC_ARB_DRAM_TIMING2__WRPLUSRP__SHIFT 0x10 581 #define MC_ARB_DRAM_TIMING2__BUS_TURN_MASK 0x1f000000 582 #define MC_ARB_DRAM_TIMING2__BUS_TURN__SHIFT 0x18 583 #define MC_ARB_WTM_CNTL_RD__WTMODE_MASK 0x3 584 #define MC_ARB_WTM_CNTL_RD__WTMODE__SHIFT 0x0 585 #define MC_ARB_WTM_CNTL_RD__HARSH_PRI_MASK 0x4 586 #define MC_ARB_WTM_CNTL_RD__HARSH_PRI__SHIFT 0x2 587 #define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP0_MASK 0x8 588 #define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP0__SHIFT 0x3 589 #define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP1_MASK 0x10 590 #define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP1__SHIFT 0x4 591 #define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP2_MASK 0x20 592 #define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP2__SHIFT 0x5 593 #define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP3_MASK 0x40 594 #define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP3__SHIFT 0x6 595 #define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP4_MASK 0x80 596 #define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP4__SHIFT 0x7 597 #define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP5_MASK 0x100 598 #define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP5__SHIFT 0x8 599 #define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP6_MASK 0x200 600 #define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP6__SHIFT 0x9 601 #define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP7_MASK 0x400 602 #define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP7__SHIFT 0xa 603 #define MC_ARB_WTM_CNTL_RD__ACP_HARSH_PRI_MASK 0x800 604 #define MC_ARB_WTM_CNTL_RD__ACP_HARSH_PRI__SHIFT 0xb 605 #define MC_ARB_WTM_CNTL_RD__ACP_OVER_DISP_MASK 0x1000 606 #define MC_ARB_WTM_CNTL_RD__ACP_OVER_DISP__SHIFT 0xc 607 #define MC_ARB_WTM_CNTL_RD__FORCE_ACP_URG_MASK 0x2000 608 #define MC_ARB_WTM_CNTL_RD__FORCE_ACP_URG__SHIFT 0xd 609 #define MC_ARB_WTM_CNTL_WR__WTMODE_MASK 0x3 610 #define MC_ARB_WTM_CNTL_WR__WTMODE__SHIFT 0x0 611 #define MC_ARB_WTM_CNTL_WR__HARSH_PRI_MASK 0x4 612 #define MC_ARB_WTM_CNTL_WR__HARSH_PRI__SHIFT 0x2 613 #define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP0_MASK 0x8 614 #define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP0__SHIFT 0x3 615 #define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP1_MASK 0x10 616 #define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP1__SHIFT 0x4 617 #define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP2_MASK 0x20 618 #define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP2__SHIFT 0x5 619 #define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP3_MASK 0x40 620 #define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP3__SHIFT 0x6 621 #define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP4_MASK 0x80 622 #define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP4__SHIFT 0x7 623 #define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP5_MASK 0x100 624 #define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP5__SHIFT 0x8 625 #define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP6_MASK 0x200 626 #define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP6__SHIFT 0x9 627 #define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP7_MASK 0x400 628 #define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP7__SHIFT 0xa 629 #define MC_ARB_WTM_CNTL_WR__ACP_HARSH_PRI_MASK 0x800 630 #define MC_ARB_WTM_CNTL_WR__ACP_HARSH_PRI__SHIFT 0xb 631 #define MC_ARB_WTM_CNTL_WR__ACP_OVER_DISP_MASK 0x1000 632 #define MC_ARB_WTM_CNTL_WR__ACP_OVER_DISP__SHIFT 0xc 633 #define MC_ARB_WTM_CNTL_WR__FORCE_ACP_URG_MASK 0x2000 634 #define MC_ARB_WTM_CNTL_WR__FORCE_ACP_URG__SHIFT 0xd 635 #define MC_ARB_WTM_GRPWT_RD__GRP0_MASK 0x3 636 #define MC_ARB_WTM_GRPWT_RD__GRP0__SHIFT 0x0 637 #define MC_ARB_WTM_GRPWT_RD__GRP1_MASK 0xc 638 #define MC_ARB_WTM_GRPWT_RD__GRP1__SHIFT 0x2 639 #define MC_ARB_WTM_GRPWT_RD__GRP2_MASK 0x30 640 #define MC_ARB_WTM_GRPWT_RD__GRP2__SHIFT 0x4 641 #define MC_ARB_WTM_GRPWT_RD__GRP3_MASK 0xc0 642 #define MC_ARB_WTM_GRPWT_RD__GRP3__SHIFT 0x6 643 #define MC_ARB_WTM_GRPWT_RD__GRP4_MASK 0x300 644 #define MC_ARB_WTM_GRPWT_RD__GRP4__SHIFT 0x8 645 #define MC_ARB_WTM_GRPWT_RD__GRP5_MASK 0xc00 646 #define MC_ARB_WTM_GRPWT_RD__GRP5__SHIFT 0xa 647 #define MC_ARB_WTM_GRPWT_RD__GRP6_MASK 0x3000 648 #define MC_ARB_WTM_GRPWT_RD__GRP6__SHIFT 0xc 649 #define MC_ARB_WTM_GRPWT_RD__GRP7_MASK 0xc000 650 #define MC_ARB_WTM_GRPWT_RD__GRP7__SHIFT 0xe 651 #define MC_ARB_WTM_GRPWT_RD__GRP_EXT_MASK 0xff0000 652 #define MC_ARB_WTM_GRPWT_RD__GRP_EXT__SHIFT 0x10 653 #define MC_ARB_WTM_GRPWT_WR__GRP0_MASK 0x3 654 #define MC_ARB_WTM_GRPWT_WR__GRP0__SHIFT 0x0 655 #define MC_ARB_WTM_GRPWT_WR__GRP1_MASK 0xc 656 #define MC_ARB_WTM_GRPWT_WR__GRP1__SHIFT 0x2 657 #define MC_ARB_WTM_GRPWT_WR__GRP2_MASK 0x30 658 #define MC_ARB_WTM_GRPWT_WR__GRP2__SHIFT 0x4 659 #define MC_ARB_WTM_GRPWT_WR__GRP3_MASK 0xc0 660 #define MC_ARB_WTM_GRPWT_WR__GRP3__SHIFT 0x6 661 #define MC_ARB_WTM_GRPWT_WR__GRP4_MASK 0x300 662 #define MC_ARB_WTM_GRPWT_WR__GRP4__SHIFT 0x8 663 #define MC_ARB_WTM_GRPWT_WR__GRP5_MASK 0xc00 664 #define MC_ARB_WTM_GRPWT_WR__GRP5__SHIFT 0xa 665 #define MC_ARB_WTM_GRPWT_WR__GRP6_MASK 0x3000 666 #define MC_ARB_WTM_GRPWT_WR__GRP6__SHIFT 0xc 667 #define MC_ARB_WTM_GRPWT_WR__GRP7_MASK 0xc000 668 #define MC_ARB_WTM_GRPWT_WR__GRP7__SHIFT 0xe 669 #define MC_ARB_WTM_GRPWT_WR__GRP_EXT_MASK 0xff0000 670 #define MC_ARB_WTM_GRPWT_WR__GRP_EXT__SHIFT 0x10 671 #define MC_ARB_TM_CNTL_RD__GROUPBY_RANK_MASK 0x1 672 #define MC_ARB_TM_CNTL_RD__GROUPBY_RANK__SHIFT 0x0 673 #define MC_ARB_TM_CNTL_RD__BANK_SELECT_MASK 0x6 674 #define MC_ARB_TM_CNTL_RD__BANK_SELECT__SHIFT 0x1 675 #define MC_ARB_TM_CNTL_RD__MATCH_RANK_MASK 0x8 676 #define MC_ARB_TM_CNTL_RD__MATCH_RANK__SHIFT 0x3 677 #define MC_ARB_TM_CNTL_RD__MATCH_BANK_MASK 0x10 678 #define MC_ARB_TM_CNTL_RD__MATCH_BANK__SHIFT 0x4 679 #define MC_ARB_TM_CNTL_WR__GROUPBY_RANK_MASK 0x1 680 #define MC_ARB_TM_CNTL_WR__GROUPBY_RANK__SHIFT 0x0 681 #define MC_ARB_TM_CNTL_WR__BANK_SELECT_MASK 0x6 682 #define MC_ARB_TM_CNTL_WR__BANK_SELECT__SHIFT 0x1 683 #define MC_ARB_TM_CNTL_WR__MATCH_RANK_MASK 0x8 684 #define MC_ARB_TM_CNTL_WR__MATCH_RANK__SHIFT 0x3 685 #define MC_ARB_TM_CNTL_WR__MATCH_BANK_MASK 0x10 686 #define MC_ARB_TM_CNTL_WR__MATCH_BANK__SHIFT 0x4 687 #define MC_ARB_LAZY0_RD__GROUP0_MASK 0xff 688 #define MC_ARB_LAZY0_RD__GROUP0__SHIFT 0x0 689 #define MC_ARB_LAZY0_RD__GROUP1_MASK 0xff00 690 #define MC_ARB_LAZY0_RD__GROUP1__SHIFT 0x8 691 #define MC_ARB_LAZY0_RD__GROUP2_MASK 0xff0000 692 #define MC_ARB_LAZY0_RD__GROUP2__SHIFT 0x10 693 #define MC_ARB_LAZY0_RD__GROUP3_MASK 0xff000000 694 #define MC_ARB_LAZY0_RD__GROUP3__SHIFT 0x18 695 #define MC_ARB_LAZY0_WR__GROUP0_MASK 0xff 696 #define MC_ARB_LAZY0_WR__GROUP0__SHIFT 0x0 697 #define MC_ARB_LAZY0_WR__GROUP1_MASK 0xff00 698 #define MC_ARB_LAZY0_WR__GROUP1__SHIFT 0x8 699 #define MC_ARB_LAZY0_WR__GROUP2_MASK 0xff0000 700 #define MC_ARB_LAZY0_WR__GROUP2__SHIFT 0x10 701 #define MC_ARB_LAZY0_WR__GROUP3_MASK 0xff000000 702 #define MC_ARB_LAZY0_WR__GROUP3__SHIFT 0x18 703 #define MC_ARB_LAZY1_RD__GROUP4_MASK 0xff 704 #define MC_ARB_LAZY1_RD__GROUP4__SHIFT 0x0 705 #define MC_ARB_LAZY1_RD__GROUP5_MASK 0xff00 706 #define MC_ARB_LAZY1_RD__GROUP5__SHIFT 0x8 707 #define MC_ARB_LAZY1_RD__GROUP6_MASK 0xff0000 708 #define MC_ARB_LAZY1_RD__GROUP6__SHIFT 0x10 709 #define MC_ARB_LAZY1_RD__GROUP7_MASK 0xff000000 710 #define MC_ARB_LAZY1_RD__GROUP7__SHIFT 0x18 711 #define MC_ARB_LAZY1_WR__GROUP4_MASK 0xff 712 #define MC_ARB_LAZY1_WR__GROUP4__SHIFT 0x0 713 #define MC_ARB_LAZY1_WR__GROUP5_MASK 0xff00 714 #define MC_ARB_LAZY1_WR__GROUP5__SHIFT 0x8 715 #define MC_ARB_LAZY1_WR__GROUP6_MASK 0xff0000 716 #define MC_ARB_LAZY1_WR__GROUP6__SHIFT 0x10 717 #define MC_ARB_LAZY1_WR__GROUP7_MASK 0xff000000 718 #define MC_ARB_LAZY1_WR__GROUP7__SHIFT 0x18 719 #define MC_ARB_AGE_RD__RATE_GROUP0_MASK 0x3 720 #define MC_ARB_AGE_RD__RATE_GROUP0__SHIFT 0x0 721 #define MC_ARB_AGE_RD__RATE_GROUP1_MASK 0xc 722 #define MC_ARB_AGE_RD__RATE_GROUP1__SHIFT 0x2 723 #define MC_ARB_AGE_RD__RATE_GROUP2_MASK 0x30 724 #define MC_ARB_AGE_RD__RATE_GROUP2__SHIFT 0x4 725 #define MC_ARB_AGE_RD__RATE_GROUP3_MASK 0xc0 726 #define MC_ARB_AGE_RD__RATE_GROUP3__SHIFT 0x6 727 #define MC_ARB_AGE_RD__RATE_GROUP4_MASK 0x300 728 #define MC_ARB_AGE_RD__RATE_GROUP4__SHIFT 0x8 729 #define MC_ARB_AGE_RD__RATE_GROUP5_MASK 0xc00 730 #define MC_ARB_AGE_RD__RATE_GROUP5__SHIFT 0xa 731 #define MC_ARB_AGE_RD__RATE_GROUP6_MASK 0x3000 732 #define MC_ARB_AGE_RD__RATE_GROUP6__SHIFT 0xc 733 #define MC_ARB_AGE_RD__RATE_GROUP7_MASK 0xc000 734 #define MC_ARB_AGE_RD__RATE_GROUP7__SHIFT 0xe 735 #define MC_ARB_AGE_RD__ENABLE_GROUP0_MASK 0x10000 736 #define MC_ARB_AGE_RD__ENABLE_GROUP0__SHIFT 0x10 737 #define MC_ARB_AGE_RD__ENABLE_GROUP1_MASK 0x20000 738 #define MC_ARB_AGE_RD__ENABLE_GROUP1__SHIFT 0x11 739 #define MC_ARB_AGE_RD__ENABLE_GROUP2_MASK 0x40000 740 #define MC_ARB_AGE_RD__ENABLE_GROUP2__SHIFT 0x12 741 #define MC_ARB_AGE_RD__ENABLE_GROUP3_MASK 0x80000 742 #define MC_ARB_AGE_RD__ENABLE_GROUP3__SHIFT 0x13 743 #define MC_ARB_AGE_RD__ENABLE_GROUP4_MASK 0x100000 744 #define MC_ARB_AGE_RD__ENABLE_GROUP4__SHIFT 0x14 745 #define MC_ARB_AGE_RD__ENABLE_GROUP5_MASK 0x200000 746 #define MC_ARB_AGE_RD__ENABLE_GROUP5__SHIFT 0x15 747 #define MC_ARB_AGE_RD__ENABLE_GROUP6_MASK 0x400000 748 #define MC_ARB_AGE_RD__ENABLE_GROUP6__SHIFT 0x16 749 #define MC_ARB_AGE_RD__ENABLE_GROUP7_MASK 0x800000 750 #define MC_ARB_AGE_RD__ENABLE_GROUP7__SHIFT 0x17 751 #define MC_ARB_AGE_RD__DIVIDE_GROUP0_MASK 0x1000000 752 #define MC_ARB_AGE_RD__DIVIDE_GROUP0__SHIFT 0x18 753 #define MC_ARB_AGE_RD__DIVIDE_GROUP1_MASK 0x2000000 754 #define MC_ARB_AGE_RD__DIVIDE_GROUP1__SHIFT 0x19 755 #define MC_ARB_AGE_RD__DIVIDE_GROUP2_MASK 0x4000000 756 #define MC_ARB_AGE_RD__DIVIDE_GROUP2__SHIFT 0x1a 757 #define MC_ARB_AGE_RD__DIVIDE_GROUP3_MASK 0x8000000 758 #define MC_ARB_AGE_RD__DIVIDE_GROUP3__SHIFT 0x1b 759 #define MC_ARB_AGE_RD__DIVIDE_GROUP4_MASK 0x10000000 760 #define MC_ARB_AGE_RD__DIVIDE_GROUP4__SHIFT 0x1c 761 #define MC_ARB_AGE_RD__DIVIDE_GROUP5_MASK 0x20000000 762 #define MC_ARB_AGE_RD__DIVIDE_GROUP5__SHIFT 0x1d 763 #define MC_ARB_AGE_RD__DIVIDE_GROUP6_MASK 0x40000000 764 #define MC_ARB_AGE_RD__DIVIDE_GROUP6__SHIFT 0x1e 765 #define MC_ARB_AGE_RD__DIVIDE_GROUP7_MASK 0x80000000 766 #define MC_ARB_AGE_RD__DIVIDE_GROUP7__SHIFT 0x1f 767 #define MC_ARB_AGE_WR__RATE_GROUP0_MASK 0x3 768 #define MC_ARB_AGE_WR__RATE_GROUP0__SHIFT 0x0 769 #define MC_ARB_AGE_WR__RATE_GROUP1_MASK 0xc 770 #define MC_ARB_AGE_WR__RATE_GROUP1__SHIFT 0x2 771 #define MC_ARB_AGE_WR__RATE_GROUP2_MASK 0x30 772 #define MC_ARB_AGE_WR__RATE_GROUP2__SHIFT 0x4 773 #define MC_ARB_AGE_WR__RATE_GROUP3_MASK 0xc0 774 #define MC_ARB_AGE_WR__RATE_GROUP3__SHIFT 0x6 775 #define MC_ARB_AGE_WR__RATE_GROUP4_MASK 0x300 776 #define MC_ARB_AGE_WR__RATE_GROUP4__SHIFT 0x8 777 #define MC_ARB_AGE_WR__RATE_GROUP5_MASK 0xc00 778 #define MC_ARB_AGE_WR__RATE_GROUP5__SHIFT 0xa 779 #define MC_ARB_AGE_WR__RATE_GROUP6_MASK 0x3000 780 #define MC_ARB_AGE_WR__RATE_GROUP6__SHIFT 0xc 781 #define MC_ARB_AGE_WR__RATE_GROUP7_MASK 0xc000 782 #define MC_ARB_AGE_WR__RATE_GROUP7__SHIFT 0xe 783 #define MC_ARB_AGE_WR__ENABLE_GROUP0_MASK 0x10000 784 #define MC_ARB_AGE_WR__ENABLE_GROUP0__SHIFT 0x10 785 #define MC_ARB_AGE_WR__ENABLE_GROUP1_MASK 0x20000 786 #define MC_ARB_AGE_WR__ENABLE_GROUP1__SHIFT 0x11 787 #define MC_ARB_AGE_WR__ENABLE_GROUP2_MASK 0x40000 788 #define MC_ARB_AGE_WR__ENABLE_GROUP2__SHIFT 0x12 789 #define MC_ARB_AGE_WR__ENABLE_GROUP3_MASK 0x80000 790 #define MC_ARB_AGE_WR__ENABLE_GROUP3__SHIFT 0x13 791 #define MC_ARB_AGE_WR__ENABLE_GROUP4_MASK 0x100000 792 #define MC_ARB_AGE_WR__ENABLE_GROUP4__SHIFT 0x14 793 #define MC_ARB_AGE_WR__ENABLE_GROUP5_MASK 0x200000 794 #define MC_ARB_AGE_WR__ENABLE_GROUP5__SHIFT 0x15 795 #define MC_ARB_AGE_WR__ENABLE_GROUP6_MASK 0x400000 796 #define MC_ARB_AGE_WR__ENABLE_GROUP6__SHIFT 0x16 797 #define MC_ARB_AGE_WR__ENABLE_GROUP7_MASK 0x800000 798 #define MC_ARB_AGE_WR__ENABLE_GROUP7__SHIFT 0x17 799 #define MC_ARB_AGE_WR__DIVIDE_GROUP0_MASK 0x1000000 800 #define MC_ARB_AGE_WR__DIVIDE_GROUP0__SHIFT 0x18 801 #define MC_ARB_AGE_WR__DIVIDE_GROUP1_MASK 0x2000000 802 #define MC_ARB_AGE_WR__DIVIDE_GROUP1__SHIFT 0x19 803 #define MC_ARB_AGE_WR__DIVIDE_GROUP2_MASK 0x4000000 804 #define MC_ARB_AGE_WR__DIVIDE_GROUP2__SHIFT 0x1a 805 #define MC_ARB_AGE_WR__DIVIDE_GROUP3_MASK 0x8000000 806 #define MC_ARB_AGE_WR__DIVIDE_GROUP3__SHIFT 0x1b 807 #define MC_ARB_AGE_WR__DIVIDE_GROUP4_MASK 0x10000000 808 #define MC_ARB_AGE_WR__DIVIDE_GROUP4__SHIFT 0x1c 809 #define MC_ARB_AGE_WR__DIVIDE_GROUP5_MASK 0x20000000 810 #define MC_ARB_AGE_WR__DIVIDE_GROUP5__SHIFT 0x1d 811 #define MC_ARB_AGE_WR__DIVIDE_GROUP6_MASK 0x40000000 812 #define MC_ARB_AGE_WR__DIVIDE_GROUP6__SHIFT 0x1e 813 #define MC_ARB_AGE_WR__DIVIDE_GROUP7_MASK 0x80000000 814 #define MC_ARB_AGE_WR__DIVIDE_GROUP7__SHIFT 0x1f 815 #define MC_ARB_RFSH_CNTL__ENABLE_MASK 0x1 816 #define MC_ARB_RFSH_CNTL__ENABLE__SHIFT 0x0 817 #define MC_ARB_RFSH_CNTL__URG0_MASK 0x3e 818 #define MC_ARB_RFSH_CNTL__URG0__SHIFT 0x1 819 #define MC_ARB_RFSH_CNTL__URG1_MASK 0x7c0 820 #define MC_ARB_RFSH_CNTL__URG1__SHIFT 0x6 821 #define MC_ARB_RFSH_CNTL__ACCUM_MASK 0x800 822 #define MC_ARB_RFSH_CNTL__ACCUM__SHIFT 0xb 823 #define MC_ARB_RFSH_CNTL__SINGLE_BANK_MASK 0x1000 824 #define MC_ARB_RFSH_CNTL__SINGLE_BANK__SHIFT 0xc 825 #define MC_ARB_RFSH_CNTL__PUSH_SINGLE_BANK_REFRESH_MASK 0x2000 826 #define MC_ARB_RFSH_CNTL__PUSH_SINGLE_BANK_REFRESH__SHIFT 0xd 827 #define MC_ARB_RFSH_CNTL__PENDING_RATE_SEL_MASK 0x1c000 828 #define MC_ARB_RFSH_CNTL__PENDING_RATE_SEL__SHIFT 0xe 829 #define MC_ARB_RFSH_RATE__POWERMODE0_MASK 0xff 830 #define MC_ARB_RFSH_RATE__POWERMODE0__SHIFT 0x0 831 #define MC_ARB_PM_CNTL__OVERRIDE_CGSTATE_MASK 0x3 832 #define MC_ARB_PM_CNTL__OVERRIDE_CGSTATE__SHIFT 0x0 833 #define MC_ARB_PM_CNTL__OVRR_CGRFSH_MASK 0x4 834 #define MC_ARB_PM_CNTL__OVRR_CGRFSH__SHIFT 0x2 835 #define MC_ARB_PM_CNTL__OVRR_CGSQM_MASK 0x8 836 #define MC_ARB_PM_CNTL__OVRR_CGSQM__SHIFT 0x3 837 #define MC_ARB_PM_CNTL__SRFSH_ON_D1_MASK 0x10 838 #define MC_ARB_PM_CNTL__SRFSH_ON_D1__SHIFT 0x4 839 #define MC_ARB_PM_CNTL__BLKOUT_ON_D1_MASK 0x20 840 #define MC_ARB_PM_CNTL__BLKOUT_ON_D1__SHIFT 0x5 841 #define MC_ARB_PM_CNTL__IDLE_ON_D1_MASK 0x40 842 #define MC_ARB_PM_CNTL__IDLE_ON_D1__SHIFT 0x6 843 #define MC_ARB_PM_CNTL__OVRR_PM_MASK 0x80 844 #define MC_ARB_PM_CNTL__OVRR_PM__SHIFT 0x7 845 #define MC_ARB_PM_CNTL__OVRR_PM_STATE_MASK 0x300 846 #define MC_ARB_PM_CNTL__OVRR_PM_STATE__SHIFT 0x8 847 #define MC_ARB_PM_CNTL__OVRR_RD_MASK 0x400 848 #define MC_ARB_PM_CNTL__OVRR_RD__SHIFT 0xa 849 #define MC_ARB_PM_CNTL__OVRR_RD_STATE_MASK 0x800 850 #define MC_ARB_PM_CNTL__OVRR_RD_STATE__SHIFT 0xb 851 #define MC_ARB_PM_CNTL__OVRR_WR_MASK 0x1000 852 #define MC_ARB_PM_CNTL__OVRR_WR__SHIFT 0xc 853 #define MC_ARB_PM_CNTL__OVRR_WR_STATE_MASK 0x2000 854 #define MC_ARB_PM_CNTL__OVRR_WR_STATE__SHIFT 0xd 855 #define MC_ARB_PM_CNTL__OVRR_RFSH_MASK 0x4000 856 #define MC_ARB_PM_CNTL__OVRR_RFSH__SHIFT 0xe 857 #define MC_ARB_PM_CNTL__OVRR_RFSH_STATE_MASK 0x8000 858 #define MC_ARB_PM_CNTL__OVRR_RFSH_STATE__SHIFT 0xf 859 #define MC_ARB_PM_CNTL__OVRR_RD0_BUSY_MASK 0x10000 860 #define MC_ARB_PM_CNTL__OVRR_RD0_BUSY__SHIFT 0x10 861 #define MC_ARB_PM_CNTL__OVRR_RD1_BUSY_MASK 0x20000 862 #define MC_ARB_PM_CNTL__OVRR_RD1_BUSY__SHIFT 0x11 863 #define MC_ARB_PM_CNTL__IDLE_ON_D2_MASK 0x40000 864 #define MC_ARB_PM_CNTL__IDLE_ON_D2__SHIFT 0x12 865 #define MC_ARB_PM_CNTL__IDLE_ON_D3_MASK 0x80000 866 #define MC_ARB_PM_CNTL__IDLE_ON_D3__SHIFT 0x13 867 #define MC_ARB_PM_CNTL__IDLE_CNT_MASK 0xf00000 868 #define MC_ARB_PM_CNTL__IDLE_CNT__SHIFT 0x14 869 #define MC_ARB_PM_CNTL__OVRR_WR0_BUSY_MASK 0x1000000 870 #define MC_ARB_PM_CNTL__OVRR_WR0_BUSY__SHIFT 0x18 871 #define MC_ARB_PM_CNTL__OVRR_WR1_BUSY_MASK 0x2000000 872 #define MC_ARB_PM_CNTL__OVRR_WR1_BUSY__SHIFT 0x19 873 #define MC_ARB_GDEC_RD_CNTL__PAGEBIT0_MASK 0xf 874 #define MC_ARB_GDEC_RD_CNTL__PAGEBIT0__SHIFT 0x0 875 #define MC_ARB_GDEC_RD_CNTL__PAGEBIT1_MASK 0xf0 876 #define MC_ARB_GDEC_RD_CNTL__PAGEBIT1__SHIFT 0x4 877 #define MC_ARB_GDEC_RD_CNTL__USE_RANK_MASK 0x100 878 #define MC_ARB_GDEC_RD_CNTL__USE_RANK__SHIFT 0x8 879 #define MC_ARB_GDEC_RD_CNTL__USE_RSNO_MASK 0x200 880 #define MC_ARB_GDEC_RD_CNTL__USE_RSNO__SHIFT 0x9 881 #define MC_ARB_GDEC_RD_CNTL__REM_DEFAULT_GRP_MASK 0x3c00 882 #define MC_ARB_GDEC_RD_CNTL__REM_DEFAULT_GRP__SHIFT 0xa 883 #define MC_ARB_GDEC_WR_CNTL__PAGEBIT0_MASK 0xf 884 #define MC_ARB_GDEC_WR_CNTL__PAGEBIT0__SHIFT 0x0 885 #define MC_ARB_GDEC_WR_CNTL__PAGEBIT1_MASK 0xf0 886 #define MC_ARB_GDEC_WR_CNTL__PAGEBIT1__SHIFT 0x4 887 #define MC_ARB_GDEC_WR_CNTL__USE_RANK_MASK 0x100 888 #define MC_ARB_GDEC_WR_CNTL__USE_RANK__SHIFT 0x8 889 #define MC_ARB_GDEC_WR_CNTL__USE_RSNO_MASK 0x200 890 #define MC_ARB_GDEC_WR_CNTL__USE_RSNO__SHIFT 0x9 891 #define MC_ARB_GDEC_WR_CNTL__REM_DEFAULT_GRP_MASK 0x3c00 892 #define MC_ARB_GDEC_WR_CNTL__REM_DEFAULT_GRP__SHIFT 0xa 893 #define MC_ARB_LM_RD__STREAK_LIMIT_MASK 0xff 894 #define MC_ARB_LM_RD__STREAK_LIMIT__SHIFT 0x0 895 #define MC_ARB_LM_RD__STREAK_LIMIT_UBER_MASK 0xff00 896 #define MC_ARB_LM_RD__STREAK_LIMIT_UBER__SHIFT 0x8 897 #define MC_ARB_LM_RD__STREAK_BREAK_MASK 0x10000 898 #define MC_ARB_LM_RD__STREAK_BREAK__SHIFT 0x10 899 #define MC_ARB_LM_RD__STREAK_UBER_MASK 0x20000 900 #define MC_ARB_LM_RD__STREAK_UBER__SHIFT 0x11 901 #define MC_ARB_LM_RD__ENABLE_TWO_LIST_MASK 0x40000 902 #define MC_ARB_LM_RD__ENABLE_TWO_LIST__SHIFT 0x12 903 #define MC_ARB_LM_RD__POPIDLE_RST_TWOLIST_MASK 0x80000 904 #define MC_ARB_LM_RD__POPIDLE_RST_TWOLIST__SHIFT 0x13 905 #define MC_ARB_LM_RD__SKID1_RST_TWOLIST_MASK 0x100000 906 #define MC_ARB_LM_RD__SKID1_RST_TWOLIST__SHIFT 0x14 907 #define MC_ARB_LM_RD__BANKGROUP_CONFIG_MASK 0xe00000 908 #define MC_ARB_LM_RD__BANKGROUP_CONFIG__SHIFT 0x15 909 #define MC_ARB_LM_WR__STREAK_LIMIT_MASK 0xff 910 #define MC_ARB_LM_WR__STREAK_LIMIT__SHIFT 0x0 911 #define MC_ARB_LM_WR__STREAK_LIMIT_UBER_MASK 0xff00 912 #define MC_ARB_LM_WR__STREAK_LIMIT_UBER__SHIFT 0x8 913 #define MC_ARB_LM_WR__STREAK_BREAK_MASK 0x10000 914 #define MC_ARB_LM_WR__STREAK_BREAK__SHIFT 0x10 915 #define MC_ARB_LM_WR__STREAK_UBER_MASK 0x20000 916 #define MC_ARB_LM_WR__STREAK_UBER__SHIFT 0x11 917 #define MC_ARB_LM_WR__ENABLE_TWO_LIST_MASK 0x40000 918 #define MC_ARB_LM_WR__ENABLE_TWO_LIST__SHIFT 0x12 919 #define MC_ARB_LM_WR__POPIDLE_RST_TWOLIST_MASK 0x80000 920 #define MC_ARB_LM_WR__POPIDLE_RST_TWOLIST__SHIFT 0x13 921 #define MC_ARB_LM_WR__SKID1_RST_TWOLIST_MASK 0x100000 922 #define MC_ARB_LM_WR__SKID1_RST_TWOLIST__SHIFT 0x14 923 #define MC_ARB_LM_WR__BANKGROUP_CONFIG_MASK 0xe00000 924 #define MC_ARB_LM_WR__BANKGROUP_CONFIG__SHIFT 0x15 925 #define MC_ARB_LM_WR__MASKWR_LM_EOB_MASK 0x1000000 926 #define MC_ARB_LM_WR__MASKWR_LM_EOB__SHIFT 0x18 927 #define MC_ARB_LM_WR__ATOMIC_LM_EOB_MASK 0x2000000 928 #define MC_ARB_LM_WR__ATOMIC_LM_EOB__SHIFT 0x19 929 #define MC_ARB_LM_WR__ATOMIC_RTN_LM_EOB_MASK 0x4000000 930 #define MC_ARB_LM_WR__ATOMIC_RTN_LM_EOB__SHIFT 0x1a 931 #define MC_ARB_REMREQ__RD_WATER_MASK 0xff 932 #define MC_ARB_REMREQ__RD_WATER__SHIFT 0x0 933 #define MC_ARB_REMREQ__WR_WATER_MASK 0xff00 934 #define MC_ARB_REMREQ__WR_WATER__SHIFT 0x8 935 #define MC_ARB_REMREQ__WR_MAXBURST_SIZE_MASK 0xf0000 936 #define MC_ARB_REMREQ__WR_MAXBURST_SIZE__SHIFT 0x10 937 #define MC_ARB_REMREQ__WR_LAZY_TIMER_MASK 0xf00000 938 #define MC_ARB_REMREQ__WR_LAZY_TIMER__SHIFT 0x14 939 #define MC_ARB_REMREQ__ENABLE_REMOTE_NACK_REQ_MASK 0x1000000 940 #define MC_ARB_REMREQ__ENABLE_REMOTE_NACK_REQ__SHIFT 0x18 941 #define MC_ARB_REPLAY__ENABLE_RD_MASK 0x1 942 #define MC_ARB_REPLAY__ENABLE_RD__SHIFT 0x0 943 #define MC_ARB_REPLAY__ENABLE_WR_MASK 0x2 944 #define MC_ARB_REPLAY__ENABLE_WR__SHIFT 0x1 945 #define MC_ARB_REPLAY__WRACK_MODE_MASK 0x4 946 #define MC_ARB_REPLAY__WRACK_MODE__SHIFT 0x2 947 #define MC_ARB_REPLAY__WAW_ENABLE_MASK 0x8 948 #define MC_ARB_REPLAY__WAW_ENABLE__SHIFT 0x3 949 #define MC_ARB_REPLAY__RAW_ENABLE_MASK 0x10 950 #define MC_ARB_REPLAY__RAW_ENABLE__SHIFT 0x4 951 #define MC_ARB_REPLAY__IGNORE_WR_CDC_MASK 0x20 952 #define MC_ARB_REPLAY__IGNORE_WR_CDC__SHIFT 0x5 953 #define MC_ARB_REPLAY__BREAK_ON_STALL_MASK 0x40 954 #define MC_ARB_REPLAY__BREAK_ON_STALL__SHIFT 0x6 955 #define MC_ARB_REPLAY__BOS_ENABLE_WAIT_CYC_MASK 0x80 956 #define MC_ARB_REPLAY__BOS_ENABLE_WAIT_CYC__SHIFT 0x7 957 #define MC_ARB_REPLAY__BOS_WAIT_CYC_MASK 0x7f00 958 #define MC_ARB_REPLAY__BOS_WAIT_CYC__SHIFT 0x8 959 #define MC_ARB_REPLAY__NO_PCH_AT_REPLAY_START_MASK 0x8000 960 #define MC_ARB_REPLAY__NO_PCH_AT_REPLAY_START__SHIFT 0xf 961 #define MC_ARB_RET_CREDITS_RD__LCL_MASK 0xff 962 #define MC_ARB_RET_CREDITS_RD__LCL__SHIFT 0x0 963 #define MC_ARB_RET_CREDITS_RD__HUB_MASK 0xff00 964 #define MC_ARB_RET_CREDITS_RD__HUB__SHIFT 0x8 965 #define MC_ARB_RET_CREDITS_RD__DISP_MASK 0xff0000 966 #define MC_ARB_RET_CREDITS_RD__DISP__SHIFT 0x10 967 #define MC_ARB_RET_CREDITS_RD__RETURN_CREDIT_MASK 0xff000000 968 #define MC_ARB_RET_CREDITS_RD__RETURN_CREDIT__SHIFT 0x18 969 #define MC_ARB_RET_CREDITS_WR__LCL_MASK 0xff 970 #define MC_ARB_RET_CREDITS_WR__LCL__SHIFT 0x0 971 #define MC_ARB_RET_CREDITS_WR__HUB_MASK 0xff00 972 #define MC_ARB_RET_CREDITS_WR__HUB__SHIFT 0x8 973 #define MC_ARB_RET_CREDITS_WR__RETURN_CREDIT_MASK 0xff0000 974 #define MC_ARB_RET_CREDITS_WR__RETURN_CREDIT__SHIFT 0x10 975 #define MC_ARB_RET_CREDITS_WR__WRRET_SEQ_SKID_MASK 0xf000000 976 #define MC_ARB_RET_CREDITS_WR__WRRET_SEQ_SKID__SHIFT 0x18 977 #define MC_ARB_RET_CREDITS_WR__WRRET_BP_MASK 0x10000000 978 #define MC_ARB_RET_CREDITS_WR__WRRET_BP__SHIFT 0x1c 979 #define MC_ARB_MAX_LAT_CID__CID_CH0_MASK 0xff 980 #define MC_ARB_MAX_LAT_CID__CID_CH0__SHIFT 0x0 981 #define MC_ARB_MAX_LAT_CID__CID_CH1_MASK 0xff00 982 #define MC_ARB_MAX_LAT_CID__CID_CH1__SHIFT 0x8 983 #define MC_ARB_MAX_LAT_CID__WRITE_CH0_MASK 0x10000 984 #define MC_ARB_MAX_LAT_CID__WRITE_CH0__SHIFT 0x10 985 #define MC_ARB_MAX_LAT_CID__WRITE_CH1_MASK 0x20000 986 #define MC_ARB_MAX_LAT_CID__WRITE_CH1__SHIFT 0x11 987 #define MC_ARB_MAX_LAT_CID__REALTIME_CH0_MASK 0x40000 988 #define MC_ARB_MAX_LAT_CID__REALTIME_CH0__SHIFT 0x12 989 #define MC_ARB_MAX_LAT_CID__REALTIME_CH1_MASK 0x80000 990 #define MC_ARB_MAX_LAT_CID__REALTIME_CH1__SHIFT 0x13 991 #define MC_ARB_MAX_LAT_RSLT0__MAX_LATENCY_MASK 0xffffffff 992 #define MC_ARB_MAX_LAT_RSLT0__MAX_LATENCY__SHIFT 0x0 993 #define MC_ARB_MAX_LAT_RSLT1__MAX_LATENCY_MASK 0xffffffff 994 #define MC_ARB_MAX_LAT_RSLT1__MAX_LATENCY__SHIFT 0x0 995 #define MC_ARB_GRUB_REALTIME_RD__CB0_MASK 0x1 996 #define MC_ARB_GRUB_REALTIME_RD__CB0__SHIFT 0x0 997 #define MC_ARB_GRUB_REALTIME_RD__CBCMASK0_MASK 0x2 998 #define MC_ARB_GRUB_REALTIME_RD__CBCMASK0__SHIFT 0x1 999 #define MC_ARB_GRUB_REALTIME_RD__CBFMASK0_MASK 0x4 1000 #define MC_ARB_GRUB_REALTIME_RD__CBFMASK0__SHIFT 0x2 1001 #define MC_ARB_GRUB_REALTIME_RD__DB0_MASK 0x8 1002 #define MC_ARB_GRUB_REALTIME_RD__DB0__SHIFT 0x3 1003 #define MC_ARB_GRUB_REALTIME_RD__DBHTILE0_MASK 0x10 1004 #define MC_ARB_GRUB_REALTIME_RD__DBHTILE0__SHIFT 0x4 1005 #define MC_ARB_GRUB_REALTIME_RD__DBSTEN0_MASK 0x20 1006 #define MC_ARB_GRUB_REALTIME_RD__DBSTEN0__SHIFT 0x5 1007 #define MC_ARB_GRUB_REALTIME_RD__TC0_MASK 0x40 1008 #define MC_ARB_GRUB_REALTIME_RD__TC0__SHIFT 0x6 1009 #define MC_ARB_GRUB_REALTIME_RD__IA_MASK 0x80 1010 #define MC_ARB_GRUB_REALTIME_RD__IA__SHIFT 0x7 1011 #define MC_ARB_GRUB_REALTIME_RD__ACPG_MASK 0x100 1012 #define MC_ARB_GRUB_REALTIME_RD__ACPG__SHIFT 0x8 1013 #define MC_ARB_GRUB_REALTIME_RD__ACPO_MASK 0x200 1014 #define MC_ARB_GRUB_REALTIME_RD__ACPO__SHIFT 0x9 1015 #define MC_ARB_GRUB_REALTIME_RD__DMIF_MASK 0x400 1016 #define MC_ARB_GRUB_REALTIME_RD__DMIF__SHIFT 0xa 1017 #define MC_ARB_GRUB_REALTIME_RD__DMIF_EXT0_MASK 0x800 1018 #define MC_ARB_GRUB_REALTIME_RD__DMIF_EXT0__SHIFT 0xb 1019 #define MC_ARB_GRUB_REALTIME_RD__DMIF_EXT1_MASK 0x1000 1020 #define MC_ARB_GRUB_REALTIME_RD__DMIF_EXT1__SHIFT 0xc 1021 #define MC_ARB_GRUB_REALTIME_RD__DMIF_TW_MASK 0x2000 1022 #define MC_ARB_GRUB_REALTIME_RD__DMIF_TW__SHIFT 0xd 1023 #define MC_ARB_GRUB_REALTIME_RD__MCIF_MASK 0x4000 1024 #define MC_ARB_GRUB_REALTIME_RD__MCIF__SHIFT 0xe 1025 #define MC_ARB_GRUB_REALTIME_RD__RLC_MASK 0x8000 1026 #define MC_ARB_GRUB_REALTIME_RD__RLC__SHIFT 0xf 1027 #define MC_ARB_GRUB_REALTIME_RD__VMC_MASK 0x10000 1028 #define MC_ARB_GRUB_REALTIME_RD__VMC__SHIFT 0x10 1029 #define MC_ARB_GRUB_REALTIME_RD__SDMA1_MASK 0x20000 1030 #define MC_ARB_GRUB_REALTIME_RD__SDMA1__SHIFT 0x11 1031 #define MC_ARB_GRUB_REALTIME_RD__SMU_MASK 0x40000 1032 #define MC_ARB_GRUB_REALTIME_RD__SMU__SHIFT 0x12 1033 #define MC_ARB_GRUB_REALTIME_RD__VCE0_MASK 0x80000 1034 #define MC_ARB_GRUB_REALTIME_RD__VCE0__SHIFT 0x13 1035 #define MC_ARB_GRUB_REALTIME_RD__VCE1_MASK 0x100000 1036 #define MC_ARB_GRUB_REALTIME_RD__VCE1__SHIFT 0x14 1037 #define MC_ARB_GRUB_REALTIME_RD__XDMAM_MASK 0x200000 1038 #define MC_ARB_GRUB_REALTIME_RD__XDMAM__SHIFT 0x15 1039 #define MC_ARB_GRUB_REALTIME_RD__SDMA0_MASK 0x400000 1040 #define MC_ARB_GRUB_REALTIME_RD__SDMA0__SHIFT 0x16 1041 #define MC_ARB_GRUB_REALTIME_RD__HDP_MASK 0x800000 1042 #define MC_ARB_GRUB_REALTIME_RD__HDP__SHIFT 0x17 1043 #define MC_ARB_GRUB_REALTIME_RD__UMC_MASK 0x1000000 1044 #define MC_ARB_GRUB_REALTIME_RD__UMC__SHIFT 0x18 1045 #define MC_ARB_GRUB_REALTIME_RD__UVD_MASK 0x2000000 1046 #define MC_ARB_GRUB_REALTIME_RD__UVD__SHIFT 0x19 1047 #define MC_ARB_GRUB_REALTIME_RD__UVD_EXT0_MASK 0x4000000 1048 #define MC_ARB_GRUB_REALTIME_RD__UVD_EXT0__SHIFT 0x1a 1049 #define MC_ARB_GRUB_REALTIME_RD__UVD_EXT1_MASK 0x8000000 1050 #define MC_ARB_GRUB_REALTIME_RD__UVD_EXT1__SHIFT 0x1b 1051 #define MC_ARB_GRUB_REALTIME_RD__SEM_MASK 0x10000000 1052 #define MC_ARB_GRUB_REALTIME_RD__SEM__SHIFT 0x1c 1053 #define MC_ARB_GRUB_REALTIME_RD__SAMMSP_MASK 0x20000000 1054 #define MC_ARB_GRUB_REALTIME_RD__SAMMSP__SHIFT 0x1d 1055 #define MC_ARB_GRUB_REALTIME_RD__VP8_MASK 0x40000000 1056 #define MC_ARB_GRUB_REALTIME_RD__VP8__SHIFT 0x1e 1057 #define MC_ARB_GRUB_REALTIME_RD__ISP_MASK 0x80000000 1058 #define MC_ARB_GRUB_REALTIME_RD__ISP__SHIFT 0x1f 1059 #define MC_ARB_CG__CG_ARB_REQ_MASK 0xff 1060 #define MC_ARB_CG__CG_ARB_REQ__SHIFT 0x0 1061 #define MC_ARB_CG__CG_ARB_RESP_MASK 0xff00 1062 #define MC_ARB_CG__CG_ARB_RESP__SHIFT 0x8 1063 #define MC_ARB_CG__RSV_0_MASK 0xff0000 1064 #define MC_ARB_CG__RSV_0__SHIFT 0x10 1065 #define MC_ARB_CG__RSV_1_MASK 0xff000000 1066 #define MC_ARB_CG__RSV_1__SHIFT 0x18 1067 #define MC_ARB_GRUB_REALTIME_WR__CB0_MASK 0x1 1068 #define MC_ARB_GRUB_REALTIME_WR__CB0__SHIFT 0x0 1069 #define MC_ARB_GRUB_REALTIME_WR__CBCMASK0_MASK 0x2 1070 #define MC_ARB_GRUB_REALTIME_WR__CBCMASK0__SHIFT 0x1 1071 #define MC_ARB_GRUB_REALTIME_WR__CBFMASK0_MASK 0x4 1072 #define MC_ARB_GRUB_REALTIME_WR__CBFMASK0__SHIFT 0x2 1073 #define MC_ARB_GRUB_REALTIME_WR__CBIMMED0_MASK 0x8 1074 #define MC_ARB_GRUB_REALTIME_WR__CBIMMED0__SHIFT 0x3 1075 #define MC_ARB_GRUB_REALTIME_WR__DB0_MASK 0x10 1076 #define MC_ARB_GRUB_REALTIME_WR__DB0__SHIFT 0x4 1077 #define MC_ARB_GRUB_REALTIME_WR__DBHTILE0_MASK 0x20 1078 #define MC_ARB_GRUB_REALTIME_WR__DBHTILE0__SHIFT 0x5 1079 #define MC_ARB_GRUB_REALTIME_WR__DBSTEN0_MASK 0x40 1080 #define MC_ARB_GRUB_REALTIME_WR__DBSTEN0__SHIFT 0x6 1081 #define MC_ARB_GRUB_REALTIME_WR__TC0_MASK 0x80 1082 #define MC_ARB_GRUB_REALTIME_WR__TC0__SHIFT 0x7 1083 #define MC_ARB_GRUB_REALTIME_WR__SH_MASK 0x100 1084 #define MC_ARB_GRUB_REALTIME_WR__SH__SHIFT 0x8 1085 #define MC_ARB_GRUB_REALTIME_WR__ACPG_MASK 0x200 1086 #define MC_ARB_GRUB_REALTIME_WR__ACPG__SHIFT 0x9 1087 #define MC_ARB_GRUB_REALTIME_WR__ACPO_MASK 0x400 1088 #define MC_ARB_GRUB_REALTIME_WR__ACPO__SHIFT 0xa 1089 #define MC_ARB_GRUB_REALTIME_WR__MCIF_MASK 0x800 1090 #define MC_ARB_GRUB_REALTIME_WR__MCIF__SHIFT 0xb 1091 #define MC_ARB_GRUB_REALTIME_WR__RLC_MASK 0x1000 1092 #define MC_ARB_GRUB_REALTIME_WR__RLC__SHIFT 0xc 1093 #define MC_ARB_GRUB_REALTIME_WR__SDMA1_MASK 0x2000 1094 #define MC_ARB_GRUB_REALTIME_WR__SDMA1__SHIFT 0xd 1095 #define MC_ARB_GRUB_REALTIME_WR__SMU_MASK 0x4000 1096 #define MC_ARB_GRUB_REALTIME_WR__SMU__SHIFT 0xe 1097 #define MC_ARB_GRUB_REALTIME_WR__VCE0_MASK 0x8000 1098 #define MC_ARB_GRUB_REALTIME_WR__VCE0__SHIFT 0xf 1099 #define MC_ARB_GRUB_REALTIME_WR__VCE1_MASK 0x10000 1100 #define MC_ARB_GRUB_REALTIME_WR__VCE1__SHIFT 0x10 1101 #define MC_ARB_GRUB_REALTIME_WR__SAMMSP_MASK 0x20000 1102 #define MC_ARB_GRUB_REALTIME_WR__SAMMSP__SHIFT 0x11 1103 #define MC_ARB_GRUB_REALTIME_WR__XDMA_MASK 0x40000 1104 #define MC_ARB_GRUB_REALTIME_WR__XDMA__SHIFT 0x12 1105 #define MC_ARB_GRUB_REALTIME_WR__XDMAM_MASK 0x80000 1106 #define MC_ARB_GRUB_REALTIME_WR__XDMAM__SHIFT 0x13 1107 #define MC_ARB_GRUB_REALTIME_WR__SDMA0_MASK 0x100000 1108 #define MC_ARB_GRUB_REALTIME_WR__SDMA0__SHIFT 0x14 1109 #define MC_ARB_GRUB_REALTIME_WR__HDP_MASK 0x200000 1110 #define MC_ARB_GRUB_REALTIME_WR__HDP__SHIFT 0x15 1111 #define MC_ARB_GRUB_REALTIME_WR__UMC_MASK 0x400000 1112 #define MC_ARB_GRUB_REALTIME_WR__UMC__SHIFT 0x16 1113 #define MC_ARB_GRUB_REALTIME_WR__UVD_MASK 0x800000 1114 #define MC_ARB_GRUB_REALTIME_WR__UVD__SHIFT 0x17 1115 #define MC_ARB_GRUB_REALTIME_WR__UVD_EXT0_MASK 0x1000000 1116 #define MC_ARB_GRUB_REALTIME_WR__UVD_EXT0__SHIFT 0x18 1117 #define MC_ARB_GRUB_REALTIME_WR__UVD_EXT1_MASK 0x2000000 1118 #define MC_ARB_GRUB_REALTIME_WR__UVD_EXT1__SHIFT 0x19 1119 #define MC_ARB_GRUB_REALTIME_WR__XDP_MASK 0x4000000 1120 #define MC_ARB_GRUB_REALTIME_WR__XDP__SHIFT 0x1a 1121 #define MC_ARB_GRUB_REALTIME_WR__SEM_MASK 0x8000000 1122 #define MC_ARB_GRUB_REALTIME_WR__SEM__SHIFT 0x1b 1123 #define MC_ARB_GRUB_REALTIME_WR__IH_MASK 0x10000000 1124 #define MC_ARB_GRUB_REALTIME_WR__IH__SHIFT 0x1c 1125 #define MC_ARB_GRUB_REALTIME_WR__VP8_MASK 0x20000000 1126 #define MC_ARB_GRUB_REALTIME_WR__VP8__SHIFT 0x1d 1127 #define MC_ARB_GRUB_REALTIME_WR__ISP_MASK 0x40000000 1128 #define MC_ARB_GRUB_REALTIME_WR__ISP__SHIFT 0x1e 1129 #define MC_ARB_GRUB_REALTIME_WR__VIN0_MASK 0x80000000 1130 #define MC_ARB_GRUB_REALTIME_WR__VIN0__SHIFT 0x1f 1131 #define MC_ARB_DRAM_TIMING_1__ACTRD_MASK 0xff 1132 #define MC_ARB_DRAM_TIMING_1__ACTRD__SHIFT 0x0 1133 #define MC_ARB_DRAM_TIMING_1__ACTWR_MASK 0xff00 1134 #define MC_ARB_DRAM_TIMING_1__ACTWR__SHIFT 0x8 1135 #define MC_ARB_DRAM_TIMING_1__RASMACTRD_MASK 0xff0000 1136 #define MC_ARB_DRAM_TIMING_1__RASMACTRD__SHIFT 0x10 1137 #define MC_ARB_DRAM_TIMING_1__RASMACTWR_MASK 0xff000000 1138 #define MC_ARB_DRAM_TIMING_1__RASMACTWR__SHIFT 0x18 1139 #define MC_ARB_BUSY_STATUS__LM_RD0_MASK 0x1 1140 #define MC_ARB_BUSY_STATUS__LM_RD0__SHIFT 0x0 1141 #define MC_ARB_BUSY_STATUS__LM_RD1_MASK 0x2 1142 #define MC_ARB_BUSY_STATUS__LM_RD1__SHIFT 0x1 1143 #define MC_ARB_BUSY_STATUS__LM_WR0_MASK 0x4 1144 #define MC_ARB_BUSY_STATUS__LM_WR0__SHIFT 0x2 1145 #define MC_ARB_BUSY_STATUS__LM_WR1_MASK 0x8 1146 #define MC_ARB_BUSY_STATUS__LM_WR1__SHIFT 0x3 1147 #define MC_ARB_BUSY_STATUS__HM_RD0_MASK 0x10 1148 #define MC_ARB_BUSY_STATUS__HM_RD0__SHIFT 0x4 1149 #define MC_ARB_BUSY_STATUS__HM_RD1_MASK 0x20 1150 #define MC_ARB_BUSY_STATUS__HM_RD1__SHIFT 0x5 1151 #define MC_ARB_BUSY_STATUS__HM_WR0_MASK 0x40 1152 #define MC_ARB_BUSY_STATUS__HM_WR0__SHIFT 0x6 1153 #define MC_ARB_BUSY_STATUS__HM_WR1_MASK 0x80 1154 #define MC_ARB_BUSY_STATUS__HM_WR1__SHIFT 0x7 1155 #define MC_ARB_BUSY_STATUS__WDE_RD0_MASK 0x100 1156 #define MC_ARB_BUSY_STATUS__WDE_RD0__SHIFT 0x8 1157 #define MC_ARB_BUSY_STATUS__WDE_RD1_MASK 0x200 1158 #define MC_ARB_BUSY_STATUS__WDE_RD1__SHIFT 0x9 1159 #define MC_ARB_BUSY_STATUS__WDE_WR0_MASK 0x400 1160 #define MC_ARB_BUSY_STATUS__WDE_WR0__SHIFT 0xa 1161 #define MC_ARB_BUSY_STATUS__WDE_WR1_MASK 0x800 1162 #define MC_ARB_BUSY_STATUS__WDE_WR1__SHIFT 0xb 1163 #define MC_ARB_BUSY_STATUS__POP0_MASK 0x1000 1164 #define MC_ARB_BUSY_STATUS__POP0__SHIFT 0xc 1165 #define MC_ARB_BUSY_STATUS__POP1_MASK 0x2000 1166 #define MC_ARB_BUSY_STATUS__POP1__SHIFT 0xd 1167 #define MC_ARB_BUSY_STATUS__TAGFIFO0_MASK 0x4000 1168 #define MC_ARB_BUSY_STATUS__TAGFIFO0__SHIFT 0xe 1169 #define MC_ARB_BUSY_STATUS__TAGFIFO1_MASK 0x8000 1170 #define MC_ARB_BUSY_STATUS__TAGFIFO1__SHIFT 0xf 1171 #define MC_ARB_BUSY_STATUS__REPLAY0_MASK 0x10000 1172 #define MC_ARB_BUSY_STATUS__REPLAY0__SHIFT 0x10 1173 #define MC_ARB_BUSY_STATUS__REPLAY1_MASK 0x20000 1174 #define MC_ARB_BUSY_STATUS__REPLAY1__SHIFT 0x11 1175 #define MC_ARB_BUSY_STATUS__RDRET0_MASK 0x40000 1176 #define MC_ARB_BUSY_STATUS__RDRET0__SHIFT 0x12 1177 #define MC_ARB_BUSY_STATUS__RDRET1_MASK 0x80000 1178 #define MC_ARB_BUSY_STATUS__RDRET1__SHIFT 0x13 1179 #define MC_ARB_BUSY_STATUS__GECC2_RD0_MASK 0x100000 1180 #define MC_ARB_BUSY_STATUS__GECC2_RD0__SHIFT 0x14 1181 #define MC_ARB_BUSY_STATUS__GECC2_RD1_MASK 0x200000 1182 #define MC_ARB_BUSY_STATUS__GECC2_RD1__SHIFT 0x15 1183 #define MC_ARB_BUSY_STATUS__GECC2_WR0_MASK 0x400000 1184 #define MC_ARB_BUSY_STATUS__GECC2_WR0__SHIFT 0x16 1185 #define MC_ARB_BUSY_STATUS__GECC2_WR1_MASK 0x800000 1186 #define MC_ARB_BUSY_STATUS__GECC2_WR1__SHIFT 0x17 1187 #define MC_ARB_BUSY_STATUS__WRRET0_MASK 0x1000000 1188 #define MC_ARB_BUSY_STATUS__WRRET0__SHIFT 0x18 1189 #define MC_ARB_BUSY_STATUS__WRRET1_MASK 0x2000000 1190 #define MC_ARB_BUSY_STATUS__WRRET1__SHIFT 0x19 1191 #define MC_ARB_BUSY_STATUS__RTT0_MASK 0x4000000 1192 #define MC_ARB_BUSY_STATUS__RTT0__SHIFT 0x1a 1193 #define MC_ARB_BUSY_STATUS__RTT1_MASK 0x8000000 1194 #define MC_ARB_BUSY_STATUS__RTT1__SHIFT 0x1b 1195 #define MC_ARB_BUSY_STATUS__REM_RD0_MASK 0x10000000 1196 #define MC_ARB_BUSY_STATUS__REM_RD0__SHIFT 0x1c 1197 #define MC_ARB_BUSY_STATUS__REM_RD1_MASK 0x20000000 1198 #define MC_ARB_BUSY_STATUS__REM_RD1__SHIFT 0x1d 1199 #define MC_ARB_BUSY_STATUS__REM_WR0_MASK 0x40000000 1200 #define MC_ARB_BUSY_STATUS__REM_WR0__SHIFT 0x1e 1201 #define MC_ARB_BUSY_STATUS__REM_WR1_MASK 0x80000000 1202 #define MC_ARB_BUSY_STATUS__REM_WR1__SHIFT 0x1f 1203 #define MC_ARB_DRAM_TIMING2_1__RAS2RAS_MASK 0xff 1204 #define MC_ARB_DRAM_TIMING2_1__RAS2RAS__SHIFT 0x0 1205 #define MC_ARB_DRAM_TIMING2_1__RP_MASK 0xff00 1206 #define MC_ARB_DRAM_TIMING2_1__RP__SHIFT 0x8 1207 #define MC_ARB_DRAM_TIMING2_1__WRPLUSRP_MASK 0xff0000 1208 #define MC_ARB_DRAM_TIMING2_1__WRPLUSRP__SHIFT 0x10 1209 #define MC_ARB_DRAM_TIMING2_1__BUS_TURN_MASK 0x1f000000 1210 #define MC_ARB_DRAM_TIMING2_1__BUS_TURN__SHIFT 0x18 1211 #define MC_ARB_GRUB2__REALTIME_GRP_RD_MASK 0xff 1212 #define MC_ARB_GRUB2__REALTIME_GRP_RD__SHIFT 0x0 1213 #define MC_ARB_GRUB2__REALTIME_GRP_WR_MASK 0xff00 1214 #define MC_ARB_GRUB2__REALTIME_GRP_WR__SHIFT 0x8 1215 #define MC_ARB_GRUB2__DISP_RD_STALL_EN_MASK 0x10000 1216 #define MC_ARB_GRUB2__DISP_RD_STALL_EN__SHIFT 0x10 1217 #define MC_ARB_GRUB2__ACP_RD_STALL_EN_MASK 0x20000 1218 #define MC_ARB_GRUB2__ACP_RD_STALL_EN__SHIFT 0x11 1219 #define MC_ARB_GRUB2__UVD_RD_STALL_EN_MASK 0x40000 1220 #define MC_ARB_GRUB2__UVD_RD_STALL_EN__SHIFT 0x12 1221 #define MC_ARB_GRUB2__VCE0_RD_STALL_EN_MASK 0x80000 1222 #define MC_ARB_GRUB2__VCE0_RD_STALL_EN__SHIFT 0x13 1223 #define MC_ARB_GRUB2__VCE1_RD_STALL_EN_MASK 0x100000 1224 #define MC_ARB_GRUB2__VCE1_RD_STALL_EN__SHIFT 0x14 1225 #define MC_ARB_GRUB2__REALTIME_RD_WTS_MASK 0x200000 1226 #define MC_ARB_GRUB2__REALTIME_RD_WTS__SHIFT 0x15 1227 #define MC_ARB_GRUB2__REALTIME_WR_WTS_MASK 0x400000 1228 #define MC_ARB_GRUB2__REALTIME_WR_WTS__SHIFT 0x16 1229 #define MC_ARB_GRUB2__URGENT_BY_DISP_STALL_MASK 0x800000 1230 #define MC_ARB_GRUB2__URGENT_BY_DISP_STALL__SHIFT 0x17 1231 #define MC_ARB_GRUB2__PROMOTE_BY_DMIF_URG_MASK 0x1000000 1232 #define MC_ARB_GRUB2__PROMOTE_BY_DMIF_URG__SHIFT 0x18 1233 #define MC_ARB_GRUB2__PRIORITY_URGENT_OUTSTANDING_ONLY_RD_MASK 0x2000000 1234 #define MC_ARB_GRUB2__PRIORITY_URGENT_OUTSTANDING_ONLY_RD__SHIFT 0x19 1235 #define MC_ARB_GRUB2__PRIORITY_PROMOTE_OUTSTANDING_ONLY_RD_MASK 0x4000000 1236 #define MC_ARB_GRUB2__PRIORITY_PROMOTE_OUTSTANDING_ONLY_RD__SHIFT 0x1a 1237 #define MC_ARB_GRUB2__PRIORITY_URGENT_OUTSTANDING_ONLY_WR_MASK 0x8000000 1238 #define MC_ARB_GRUB2__PRIORITY_URGENT_OUTSTANDING_ONLY_WR__SHIFT 0x1b 1239 #define MC_ARB_GRUB2__PRIORITY_PROMOTE_OUTSTANDING_ONLY_WR_MASK 0x10000000 1240 #define MC_ARB_GRUB2__PRIORITY_PROMOTE_OUTSTANDING_ONLY_WR__SHIFT 0x1c 1241 #define MC_ARB_BURST_TIME__STATE0_MASK 0x1f 1242 #define MC_ARB_BURST_TIME__STATE0__SHIFT 0x0 1243 #define MC_ARB_BURST_TIME__STATE1_MASK 0x3e0 1244 #define MC_ARB_BURST_TIME__STATE1__SHIFT 0x5 1245 #define MC_ARB_BURST_TIME__STATE2_MASK 0x7c00 1246 #define MC_ARB_BURST_TIME__STATE2__SHIFT 0xa 1247 #define MC_ARB_BURST_TIME__STATE3_MASK 0xf8000 1248 #define MC_ARB_BURST_TIME__STATE3__SHIFT 0xf 1249 #define MC_CITF_XTRA_ENABLE__CB1_RD_MASK 0x1 1250 #define MC_CITF_XTRA_ENABLE__CB1_RD__SHIFT 0x0 1251 #define MC_CITF_XTRA_ENABLE__CB1_WR_MASK 0x2 1252 #define MC_CITF_XTRA_ENABLE__CB1_WR__SHIFT 0x1 1253 #define MC_CITF_XTRA_ENABLE__DB1_RD_MASK 0x4 1254 #define MC_CITF_XTRA_ENABLE__DB1_RD__SHIFT 0x2 1255 #define MC_CITF_XTRA_ENABLE__DB1_WR_MASK 0x8 1256 #define MC_CITF_XTRA_ENABLE__DB1_WR__SHIFT 0x3 1257 #define MC_CITF_XTRA_ENABLE__TC2_RD_MASK 0x10 1258 #define MC_CITF_XTRA_ENABLE__TC2_RD__SHIFT 0x4 1259 #define MC_CITF_XTRA_ENABLE__ARB_DBG_MASK 0xf00 1260 #define MC_CITF_XTRA_ENABLE__ARB_DBG__SHIFT 0x8 1261 #define MC_CITF_XTRA_ENABLE__TC2_WR_MASK 0x1000 1262 #define MC_CITF_XTRA_ENABLE__TC2_WR__SHIFT 0xc 1263 #define MC_CITF_XTRA_ENABLE__CB0_CONNECT_CNTL_MASK 0x6000 1264 #define MC_CITF_XTRA_ENABLE__CB0_CONNECT_CNTL__SHIFT 0xd 1265 #define MC_CITF_XTRA_ENABLE__DB0_CONNECT_CNTL_MASK 0x18000 1266 #define MC_CITF_XTRA_ENABLE__DB0_CONNECT_CNTL__SHIFT 0xf 1267 #define MC_CITF_XTRA_ENABLE__CB1_CONNECT_CNTL_MASK 0x60000 1268 #define MC_CITF_XTRA_ENABLE__CB1_CONNECT_CNTL__SHIFT 0x11 1269 #define MC_CITF_XTRA_ENABLE__DB1_CONNECT_CNTL_MASK 0x180000 1270 #define MC_CITF_XTRA_ENABLE__DB1_CONNECT_CNTL__SHIFT 0x13 1271 #define MC_CITF_XTRA_ENABLE__TC0_CONNECT_CNTL_MASK 0x600000 1272 #define MC_CITF_XTRA_ENABLE__TC0_CONNECT_CNTL__SHIFT 0x15 1273 #define MC_CITF_XTRA_ENABLE__TC1_CONNECT_CNTL_MASK 0x1800000 1274 #define MC_CITF_XTRA_ENABLE__TC1_CONNECT_CNTL__SHIFT 0x17 1275 #define MC_CITF_XTRA_ENABLE__CB0_CID_CNTL_ENABLE_MASK 0x2000000 1276 #define MC_CITF_XTRA_ENABLE__CB0_CID_CNTL_ENABLE__SHIFT 0x19 1277 #define MC_CITF_XTRA_ENABLE__DB0_CID_CNTL_ENABLE_MASK 0x4000000 1278 #define MC_CITF_XTRA_ENABLE__DB0_CID_CNTL_ENABLE__SHIFT 0x1a 1279 #define MC_CITF_XTRA_ENABLE__CB1_CID_CNTL_ENABLE_MASK 0x8000000 1280 #define MC_CITF_XTRA_ENABLE__CB1_CID_CNTL_ENABLE__SHIFT 0x1b 1281 #define MC_CITF_XTRA_ENABLE__DB1_CID_CNTL_ENABLE_MASK 0x10000000 1282 #define MC_CITF_XTRA_ENABLE__DB1_CID_CNTL_ENABLE__SHIFT 0x1c 1283 #define MC_CITF_XTRA_ENABLE__TC2_REPAIR_ENABLE_MASK 0x60000000 1284 #define MC_CITF_XTRA_ENABLE__TC2_REPAIR_ENABLE__SHIFT 0x1d 1285 #define CC_MC_MAX_CHANNEL__NOOFCHAN_MASK 0x1e 1286 #define CC_MC_MAX_CHANNEL__NOOFCHAN__SHIFT 0x1 1287 #define MC_CG_CONFIG__MCDW_WR_ENABLE_MASK 0x1 1288 #define MC_CG_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0 1289 #define MC_CG_CONFIG__MCDX_WR_ENABLE_MASK 0x2 1290 #define MC_CG_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1 1291 #define MC_CG_CONFIG__MCDY_WR_ENABLE_MASK 0x4 1292 #define MC_CG_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2 1293 #define MC_CG_CONFIG__MCDZ_WR_ENABLE_MASK 0x8 1294 #define MC_CG_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3 1295 #define MC_CG_CONFIG__MC_RD_ENABLE_MASK 0x30 1296 #define MC_CG_CONFIG__MC_RD_ENABLE__SHIFT 0x4 1297 #define MC_CG_CONFIG__INDEX_MASK 0x3fffc0 1298 #define MC_CG_CONFIG__INDEX__SHIFT 0x6 1299 #define MC_CITF_CNTL__IGNOREPM_MASK 0x4 1300 #define MC_CITF_CNTL__IGNOREPM__SHIFT 0x2 1301 #define MC_CITF_CNTL__EXEMPTPM_MASK 0x8 1302 #define MC_CITF_CNTL__EXEMPTPM__SHIFT 0x3 1303 #define MC_CITF_CNTL__GFX_IDLE_OVERRIDE_MASK 0x30 1304 #define MC_CITF_CNTL__GFX_IDLE_OVERRIDE__SHIFT 0x4 1305 #define MC_CITF_CNTL__MCD_SRBM_MASK_ENABLE_MASK 0x40 1306 #define MC_CITF_CNTL__MCD_SRBM_MASK_ENABLE__SHIFT 0x6 1307 #define MC_CITF_CNTL__CNTR_CHMAP_MODE_MASK 0x180 1308 #define MC_CITF_CNTL__CNTR_CHMAP_MODE__SHIFT 0x7 1309 #define MC_CITF_CNTL__REMOTE_RB_CONNECT_ENABLE_MASK 0x200 1310 #define MC_CITF_CNTL__REMOTE_RB_CONNECT_ENABLE__SHIFT 0x9 1311 #define MC_CITF_CREDITS_VM__READ_ALL_MASK 0x3f 1312 #define MC_CITF_CREDITS_VM__READ_ALL__SHIFT 0x0 1313 #define MC_CITF_CREDITS_VM__WRITE_ALL_MASK 0xfc0 1314 #define MC_CITF_CREDITS_VM__WRITE_ALL__SHIFT 0x6 1315 #define MC_CITF_CREDITS_ARB_RD__READ_LCL_MASK 0xff 1316 #define MC_CITF_CREDITS_ARB_RD__READ_LCL__SHIFT 0x0 1317 #define MC_CITF_CREDITS_ARB_RD__READ_HUB_MASK 0xff00 1318 #define MC_CITF_CREDITS_ARB_RD__READ_HUB__SHIFT 0x8 1319 #define MC_CITF_CREDITS_ARB_RD__READ_PRI_MASK 0xff0000 1320 #define MC_CITF_CREDITS_ARB_RD__READ_PRI__SHIFT 0x10 1321 #define MC_CITF_CREDITS_ARB_RD__LCL_PRI_MASK 0x1000000 1322 #define MC_CITF_CREDITS_ARB_RD__LCL_PRI__SHIFT 0x18 1323 #define MC_CITF_CREDITS_ARB_RD__HUB_PRI_MASK 0x2000000 1324 #define MC_CITF_CREDITS_ARB_RD__HUB_PRI__SHIFT 0x19 1325 #define MC_CITF_CREDITS_ARB_WR__WRITE_LCL_MASK 0xff 1326 #define MC_CITF_CREDITS_ARB_WR__WRITE_LCL__SHIFT 0x0 1327 #define MC_CITF_CREDITS_ARB_WR__WRITE_HUB_MASK 0xff00 1328 #define MC_CITF_CREDITS_ARB_WR__WRITE_HUB__SHIFT 0x8 1329 #define MC_CITF_CREDITS_ARB_WR__WRITE_PRI_MASK 0xff0000 1330 #define MC_CITF_CREDITS_ARB_WR__WRITE_PRI__SHIFT 0x10 1331 #define MC_CITF_CREDITS_ARB_WR__HUB_PRI_MASK 0x1000000 1332 #define MC_CITF_CREDITS_ARB_WR__HUB_PRI__SHIFT 0x18 1333 #define MC_CITF_CREDITS_ARB_WR__LCL_PRI_MASK 0x2000000 1334 #define MC_CITF_CREDITS_ARB_WR__LCL_PRI__SHIFT 0x19 1335 #define MC_CITF_DAGB_CNTL__JUMP_AHEAD_MASK 0x1 1336 #define MC_CITF_DAGB_CNTL__JUMP_AHEAD__SHIFT 0x0 1337 #define MC_CITF_DAGB_CNTL__CENTER_RD_MAX_BURST_MASK 0x1e 1338 #define MC_CITF_DAGB_CNTL__CENTER_RD_MAX_BURST__SHIFT 0x1 1339 #define MC_CITF_DAGB_CNTL__DISABLE_SELF_INIT_MASK 0x20 1340 #define MC_CITF_DAGB_CNTL__DISABLE_SELF_INIT__SHIFT 0x5 1341 #define MC_CITF_DAGB_CNTL__CENTER_WR_MAX_BURST_MASK 0x3c0 1342 #define MC_CITF_DAGB_CNTL__CENTER_WR_MAX_BURST__SHIFT 0x6 1343 #define MC_CITF_INT_CREDITS__REMRDRET_MASK 0x3f 1344 #define MC_CITF_INT_CREDITS__REMRDRET__SHIFT 0x0 1345 #define MC_CITF_INT_CREDITS__CNTR_RD_HUB_LP_MASK 0x3f000 1346 #define MC_CITF_INT_CREDITS__CNTR_RD_HUB_LP__SHIFT 0xc 1347 #define MC_CITF_INT_CREDITS__CNTR_RD_HUB_HP_MASK 0xfc0000 1348 #define MC_CITF_INT_CREDITS__CNTR_RD_HUB_HP__SHIFT 0x12 1349 #define MC_CITF_INT_CREDITS__CNTR_RD_LCL_MASK 0x3f000000 1350 #define MC_CITF_INT_CREDITS__CNTR_RD_LCL__SHIFT 0x18 1351 #define MC_CITF_RET_MODE__INORDER_RD_MASK 0x1 1352 #define MC_CITF_RET_MODE__INORDER_RD__SHIFT 0x0 1353 #define MC_CITF_RET_MODE__INORDER_WR_MASK 0x2 1354 #define MC_CITF_RET_MODE__INORDER_WR__SHIFT 0x1 1355 #define MC_CITF_RET_MODE__REMPRI_RD_MASK 0x4 1356 #define MC_CITF_RET_MODE__REMPRI_RD__SHIFT 0x2 1357 #define MC_CITF_RET_MODE__REMPRI_WR_MASK 0x8 1358 #define MC_CITF_RET_MODE__REMPRI_WR__SHIFT 0x3 1359 #define MC_CITF_RET_MODE__LCLPRI_RD_MASK 0x10 1360 #define MC_CITF_RET_MODE__LCLPRI_RD__SHIFT 0x4 1361 #define MC_CITF_RET_MODE__LCLPRI_WR_MASK 0x20 1362 #define MC_CITF_RET_MODE__LCLPRI_WR__SHIFT 0x5 1363 #define MC_CITF_RET_MODE__RDRET_STALL_EN_MASK 0x40 1364 #define MC_CITF_RET_MODE__RDRET_STALL_EN__SHIFT 0x6 1365 #define MC_CITF_RET_MODE__RDRET_STALL_THRESHOLD_MASK 0x7f80 1366 #define MC_CITF_RET_MODE__RDRET_STALL_THRESHOLD__SHIFT 0x7 1367 #define MC_CITF_DAGB_DLY__DLY_MASK 0x1f 1368 #define MC_CITF_DAGB_DLY__DLY__SHIFT 0x0 1369 #define MC_CITF_DAGB_DLY__CLI_MASK 0x3f0000 1370 #define MC_CITF_DAGB_DLY__CLI__SHIFT 0x10 1371 #define MC_CITF_DAGB_DLY__POS_MASK 0x3f000000 1372 #define MC_CITF_DAGB_DLY__POS__SHIFT 0x18 1373 #define MC_RD_GRP_EXT__DBSTEN0_MASK 0xf 1374 #define MC_RD_GRP_EXT__DBSTEN0__SHIFT 0x0 1375 #define MC_RD_GRP_EXT__TC0_MASK 0xf0 1376 #define MC_RD_GRP_EXT__TC0__SHIFT 0x4 1377 #define MC_WR_GRP_EXT__DBSTEN0_MASK 0xf 1378 #define MC_WR_GRP_EXT__DBSTEN0__SHIFT 0x0 1379 #define MC_WR_GRP_EXT__TC0_MASK 0xf0 1380 #define MC_WR_GRP_EXT__TC0__SHIFT 0x4 1381 #define MC_CITF_REMREQ__READ_CREDITS_MASK 0x7f 1382 #define MC_CITF_REMREQ__READ_CREDITS__SHIFT 0x0 1383 #define MC_CITF_REMREQ__WRITE_CREDITS_MASK 0x3f80 1384 #define MC_CITF_REMREQ__WRITE_CREDITS__SHIFT 0x7 1385 #define MC_CITF_REMREQ__CREDITS_ENABLE_MASK 0x4000 1386 #define MC_CITF_REMREQ__CREDITS_ENABLE__SHIFT 0xe 1387 #define MC_WR_TC0__ENABLE_MASK 0x1 1388 #define MC_WR_TC0__ENABLE__SHIFT 0x0 1389 #define MC_WR_TC0__PRESCALE_MASK 0x6 1390 #define MC_WR_TC0__PRESCALE__SHIFT 0x1 1391 #define MC_WR_TC0__BLACKOUT_EXEMPT_MASK 0x8 1392 #define MC_WR_TC0__BLACKOUT_EXEMPT__SHIFT 0x3 1393 #define MC_WR_TC0__STALL_MODE_MASK 0x30 1394 #define MC_WR_TC0__STALL_MODE__SHIFT 0x4 1395 #define MC_WR_TC0__STALL_OVERRIDE_MASK 0x40 1396 #define MC_WR_TC0__STALL_OVERRIDE__SHIFT 0x6 1397 #define MC_WR_TC0__MAX_BURST_MASK 0x780 1398 #define MC_WR_TC0__MAX_BURST__SHIFT 0x7 1399 #define MC_WR_TC0__LAZY_TIMER_MASK 0x7800 1400 #define MC_WR_TC0__LAZY_TIMER__SHIFT 0xb 1401 #define MC_WR_TC0__STALL_OVERRIDE_WTM_MASK 0x8000 1402 #define MC_WR_TC0__STALL_OVERRIDE_WTM__SHIFT 0xf 1403 #define MC_WR_TC1__ENABLE_MASK 0x1 1404 #define MC_WR_TC1__ENABLE__SHIFT 0x0 1405 #define MC_WR_TC1__PRESCALE_MASK 0x6 1406 #define MC_WR_TC1__PRESCALE__SHIFT 0x1 1407 #define MC_WR_TC1__BLACKOUT_EXEMPT_MASK 0x8 1408 #define MC_WR_TC1__BLACKOUT_EXEMPT__SHIFT 0x3 1409 #define MC_WR_TC1__STALL_MODE_MASK 0x30 1410 #define MC_WR_TC1__STALL_MODE__SHIFT 0x4 1411 #define MC_WR_TC1__STALL_OVERRIDE_MASK 0x40 1412 #define MC_WR_TC1__STALL_OVERRIDE__SHIFT 0x6 1413 #define MC_WR_TC1__MAX_BURST_MASK 0x780 1414 #define MC_WR_TC1__MAX_BURST__SHIFT 0x7 1415 #define MC_WR_TC1__LAZY_TIMER_MASK 0x7800 1416 #define MC_WR_TC1__LAZY_TIMER__SHIFT 0xb 1417 #define MC_WR_TC1__STALL_OVERRIDE_WTM_MASK 0x8000 1418 #define MC_WR_TC1__STALL_OVERRIDE_WTM__SHIFT 0xf 1419 #define MC_CITF_INT_CREDITS_WR__CNTR_WR_HUB_MASK 0x3f 1420 #define MC_CITF_INT_CREDITS_WR__CNTR_WR_HUB__SHIFT 0x0 1421 #define MC_CITF_INT_CREDITS_WR__CNTR_WR_LCL_MASK 0xfc0 1422 #define MC_CITF_INT_CREDITS_WR__CNTR_WR_LCL__SHIFT 0x6 1423 #define MC_CITF_CREDITS_ARB_RD2__READ_MED_MASK 0xff 1424 #define MC_CITF_CREDITS_ARB_RD2__READ_MED__SHIFT 0x0 1425 #define MC_CITF_WTM_RD_CNTL__GROUP0_DECREMENT_MASK 0x7 1426 #define MC_CITF_WTM_RD_CNTL__GROUP0_DECREMENT__SHIFT 0x0 1427 #define MC_CITF_WTM_RD_CNTL__GROUP1_DECREMENT_MASK 0x38 1428 #define MC_CITF_WTM_RD_CNTL__GROUP1_DECREMENT__SHIFT 0x3 1429 #define MC_CITF_WTM_RD_CNTL__GROUP2_DECREMENT_MASK 0x1c0 1430 #define MC_CITF_WTM_RD_CNTL__GROUP2_DECREMENT__SHIFT 0x6 1431 #define MC_CITF_WTM_RD_CNTL__GROUP3_DECREMENT_MASK 0xe00 1432 #define MC_CITF_WTM_RD_CNTL__GROUP3_DECREMENT__SHIFT 0x9 1433 #define MC_CITF_WTM_RD_CNTL__GROUP4_DECREMENT_MASK 0x7000 1434 #define MC_CITF_WTM_RD_CNTL__GROUP4_DECREMENT__SHIFT 0xc 1435 #define MC_CITF_WTM_RD_CNTL__GROUP5_DECREMENT_MASK 0x38000 1436 #define MC_CITF_WTM_RD_CNTL__GROUP5_DECREMENT__SHIFT 0xf 1437 #define MC_CITF_WTM_RD_CNTL__GROUP6_DECREMENT_MASK 0x1c0000 1438 #define MC_CITF_WTM_RD_CNTL__GROUP6_DECREMENT__SHIFT 0x12 1439 #define MC_CITF_WTM_RD_CNTL__GROUP7_DECREMENT_MASK 0xe00000 1440 #define MC_CITF_WTM_RD_CNTL__GROUP7_DECREMENT__SHIFT 0x15 1441 #define MC_CITF_WTM_RD_CNTL__DISABLE_REMOTE_MASK 0x1000000 1442 #define MC_CITF_WTM_RD_CNTL__DISABLE_REMOTE__SHIFT 0x18 1443 #define MC_CITF_WTM_RD_CNTL__DISABLE_LOCAL_MASK 0x2000000 1444 #define MC_CITF_WTM_RD_CNTL__DISABLE_LOCAL__SHIFT 0x19 1445 #define MC_CITF_WTM_WR_CNTL__GROUP0_DECREMENT_MASK 0x7 1446 #define MC_CITF_WTM_WR_CNTL__GROUP0_DECREMENT__SHIFT 0x0 1447 #define MC_CITF_WTM_WR_CNTL__GROUP1_DECREMENT_MASK 0x38 1448 #define MC_CITF_WTM_WR_CNTL__GROUP1_DECREMENT__SHIFT 0x3 1449 #define MC_CITF_WTM_WR_CNTL__GROUP2_DECREMENT_MASK 0x1c0 1450 #define MC_CITF_WTM_WR_CNTL__GROUP2_DECREMENT__SHIFT 0x6 1451 #define MC_CITF_WTM_WR_CNTL__GROUP3_DECREMENT_MASK 0xe00 1452 #define MC_CITF_WTM_WR_CNTL__GROUP3_DECREMENT__SHIFT 0x9 1453 #define MC_CITF_WTM_WR_CNTL__GROUP4_DECREMENT_MASK 0x7000 1454 #define MC_CITF_WTM_WR_CNTL__GROUP4_DECREMENT__SHIFT 0xc 1455 #define MC_CITF_WTM_WR_CNTL__GROUP5_DECREMENT_MASK 0x38000 1456 #define MC_CITF_WTM_WR_CNTL__GROUP5_DECREMENT__SHIFT 0xf 1457 #define MC_CITF_WTM_WR_CNTL__GROUP6_DECREMENT_MASK 0x1c0000 1458 #define MC_CITF_WTM_WR_CNTL__GROUP6_DECREMENT__SHIFT 0x12 1459 #define MC_CITF_WTM_WR_CNTL__GROUP7_DECREMENT_MASK 0xe00000 1460 #define MC_CITF_WTM_WR_CNTL__GROUP7_DECREMENT__SHIFT 0x15 1461 #define MC_CITF_WTM_WR_CNTL__DISABLE_REMOTE_MASK 0x1000000 1462 #define MC_CITF_WTM_WR_CNTL__DISABLE_REMOTE__SHIFT 0x18 1463 #define MC_CITF_WTM_WR_CNTL__DISABLE_LOCAL_MASK 0x2000000 1464 #define MC_CITF_WTM_WR_CNTL__DISABLE_LOCAL__SHIFT 0x19 1465 #define MC_RD_CB__ENABLE_MASK 0x1 1466 #define MC_RD_CB__ENABLE__SHIFT 0x0 1467 #define MC_RD_CB__PRESCALE_MASK 0x6 1468 #define MC_RD_CB__PRESCALE__SHIFT 0x1 1469 #define MC_RD_CB__BLACKOUT_EXEMPT_MASK 0x8 1470 #define MC_RD_CB__BLACKOUT_EXEMPT__SHIFT 0x3 1471 #define MC_RD_CB__STALL_MODE_MASK 0x30 1472 #define MC_RD_CB__STALL_MODE__SHIFT 0x4 1473 #define MC_RD_CB__STALL_OVERRIDE_MASK 0x40 1474 #define MC_RD_CB__STALL_OVERRIDE__SHIFT 0x6 1475 #define MC_RD_CB__MAX_BURST_MASK 0x780 1476 #define MC_RD_CB__MAX_BURST__SHIFT 0x7 1477 #define MC_RD_CB__LAZY_TIMER_MASK 0x7800 1478 #define MC_RD_CB__LAZY_TIMER__SHIFT 0xb 1479 #define MC_RD_CB__STALL_OVERRIDE_WTM_MASK 0x8000 1480 #define MC_RD_CB__STALL_OVERRIDE_WTM__SHIFT 0xf 1481 #define MC_RD_DB__ENABLE_MASK 0x1 1482 #define MC_RD_DB__ENABLE__SHIFT 0x0 1483 #define MC_RD_DB__PRESCALE_MASK 0x6 1484 #define MC_RD_DB__PRESCALE__SHIFT 0x1 1485 #define MC_RD_DB__BLACKOUT_EXEMPT_MASK 0x8 1486 #define MC_RD_DB__BLACKOUT_EXEMPT__SHIFT 0x3 1487 #define MC_RD_DB__STALL_MODE_MASK 0x30 1488 #define MC_RD_DB__STALL_MODE__SHIFT 0x4 1489 #define MC_RD_DB__STALL_OVERRIDE_MASK 0x40 1490 #define MC_RD_DB__STALL_OVERRIDE__SHIFT 0x6 1491 #define MC_RD_DB__MAX_BURST_MASK 0x780 1492 #define MC_RD_DB__MAX_BURST__SHIFT 0x7 1493 #define MC_RD_DB__LAZY_TIMER_MASK 0x7800 1494 #define MC_RD_DB__LAZY_TIMER__SHIFT 0xb 1495 #define MC_RD_DB__STALL_OVERRIDE_WTM_MASK 0x8000 1496 #define MC_RD_DB__STALL_OVERRIDE_WTM__SHIFT 0xf 1497 #define MC_RD_TC0__ENABLE_MASK 0x1 1498 #define MC_RD_TC0__ENABLE__SHIFT 0x0 1499 #define MC_RD_TC0__PRESCALE_MASK 0x6 1500 #define MC_RD_TC0__PRESCALE__SHIFT 0x1 1501 #define MC_RD_TC0__BLACKOUT_EXEMPT_MASK 0x8 1502 #define MC_RD_TC0__BLACKOUT_EXEMPT__SHIFT 0x3 1503 #define MC_RD_TC0__STALL_MODE_MASK 0x30 1504 #define MC_RD_TC0__STALL_MODE__SHIFT 0x4 1505 #define MC_RD_TC0__STALL_OVERRIDE_MASK 0x40 1506 #define MC_RD_TC0__STALL_OVERRIDE__SHIFT 0x6 1507 #define MC_RD_TC0__MAX_BURST_MASK 0x780 1508 #define MC_RD_TC0__MAX_BURST__SHIFT 0x7 1509 #define MC_RD_TC0__LAZY_TIMER_MASK 0x7800 1510 #define MC_RD_TC0__LAZY_TIMER__SHIFT 0xb 1511 #define MC_RD_TC0__STALL_OVERRIDE_WTM_MASK 0x8000 1512 #define MC_RD_TC0__STALL_OVERRIDE_WTM__SHIFT 0xf 1513 #define MC_RD_TC1__ENABLE_MASK 0x1 1514 #define MC_RD_TC1__ENABLE__SHIFT 0x0 1515 #define MC_RD_TC1__PRESCALE_MASK 0x6 1516 #define MC_RD_TC1__PRESCALE__SHIFT 0x1 1517 #define MC_RD_TC1__BLACKOUT_EXEMPT_MASK 0x8 1518 #define MC_RD_TC1__BLACKOUT_EXEMPT__SHIFT 0x3 1519 #define MC_RD_TC1__STALL_MODE_MASK 0x30 1520 #define MC_RD_TC1__STALL_MODE__SHIFT 0x4 1521 #define MC_RD_TC1__STALL_OVERRIDE_MASK 0x40 1522 #define MC_RD_TC1__STALL_OVERRIDE__SHIFT 0x6 1523 #define MC_RD_TC1__MAX_BURST_MASK 0x780 1524 #define MC_RD_TC1__MAX_BURST__SHIFT 0x7 1525 #define MC_RD_TC1__LAZY_TIMER_MASK 0x7800 1526 #define MC_RD_TC1__LAZY_TIMER__SHIFT 0xb 1527 #define MC_RD_TC1__STALL_OVERRIDE_WTM_MASK 0x8000 1528 #define MC_RD_TC1__STALL_OVERRIDE_WTM__SHIFT 0xf 1529 #define MC_RD_HUB__ENABLE_MASK 0x1 1530 #define MC_RD_HUB__ENABLE__SHIFT 0x0 1531 #define MC_RD_HUB__PRESCALE_MASK 0x6 1532 #define MC_RD_HUB__PRESCALE__SHIFT 0x1 1533 #define MC_RD_HUB__BLACKOUT_EXEMPT_MASK 0x8 1534 #define MC_RD_HUB__BLACKOUT_EXEMPT__SHIFT 0x3 1535 #define MC_RD_HUB__STALL_MODE_MASK 0x30 1536 #define MC_RD_HUB__STALL_MODE__SHIFT 0x4 1537 #define MC_RD_HUB__STALL_OVERRIDE_MASK 0x40 1538 #define MC_RD_HUB__STALL_OVERRIDE__SHIFT 0x6 1539 #define MC_RD_HUB__MAX_BURST_MASK 0x780 1540 #define MC_RD_HUB__MAX_BURST__SHIFT 0x7 1541 #define MC_RD_HUB__LAZY_TIMER_MASK 0x7800 1542 #define MC_RD_HUB__LAZY_TIMER__SHIFT 0xb 1543 #define MC_RD_HUB__STALL_OVERRIDE_WTM_MASK 0x8000 1544 #define MC_RD_HUB__STALL_OVERRIDE_WTM__SHIFT 0xf 1545 #define MC_WR_CB__ENABLE_MASK 0x1 1546 #define MC_WR_CB__ENABLE__SHIFT 0x0 1547 #define MC_WR_CB__PRESCALE_MASK 0x6 1548 #define MC_WR_CB__PRESCALE__SHIFT 0x1 1549 #define MC_WR_CB__BLACKOUT_EXEMPT_MASK 0x8 1550 #define MC_WR_CB__BLACKOUT_EXEMPT__SHIFT 0x3 1551 #define MC_WR_CB__STALL_MODE_MASK 0x30 1552 #define MC_WR_CB__STALL_MODE__SHIFT 0x4 1553 #define MC_WR_CB__STALL_OVERRIDE_MASK 0x40 1554 #define MC_WR_CB__STALL_OVERRIDE__SHIFT 0x6 1555 #define MC_WR_CB__MAX_BURST_MASK 0x780 1556 #define MC_WR_CB__MAX_BURST__SHIFT 0x7 1557 #define MC_WR_CB__LAZY_TIMER_MASK 0x7800 1558 #define MC_WR_CB__LAZY_TIMER__SHIFT 0xb 1559 #define MC_WR_CB__STALL_OVERRIDE_WTM_MASK 0x8000 1560 #define MC_WR_CB__STALL_OVERRIDE_WTM__SHIFT 0xf 1561 #define MC_WR_DB__ENABLE_MASK 0x1 1562 #define MC_WR_DB__ENABLE__SHIFT 0x0 1563 #define MC_WR_DB__PRESCALE_MASK 0x6 1564 #define MC_WR_DB__PRESCALE__SHIFT 0x1 1565 #define MC_WR_DB__BLACKOUT_EXEMPT_MASK 0x8 1566 #define MC_WR_DB__BLACKOUT_EXEMPT__SHIFT 0x3 1567 #define MC_WR_DB__STALL_MODE_MASK 0x30 1568 #define MC_WR_DB__STALL_MODE__SHIFT 0x4 1569 #define MC_WR_DB__STALL_OVERRIDE_MASK 0x40 1570 #define MC_WR_DB__STALL_OVERRIDE__SHIFT 0x6 1571 #define MC_WR_DB__MAX_BURST_MASK 0x780 1572 #define MC_WR_DB__MAX_BURST__SHIFT 0x7 1573 #define MC_WR_DB__LAZY_TIMER_MASK 0x7800 1574 #define MC_WR_DB__LAZY_TIMER__SHIFT 0xb 1575 #define MC_WR_DB__STALL_OVERRIDE_WTM_MASK 0x8000 1576 #define MC_WR_DB__STALL_OVERRIDE_WTM__SHIFT 0xf 1577 #define MC_WR_HUB__ENABLE_MASK 0x1 1578 #define MC_WR_HUB__ENABLE__SHIFT 0x0 1579 #define MC_WR_HUB__PRESCALE_MASK 0x6 1580 #define MC_WR_HUB__PRESCALE__SHIFT 0x1 1581 #define MC_WR_HUB__BLACKOUT_EXEMPT_MASK 0x8 1582 #define MC_WR_HUB__BLACKOUT_EXEMPT__SHIFT 0x3 1583 #define MC_WR_HUB__STALL_MODE_MASK 0x30 1584 #define MC_WR_HUB__STALL_MODE__SHIFT 0x4 1585 #define MC_WR_HUB__STALL_OVERRIDE_MASK 0x40 1586 #define MC_WR_HUB__STALL_OVERRIDE__SHIFT 0x6 1587 #define MC_WR_HUB__MAX_BURST_MASK 0x780 1588 #define MC_WR_HUB__MAX_BURST__SHIFT 0x7 1589 #define MC_WR_HUB__LAZY_TIMER_MASK 0x7800 1590 #define MC_WR_HUB__LAZY_TIMER__SHIFT 0xb 1591 #define MC_WR_HUB__STALL_OVERRIDE_WTM_MASK 0x8000 1592 #define MC_WR_HUB__STALL_OVERRIDE_WTM__SHIFT 0xf 1593 #define MC_CITF_CREDITS_XBAR__READ_LCL_MASK 0xff 1594 #define MC_CITF_CREDITS_XBAR__READ_LCL__SHIFT 0x0 1595 #define MC_CITF_CREDITS_XBAR__WRITE_LCL_MASK 0xff00 1596 #define MC_CITF_CREDITS_XBAR__WRITE_LCL__SHIFT 0x8 1597 #define MC_RD_GRP_LCL__CB0_MASK 0xf000 1598 #define MC_RD_GRP_LCL__CB0__SHIFT 0xc 1599 #define MC_RD_GRP_LCL__CBCMASK0_MASK 0xf0000 1600 #define MC_RD_GRP_LCL__CBCMASK0__SHIFT 0x10 1601 #define MC_RD_GRP_LCL__CBFMASK0_MASK 0xf00000 1602 #define MC_RD_GRP_LCL__CBFMASK0__SHIFT 0x14 1603 #define MC_RD_GRP_LCL__DB0_MASK 0xf000000 1604 #define MC_RD_GRP_LCL__DB0__SHIFT 0x18 1605 #define MC_RD_GRP_LCL__DBHTILE0_MASK 0xf0000000 1606 #define MC_RD_GRP_LCL__DBHTILE0__SHIFT 0x1c 1607 #define MC_WR_GRP_LCL__CB0_MASK 0xf 1608 #define MC_WR_GRP_LCL__CB0__SHIFT 0x0 1609 #define MC_WR_GRP_LCL__CBCMASK0_MASK 0xf0 1610 #define MC_WR_GRP_LCL__CBCMASK0__SHIFT 0x4 1611 #define MC_WR_GRP_LCL__CBFMASK0_MASK 0xf00 1612 #define MC_WR_GRP_LCL__CBFMASK0__SHIFT 0x8 1613 #define MC_WR_GRP_LCL__DB0_MASK 0xf000 1614 #define MC_WR_GRP_LCL__DB0__SHIFT 0xc 1615 #define MC_WR_GRP_LCL__DBHTILE0_MASK 0xf0000 1616 #define MC_WR_GRP_LCL__DBHTILE0__SHIFT 0x10 1617 #define MC_WR_GRP_LCL__SX0_MASK 0xf00000 1618 #define MC_WR_GRP_LCL__SX0__SHIFT 0x14 1619 #define MC_WR_GRP_LCL__CBIMMED0_MASK 0xf0000000 1620 #define MC_WR_GRP_LCL__CBIMMED0__SHIFT 0x1c 1621 #define MC_CITF_PERF_MON_CNTL2__CID_MASK 0xff 1622 #define MC_CITF_PERF_MON_CNTL2__CID__SHIFT 0x0 1623 #define MC_CITF_PERF_MON_RSLT2__CB_RD_BUSY_MASK 0x2 1624 #define MC_CITF_PERF_MON_RSLT2__CB_RD_BUSY__SHIFT 0x1 1625 #define MC_CITF_PERF_MON_RSLT2__DB_RD_BUSY_MASK 0x4 1626 #define MC_CITF_PERF_MON_RSLT2__DB_RD_BUSY__SHIFT 0x2 1627 #define MC_CITF_PERF_MON_RSLT2__TC0_RD_BUSY_MASK 0x8 1628 #define MC_CITF_PERF_MON_RSLT2__TC0_RD_BUSY__SHIFT 0x3 1629 #define MC_CITF_PERF_MON_RSLT2__VC0_RD_BUSY_MASK 0x10 1630 #define MC_CITF_PERF_MON_RSLT2__VC0_RD_BUSY__SHIFT 0x4 1631 #define MC_CITF_PERF_MON_RSLT2__TC1_RD_BUSY_MASK 0x20 1632 #define MC_CITF_PERF_MON_RSLT2__TC1_RD_BUSY__SHIFT 0x5 1633 #define MC_CITF_PERF_MON_RSLT2__VC1_RD_BUSY_MASK 0x40 1634 #define MC_CITF_PERF_MON_RSLT2__VC1_RD_BUSY__SHIFT 0x6 1635 #define MC_CITF_PERF_MON_RSLT2__CB_WR_BUSY_MASK 0x80 1636 #define MC_CITF_PERF_MON_RSLT2__CB_WR_BUSY__SHIFT 0x7 1637 #define MC_CITF_PERF_MON_RSLT2__DB_WR_BUSY_MASK 0x100 1638 #define MC_CITF_PERF_MON_RSLT2__DB_WR_BUSY__SHIFT 0x8 1639 #define MC_CITF_PERF_MON_RSLT2__SX_WR_BUSY_MASK 0x200 1640 #define MC_CITF_PERF_MON_RSLT2__SX_WR_BUSY__SHIFT 0x9 1641 #define MC_CITF_PERF_MON_RSLT2__TC2_RD_BUSY_MASK 0x400 1642 #define MC_CITF_PERF_MON_RSLT2__TC2_RD_BUSY__SHIFT 0xa 1643 #define MC_CITF_PERF_MON_RSLT2__TC0_WR_BUSY_MASK 0x800 1644 #define MC_CITF_PERF_MON_RSLT2__TC0_WR_BUSY__SHIFT 0xb 1645 #define MC_CITF_PERF_MON_RSLT2__TC1_WR_BUSY_MASK 0x1000 1646 #define MC_CITF_PERF_MON_RSLT2__TC1_WR_BUSY__SHIFT 0xc 1647 #define MC_CITF_PERF_MON_RSLT2__TC2_WR_BUSY_MASK 0x2000 1648 #define MC_CITF_PERF_MON_RSLT2__TC2_WR_BUSY__SHIFT 0xd 1649 #define MC_CITF_PERF_MON_RSLT2__TC0_ATOM_BUSY_MASK 0x4000 1650 #define MC_CITF_PERF_MON_RSLT2__TC0_ATOM_BUSY__SHIFT 0xe 1651 #define MC_CITF_PERF_MON_RSLT2__TC1_ATOM_BUSY_MASK 0x8000 1652 #define MC_CITF_PERF_MON_RSLT2__TC1_ATOM_BUSY__SHIFT 0xf 1653 #define MC_CITF_PERF_MON_RSLT2__TC2_ATOM_BUSY_MASK 0x10000 1654 #define MC_CITF_PERF_MON_RSLT2__TC2_ATOM_BUSY__SHIFT 0x10 1655 #define MC_CITF_PERF_MON_RSLT2__CB_ATOM_BUSY_MASK 0x20000 1656 #define MC_CITF_PERF_MON_RSLT2__CB_ATOM_BUSY__SHIFT 0x11 1657 #define MC_CITF_PERF_MON_RSLT2__DB_ATOM_BUSY_MASK 0x40000 1658 #define MC_CITF_PERF_MON_RSLT2__DB_ATOM_BUSY__SHIFT 0x12 1659 #define MC_CITF_MISC_RD_CG__ONDLY_MASK 0x3f 1660 #define MC_CITF_MISC_RD_CG__ONDLY__SHIFT 0x0 1661 #define MC_CITF_MISC_RD_CG__OFFDLY_MASK 0xfc0 1662 #define MC_CITF_MISC_RD_CG__OFFDLY__SHIFT 0x6 1663 #define MC_CITF_MISC_RD_CG__RDYDLY_MASK 0x3f000 1664 #define MC_CITF_MISC_RD_CG__RDYDLY__SHIFT 0xc 1665 #define MC_CITF_MISC_RD_CG__ENABLE_MASK 0x40000 1666 #define MC_CITF_MISC_RD_CG__ENABLE__SHIFT 0x12 1667 #define MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK 0x80000 1668 #define MC_CITF_MISC_RD_CG__MEM_LS_ENABLE__SHIFT 0x13 1669 #define MC_CITF_MISC_WR_CG__ONDLY_MASK 0x3f 1670 #define MC_CITF_MISC_WR_CG__ONDLY__SHIFT 0x0 1671 #define MC_CITF_MISC_WR_CG__OFFDLY_MASK 0xfc0 1672 #define MC_CITF_MISC_WR_CG__OFFDLY__SHIFT 0x6 1673 #define MC_CITF_MISC_WR_CG__RDYDLY_MASK 0x3f000 1674 #define MC_CITF_MISC_WR_CG__RDYDLY__SHIFT 0xc 1675 #define MC_CITF_MISC_WR_CG__ENABLE_MASK 0x40000 1676 #define MC_CITF_MISC_WR_CG__ENABLE__SHIFT 0x12 1677 #define MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK 0x80000 1678 #define MC_CITF_MISC_WR_CG__MEM_LS_ENABLE__SHIFT 0x13 1679 #define MC_CITF_MISC_VM_CG__ONDLY_MASK 0x3f 1680 #define MC_CITF_MISC_VM_CG__ONDLY__SHIFT 0x0 1681 #define MC_CITF_MISC_VM_CG__OFFDLY_MASK 0xfc0 1682 #define MC_CITF_MISC_VM_CG__OFFDLY__SHIFT 0x6 1683 #define MC_CITF_MISC_VM_CG__RDYDLY_MASK 0x3f000 1684 #define MC_CITF_MISC_VM_CG__RDYDLY__SHIFT 0xc 1685 #define MC_CITF_MISC_VM_CG__ENABLE_MASK 0x40000 1686 #define MC_CITF_MISC_VM_CG__ENABLE__SHIFT 0x12 1687 #define MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK 0x80000 1688 #define MC_CITF_MISC_VM_CG__MEM_LS_ENABLE__SHIFT 0x13 1689 #define MC_HUB_MISC_POWER__SRBM_GATE_OVERRIDE_MASK 0x4 1690 #define MC_HUB_MISC_POWER__SRBM_GATE_OVERRIDE__SHIFT 0x2 1691 #define MC_HUB_MISC_POWER__PM_BLACKOUT_CNTL_MASK 0x18 1692 #define MC_HUB_MISC_POWER__PM_BLACKOUT_CNTL__SHIFT 0x3 1693 #define MC_HUB_MISC_HUB_CG__ONDLY_MASK 0x3f 1694 #define MC_HUB_MISC_HUB_CG__ONDLY__SHIFT 0x0 1695 #define MC_HUB_MISC_HUB_CG__OFFDLY_MASK 0xfc0 1696 #define MC_HUB_MISC_HUB_CG__OFFDLY__SHIFT 0x6 1697 #define MC_HUB_MISC_HUB_CG__RDYDLY_MASK 0x3f000 1698 #define MC_HUB_MISC_HUB_CG__RDYDLY__SHIFT 0xc 1699 #define MC_HUB_MISC_HUB_CG__ENABLE_MASK 0x40000 1700 #define MC_HUB_MISC_HUB_CG__ENABLE__SHIFT 0x12 1701 #define MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK 0x80000 1702 #define MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE__SHIFT 0x13 1703 #define MC_HUB_MISC_VM_CG__ONDLY_MASK 0x3f 1704 #define MC_HUB_MISC_VM_CG__ONDLY__SHIFT 0x0 1705 #define MC_HUB_MISC_VM_CG__OFFDLY_MASK 0xfc0 1706 #define MC_HUB_MISC_VM_CG__OFFDLY__SHIFT 0x6 1707 #define MC_HUB_MISC_VM_CG__RDYDLY_MASK 0x3f000 1708 #define MC_HUB_MISC_VM_CG__RDYDLY__SHIFT 0xc 1709 #define MC_HUB_MISC_VM_CG__ENABLE_MASK 0x40000 1710 #define MC_HUB_MISC_VM_CG__ENABLE__SHIFT 0x12 1711 #define MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK 0x80000 1712 #define MC_HUB_MISC_VM_CG__MEM_LS_ENABLE__SHIFT 0x13 1713 #define MC_HUB_MISC_SIP_CG__ONDLY_MASK 0x3f 1714 #define MC_HUB_MISC_SIP_CG__ONDLY__SHIFT 0x0 1715 #define MC_HUB_MISC_SIP_CG__OFFDLY_MASK 0xfc0 1716 #define MC_HUB_MISC_SIP_CG__OFFDLY__SHIFT 0x6 1717 #define MC_HUB_MISC_SIP_CG__RDYDLY_MASK 0x3f000 1718 #define MC_HUB_MISC_SIP_CG__RDYDLY__SHIFT 0xc 1719 #define MC_HUB_MISC_SIP_CG__ENABLE_MASK 0x40000 1720 #define MC_HUB_MISC_SIP_CG__ENABLE__SHIFT 0x12 1721 #define MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK 0x80000 1722 #define MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE__SHIFT 0x13 1723 #define MC_HUB_MISC_STATUS__OUTSTANDING_READ_MASK 0x1 1724 #define MC_HUB_MISC_STATUS__OUTSTANDING_READ__SHIFT 0x0 1725 #define MC_HUB_MISC_STATUS__OUTSTANDING_WRITE_MASK 0x2 1726 #define MC_HUB_MISC_STATUS__OUTSTANDING_WRITE__SHIFT 0x1 1727 #define MC_HUB_MISC_STATUS__OUTSTANDING_ATOMIC_MASK 0x4 1728 #define MC_HUB_MISC_STATUS__OUTSTANDING_ATOMIC__SHIFT 0x2 1729 #define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDREQ_MASK 0x8 1730 #define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDREQ__SHIFT 0x3 1731 #define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDRET_MASK 0x10 1732 #define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDRET__SHIFT 0x4 1733 #define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRREQ_MASK 0x20 1734 #define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRREQ__SHIFT 0x5 1735 #define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRRET_MASK 0x40 1736 #define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRRET__SHIFT 0x6 1737 #define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_ATOMIC_REQ_MASK 0x80 1738 #define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_ATOMIC_REQ__SHIFT 0x7 1739 #define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_ATOMIC_RET_MASK 0x100 1740 #define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_ATOMIC_RET__SHIFT 0x8 1741 #define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_READ_MASK 0x200 1742 #define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_READ__SHIFT 0x9 1743 #define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_WRITE_MASK 0x400 1744 #define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_WRITE__SHIFT 0xa 1745 #define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_ATOMIC_MASK 0x800 1746 #define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_ATOMIC__SHIFT 0xb 1747 #define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_READ_MASK 0x1000 1748 #define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_READ__SHIFT 0xc 1749 #define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_WRITE_MASK 0x2000 1750 #define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_WRITE__SHIFT 0xd 1751 #define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_ATOMIC_MASK 0x4000 1752 #define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_ATOMIC__SHIFT 0xe 1753 #define MC_HUB_MISC_STATUS__RPB_BUSY_MASK 0x8000 1754 #define MC_HUB_MISC_STATUS__RPB_BUSY__SHIFT 0xf 1755 #define MC_HUB_MISC_STATUS__WRITE_DEADLOCK_WARNING_MASK 0x10000 1756 #define MC_HUB_MISC_STATUS__WRITE_DEADLOCK_WARNING__SHIFT 0x10 1757 #define MC_HUB_MISC_STATUS__READ_DEADLOCK_WARNING_MASK 0x20000 1758 #define MC_HUB_MISC_STATUS__READ_DEADLOCK_WARNING__SHIFT 0x11 1759 #define MC_HUB_MISC_STATUS__ATOMIC_DEADLOCK_WARNING_MASK 0x40000 1760 #define MC_HUB_MISC_STATUS__ATOMIC_DEADLOCK_WARNING__SHIFT 0x12 1761 #define MC_HUB_MISC_STATUS__GFX_BUSY_MASK 0x80000 1762 #define MC_HUB_MISC_STATUS__GFX_BUSY__SHIFT 0x13 1763 #define MC_HUB_MISC_OVERRIDE__IDLE_MASK 0x3 1764 #define MC_HUB_MISC_OVERRIDE__IDLE__SHIFT 0x0 1765 #define MC_HUB_MISC_FRAMING__BITS_MASK 0xffffffff 1766 #define MC_HUB_MISC_FRAMING__BITS__SHIFT 0x0 1767 #define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL0_MASK 0x2 1768 #define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL0__SHIFT 0x1 1769 #define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL1_MASK 0x4 1770 #define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL1__SHIFT 0x2 1771 #define MC_HUB_WDP_CNTL__JUMPAHEAD_INTERNAL_MASK 0x8 1772 #define MC_HUB_WDP_CNTL__JUMPAHEAD_INTERNAL__SHIFT 0x3 1773 #define MC_HUB_WDP_CNTL__OVERRIDE_STALL_ENABLE_MASK 0x10 1774 #define MC_HUB_WDP_CNTL__OVERRIDE_STALL_ENABLE__SHIFT 0x4 1775 #define MC_HUB_WDP_CNTL__DEBUG_REG_MASK 0x1fe0 1776 #define MC_HUB_WDP_CNTL__DEBUG_REG__SHIFT 0x5 1777 #define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL0_MASK 0x2000 1778 #define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL0__SHIFT 0xd 1779 #define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL1_MASK 0x4000 1780 #define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL1__SHIFT 0xe 1781 #define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_INTERNAL_MASK 0x8000 1782 #define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_INTERNAL__SHIFT 0xf 1783 #define MC_HUB_WDP_CNTL__FAIR_CH_SW_MASK 0x10000 1784 #define MC_HUB_WDP_CNTL__FAIR_CH_SW__SHIFT 0x10 1785 #define MC_HUB_WDP_CNTL__LCLWRREQ_BYPASS_MASK 0x20000 1786 #define MC_HUB_WDP_CNTL__LCLWRREQ_BYPASS__SHIFT 0x11 1787 #define MC_HUB_WDP_CNTL__DISP_WAIT_EOP_MASK 0x40000 1788 #define MC_HUB_WDP_CNTL__DISP_WAIT_EOP__SHIFT 0x12 1789 #define MC_HUB_WDP_CNTL__MCD_WAIT_EOP_MASK 0x80000 1790 #define MC_HUB_WDP_CNTL__MCD_WAIT_EOP__SHIFT 0x13 1791 #define MC_HUB_WDP_CNTL__SIP_WAIT_EOP_MASK 0x100000 1792 #define MC_HUB_WDP_CNTL__SIP_WAIT_EOP__SHIFT 0x14 1793 #define MC_HUB_WDP_CNTL__UVD_VCE_WRITE_PRI_EN_MASK 0x200000 1794 #define MC_HUB_WDP_CNTL__UVD_VCE_WRITE_PRI_EN__SHIFT 0x15 1795 #define MC_HUB_WDP_CNTL__WRITE_PRI_EN_MASK 0x400000 1796 #define MC_HUB_WDP_CNTL__WRITE_PRI_EN__SHIFT 0x16 1797 #define MC_HUB_WDP_CNTL__IH_PHYSADDR_ENABLE_MASK 0x800000 1798 #define MC_HUB_WDP_CNTL__IH_PHYSADDR_ENABLE__SHIFT 0x17 1799 #define MC_HUB_WDP_ERR__MGPU1_TARG_SYS_MASK 0x1 1800 #define MC_HUB_WDP_ERR__MGPU1_TARG_SYS__SHIFT 0x0 1801 #define MC_HUB_WDP_ERR__MGPU2_TARG_SYS_MASK 0x2 1802 #define MC_HUB_WDP_ERR__MGPU2_TARG_SYS__SHIFT 0x1 1803 #define MC_HUB_WDP_BP__ENABLE_MASK 0x1 1804 #define MC_HUB_WDP_BP__ENABLE__SHIFT 0x0 1805 #define MC_HUB_WDP_BP__RDRET_MASK 0x3fffe 1806 #define MC_HUB_WDP_BP__RDRET__SHIFT 0x1 1807 #define MC_HUB_WDP_BP__WRREQ_MASK 0x3ffc0000 1808 #define MC_HUB_WDP_BP__WRREQ__SHIFT 0x12 1809 #define MC_HUB_WDP_STATUS__SIP_AVAIL_MASK 0x1 1810 #define MC_HUB_WDP_STATUS__SIP_AVAIL__SHIFT 0x0 1811 #define MC_HUB_WDP_STATUS__MCDW_RD_AVAIL_MASK 0x2 1812 #define MC_HUB_WDP_STATUS__MCDW_RD_AVAIL__SHIFT 0x1 1813 #define MC_HUB_WDP_STATUS__MCDX_RD_AVAIL_MASK 0x4 1814 #define MC_HUB_WDP_STATUS__MCDX_RD_AVAIL__SHIFT 0x2 1815 #define MC_HUB_WDP_STATUS__MCDY_RD_AVAIL_MASK 0x8 1816 #define MC_HUB_WDP_STATUS__MCDY_RD_AVAIL__SHIFT 0x3 1817 #define MC_HUB_WDP_STATUS__MCDZ_RD_AVAIL_MASK 0x10 1818 #define MC_HUB_WDP_STATUS__MCDZ_RD_AVAIL__SHIFT 0x4 1819 #define MC_HUB_WDP_STATUS__MCDS_RD_AVAIL_MASK 0x20 1820 #define MC_HUB_WDP_STATUS__MCDS_RD_AVAIL__SHIFT 0x5 1821 #define MC_HUB_WDP_STATUS__MCDT_RD_AVAIL_MASK 0x40 1822 #define MC_HUB_WDP_STATUS__MCDT_RD_AVAIL__SHIFT 0x6 1823 #define MC_HUB_WDP_STATUS__MCDU_RD_AVAIL_MASK 0x80 1824 #define MC_HUB_WDP_STATUS__MCDU_RD_AVAIL__SHIFT 0x7 1825 #define MC_HUB_WDP_STATUS__MCDV_RD_AVAIL_MASK 0x100 1826 #define MC_HUB_WDP_STATUS__MCDV_RD_AVAIL__SHIFT 0x8 1827 #define MC_HUB_WDP_STATUS__MCDW_WR_AVAIL_MASK 0x200 1828 #define MC_HUB_WDP_STATUS__MCDW_WR_AVAIL__SHIFT 0x9 1829 #define MC_HUB_WDP_STATUS__MCDX_WR_AVAIL_MASK 0x400 1830 #define MC_HUB_WDP_STATUS__MCDX_WR_AVAIL__SHIFT 0xa 1831 #define MC_HUB_WDP_STATUS__MCDY_WR_AVAIL_MASK 0x800 1832 #define MC_HUB_WDP_STATUS__MCDY_WR_AVAIL__SHIFT 0xb 1833 #define MC_HUB_WDP_STATUS__MCDZ_WR_AVAIL_MASK 0x1000 1834 #define MC_HUB_WDP_STATUS__MCDZ_WR_AVAIL__SHIFT 0xc 1835 #define MC_HUB_WDP_STATUS__MCDS_WR_AVAIL_MASK 0x2000 1836 #define MC_HUB_WDP_STATUS__MCDS_WR_AVAIL__SHIFT 0xd 1837 #define MC_HUB_WDP_STATUS__MCDT_WR_AVAIL_MASK 0x4000 1838 #define MC_HUB_WDP_STATUS__MCDT_WR_AVAIL__SHIFT 0xe 1839 #define MC_HUB_WDP_STATUS__MCDU_WR_AVAIL_MASK 0x8000 1840 #define MC_HUB_WDP_STATUS__MCDU_WR_AVAIL__SHIFT 0xf 1841 #define MC_HUB_WDP_STATUS__MCDV_WR_AVAIL_MASK 0x10000 1842 #define MC_HUB_WDP_STATUS__MCDV_WR_AVAIL__SHIFT 0x10 1843 #define MC_HUB_WDP_STATUS__GBL0_VM_FULL_MASK 0x20000 1844 #define MC_HUB_WDP_STATUS__GBL0_VM_FULL__SHIFT 0x11 1845 #define MC_HUB_WDP_STATUS__GBL0_STOR_FULL_MASK 0x40000 1846 #define MC_HUB_WDP_STATUS__GBL0_STOR_FULL__SHIFT 0x12 1847 #define MC_HUB_WDP_STATUS__GBL0_BYPASS_STOR_FULL_MASK 0x80000 1848 #define MC_HUB_WDP_STATUS__GBL0_BYPASS_STOR_FULL__SHIFT 0x13 1849 #define MC_HUB_WDP_STATUS__GBL1_VM_FULL_MASK 0x100000 1850 #define MC_HUB_WDP_STATUS__GBL1_VM_FULL__SHIFT 0x14 1851 #define MC_HUB_WDP_STATUS__GBL1_STOR_FULL_MASK 0x200000 1852 #define MC_HUB_WDP_STATUS__GBL1_STOR_FULL__SHIFT 0x15 1853 #define MC_HUB_WDP_STATUS__GBL1_BYPASS_STOR_FULL_MASK 0x400000 1854 #define MC_HUB_WDP_STATUS__GBL1_BYPASS_STOR_FULL__SHIFT 0x16 1855 #define MC_HUB_RDREQ_STATUS__SIP_AVAIL_MASK 0x1 1856 #define MC_HUB_RDREQ_STATUS__SIP_AVAIL__SHIFT 0x0 1857 #define MC_HUB_RDREQ_STATUS__MCDW_RD_AVAIL_MASK 0x2 1858 #define MC_HUB_RDREQ_STATUS__MCDW_RD_AVAIL__SHIFT 0x1 1859 #define MC_HUB_RDREQ_STATUS__MCDX_RD_AVAIL_MASK 0x4 1860 #define MC_HUB_RDREQ_STATUS__MCDX_RD_AVAIL__SHIFT 0x2 1861 #define MC_HUB_RDREQ_STATUS__MCDY_RD_AVAIL_MASK 0x8 1862 #define MC_HUB_RDREQ_STATUS__MCDY_RD_AVAIL__SHIFT 0x3 1863 #define MC_HUB_RDREQ_STATUS__MCDZ_RD_AVAIL_MASK 0x10 1864 #define MC_HUB_RDREQ_STATUS__MCDZ_RD_AVAIL__SHIFT 0x4 1865 #define MC_HUB_RDREQ_STATUS__MCDS_RD_AVAIL_MASK 0x20 1866 #define MC_HUB_RDREQ_STATUS__MCDS_RD_AVAIL__SHIFT 0x5 1867 #define MC_HUB_RDREQ_STATUS__MCDT_RD_AVAIL_MASK 0x40 1868 #define MC_HUB_RDREQ_STATUS__MCDT_RD_AVAIL__SHIFT 0x6 1869 #define MC_HUB_RDREQ_STATUS__MCDU_RD_AVAIL_MASK 0x80 1870 #define MC_HUB_RDREQ_STATUS__MCDU_RD_AVAIL__SHIFT 0x7 1871 #define MC_HUB_RDREQ_STATUS__MCDV_RD_AVAIL_MASK 0x100 1872 #define MC_HUB_RDREQ_STATUS__MCDV_RD_AVAIL__SHIFT 0x8 1873 #define MC_HUB_RDREQ_STATUS__GBL0_VM_FULL_MASK 0x200 1874 #define MC_HUB_RDREQ_STATUS__GBL0_VM_FULL__SHIFT 0x9 1875 #define MC_HUB_RDREQ_STATUS__GBL0_STOR_FULL_MASK 0x400 1876 #define MC_HUB_RDREQ_STATUS__GBL0_STOR_FULL__SHIFT 0xa 1877 #define MC_HUB_RDREQ_STATUS__GBL0_BYPASS_STOR_FULL_MASK 0x800 1878 #define MC_HUB_RDREQ_STATUS__GBL0_BYPASS_STOR_FULL__SHIFT 0xb 1879 #define MC_HUB_RDREQ_STATUS__GBL1_VM_FULL_MASK 0x1000 1880 #define MC_HUB_RDREQ_STATUS__GBL1_VM_FULL__SHIFT 0xc 1881 #define MC_HUB_RDREQ_STATUS__GBL1_STOR_FULL_MASK 0x2000 1882 #define MC_HUB_RDREQ_STATUS__GBL1_STOR_FULL__SHIFT 0xd 1883 #define MC_HUB_RDREQ_STATUS__GBL1_BYPASS_STOR_FULL_MASK 0x4000 1884 #define MC_HUB_RDREQ_STATUS__GBL1_BYPASS_STOR_FULL__SHIFT 0xe 1885 #define MC_HUB_RDREQ_STATUS__PWRXPRESS_ERR_MASK 0x8000 1886 #define MC_HUB_RDREQ_STATUS__PWRXPRESS_ERR__SHIFT 0xf 1887 #define MC_HUB_WRRET_STATUS__MCDW_AVAIL_MASK 0x1 1888 #define MC_HUB_WRRET_STATUS__MCDW_AVAIL__SHIFT 0x0 1889 #define MC_HUB_WRRET_STATUS__MCDX_AVAIL_MASK 0x2 1890 #define MC_HUB_WRRET_STATUS__MCDX_AVAIL__SHIFT 0x1 1891 #define MC_HUB_WRRET_STATUS__MCDY_AVAIL_MASK 0x4 1892 #define MC_HUB_WRRET_STATUS__MCDY_AVAIL__SHIFT 0x2 1893 #define MC_HUB_WRRET_STATUS__MCDZ_AVAIL_MASK 0x8 1894 #define MC_HUB_WRRET_STATUS__MCDZ_AVAIL__SHIFT 0x3 1895 #define MC_HUB_WRRET_STATUS__MCDS_AVAIL_MASK 0x10 1896 #define MC_HUB_WRRET_STATUS__MCDS_AVAIL__SHIFT 0x4 1897 #define MC_HUB_WRRET_STATUS__MCDT_AVAIL_MASK 0x20 1898 #define MC_HUB_WRRET_STATUS__MCDT_AVAIL__SHIFT 0x5 1899 #define MC_HUB_WRRET_STATUS__MCDU_AVAIL_MASK 0x40 1900 #define MC_HUB_WRRET_STATUS__MCDU_AVAIL__SHIFT 0x6 1901 #define MC_HUB_WRRET_STATUS__MCDV_AVAIL_MASK 0x80 1902 #define MC_HUB_WRRET_STATUS__MCDV_AVAIL__SHIFT 0x7 1903 #define MC_HUB_RDREQ_CNTL__REMOTE_BLACKOUT_MASK 0x1 1904 #define MC_HUB_RDREQ_CNTL__REMOTE_BLACKOUT__SHIFT 0x0 1905 #define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL0_MASK 0x4 1906 #define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL0__SHIFT 0x2 1907 #define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL1_MASK 0x8 1908 #define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL1__SHIFT 0x3 1909 #define MC_HUB_RDREQ_CNTL__OVERRIDE_STALL_ENABLE_MASK 0x10 1910 #define MC_HUB_RDREQ_CNTL__OVERRIDE_STALL_ENABLE__SHIFT 0x4 1911 #define MC_HUB_RDREQ_CNTL__MCDW_STALL_MODE_MASK 0x20 1912 #define MC_HUB_RDREQ_CNTL__MCDW_STALL_MODE__SHIFT 0x5 1913 #define MC_HUB_RDREQ_CNTL__MCDX_STALL_MODE_MASK 0x40 1914 #define MC_HUB_RDREQ_CNTL__MCDX_STALL_MODE__SHIFT 0x6 1915 #define MC_HUB_RDREQ_CNTL__MCDY_STALL_MODE_MASK 0x80 1916 #define MC_HUB_RDREQ_CNTL__MCDY_STALL_MODE__SHIFT 0x7 1917 #define MC_HUB_RDREQ_CNTL__MCDZ_STALL_MODE_MASK 0x100 1918 #define MC_HUB_RDREQ_CNTL__MCDZ_STALL_MODE__SHIFT 0x8 1919 #define MC_HUB_RDREQ_CNTL__MCDS_STALL_MODE_MASK 0x200 1920 #define MC_HUB_RDREQ_CNTL__MCDS_STALL_MODE__SHIFT 0x9 1921 #define MC_HUB_RDREQ_CNTL__MCDT_STALL_MODE_MASK 0x400 1922 #define MC_HUB_RDREQ_CNTL__MCDT_STALL_MODE__SHIFT 0xa 1923 #define MC_HUB_RDREQ_CNTL__MCDU_STALL_MODE_MASK 0x800 1924 #define MC_HUB_RDREQ_CNTL__MCDU_STALL_MODE__SHIFT 0xb 1925 #define MC_HUB_RDREQ_CNTL__MCDV_STALL_MODE_MASK 0x1000 1926 #define MC_HUB_RDREQ_CNTL__MCDV_STALL_MODE__SHIFT 0xc 1927 #define MC_HUB_RDREQ_CNTL__BREAK_HDP_DEADLOCK_MASK 0x2000 1928 #define MC_HUB_RDREQ_CNTL__BREAK_HDP_DEADLOCK__SHIFT 0xd 1929 #define MC_HUB_RDREQ_CNTL__DEBUG_REG_MASK 0x1fc000 1930 #define MC_HUB_RDREQ_CNTL__DEBUG_REG__SHIFT 0xe 1931 #define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL0_MASK 0x200000 1932 #define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL0__SHIFT 0x15 1933 #define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL1_MASK 0x400000 1934 #define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL1__SHIFT 0x16 1935 #define MC_HUB_RDREQ_CNTL__PWRXPRESS_MODE_MASK 0x800000 1936 #define MC_HUB_RDREQ_CNTL__PWRXPRESS_MODE__SHIFT 0x17 1937 #define MC_HUB_RDREQ_CNTL__ACPG_HP_TO_MCD_OVERRIDE_MASK 0x1000000 1938 #define MC_HUB_RDREQ_CNTL__ACPG_HP_TO_MCD_OVERRIDE__SHIFT 0x18 1939 #define MC_HUB_RDREQ_CNTL__GBL0_PRI_ENABLE_MASK 0x2000000 1940 #define MC_HUB_RDREQ_CNTL__GBL0_PRI_ENABLE__SHIFT 0x19 1941 #define MC_HUB_RDREQ_CNTL__UVD_TRANSCODE_ENABLE_MASK 0x4000000 1942 #define MC_HUB_RDREQ_CNTL__UVD_TRANSCODE_ENABLE__SHIFT 0x1a 1943 #define MC_HUB_RDREQ_CNTL__DMIF_URG_THRESHOLD_MASK 0x78000000 1944 #define MC_HUB_RDREQ_CNTL__DMIF_URG_THRESHOLD__SHIFT 0x1b 1945 #define MC_HUB_WRRET_CNTL__JUMPAHEAD_MASK 0x1 1946 #define MC_HUB_WRRET_CNTL__JUMPAHEAD__SHIFT 0x0 1947 #define MC_HUB_WRRET_CNTL__BP_MASK 0x1ffffe 1948 #define MC_HUB_WRRET_CNTL__BP__SHIFT 0x1 1949 #define MC_HUB_WRRET_CNTL__BP_ENABLE_MASK 0x200000 1950 #define MC_HUB_WRRET_CNTL__BP_ENABLE__SHIFT 0x15 1951 #define MC_HUB_WRRET_CNTL__DEBUG_REG_MASK 0x3fc00000 1952 #define MC_HUB_WRRET_CNTL__DEBUG_REG__SHIFT 0x16 1953 #define MC_HUB_WRRET_CNTL__DISABLE_SELF_INIT_MASK 0x40000000 1954 #define MC_HUB_WRRET_CNTL__DISABLE_SELF_INIT__SHIFT 0x1e 1955 #define MC_HUB_WRRET_CNTL__FAIR_CH_SW_MASK 0x80000000 1956 #define MC_HUB_WRRET_CNTL__FAIR_CH_SW__SHIFT 0x1f 1957 #define MC_HUB_RDREQ_WTM_CNTL__GROUP0_DECREMENT_MASK 0x7 1958 #define MC_HUB_RDREQ_WTM_CNTL__GROUP0_DECREMENT__SHIFT 0x0 1959 #define MC_HUB_RDREQ_WTM_CNTL__GROUP1_DECREMENT_MASK 0x38 1960 #define MC_HUB_RDREQ_WTM_CNTL__GROUP1_DECREMENT__SHIFT 0x3 1961 #define MC_HUB_RDREQ_WTM_CNTL__GROUP2_DECREMENT_MASK 0x1c0 1962 #define MC_HUB_RDREQ_WTM_CNTL__GROUP2_DECREMENT__SHIFT 0x6 1963 #define MC_HUB_RDREQ_WTM_CNTL__GROUP3_DECREMENT_MASK 0xe00 1964 #define MC_HUB_RDREQ_WTM_CNTL__GROUP3_DECREMENT__SHIFT 0x9 1965 #define MC_HUB_RDREQ_WTM_CNTL__GROUP4_DECREMENT_MASK 0x7000 1966 #define MC_HUB_RDREQ_WTM_CNTL__GROUP4_DECREMENT__SHIFT 0xc 1967 #define MC_HUB_RDREQ_WTM_CNTL__GROUP5_DECREMENT_MASK 0x38000 1968 #define MC_HUB_RDREQ_WTM_CNTL__GROUP5_DECREMENT__SHIFT 0xf 1969 #define MC_HUB_RDREQ_WTM_CNTL__GROUP6_DECREMENT_MASK 0x1c0000 1970 #define MC_HUB_RDREQ_WTM_CNTL__GROUP6_DECREMENT__SHIFT 0x12 1971 #define MC_HUB_RDREQ_WTM_CNTL__GROUP7_DECREMENT_MASK 0xe00000 1972 #define MC_HUB_RDREQ_WTM_CNTL__GROUP7_DECREMENT__SHIFT 0x15 1973 #define MC_HUB_WDP_WTM_CNTL__GROUP0_DECREMENT_MASK 0x7 1974 #define MC_HUB_WDP_WTM_CNTL__GROUP0_DECREMENT__SHIFT 0x0 1975 #define MC_HUB_WDP_WTM_CNTL__GROUP1_DECREMENT_MASK 0x38 1976 #define MC_HUB_WDP_WTM_CNTL__GROUP1_DECREMENT__SHIFT 0x3 1977 #define MC_HUB_WDP_WTM_CNTL__GROUP2_DECREMENT_MASK 0x1c0 1978 #define MC_HUB_WDP_WTM_CNTL__GROUP2_DECREMENT__SHIFT 0x6 1979 #define MC_HUB_WDP_WTM_CNTL__GROUP3_DECREMENT_MASK 0xe00 1980 #define MC_HUB_WDP_WTM_CNTL__GROUP3_DECREMENT__SHIFT 0x9 1981 #define MC_HUB_WDP_WTM_CNTL__GROUP4_DECREMENT_MASK 0x7000 1982 #define MC_HUB_WDP_WTM_CNTL__GROUP4_DECREMENT__SHIFT 0xc 1983 #define MC_HUB_WDP_WTM_CNTL__GROUP5_DECREMENT_MASK 0x38000 1984 #define MC_HUB_WDP_WTM_CNTL__GROUP5_DECREMENT__SHIFT 0xf 1985 #define MC_HUB_WDP_WTM_CNTL__GROUP6_DECREMENT_MASK 0x1c0000 1986 #define MC_HUB_WDP_WTM_CNTL__GROUP6_DECREMENT__SHIFT 0x12 1987 #define MC_HUB_WDP_WTM_CNTL__GROUP7_DECREMENT_MASK 0xe00000 1988 #define MC_HUB_WDP_WTM_CNTL__GROUP7_DECREMENT__SHIFT 0x15 1989 #define MC_HUB_WDP_CREDITS__VM0_MASK 0xff 1990 #define MC_HUB_WDP_CREDITS__VM0__SHIFT 0x0 1991 #define MC_HUB_WDP_CREDITS__VM1_MASK 0xff00 1992 #define MC_HUB_WDP_CREDITS__VM1__SHIFT 0x8 1993 #define MC_HUB_WDP_CREDITS__STOR0_MASK 0xff0000 1994 #define MC_HUB_WDP_CREDITS__STOR0__SHIFT 0x10 1995 #define MC_HUB_WDP_CREDITS__STOR1_MASK 0xff000000 1996 #define MC_HUB_WDP_CREDITS__STOR1__SHIFT 0x18 1997 #define MC_HUB_WDP_CREDITS2__STOR0_PRI_MASK 0xff 1998 #define MC_HUB_WDP_CREDITS2__STOR0_PRI__SHIFT 0x0 1999 #define MC_HUB_WDP_CREDITS2__STOR1_PRI_MASK 0xff00 2000 #define MC_HUB_WDP_CREDITS2__STOR1_PRI__SHIFT 0x8 2001 #define MC_HUB_WDP_CREDITS2__VM2_MASK 0xff0000 2002 #define MC_HUB_WDP_CREDITS2__VM2__SHIFT 0x10 2003 #define MC_HUB_WDP_GBL0__MAXBURST_MASK 0xf 2004 #define MC_HUB_WDP_GBL0__MAXBURST__SHIFT 0x0 2005 #define MC_HUB_WDP_GBL0__LAZY_TIMER_MASK 0xf0 2006 #define MC_HUB_WDP_GBL0__LAZY_TIMER__SHIFT 0x4 2007 #define MC_HUB_WDP_GBL0__STALL_THRESHOLD_MASK 0xff00 2008 #define MC_HUB_WDP_GBL0__STALL_THRESHOLD__SHIFT 0x8 2009 #define MC_HUB_WDP_GBL0__STALL_MODE_MASK 0x10000 2010 #define MC_HUB_WDP_GBL0__STALL_MODE__SHIFT 0x10 2011 #define MC_HUB_WDP_GBL0__STALL_THRESHOLD_PRI_MASK 0x1fe0000 2012 #define MC_HUB_WDP_GBL0__STALL_THRESHOLD_PRI__SHIFT 0x11 2013 #define MC_HUB_WDP_GBL1__MAXBURST_MASK 0xf 2014 #define MC_HUB_WDP_GBL1__MAXBURST__SHIFT 0x0 2015 #define MC_HUB_WDP_GBL1__LAZY_TIMER_MASK 0xf0 2016 #define MC_HUB_WDP_GBL1__LAZY_TIMER__SHIFT 0x4 2017 #define MC_HUB_WDP_GBL1__STALL_THRESHOLD_MASK 0xff00 2018 #define MC_HUB_WDP_GBL1__STALL_THRESHOLD__SHIFT 0x8 2019 #define MC_HUB_WDP_GBL1__STALL_MODE_MASK 0x10000 2020 #define MC_HUB_WDP_GBL1__STALL_MODE__SHIFT 0x10 2021 #define MC_HUB_WDP_GBL1__STALL_THRESHOLD_PRI_MASK 0x1fe0000 2022 #define MC_HUB_WDP_GBL1__STALL_THRESHOLD_PRI__SHIFT 0x11 2023 #define MC_HUB_RDREQ_CREDITS__VM0_MASK 0xff 2024 #define MC_HUB_RDREQ_CREDITS__VM0__SHIFT 0x0 2025 #define MC_HUB_RDREQ_CREDITS__VM1_MASK 0xff00 2026 #define MC_HUB_RDREQ_CREDITS__VM1__SHIFT 0x8 2027 #define MC_HUB_RDREQ_CREDITS__STOR0_MASK 0xff0000 2028 #define MC_HUB_RDREQ_CREDITS__STOR0__SHIFT 0x10 2029 #define MC_HUB_RDREQ_CREDITS__STOR1_MASK 0xff000000 2030 #define MC_HUB_RDREQ_CREDITS__STOR1__SHIFT 0x18 2031 #define MC_HUB_RDREQ_CREDITS2__STOR0_PRI_MASK 0xff 2032 #define MC_HUB_RDREQ_CREDITS2__STOR0_PRI__SHIFT 0x0 2033 #define MC_HUB_RDREQ_CREDITS2__STOR1_PRI_MASK 0xff00 2034 #define MC_HUB_RDREQ_CREDITS2__STOR1_PRI__SHIFT 0x8 2035 #define MC_HUB_SHARED_DAGB_DLY__DLY_MASK 0x3f 2036 #define MC_HUB_SHARED_DAGB_DLY__DLY__SHIFT 0x0 2037 #define MC_HUB_SHARED_DAGB_DLY__CLI_MASK 0x3f0000 2038 #define MC_HUB_SHARED_DAGB_DLY__CLI__SHIFT 0x10 2039 #define MC_HUB_SHARED_DAGB_DLY__POS_MASK 0x1f000000 2040 #define MC_HUB_SHARED_DAGB_DLY__POS__SHIFT 0x18 2041 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_READ_MASK 0x1 2042 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_READ__SHIFT 0x0 2043 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_WRITE_MASK 0x2 2044 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_WRITE__SHIFT 0x1 2045 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_READ_MASK 0x4 2046 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_READ__SHIFT 0x2 2047 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_WRITE_MASK 0x8 2048 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_WRITE__SHIFT 0x3 2049 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA0_READ_MASK 0x10 2050 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA0_READ__SHIFT 0x4 2051 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA0_WRITE_MASK 0x20 2052 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA0_WRITE__SHIFT 0x5 2053 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA1_READ_MASK 0x40 2054 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA1_READ__SHIFT 0x6 2055 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA1_WRITE_MASK 0x80 2056 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA1_WRITE__SHIFT 0x7 2057 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_READ_MASK 0x100 2058 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_READ__SHIFT 0x8 2059 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_WRITE_MASK 0x200 2060 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_WRITE__SHIFT 0x9 2061 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_READ_MASK 0x400 2062 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_READ__SHIFT 0xa 2063 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_WRITE_MASK 0x800 2064 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_WRITE__SHIFT 0xb 2065 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_READ_MASK 0x1000 2066 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_READ__SHIFT 0xc 2067 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_WRITE_MASK 0x2000 2068 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_WRITE__SHIFT 0xd 2069 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_READ_MASK 0x4000 2070 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_READ__SHIFT 0xe 2071 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_WRITE_MASK 0x8000 2072 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_WRITE__SHIFT 0xf 2073 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_READ_MASK 0x10000 2074 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_READ__SHIFT 0x10 2075 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_WRITE_MASK 0x20000 2076 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_WRITE__SHIFT 0x11 2077 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_READ_MASK 0x40000 2078 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_READ__SHIFT 0x12 2079 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_WRITE_MASK 0x80000 2080 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_WRITE__SHIFT 0x13 2081 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_READ_MASK 0x100000 2082 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_READ__SHIFT 0x14 2083 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_WRITE_MASK 0x200000 2084 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_WRITE__SHIFT 0x15 2085 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ACP_READ_MASK 0x400000 2086 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ACP_READ__SHIFT 0x16 2087 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ACP_WRITE_MASK 0x800000 2088 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ACP_WRITE__SHIFT 0x17 2089 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SAMMSP_READ_MASK 0x1000000 2090 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SAMMSP_READ__SHIFT 0x18 2091 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SAMMSP_WRITE_MASK 0x2000000 2092 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SAMMSP_WRITE__SHIFT 0x19 2093 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_XDMA_READ_MASK 0x4000000 2094 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_XDMA_READ__SHIFT 0x1a 2095 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_XDMA_WRITE_MASK 0x8000000 2096 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_XDMA_WRITE__SHIFT 0x1b 2097 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ISP_READ_MASK 0x10000000 2098 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ISP_READ__SHIFT 0x1c 2099 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ISP_WRITE_MASK 0x20000000 2100 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ISP_WRITE__SHIFT 0x1d 2101 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VP8_READ_MASK 0x40000000 2102 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VP8_READ__SHIFT 0x1e 2103 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VP8_WRITE_MASK 0x80000000 2104 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VP8_WRITE__SHIFT 0x1f 2105 #define MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK 0x3 2106 #define MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT 0x0 2107 #define MC_HUB_RDREQ_DMIF_LIMIT__LIMIT_COUNT_MASK 0x7c 2108 #define MC_HUB_RDREQ_DMIF_LIMIT__LIMIT_COUNT__SHIFT 0x2 2109 #define MC_HUB_RDREQ_ACPG_LIMIT__ENABLE_MASK 0x3 2110 #define MC_HUB_RDREQ_ACPG_LIMIT__ENABLE__SHIFT 0x0 2111 #define MC_HUB_RDREQ_ACPG_LIMIT__LIMIT_COUNT_MASK 0x7c 2112 #define MC_HUB_RDREQ_ACPG_LIMIT__LIMIT_COUNT__SHIFT 0x2 2113 #define MC_HUB_WDP_BYPASS_GBL0__ENABLE_MASK 0x1 2114 #define MC_HUB_WDP_BYPASS_GBL0__ENABLE__SHIFT 0x0 2115 #define MC_HUB_WDP_BYPASS_GBL0__CID1_MASK 0x1fe 2116 #define MC_HUB_WDP_BYPASS_GBL0__CID1__SHIFT 0x1 2117 #define MC_HUB_WDP_BYPASS_GBL0__CID2_MASK 0x1fe00 2118 #define MC_HUB_WDP_BYPASS_GBL0__CID2__SHIFT 0x9 2119 #define MC_HUB_WDP_BYPASS_GBL0__HDP_PRIORITY_TIME_MASK 0xfe0000 2120 #define MC_HUB_WDP_BYPASS_GBL0__HDP_PRIORITY_TIME__SHIFT 0x11 2121 #define MC_HUB_WDP_BYPASS_GBL0__OTH_PRIORITY_TIME_MASK 0x7f000000 2122 #define MC_HUB_WDP_BYPASS_GBL0__OTH_PRIORITY_TIME__SHIFT 0x18 2123 #define MC_HUB_WDP_BYPASS_GBL1__ENABLE_MASK 0x1 2124 #define MC_HUB_WDP_BYPASS_GBL1__ENABLE__SHIFT 0x0 2125 #define MC_HUB_WDP_BYPASS_GBL1__CID1_MASK 0x1fe 2126 #define MC_HUB_WDP_BYPASS_GBL1__CID1__SHIFT 0x1 2127 #define MC_HUB_WDP_BYPASS_GBL1__CID2_MASK 0x1fe00 2128 #define MC_HUB_WDP_BYPASS_GBL1__CID2__SHIFT 0x9 2129 #define MC_HUB_WDP_BYPASS_GBL1__HDP_PRIORITY_TIME_MASK 0xfe0000 2130 #define MC_HUB_WDP_BYPASS_GBL1__HDP_PRIORITY_TIME__SHIFT 0x11 2131 #define MC_HUB_WDP_BYPASS_GBL1__OTH_PRIORITY_TIME_MASK 0x7f000000 2132 #define MC_HUB_WDP_BYPASS_GBL1__OTH_PRIORITY_TIME__SHIFT 0x18 2133 #define MC_HUB_RDREQ_BYPASS_GBL0__ENABLE_MASK 0x1 2134 #define MC_HUB_RDREQ_BYPASS_GBL0__ENABLE__SHIFT 0x0 2135 #define MC_HUB_RDREQ_BYPASS_GBL0__CID1_MASK 0x1fe 2136 #define MC_HUB_RDREQ_BYPASS_GBL0__CID1__SHIFT 0x1 2137 #define MC_HUB_RDREQ_BYPASS_GBL0__CID2_MASK 0x1fe00 2138 #define MC_HUB_RDREQ_BYPASS_GBL0__CID2__SHIFT 0x9 2139 #define MC_HUB_WDP_SH2__ENABLE_MASK 0x1 2140 #define MC_HUB_WDP_SH2__ENABLE__SHIFT 0x0 2141 #define MC_HUB_WDP_SH2__PRESCALE_MASK 0x6 2142 #define MC_HUB_WDP_SH2__PRESCALE__SHIFT 0x1 2143 #define MC_HUB_WDP_SH2__BLACKOUT_EXEMPT_MASK 0x8 2144 #define MC_HUB_WDP_SH2__BLACKOUT_EXEMPT__SHIFT 0x3 2145 #define MC_HUB_WDP_SH2__STALL_MODE_MASK 0x30 2146 #define MC_HUB_WDP_SH2__STALL_MODE__SHIFT 0x4 2147 #define MC_HUB_WDP_SH2__STALL_OVERRIDE_MASK 0x40 2148 #define MC_HUB_WDP_SH2__STALL_OVERRIDE__SHIFT 0x6 2149 #define MC_HUB_WDP_SH2__MAXBURST_MASK 0x780 2150 #define MC_HUB_WDP_SH2__MAXBURST__SHIFT 0x7 2151 #define MC_HUB_WDP_SH2__LAZY_TIMER_MASK 0x7800 2152 #define MC_HUB_WDP_SH2__LAZY_TIMER__SHIFT 0xb 2153 #define MC_HUB_WDP_SH2__STALL_OVERRIDE_WTM_MASK 0x8000 2154 #define MC_HUB_WDP_SH2__STALL_OVERRIDE_WTM__SHIFT 0xf 2155 #define MC_HUB_WDP_SH2__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 2156 #define MC_HUB_WDP_SH2__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 2157 #define MC_HUB_WDP_SH3__ENABLE_MASK 0x1 2158 #define MC_HUB_WDP_SH3__ENABLE__SHIFT 0x0 2159 #define MC_HUB_WDP_SH3__PRESCALE_MASK 0x6 2160 #define MC_HUB_WDP_SH3__PRESCALE__SHIFT 0x1 2161 #define MC_HUB_WDP_SH3__BLACKOUT_EXEMPT_MASK 0x8 2162 #define MC_HUB_WDP_SH3__BLACKOUT_EXEMPT__SHIFT 0x3 2163 #define MC_HUB_WDP_SH3__STALL_MODE_MASK 0x30 2164 #define MC_HUB_WDP_SH3__STALL_MODE__SHIFT 0x4 2165 #define MC_HUB_WDP_SH3__STALL_OVERRIDE_MASK 0x40 2166 #define MC_HUB_WDP_SH3__STALL_OVERRIDE__SHIFT 0x6 2167 #define MC_HUB_WDP_SH3__MAXBURST_MASK 0x780 2168 #define MC_HUB_WDP_SH3__MAXBURST__SHIFT 0x7 2169 #define MC_HUB_WDP_SH3__LAZY_TIMER_MASK 0x7800 2170 #define MC_HUB_WDP_SH3__LAZY_TIMER__SHIFT 0xb 2171 #define MC_HUB_WDP_SH3__STALL_OVERRIDE_WTM_MASK 0x8000 2172 #define MC_HUB_WDP_SH3__STALL_OVERRIDE_WTM__SHIFT 0xf 2173 #define MC_HUB_WDP_SH3__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 2174 #define MC_HUB_WDP_SH3__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 2175 #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_GFX_ATOMIC_MASK 0x1 2176 #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_GFX_ATOMIC__SHIFT 0x0 2177 #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_RLC_ATOMIC_MASK 0x2 2178 #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_RLC_ATOMIC__SHIFT 0x1 2179 #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_SDMA0_ATOMIC_MASK 0x4 2180 #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_SDMA0_ATOMIC__SHIFT 0x2 2181 #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_SDMA1_ATOMIC_MASK 0x8 2182 #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_SDMA1_ATOMIC__SHIFT 0x3 2183 #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_DISP_ATOMIC_MASK 0x10 2184 #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_DISP_ATOMIC__SHIFT 0x4 2185 #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_UVD_ATOMIC_MASK 0x20 2186 #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_UVD_ATOMIC__SHIFT 0x5 2187 #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_SMU_ATOMIC_MASK 0x40 2188 #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_SMU_ATOMIC__SHIFT 0x6 2189 #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_HDP_ATOMIC_MASK 0x80 2190 #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_HDP_ATOMIC__SHIFT 0x7 2191 #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_OTH_ATOMIC_MASK 0x100 2192 #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_OTH_ATOMIC__SHIFT 0x8 2193 #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VMC_ATOMIC_MASK 0x200 2194 #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VMC_ATOMIC__SHIFT 0x9 2195 #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VCE_ATOMIC_MASK 0x400 2196 #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VCE_ATOMIC__SHIFT 0xa 2197 #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_ACP_ATOMIC_MASK 0x800 2198 #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_ACP_ATOMIC__SHIFT 0xb 2199 #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_SAMMSP_ATOMIC_MASK 0x1000 2200 #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_SAMMSP_ATOMIC__SHIFT 0xc 2201 #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_XDMA_ATOMIC_MASK 0x2000 2202 #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_XDMA_ATOMIC__SHIFT 0xd 2203 #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_ISP_ATOMIC_MASK 0x4000 2204 #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_ISP_ATOMIC__SHIFT 0xe 2205 #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VP8_ATOMIC_MASK 0x8000 2206 #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VP8_ATOMIC__SHIFT 0xf 2207 #define MC_HUB_RDREQ_MCDW__ENABLE_MASK 0x1 2208 #define MC_HUB_RDREQ_MCDW__ENABLE__SHIFT 0x0 2209 #define MC_HUB_RDREQ_MCDW__BLACKOUT_EXEMPT_MASK 0x2 2210 #define MC_HUB_RDREQ_MCDW__BLACKOUT_EXEMPT__SHIFT 0x1 2211 #define MC_HUB_RDREQ_MCDW__BUS_MASK 0x4 2212 #define MC_HUB_RDREQ_MCDW__BUS__SHIFT 0x2 2213 #define MC_HUB_RDREQ_MCDW__MAXBURST_MASK 0x78 2214 #define MC_HUB_RDREQ_MCDW__MAXBURST__SHIFT 0x3 2215 #define MC_HUB_RDREQ_MCDW__LAZY_TIMER_MASK 0x780 2216 #define MC_HUB_RDREQ_MCDW__LAZY_TIMER__SHIFT 0x7 2217 #define MC_HUB_RDREQ_MCDW__ASK_CREDITS_MASK 0x3f800 2218 #define MC_HUB_RDREQ_MCDW__ASK_CREDITS__SHIFT 0xb 2219 #define MC_HUB_RDREQ_MCDW__DISPLAY_CREDITS_MASK 0x1fc0000 2220 #define MC_HUB_RDREQ_MCDW__DISPLAY_CREDITS__SHIFT 0x12 2221 #define MC_HUB_RDREQ_MCDW__MED_CREDITS_MASK 0xfe000000 2222 #define MC_HUB_RDREQ_MCDW__MED_CREDITS__SHIFT 0x19 2223 #define MC_HUB_RDREQ_MCDX__ENABLE_MASK 0x1 2224 #define MC_HUB_RDREQ_MCDX__ENABLE__SHIFT 0x0 2225 #define MC_HUB_RDREQ_MCDX__BLACKOUT_EXEMPT_MASK 0x2 2226 #define MC_HUB_RDREQ_MCDX__BLACKOUT_EXEMPT__SHIFT 0x1 2227 #define MC_HUB_RDREQ_MCDX__BUS_MASK 0x4 2228 #define MC_HUB_RDREQ_MCDX__BUS__SHIFT 0x2 2229 #define MC_HUB_RDREQ_MCDX__MAXBURST_MASK 0x78 2230 #define MC_HUB_RDREQ_MCDX__MAXBURST__SHIFT 0x3 2231 #define MC_HUB_RDREQ_MCDX__LAZY_TIMER_MASK 0x780 2232 #define MC_HUB_RDREQ_MCDX__LAZY_TIMER__SHIFT 0x7 2233 #define MC_HUB_RDREQ_MCDX__ASK_CREDITS_MASK 0x3f800 2234 #define MC_HUB_RDREQ_MCDX__ASK_CREDITS__SHIFT 0xb 2235 #define MC_HUB_RDREQ_MCDX__DISPLAY_CREDITS_MASK 0x1fc0000 2236 #define MC_HUB_RDREQ_MCDX__DISPLAY_CREDITS__SHIFT 0x12 2237 #define MC_HUB_RDREQ_MCDX__MED_CREDITS_MASK 0xfe000000 2238 #define MC_HUB_RDREQ_MCDX__MED_CREDITS__SHIFT 0x19 2239 #define MC_HUB_RDREQ_MCDY__ENABLE_MASK 0x1 2240 #define MC_HUB_RDREQ_MCDY__ENABLE__SHIFT 0x0 2241 #define MC_HUB_RDREQ_MCDY__BLACKOUT_EXEMPT_MASK 0x2 2242 #define MC_HUB_RDREQ_MCDY__BLACKOUT_EXEMPT__SHIFT 0x1 2243 #define MC_HUB_RDREQ_MCDY__BUS_MASK 0x4 2244 #define MC_HUB_RDREQ_MCDY__BUS__SHIFT 0x2 2245 #define MC_HUB_RDREQ_MCDY__MAXBURST_MASK 0x78 2246 #define MC_HUB_RDREQ_MCDY__MAXBURST__SHIFT 0x3 2247 #define MC_HUB_RDREQ_MCDY__LAZY_TIMER_MASK 0x780 2248 #define MC_HUB_RDREQ_MCDY__LAZY_TIMER__SHIFT 0x7 2249 #define MC_HUB_RDREQ_MCDY__ASK_CREDITS_MASK 0x3f800 2250 #define MC_HUB_RDREQ_MCDY__ASK_CREDITS__SHIFT 0xb 2251 #define MC_HUB_RDREQ_MCDY__DISPLAY_CREDITS_MASK 0x1fc0000 2252 #define MC_HUB_RDREQ_MCDY__DISPLAY_CREDITS__SHIFT 0x12 2253 #define MC_HUB_RDREQ_MCDY__MED_CREDITS_MASK 0xfe000000 2254 #define MC_HUB_RDREQ_MCDY__MED_CREDITS__SHIFT 0x19 2255 #define MC_HUB_RDREQ_MCDZ__ENABLE_MASK 0x1 2256 #define MC_HUB_RDREQ_MCDZ__ENABLE__SHIFT 0x0 2257 #define MC_HUB_RDREQ_MCDZ__BLACKOUT_EXEMPT_MASK 0x2 2258 #define MC_HUB_RDREQ_MCDZ__BLACKOUT_EXEMPT__SHIFT 0x1 2259 #define MC_HUB_RDREQ_MCDZ__BUS_MASK 0x4 2260 #define MC_HUB_RDREQ_MCDZ__BUS__SHIFT 0x2 2261 #define MC_HUB_RDREQ_MCDZ__MAXBURST_MASK 0x78 2262 #define MC_HUB_RDREQ_MCDZ__MAXBURST__SHIFT 0x3 2263 #define MC_HUB_RDREQ_MCDZ__LAZY_TIMER_MASK 0x780 2264 #define MC_HUB_RDREQ_MCDZ__LAZY_TIMER__SHIFT 0x7 2265 #define MC_HUB_RDREQ_MCDZ__ASK_CREDITS_MASK 0x3f800 2266 #define MC_HUB_RDREQ_MCDZ__ASK_CREDITS__SHIFT 0xb 2267 #define MC_HUB_RDREQ_MCDZ__DISPLAY_CREDITS_MASK 0x1fc0000 2268 #define MC_HUB_RDREQ_MCDZ__DISPLAY_CREDITS__SHIFT 0x12 2269 #define MC_HUB_RDREQ_MCDZ__MED_CREDITS_MASK 0xfe000000 2270 #define MC_HUB_RDREQ_MCDZ__MED_CREDITS__SHIFT 0x19 2271 #define MC_HUB_RDREQ_SIP__ASK_CREDITS_MASK 0x7f 2272 #define MC_HUB_RDREQ_SIP__ASK_CREDITS__SHIFT 0x0 2273 #define MC_HUB_RDREQ_SIP__MED_CREDIT_SEL_MASK 0x80 2274 #define MC_HUB_RDREQ_SIP__MED_CREDIT_SEL__SHIFT 0x7 2275 #define MC_HUB_RDREQ_SIP__DISPLAY_CREDITS_MASK 0x7f00 2276 #define MC_HUB_RDREQ_SIP__DISPLAY_CREDITS__SHIFT 0x8 2277 #define MC_HUB_RDREQ_GBL0__STALL_THRESHOLD_MASK 0xff 2278 #define MC_HUB_RDREQ_GBL0__STALL_THRESHOLD__SHIFT 0x0 2279 #define MC_HUB_RDREQ_GBL0__STALL_THRESHOLD_PRI_MASK 0xff00 2280 #define MC_HUB_RDREQ_GBL0__STALL_THRESHOLD_PRI__SHIFT 0x8 2281 #define MC_HUB_RDREQ_GBL1__STALL_THRESHOLD_MASK 0xff 2282 #define MC_HUB_RDREQ_GBL1__STALL_THRESHOLD__SHIFT 0x0 2283 #define MC_HUB_RDREQ_GBL1__STALL_THRESHOLD_PRI_MASK 0xff00 2284 #define MC_HUB_RDREQ_GBL1__STALL_THRESHOLD_PRI__SHIFT 0x8 2285 #define MC_HUB_RDREQ_SMU__ENABLE_MASK 0x1 2286 #define MC_HUB_RDREQ_SMU__ENABLE__SHIFT 0x0 2287 #define MC_HUB_RDREQ_SMU__PRESCALE_MASK 0x6 2288 #define MC_HUB_RDREQ_SMU__PRESCALE__SHIFT 0x1 2289 #define MC_HUB_RDREQ_SMU__BLACKOUT_EXEMPT_MASK 0x8 2290 #define MC_HUB_RDREQ_SMU__BLACKOUT_EXEMPT__SHIFT 0x3 2291 #define MC_HUB_RDREQ_SMU__STALL_MODE_MASK 0x30 2292 #define MC_HUB_RDREQ_SMU__STALL_MODE__SHIFT 0x4 2293 #define MC_HUB_RDREQ_SMU__STALL_OVERRIDE_MASK 0x40 2294 #define MC_HUB_RDREQ_SMU__STALL_OVERRIDE__SHIFT 0x6 2295 #define MC_HUB_RDREQ_SMU__MAXBURST_MASK 0x780 2296 #define MC_HUB_RDREQ_SMU__MAXBURST__SHIFT 0x7 2297 #define MC_HUB_RDREQ_SMU__LAZY_TIMER_MASK 0x7800 2298 #define MC_HUB_RDREQ_SMU__LAZY_TIMER__SHIFT 0xb 2299 #define MC_HUB_RDREQ_SMU__STALL_OVERRIDE_WTM_MASK 0x8000 2300 #define MC_HUB_RDREQ_SMU__STALL_OVERRIDE_WTM__SHIFT 0xf 2301 #define MC_HUB_RDREQ_SMU__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 2302 #define MC_HUB_RDREQ_SMU__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 2303 #define MC_HUB_RDREQ_SDMA0__ENABLE_MASK 0x1 2304 #define MC_HUB_RDREQ_SDMA0__ENABLE__SHIFT 0x0 2305 #define MC_HUB_RDREQ_SDMA0__PRESCALE_MASK 0x6 2306 #define MC_HUB_RDREQ_SDMA0__PRESCALE__SHIFT 0x1 2307 #define MC_HUB_RDREQ_SDMA0__BLACKOUT_EXEMPT_MASK 0x8 2308 #define MC_HUB_RDREQ_SDMA0__BLACKOUT_EXEMPT__SHIFT 0x3 2309 #define MC_HUB_RDREQ_SDMA0__STALL_MODE_MASK 0x30 2310 #define MC_HUB_RDREQ_SDMA0__STALL_MODE__SHIFT 0x4 2311 #define MC_HUB_RDREQ_SDMA0__STALL_OVERRIDE_MASK 0x40 2312 #define MC_HUB_RDREQ_SDMA0__STALL_OVERRIDE__SHIFT 0x6 2313 #define MC_HUB_RDREQ_SDMA0__MAXBURST_MASK 0x780 2314 #define MC_HUB_RDREQ_SDMA0__MAXBURST__SHIFT 0x7 2315 #define MC_HUB_RDREQ_SDMA0__LAZY_TIMER_MASK 0x7800 2316 #define MC_HUB_RDREQ_SDMA0__LAZY_TIMER__SHIFT 0xb 2317 #define MC_HUB_RDREQ_SDMA0__STALL_OVERRIDE_WTM_MASK 0x8000 2318 #define MC_HUB_RDREQ_SDMA0__STALL_OVERRIDE_WTM__SHIFT 0xf 2319 #define MC_HUB_RDREQ_SDMA0__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 2320 #define MC_HUB_RDREQ_SDMA0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 2321 #define MC_HUB_RDREQ_HDP__ENABLE_MASK 0x1 2322 #define MC_HUB_RDREQ_HDP__ENABLE__SHIFT 0x0 2323 #define MC_HUB_RDREQ_HDP__PRESCALE_MASK 0x6 2324 #define MC_HUB_RDREQ_HDP__PRESCALE__SHIFT 0x1 2325 #define MC_HUB_RDREQ_HDP__BLACKOUT_EXEMPT_MASK 0x8 2326 #define MC_HUB_RDREQ_HDP__BLACKOUT_EXEMPT__SHIFT 0x3 2327 #define MC_HUB_RDREQ_HDP__STALL_MODE_MASK 0x30 2328 #define MC_HUB_RDREQ_HDP__STALL_MODE__SHIFT 0x4 2329 #define MC_HUB_RDREQ_HDP__STALL_OVERRIDE_MASK 0x40 2330 #define MC_HUB_RDREQ_HDP__STALL_OVERRIDE__SHIFT 0x6 2331 #define MC_HUB_RDREQ_HDP__MAXBURST_MASK 0x780 2332 #define MC_HUB_RDREQ_HDP__MAXBURST__SHIFT 0x7 2333 #define MC_HUB_RDREQ_HDP__LAZY_TIMER_MASK 0x7800 2334 #define MC_HUB_RDREQ_HDP__LAZY_TIMER__SHIFT 0xb 2335 #define MC_HUB_RDREQ_HDP__STALL_OVERRIDE_WTM_MASK 0x8000 2336 #define MC_HUB_RDREQ_HDP__STALL_OVERRIDE_WTM__SHIFT 0xf 2337 #define MC_HUB_RDREQ_HDP__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 2338 #define MC_HUB_RDREQ_HDP__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 2339 #define MC_HUB_RDREQ_SDMA1__ENABLE_MASK 0x1 2340 #define MC_HUB_RDREQ_SDMA1__ENABLE__SHIFT 0x0 2341 #define MC_HUB_RDREQ_SDMA1__PRESCALE_MASK 0x6 2342 #define MC_HUB_RDREQ_SDMA1__PRESCALE__SHIFT 0x1 2343 #define MC_HUB_RDREQ_SDMA1__BLACKOUT_EXEMPT_MASK 0x8 2344 #define MC_HUB_RDREQ_SDMA1__BLACKOUT_EXEMPT__SHIFT 0x3 2345 #define MC_HUB_RDREQ_SDMA1__STALL_MODE_MASK 0x30 2346 #define MC_HUB_RDREQ_SDMA1__STALL_MODE__SHIFT 0x4 2347 #define MC_HUB_RDREQ_SDMA1__STALL_OVERRIDE_MASK 0x40 2348 #define MC_HUB_RDREQ_SDMA1__STALL_OVERRIDE__SHIFT 0x6 2349 #define MC_HUB_RDREQ_SDMA1__MAXBURST_MASK 0x780 2350 #define MC_HUB_RDREQ_SDMA1__MAXBURST__SHIFT 0x7 2351 #define MC_HUB_RDREQ_SDMA1__LAZY_TIMER_MASK 0x7800 2352 #define MC_HUB_RDREQ_SDMA1__LAZY_TIMER__SHIFT 0xb 2353 #define MC_HUB_RDREQ_SDMA1__STALL_OVERRIDE_WTM_MASK 0x8000 2354 #define MC_HUB_RDREQ_SDMA1__STALL_OVERRIDE_WTM__SHIFT 0xf 2355 #define MC_HUB_RDREQ_SDMA1__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 2356 #define MC_HUB_RDREQ_SDMA1__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 2357 #define MC_HUB_RDREQ_RLC__ENABLE_MASK 0x1 2358 #define MC_HUB_RDREQ_RLC__ENABLE__SHIFT 0x0 2359 #define MC_HUB_RDREQ_RLC__PRESCALE_MASK 0x6 2360 #define MC_HUB_RDREQ_RLC__PRESCALE__SHIFT 0x1 2361 #define MC_HUB_RDREQ_RLC__BLACKOUT_EXEMPT_MASK 0x8 2362 #define MC_HUB_RDREQ_RLC__BLACKOUT_EXEMPT__SHIFT 0x3 2363 #define MC_HUB_RDREQ_RLC__STALL_MODE_MASK 0x30 2364 #define MC_HUB_RDREQ_RLC__STALL_MODE__SHIFT 0x4 2365 #define MC_HUB_RDREQ_RLC__STALL_OVERRIDE_MASK 0x40 2366 #define MC_HUB_RDREQ_RLC__STALL_OVERRIDE__SHIFT 0x6 2367 #define MC_HUB_RDREQ_RLC__MAXBURST_MASK 0x780 2368 #define MC_HUB_RDREQ_RLC__MAXBURST__SHIFT 0x7 2369 #define MC_HUB_RDREQ_RLC__LAZY_TIMER_MASK 0x7800 2370 #define MC_HUB_RDREQ_RLC__LAZY_TIMER__SHIFT 0xb 2371 #define MC_HUB_RDREQ_RLC__STALL_OVERRIDE_WTM_MASK 0x8000 2372 #define MC_HUB_RDREQ_RLC__STALL_OVERRIDE_WTM__SHIFT 0xf 2373 #define MC_HUB_RDREQ_RLC__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 2374 #define MC_HUB_RDREQ_RLC__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 2375 #define MC_HUB_RDREQ_SEM__ENABLE_MASK 0x1 2376 #define MC_HUB_RDREQ_SEM__ENABLE__SHIFT 0x0 2377 #define MC_HUB_RDREQ_SEM__PRESCALE_MASK 0x6 2378 #define MC_HUB_RDREQ_SEM__PRESCALE__SHIFT 0x1 2379 #define MC_HUB_RDREQ_SEM__BLACKOUT_EXEMPT_MASK 0x8 2380 #define MC_HUB_RDREQ_SEM__BLACKOUT_EXEMPT__SHIFT 0x3 2381 #define MC_HUB_RDREQ_SEM__STALL_MODE_MASK 0x30 2382 #define MC_HUB_RDREQ_SEM__STALL_MODE__SHIFT 0x4 2383 #define MC_HUB_RDREQ_SEM__STALL_OVERRIDE_MASK 0x40 2384 #define MC_HUB_RDREQ_SEM__STALL_OVERRIDE__SHIFT 0x6 2385 #define MC_HUB_RDREQ_SEM__MAXBURST_MASK 0x780 2386 #define MC_HUB_RDREQ_SEM__MAXBURST__SHIFT 0x7 2387 #define MC_HUB_RDREQ_SEM__LAZY_TIMER_MASK 0x7800 2388 #define MC_HUB_RDREQ_SEM__LAZY_TIMER__SHIFT 0xb 2389 #define MC_HUB_RDREQ_SEM__STALL_OVERRIDE_WTM_MASK 0x8000 2390 #define MC_HUB_RDREQ_SEM__STALL_OVERRIDE_WTM__SHIFT 0xf 2391 #define MC_HUB_RDREQ_SEM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 2392 #define MC_HUB_RDREQ_SEM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 2393 #define MC_HUB_RDREQ_VCE0__ENABLE_MASK 0x1 2394 #define MC_HUB_RDREQ_VCE0__ENABLE__SHIFT 0x0 2395 #define MC_HUB_RDREQ_VCE0__PRESCALE_MASK 0x6 2396 #define MC_HUB_RDREQ_VCE0__PRESCALE__SHIFT 0x1 2397 #define MC_HUB_RDREQ_VCE0__BLACKOUT_EXEMPT_MASK 0x8 2398 #define MC_HUB_RDREQ_VCE0__BLACKOUT_EXEMPT__SHIFT 0x3 2399 #define MC_HUB_RDREQ_VCE0__STALL_MODE_MASK 0x30 2400 #define MC_HUB_RDREQ_VCE0__STALL_MODE__SHIFT 0x4 2401 #define MC_HUB_RDREQ_VCE0__STALL_OVERRIDE_MASK 0x40 2402 #define MC_HUB_RDREQ_VCE0__STALL_OVERRIDE__SHIFT 0x6 2403 #define MC_HUB_RDREQ_VCE0__MAXBURST_MASK 0x780 2404 #define MC_HUB_RDREQ_VCE0__MAXBURST__SHIFT 0x7 2405 #define MC_HUB_RDREQ_VCE0__LAZY_TIMER_MASK 0x7800 2406 #define MC_HUB_RDREQ_VCE0__LAZY_TIMER__SHIFT 0xb 2407 #define MC_HUB_RDREQ_VCE0__STALL_OVERRIDE_WTM_MASK 0x8000 2408 #define MC_HUB_RDREQ_VCE0__STALL_OVERRIDE_WTM__SHIFT 0xf 2409 #define MC_HUB_RDREQ_VCE0__VM_BYPASS_MASK 0x10000 2410 #define MC_HUB_RDREQ_VCE0__VM_BYPASS__SHIFT 0x10 2411 #define MC_HUB_RDREQ_VCE0__BYPASS_AVAIL_OVERRIDE_MASK 0x20000 2412 #define MC_HUB_RDREQ_VCE0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11 2413 #define MC_HUB_RDREQ_UMC__ENABLE_MASK 0x1 2414 #define MC_HUB_RDREQ_UMC__ENABLE__SHIFT 0x0 2415 #define MC_HUB_RDREQ_UMC__PRESCALE_MASK 0x6 2416 #define MC_HUB_RDREQ_UMC__PRESCALE__SHIFT 0x1 2417 #define MC_HUB_RDREQ_UMC__BLACKOUT_EXEMPT_MASK 0x8 2418 #define MC_HUB_RDREQ_UMC__BLACKOUT_EXEMPT__SHIFT 0x3 2419 #define MC_HUB_RDREQ_UMC__STALL_MODE_MASK 0x30 2420 #define MC_HUB_RDREQ_UMC__STALL_MODE__SHIFT 0x4 2421 #define MC_HUB_RDREQ_UMC__STALL_OVERRIDE_MASK 0x40 2422 #define MC_HUB_RDREQ_UMC__STALL_OVERRIDE__SHIFT 0x6 2423 #define MC_HUB_RDREQ_UMC__MAXBURST_MASK 0x780 2424 #define MC_HUB_RDREQ_UMC__MAXBURST__SHIFT 0x7 2425 #define MC_HUB_RDREQ_UMC__LAZY_TIMER_MASK 0x7800 2426 #define MC_HUB_RDREQ_UMC__LAZY_TIMER__SHIFT 0xb 2427 #define MC_HUB_RDREQ_UMC__STALL_OVERRIDE_WTM_MASK 0x8000 2428 #define MC_HUB_RDREQ_UMC__STALL_OVERRIDE_WTM__SHIFT 0xf 2429 #define MC_HUB_RDREQ_UMC__VM_BYPASS_MASK 0x10000 2430 #define MC_HUB_RDREQ_UMC__VM_BYPASS__SHIFT 0x10 2431 #define MC_HUB_RDREQ_UMC__BYPASS_AVAIL_OVERRIDE_MASK 0x20000 2432 #define MC_HUB_RDREQ_UMC__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11 2433 #define MC_HUB_RDREQ_UVD__ENABLE_MASK 0x1 2434 #define MC_HUB_RDREQ_UVD__ENABLE__SHIFT 0x0 2435 #define MC_HUB_RDREQ_UVD__PRESCALE_MASK 0x6 2436 #define MC_HUB_RDREQ_UVD__PRESCALE__SHIFT 0x1 2437 #define MC_HUB_RDREQ_UVD__BLACKOUT_EXEMPT_MASK 0x8 2438 #define MC_HUB_RDREQ_UVD__BLACKOUT_EXEMPT__SHIFT 0x3 2439 #define MC_HUB_RDREQ_UVD__STALL_MODE_MASK 0x30 2440 #define MC_HUB_RDREQ_UVD__STALL_MODE__SHIFT 0x4 2441 #define MC_HUB_RDREQ_UVD__STALL_OVERRIDE_MASK 0x40 2442 #define MC_HUB_RDREQ_UVD__STALL_OVERRIDE__SHIFT 0x6 2443 #define MC_HUB_RDREQ_UVD__MAXBURST_MASK 0x780 2444 #define MC_HUB_RDREQ_UVD__MAXBURST__SHIFT 0x7 2445 #define MC_HUB_RDREQ_UVD__LAZY_TIMER_MASK 0x7800 2446 #define MC_HUB_RDREQ_UVD__LAZY_TIMER__SHIFT 0xb 2447 #define MC_HUB_RDREQ_UVD__STALL_OVERRIDE_WTM_MASK 0x8000 2448 #define MC_HUB_RDREQ_UVD__STALL_OVERRIDE_WTM__SHIFT 0xf 2449 #define MC_HUB_RDREQ_UVD__VM_BYPASS_MASK 0x10000 2450 #define MC_HUB_RDREQ_UVD__VM_BYPASS__SHIFT 0x10 2451 #define MC_HUB_RDREQ_UVD__BYPASS_AVAIL_OVERRIDE_MASK 0x20000 2452 #define MC_HUB_RDREQ_UVD__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11 2453 #define MC_HUB_RDREQ_DMIF__ENABLE_MASK 0x1 2454 #define MC_HUB_RDREQ_DMIF__ENABLE__SHIFT 0x0 2455 #define MC_HUB_RDREQ_DMIF__PRESCALE_MASK 0x6 2456 #define MC_HUB_RDREQ_DMIF__PRESCALE__SHIFT 0x1 2457 #define MC_HUB_RDREQ_DMIF__BLACKOUT_EXEMPT_MASK 0x8 2458 #define MC_HUB_RDREQ_DMIF__BLACKOUT_EXEMPT__SHIFT 0x3 2459 #define MC_HUB_RDREQ_DMIF__STALL_MODE_MASK 0x30 2460 #define MC_HUB_RDREQ_DMIF__STALL_MODE__SHIFT 0x4 2461 #define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE_MASK 0x40 2462 #define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE__SHIFT 0x6 2463 #define MC_HUB_RDREQ_DMIF__MAXBURST_MASK 0x780 2464 #define MC_HUB_RDREQ_DMIF__MAXBURST__SHIFT 0x7 2465 #define MC_HUB_RDREQ_DMIF__LAZY_TIMER_MASK 0x7800 2466 #define MC_HUB_RDREQ_DMIF__LAZY_TIMER__SHIFT 0xb 2467 #define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE_WTM_MASK 0x8000 2468 #define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE_WTM__SHIFT 0xf 2469 #define MC_HUB_RDREQ_DMIF__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 2470 #define MC_HUB_RDREQ_DMIF__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 2471 #define MC_HUB_RDREQ_MCIF__ENABLE_MASK 0x1 2472 #define MC_HUB_RDREQ_MCIF__ENABLE__SHIFT 0x0 2473 #define MC_HUB_RDREQ_MCIF__PRESCALE_MASK 0x6 2474 #define MC_HUB_RDREQ_MCIF__PRESCALE__SHIFT 0x1 2475 #define MC_HUB_RDREQ_MCIF__BLACKOUT_EXEMPT_MASK 0x8 2476 #define MC_HUB_RDREQ_MCIF__BLACKOUT_EXEMPT__SHIFT 0x3 2477 #define MC_HUB_RDREQ_MCIF__STALL_MODE_MASK 0x30 2478 #define MC_HUB_RDREQ_MCIF__STALL_MODE__SHIFT 0x4 2479 #define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE_MASK 0x40 2480 #define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE__SHIFT 0x6 2481 #define MC_HUB_RDREQ_MCIF__MAXBURST_MASK 0x780 2482 #define MC_HUB_RDREQ_MCIF__MAXBURST__SHIFT 0x7 2483 #define MC_HUB_RDREQ_MCIF__LAZY_TIMER_MASK 0x7800 2484 #define MC_HUB_RDREQ_MCIF__LAZY_TIMER__SHIFT 0xb 2485 #define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE_WTM_MASK 0x8000 2486 #define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE_WTM__SHIFT 0xf 2487 #define MC_HUB_RDREQ_MCIF__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 2488 #define MC_HUB_RDREQ_MCIF__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 2489 #define MC_HUB_RDREQ_VMC__ENABLE_MASK 0x1 2490 #define MC_HUB_RDREQ_VMC__ENABLE__SHIFT 0x0 2491 #define MC_HUB_RDREQ_VMC__PRESCALE_MASK 0x6 2492 #define MC_HUB_RDREQ_VMC__PRESCALE__SHIFT 0x1 2493 #define MC_HUB_RDREQ_VMC__BLACKOUT_EXEMPT_MASK 0x8 2494 #define MC_HUB_RDREQ_VMC__BLACKOUT_EXEMPT__SHIFT 0x3 2495 #define MC_HUB_RDREQ_VMC__STALL_MODE_MASK 0x30 2496 #define MC_HUB_RDREQ_VMC__STALL_MODE__SHIFT 0x4 2497 #define MC_HUB_RDREQ_VMC__STALL_OVERRIDE_MASK 0x40 2498 #define MC_HUB_RDREQ_VMC__STALL_OVERRIDE__SHIFT 0x6 2499 #define MC_HUB_RDREQ_VMC__MAXBURST_MASK 0x780 2500 #define MC_HUB_RDREQ_VMC__MAXBURST__SHIFT 0x7 2501 #define MC_HUB_RDREQ_VMC__LAZY_TIMER_MASK 0x7800 2502 #define MC_HUB_RDREQ_VMC__LAZY_TIMER__SHIFT 0xb 2503 #define MC_HUB_RDREQ_VMC__STALL_OVERRIDE_WTM_MASK 0x8000 2504 #define MC_HUB_RDREQ_VMC__STALL_OVERRIDE_WTM__SHIFT 0xf 2505 #define MC_HUB_RDREQ_VMC__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 2506 #define MC_HUB_RDREQ_VMC__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 2507 #define MC_HUB_RDREQ_VCEU0__ENABLE_MASK 0x1 2508 #define MC_HUB_RDREQ_VCEU0__ENABLE__SHIFT 0x0 2509 #define MC_HUB_RDREQ_VCEU0__PRESCALE_MASK 0x6 2510 #define MC_HUB_RDREQ_VCEU0__PRESCALE__SHIFT 0x1 2511 #define MC_HUB_RDREQ_VCEU0__BLACKOUT_EXEMPT_MASK 0x8 2512 #define MC_HUB_RDREQ_VCEU0__BLACKOUT_EXEMPT__SHIFT 0x3 2513 #define MC_HUB_RDREQ_VCEU0__STALL_MODE_MASK 0x30 2514 #define MC_HUB_RDREQ_VCEU0__STALL_MODE__SHIFT 0x4 2515 #define MC_HUB_RDREQ_VCEU0__STALL_OVERRIDE_MASK 0x40 2516 #define MC_HUB_RDREQ_VCEU0__STALL_OVERRIDE__SHIFT 0x6 2517 #define MC_HUB_RDREQ_VCEU0__MAXBURST_MASK 0x780 2518 #define MC_HUB_RDREQ_VCEU0__MAXBURST__SHIFT 0x7 2519 #define MC_HUB_RDREQ_VCEU0__LAZY_TIMER_MASK 0x7800 2520 #define MC_HUB_RDREQ_VCEU0__LAZY_TIMER__SHIFT 0xb 2521 #define MC_HUB_RDREQ_VCEU0__STALL_OVERRIDE_WTM_MASK 0x8000 2522 #define MC_HUB_RDREQ_VCEU0__STALL_OVERRIDE_WTM__SHIFT 0xf 2523 #define MC_HUB_RDREQ_VCEU0__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 2524 #define MC_HUB_RDREQ_VCEU0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 2525 #define MC_HUB_WDP_MCDW__ENABLE_MASK 0x1 2526 #define MC_HUB_WDP_MCDW__ENABLE__SHIFT 0x0 2527 #define MC_HUB_WDP_MCDW__BLACKOUT_EXEMPT_MASK 0x2 2528 #define MC_HUB_WDP_MCDW__BLACKOUT_EXEMPT__SHIFT 0x1 2529 #define MC_HUB_WDP_MCDW__STALL_MODE_MASK 0x4 2530 #define MC_HUB_WDP_MCDW__STALL_MODE__SHIFT 0x2 2531 #define MC_HUB_WDP_MCDW__MAXBURST_MASK 0x78 2532 #define MC_HUB_WDP_MCDW__MAXBURST__SHIFT 0x3 2533 #define MC_HUB_WDP_MCDW__ASK_CREDITS_MASK 0x1f80 2534 #define MC_HUB_WDP_MCDW__ASK_CREDITS__SHIFT 0x7 2535 #define MC_HUB_WDP_MCDW__LAZY_TIMER_MASK 0x1e000 2536 #define MC_HUB_WDP_MCDW__LAZY_TIMER__SHIFT 0xd 2537 #define MC_HUB_WDP_MCDW__STALL_THRESHOLD_MASK 0xfe0000 2538 #define MC_HUB_WDP_MCDW__STALL_THRESHOLD__SHIFT 0x11 2539 #define MC_HUB_WDP_MCDW__ASK_CREDITS_W_MASK 0x7f000000 2540 #define MC_HUB_WDP_MCDW__ASK_CREDITS_W__SHIFT 0x18 2541 #define MC_HUB_WDP_MCDX__ENABLE_MASK 0x1 2542 #define MC_HUB_WDP_MCDX__ENABLE__SHIFT 0x0 2543 #define MC_HUB_WDP_MCDX__BLACKOUT_EXEMPT_MASK 0x2 2544 #define MC_HUB_WDP_MCDX__BLACKOUT_EXEMPT__SHIFT 0x1 2545 #define MC_HUB_WDP_MCDX__STALL_MODE_MASK 0x4 2546 #define MC_HUB_WDP_MCDX__STALL_MODE__SHIFT 0x2 2547 #define MC_HUB_WDP_MCDX__MAXBURST_MASK 0x78 2548 #define MC_HUB_WDP_MCDX__MAXBURST__SHIFT 0x3 2549 #define MC_HUB_WDP_MCDX__ASK_CREDITS_MASK 0x1f80 2550 #define MC_HUB_WDP_MCDX__ASK_CREDITS__SHIFT 0x7 2551 #define MC_HUB_WDP_MCDX__LAZY_TIMER_MASK 0x1e000 2552 #define MC_HUB_WDP_MCDX__LAZY_TIMER__SHIFT 0xd 2553 #define MC_HUB_WDP_MCDX__STALL_THRESHOLD_MASK 0xfe0000 2554 #define MC_HUB_WDP_MCDX__STALL_THRESHOLD__SHIFT 0x11 2555 #define MC_HUB_WDP_MCDX__ASK_CREDITS_W_MASK 0x7f000000 2556 #define MC_HUB_WDP_MCDX__ASK_CREDITS_W__SHIFT 0x18 2557 #define MC_HUB_WDP_MCDY__ENABLE_MASK 0x1 2558 #define MC_HUB_WDP_MCDY__ENABLE__SHIFT 0x0 2559 #define MC_HUB_WDP_MCDY__BLACKOUT_EXEMPT_MASK 0x2 2560 #define MC_HUB_WDP_MCDY__BLACKOUT_EXEMPT__SHIFT 0x1 2561 #define MC_HUB_WDP_MCDY__STALL_MODE_MASK 0x4 2562 #define MC_HUB_WDP_MCDY__STALL_MODE__SHIFT 0x2 2563 #define MC_HUB_WDP_MCDY__MAXBURST_MASK 0x78 2564 #define MC_HUB_WDP_MCDY__MAXBURST__SHIFT 0x3 2565 #define MC_HUB_WDP_MCDY__ASK_CREDITS_MASK 0x1f80 2566 #define MC_HUB_WDP_MCDY__ASK_CREDITS__SHIFT 0x7 2567 #define MC_HUB_WDP_MCDY__LAZY_TIMER_MASK 0x1e000 2568 #define MC_HUB_WDP_MCDY__LAZY_TIMER__SHIFT 0xd 2569 #define MC_HUB_WDP_MCDY__STALL_THRESHOLD_MASK 0xfe0000 2570 #define MC_HUB_WDP_MCDY__STALL_THRESHOLD__SHIFT 0x11 2571 #define MC_HUB_WDP_MCDY__ASK_CREDITS_W_MASK 0x7f000000 2572 #define MC_HUB_WDP_MCDY__ASK_CREDITS_W__SHIFT 0x18 2573 #define MC_HUB_WDP_MCDZ__ENABLE_MASK 0x1 2574 #define MC_HUB_WDP_MCDZ__ENABLE__SHIFT 0x0 2575 #define MC_HUB_WDP_MCDZ__BLACKOUT_EXEMPT_MASK 0x2 2576 #define MC_HUB_WDP_MCDZ__BLACKOUT_EXEMPT__SHIFT 0x1 2577 #define MC_HUB_WDP_MCDZ__STALL_MODE_MASK 0x4 2578 #define MC_HUB_WDP_MCDZ__STALL_MODE__SHIFT 0x2 2579 #define MC_HUB_WDP_MCDZ__MAXBURST_MASK 0x78 2580 #define MC_HUB_WDP_MCDZ__MAXBURST__SHIFT 0x3 2581 #define MC_HUB_WDP_MCDZ__ASK_CREDITS_MASK 0x1f80 2582 #define MC_HUB_WDP_MCDZ__ASK_CREDITS__SHIFT 0x7 2583 #define MC_HUB_WDP_MCDZ__LAZY_TIMER_MASK 0x1e000 2584 #define MC_HUB_WDP_MCDZ__LAZY_TIMER__SHIFT 0xd 2585 #define MC_HUB_WDP_MCDZ__STALL_THRESHOLD_MASK 0xfe0000 2586 #define MC_HUB_WDP_MCDZ__STALL_THRESHOLD__SHIFT 0x11 2587 #define MC_HUB_WDP_MCDZ__ASK_CREDITS_W_MASK 0x7f000000 2588 #define MC_HUB_WDP_MCDZ__ASK_CREDITS_W__SHIFT 0x18 2589 #define MC_HUB_WDP_SIP__STALL_MODE_MASK 0x3 2590 #define MC_HUB_WDP_SIP__STALL_MODE__SHIFT 0x0 2591 #define MC_HUB_WDP_SIP__ASK_CREDITS_MASK 0x1fc 2592 #define MC_HUB_WDP_SIP__ASK_CREDITS__SHIFT 0x2 2593 #define MC_HUB_WDP_SDMA1__ENABLE_MASK 0x1 2594 #define MC_HUB_WDP_SDMA1__ENABLE__SHIFT 0x0 2595 #define MC_HUB_WDP_SDMA1__PRESCALE_MASK 0x6 2596 #define MC_HUB_WDP_SDMA1__PRESCALE__SHIFT 0x1 2597 #define MC_HUB_WDP_SDMA1__BLACKOUT_EXEMPT_MASK 0x8 2598 #define MC_HUB_WDP_SDMA1__BLACKOUT_EXEMPT__SHIFT 0x3 2599 #define MC_HUB_WDP_SDMA1__STALL_MODE_MASK 0x30 2600 #define MC_HUB_WDP_SDMA1__STALL_MODE__SHIFT 0x4 2601 #define MC_HUB_WDP_SDMA1__STALL_OVERRIDE_MASK 0x40 2602 #define MC_HUB_WDP_SDMA1__STALL_OVERRIDE__SHIFT 0x6 2603 #define MC_HUB_WDP_SDMA1__MAXBURST_MASK 0x780 2604 #define MC_HUB_WDP_SDMA1__MAXBURST__SHIFT 0x7 2605 #define MC_HUB_WDP_SDMA1__LAZY_TIMER_MASK 0x7800 2606 #define MC_HUB_WDP_SDMA1__LAZY_TIMER__SHIFT 0xb 2607 #define MC_HUB_WDP_SDMA1__STALL_OVERRIDE_WTM_MASK 0x8000 2608 #define MC_HUB_WDP_SDMA1__STALL_OVERRIDE_WTM__SHIFT 0xf 2609 #define MC_HUB_WDP_SDMA1__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 2610 #define MC_HUB_WDP_SDMA1__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 2611 #define MC_HUB_WDP_SH0__ENABLE_MASK 0x1 2612 #define MC_HUB_WDP_SH0__ENABLE__SHIFT 0x0 2613 #define MC_HUB_WDP_SH0__PRESCALE_MASK 0x6 2614 #define MC_HUB_WDP_SH0__PRESCALE__SHIFT 0x1 2615 #define MC_HUB_WDP_SH0__BLACKOUT_EXEMPT_MASK 0x8 2616 #define MC_HUB_WDP_SH0__BLACKOUT_EXEMPT__SHIFT 0x3 2617 #define MC_HUB_WDP_SH0__STALL_MODE_MASK 0x30 2618 #define MC_HUB_WDP_SH0__STALL_MODE__SHIFT 0x4 2619 #define MC_HUB_WDP_SH0__STALL_OVERRIDE_MASK 0x40 2620 #define MC_HUB_WDP_SH0__STALL_OVERRIDE__SHIFT 0x6 2621 #define MC_HUB_WDP_SH0__MAXBURST_MASK 0x780 2622 #define MC_HUB_WDP_SH0__MAXBURST__SHIFT 0x7 2623 #define MC_HUB_WDP_SH0__LAZY_TIMER_MASK 0x7800 2624 #define MC_HUB_WDP_SH0__LAZY_TIMER__SHIFT 0xb 2625 #define MC_HUB_WDP_SH0__STALL_OVERRIDE_WTM_MASK 0x8000 2626 #define MC_HUB_WDP_SH0__STALL_OVERRIDE_WTM__SHIFT 0xf 2627 #define MC_HUB_WDP_SH0__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 2628 #define MC_HUB_WDP_SH0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 2629 #define MC_HUB_WDP_MCIF__ENABLE_MASK 0x1 2630 #define MC_HUB_WDP_MCIF__ENABLE__SHIFT 0x0 2631 #define MC_HUB_WDP_MCIF__PRESCALE_MASK 0x6 2632 #define MC_HUB_WDP_MCIF__PRESCALE__SHIFT 0x1 2633 #define MC_HUB_WDP_MCIF__BLACKOUT_EXEMPT_MASK 0x8 2634 #define MC_HUB_WDP_MCIF__BLACKOUT_EXEMPT__SHIFT 0x3 2635 #define MC_HUB_WDP_MCIF__STALL_MODE_MASK 0x30 2636 #define MC_HUB_WDP_MCIF__STALL_MODE__SHIFT 0x4 2637 #define MC_HUB_WDP_MCIF__STALL_OVERRIDE_MASK 0x40 2638 #define MC_HUB_WDP_MCIF__STALL_OVERRIDE__SHIFT 0x6 2639 #define MC_HUB_WDP_MCIF__MAXBURST_MASK 0x780 2640 #define MC_HUB_WDP_MCIF__MAXBURST__SHIFT 0x7 2641 #define MC_HUB_WDP_MCIF__LAZY_TIMER_MASK 0x7800 2642 #define MC_HUB_WDP_MCIF__LAZY_TIMER__SHIFT 0xb 2643 #define MC_HUB_WDP_MCIF__STALL_OVERRIDE_WTM_MASK 0x8000 2644 #define MC_HUB_WDP_MCIF__STALL_OVERRIDE_WTM__SHIFT 0xf 2645 #define MC_HUB_WDP_MCIF__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 2646 #define MC_HUB_WDP_MCIF__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 2647 #define MC_HUB_WDP_VCE0__ENABLE_MASK 0x1 2648 #define MC_HUB_WDP_VCE0__ENABLE__SHIFT 0x0 2649 #define MC_HUB_WDP_VCE0__PRESCALE_MASK 0x6 2650 #define MC_HUB_WDP_VCE0__PRESCALE__SHIFT 0x1 2651 #define MC_HUB_WDP_VCE0__BLACKOUT_EXEMPT_MASK 0x8 2652 #define MC_HUB_WDP_VCE0__BLACKOUT_EXEMPT__SHIFT 0x3 2653 #define MC_HUB_WDP_VCE0__STALL_MODE_MASK 0x30 2654 #define MC_HUB_WDP_VCE0__STALL_MODE__SHIFT 0x4 2655 #define MC_HUB_WDP_VCE0__STALL_OVERRIDE_MASK 0x40 2656 #define MC_HUB_WDP_VCE0__STALL_OVERRIDE__SHIFT 0x6 2657 #define MC_HUB_WDP_VCE0__MAXBURST_MASK 0x780 2658 #define MC_HUB_WDP_VCE0__MAXBURST__SHIFT 0x7 2659 #define MC_HUB_WDP_VCE0__LAZY_TIMER_MASK 0x7800 2660 #define MC_HUB_WDP_VCE0__LAZY_TIMER__SHIFT 0xb 2661 #define MC_HUB_WDP_VCE0__STALL_OVERRIDE_WTM_MASK 0x8000 2662 #define MC_HUB_WDP_VCE0__STALL_OVERRIDE_WTM__SHIFT 0xf 2663 #define MC_HUB_WDP_VCE0__VM_BYPASS_MASK 0x10000 2664 #define MC_HUB_WDP_VCE0__VM_BYPASS__SHIFT 0x10 2665 #define MC_HUB_WDP_VCE0__BYPASS_AVAIL_OVERRIDE_MASK 0x20000 2666 #define MC_HUB_WDP_VCE0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11 2667 #define MC_HUB_WDP_XDP__ENABLE_MASK 0x1 2668 #define MC_HUB_WDP_XDP__ENABLE__SHIFT 0x0 2669 #define MC_HUB_WDP_XDP__PRESCALE_MASK 0x6 2670 #define MC_HUB_WDP_XDP__PRESCALE__SHIFT 0x1 2671 #define MC_HUB_WDP_XDP__BLACKOUT_EXEMPT_MASK 0x8 2672 #define MC_HUB_WDP_XDP__BLACKOUT_EXEMPT__SHIFT 0x3 2673 #define MC_HUB_WDP_XDP__STALL_MODE_MASK 0x30 2674 #define MC_HUB_WDP_XDP__STALL_MODE__SHIFT 0x4 2675 #define MC_HUB_WDP_XDP__STALL_OVERRIDE_MASK 0x40 2676 #define MC_HUB_WDP_XDP__STALL_OVERRIDE__SHIFT 0x6 2677 #define MC_HUB_WDP_XDP__MAXBURST_MASK 0x780 2678 #define MC_HUB_WDP_XDP__MAXBURST__SHIFT 0x7 2679 #define MC_HUB_WDP_XDP__LAZY_TIMER_MASK 0x7800 2680 #define MC_HUB_WDP_XDP__LAZY_TIMER__SHIFT 0xb 2681 #define MC_HUB_WDP_XDP__STALL_OVERRIDE_WTM_MASK 0x8000 2682 #define MC_HUB_WDP_XDP__STALL_OVERRIDE_WTM__SHIFT 0xf 2683 #define MC_HUB_WDP_XDP__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 2684 #define MC_HUB_WDP_XDP__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 2685 #define MC_HUB_WDP_IH__ENABLE_MASK 0x1 2686 #define MC_HUB_WDP_IH__ENABLE__SHIFT 0x0 2687 #define MC_HUB_WDP_IH__PRESCALE_MASK 0x6 2688 #define MC_HUB_WDP_IH__PRESCALE__SHIFT 0x1 2689 #define MC_HUB_WDP_IH__BLACKOUT_EXEMPT_MASK 0x8 2690 #define MC_HUB_WDP_IH__BLACKOUT_EXEMPT__SHIFT 0x3 2691 #define MC_HUB_WDP_IH__STALL_MODE_MASK 0x30 2692 #define MC_HUB_WDP_IH__STALL_MODE__SHIFT 0x4 2693 #define MC_HUB_WDP_IH__STALL_OVERRIDE_MASK 0x40 2694 #define MC_HUB_WDP_IH__STALL_OVERRIDE__SHIFT 0x6 2695 #define MC_HUB_WDP_IH__MAXBURST_MASK 0x780 2696 #define MC_HUB_WDP_IH__MAXBURST__SHIFT 0x7 2697 #define MC_HUB_WDP_IH__LAZY_TIMER_MASK 0x7800 2698 #define MC_HUB_WDP_IH__LAZY_TIMER__SHIFT 0xb 2699 #define MC_HUB_WDP_IH__STALL_OVERRIDE_WTM_MASK 0x8000 2700 #define MC_HUB_WDP_IH__STALL_OVERRIDE_WTM__SHIFT 0xf 2701 #define MC_HUB_WDP_IH__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 2702 #define MC_HUB_WDP_IH__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 2703 #define MC_HUB_WDP_RLC__ENABLE_MASK 0x1 2704 #define MC_HUB_WDP_RLC__ENABLE__SHIFT 0x0 2705 #define MC_HUB_WDP_RLC__PRESCALE_MASK 0x6 2706 #define MC_HUB_WDP_RLC__PRESCALE__SHIFT 0x1 2707 #define MC_HUB_WDP_RLC__BLACKOUT_EXEMPT_MASK 0x8 2708 #define MC_HUB_WDP_RLC__BLACKOUT_EXEMPT__SHIFT 0x3 2709 #define MC_HUB_WDP_RLC__STALL_MODE_MASK 0x30 2710 #define MC_HUB_WDP_RLC__STALL_MODE__SHIFT 0x4 2711 #define MC_HUB_WDP_RLC__STALL_OVERRIDE_MASK 0x40 2712 #define MC_HUB_WDP_RLC__STALL_OVERRIDE__SHIFT 0x6 2713 #define MC_HUB_WDP_RLC__MAXBURST_MASK 0x780 2714 #define MC_HUB_WDP_RLC__MAXBURST__SHIFT 0x7 2715 #define MC_HUB_WDP_RLC__LAZY_TIMER_MASK 0x7800 2716 #define MC_HUB_WDP_RLC__LAZY_TIMER__SHIFT 0xb 2717 #define MC_HUB_WDP_RLC__STALL_OVERRIDE_WTM_MASK 0x8000 2718 #define MC_HUB_WDP_RLC__STALL_OVERRIDE_WTM__SHIFT 0xf 2719 #define MC_HUB_WDP_RLC__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 2720 #define MC_HUB_WDP_RLC__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 2721 #define MC_HUB_WDP_SEM__ENABLE_MASK 0x1 2722 #define MC_HUB_WDP_SEM__ENABLE__SHIFT 0x0 2723 #define MC_HUB_WDP_SEM__PRESCALE_MASK 0x6 2724 #define MC_HUB_WDP_SEM__PRESCALE__SHIFT 0x1 2725 #define MC_HUB_WDP_SEM__BLACKOUT_EXEMPT_MASK 0x8 2726 #define MC_HUB_WDP_SEM__BLACKOUT_EXEMPT__SHIFT 0x3 2727 #define MC_HUB_WDP_SEM__STALL_MODE_MASK 0x30 2728 #define MC_HUB_WDP_SEM__STALL_MODE__SHIFT 0x4 2729 #define MC_HUB_WDP_SEM__STALL_OVERRIDE_MASK 0x40 2730 #define MC_HUB_WDP_SEM__STALL_OVERRIDE__SHIFT 0x6 2731 #define MC_HUB_WDP_SEM__MAXBURST_MASK 0x780 2732 #define MC_HUB_WDP_SEM__MAXBURST__SHIFT 0x7 2733 #define MC_HUB_WDP_SEM__LAZY_TIMER_MASK 0x7800 2734 #define MC_HUB_WDP_SEM__LAZY_TIMER__SHIFT 0xb 2735 #define MC_HUB_WDP_SEM__STALL_OVERRIDE_WTM_MASK 0x8000 2736 #define MC_HUB_WDP_SEM__STALL_OVERRIDE_WTM__SHIFT 0xf 2737 #define MC_HUB_WDP_SEM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 2738 #define MC_HUB_WDP_SEM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 2739 #define MC_HUB_WDP_SMU__ENABLE_MASK 0x1 2740 #define MC_HUB_WDP_SMU__ENABLE__SHIFT 0x0 2741 #define MC_HUB_WDP_SMU__PRESCALE_MASK 0x6 2742 #define MC_HUB_WDP_SMU__PRESCALE__SHIFT 0x1 2743 #define MC_HUB_WDP_SMU__BLACKOUT_EXEMPT_MASK 0x8 2744 #define MC_HUB_WDP_SMU__BLACKOUT_EXEMPT__SHIFT 0x3 2745 #define MC_HUB_WDP_SMU__STALL_MODE_MASK 0x30 2746 #define MC_HUB_WDP_SMU__STALL_MODE__SHIFT 0x4 2747 #define MC_HUB_WDP_SMU__STALL_OVERRIDE_MASK 0x40 2748 #define MC_HUB_WDP_SMU__STALL_OVERRIDE__SHIFT 0x6 2749 #define MC_HUB_WDP_SMU__MAXBURST_MASK 0x780 2750 #define MC_HUB_WDP_SMU__MAXBURST__SHIFT 0x7 2751 #define MC_HUB_WDP_SMU__LAZY_TIMER_MASK 0x7800 2752 #define MC_HUB_WDP_SMU__LAZY_TIMER__SHIFT 0xb 2753 #define MC_HUB_WDP_SMU__STALL_OVERRIDE_WTM_MASK 0x8000 2754 #define MC_HUB_WDP_SMU__STALL_OVERRIDE_WTM__SHIFT 0xf 2755 #define MC_HUB_WDP_SMU__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 2756 #define MC_HUB_WDP_SMU__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 2757 #define MC_HUB_WDP_SH1__ENABLE_MASK 0x1 2758 #define MC_HUB_WDP_SH1__ENABLE__SHIFT 0x0 2759 #define MC_HUB_WDP_SH1__PRESCALE_MASK 0x6 2760 #define MC_HUB_WDP_SH1__PRESCALE__SHIFT 0x1 2761 #define MC_HUB_WDP_SH1__BLACKOUT_EXEMPT_MASK 0x8 2762 #define MC_HUB_WDP_SH1__BLACKOUT_EXEMPT__SHIFT 0x3 2763 #define MC_HUB_WDP_SH1__STALL_MODE_MASK 0x30 2764 #define MC_HUB_WDP_SH1__STALL_MODE__SHIFT 0x4 2765 #define MC_HUB_WDP_SH1__STALL_OVERRIDE_MASK 0x40 2766 #define MC_HUB_WDP_SH1__STALL_OVERRIDE__SHIFT 0x6 2767 #define MC_HUB_WDP_SH1__MAXBURST_MASK 0x780 2768 #define MC_HUB_WDP_SH1__MAXBURST__SHIFT 0x7 2769 #define MC_HUB_WDP_SH1__LAZY_TIMER_MASK 0x7800 2770 #define MC_HUB_WDP_SH1__LAZY_TIMER__SHIFT 0xb 2771 #define MC_HUB_WDP_SH1__STALL_OVERRIDE_WTM_MASK 0x8000 2772 #define MC_HUB_WDP_SH1__STALL_OVERRIDE_WTM__SHIFT 0xf 2773 #define MC_HUB_WDP_SH1__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 2774 #define MC_HUB_WDP_SH1__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 2775 #define MC_HUB_WDP_UMC__ENABLE_MASK 0x1 2776 #define MC_HUB_WDP_UMC__ENABLE__SHIFT 0x0 2777 #define MC_HUB_WDP_UMC__PRESCALE_MASK 0x6 2778 #define MC_HUB_WDP_UMC__PRESCALE__SHIFT 0x1 2779 #define MC_HUB_WDP_UMC__BLACKOUT_EXEMPT_MASK 0x8 2780 #define MC_HUB_WDP_UMC__BLACKOUT_EXEMPT__SHIFT 0x3 2781 #define MC_HUB_WDP_UMC__STALL_MODE_MASK 0x30 2782 #define MC_HUB_WDP_UMC__STALL_MODE__SHIFT 0x4 2783 #define MC_HUB_WDP_UMC__STALL_OVERRIDE_MASK 0x40 2784 #define MC_HUB_WDP_UMC__STALL_OVERRIDE__SHIFT 0x6 2785 #define MC_HUB_WDP_UMC__MAXBURST_MASK 0x780 2786 #define MC_HUB_WDP_UMC__MAXBURST__SHIFT 0x7 2787 #define MC_HUB_WDP_UMC__LAZY_TIMER_MASK 0x7800 2788 #define MC_HUB_WDP_UMC__LAZY_TIMER__SHIFT 0xb 2789 #define MC_HUB_WDP_UMC__STALL_OVERRIDE_WTM_MASK 0x8000 2790 #define MC_HUB_WDP_UMC__STALL_OVERRIDE_WTM__SHIFT 0xf 2791 #define MC_HUB_WDP_UMC__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 2792 #define MC_HUB_WDP_UMC__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 2793 #define MC_HUB_WDP_UVD__ENABLE_MASK 0x1 2794 #define MC_HUB_WDP_UVD__ENABLE__SHIFT 0x0 2795 #define MC_HUB_WDP_UVD__PRESCALE_MASK 0x6 2796 #define MC_HUB_WDP_UVD__PRESCALE__SHIFT 0x1 2797 #define MC_HUB_WDP_UVD__BLACKOUT_EXEMPT_MASK 0x8 2798 #define MC_HUB_WDP_UVD__BLACKOUT_EXEMPT__SHIFT 0x3 2799 #define MC_HUB_WDP_UVD__STALL_MODE_MASK 0x30 2800 #define MC_HUB_WDP_UVD__STALL_MODE__SHIFT 0x4 2801 #define MC_HUB_WDP_UVD__STALL_OVERRIDE_MASK 0x40 2802 #define MC_HUB_WDP_UVD__STALL_OVERRIDE__SHIFT 0x6 2803 #define MC_HUB_WDP_UVD__MAXBURST_MASK 0x780 2804 #define MC_HUB_WDP_UVD__MAXBURST__SHIFT 0x7 2805 #define MC_HUB_WDP_UVD__LAZY_TIMER_MASK 0x7800 2806 #define MC_HUB_WDP_UVD__LAZY_TIMER__SHIFT 0xb 2807 #define MC_HUB_WDP_UVD__STALL_OVERRIDE_WTM_MASK 0x8000 2808 #define MC_HUB_WDP_UVD__STALL_OVERRIDE_WTM__SHIFT 0xf 2809 #define MC_HUB_WDP_UVD__VM_BYPASS_MASK 0x10000 2810 #define MC_HUB_WDP_UVD__VM_BYPASS__SHIFT 0x10 2811 #define MC_HUB_WDP_UVD__BYPASS_AVAIL_OVERRIDE_MASK 0x20000 2812 #define MC_HUB_WDP_UVD__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11 2813 #define MC_HUB_WDP_HDP__ENABLE_MASK 0x1 2814 #define MC_HUB_WDP_HDP__ENABLE__SHIFT 0x0 2815 #define MC_HUB_WDP_HDP__PRESCALE_MASK 0x6 2816 #define MC_HUB_WDP_HDP__PRESCALE__SHIFT 0x1 2817 #define MC_HUB_WDP_HDP__BLACKOUT_EXEMPT_MASK 0x8 2818 #define MC_HUB_WDP_HDP__BLACKOUT_EXEMPT__SHIFT 0x3 2819 #define MC_HUB_WDP_HDP__STALL_MODE_MASK 0x30 2820 #define MC_HUB_WDP_HDP__STALL_MODE__SHIFT 0x4 2821 #define MC_HUB_WDP_HDP__STALL_OVERRIDE_MASK 0x40 2822 #define MC_HUB_WDP_HDP__STALL_OVERRIDE__SHIFT 0x6 2823 #define MC_HUB_WDP_HDP__MAXBURST_MASK 0x780 2824 #define MC_HUB_WDP_HDP__MAXBURST__SHIFT 0x7 2825 #define MC_HUB_WDP_HDP__LAZY_TIMER_MASK 0x7800 2826 #define MC_HUB_WDP_HDP__LAZY_TIMER__SHIFT 0xb 2827 #define MC_HUB_WDP_HDP__STALL_OVERRIDE_WTM_MASK 0x8000 2828 #define MC_HUB_WDP_HDP__STALL_OVERRIDE_WTM__SHIFT 0xf 2829 #define MC_HUB_WDP_HDP__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 2830 #define MC_HUB_WDP_HDP__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 2831 #define MC_HUB_WDP_SDMA0__ENABLE_MASK 0x1 2832 #define MC_HUB_WDP_SDMA0__ENABLE__SHIFT 0x0 2833 #define MC_HUB_WDP_SDMA0__PRESCALE_MASK 0x6 2834 #define MC_HUB_WDP_SDMA0__PRESCALE__SHIFT 0x1 2835 #define MC_HUB_WDP_SDMA0__BLACKOUT_EXEMPT_MASK 0x8 2836 #define MC_HUB_WDP_SDMA0__BLACKOUT_EXEMPT__SHIFT 0x3 2837 #define MC_HUB_WDP_SDMA0__STALL_MODE_MASK 0x30 2838 #define MC_HUB_WDP_SDMA0__STALL_MODE__SHIFT 0x4 2839 #define MC_HUB_WDP_SDMA0__STALL_OVERRIDE_MASK 0x40 2840 #define MC_HUB_WDP_SDMA0__STALL_OVERRIDE__SHIFT 0x6 2841 #define MC_HUB_WDP_SDMA0__MAXBURST_MASK 0x780 2842 #define MC_HUB_WDP_SDMA0__MAXBURST__SHIFT 0x7 2843 #define MC_HUB_WDP_SDMA0__LAZY_TIMER_MASK 0x7800 2844 #define MC_HUB_WDP_SDMA0__LAZY_TIMER__SHIFT 0xb 2845 #define MC_HUB_WDP_SDMA0__STALL_OVERRIDE_WTM_MASK 0x8000 2846 #define MC_HUB_WDP_SDMA0__STALL_OVERRIDE_WTM__SHIFT 0xf 2847 #define MC_HUB_WDP_SDMA0__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 2848 #define MC_HUB_WDP_SDMA0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 2849 #define MC_HUB_WRRET_MCDW__STALL_MODE_MASK 0x1 2850 #define MC_HUB_WRRET_MCDW__STALL_MODE__SHIFT 0x0 2851 #define MC_HUB_WRRET_MCDW__CREDIT_COUNT_MASK 0xfe 2852 #define MC_HUB_WRRET_MCDW__CREDIT_COUNT__SHIFT 0x1 2853 #define MC_HUB_WRRET_MCDX__STALL_MODE_MASK 0x1 2854 #define MC_HUB_WRRET_MCDX__STALL_MODE__SHIFT 0x0 2855 #define MC_HUB_WRRET_MCDX__CREDIT_COUNT_MASK 0xfe 2856 #define MC_HUB_WRRET_MCDX__CREDIT_COUNT__SHIFT 0x1 2857 #define MC_HUB_WRRET_MCDY__STALL_MODE_MASK 0x1 2858 #define MC_HUB_WRRET_MCDY__STALL_MODE__SHIFT 0x0 2859 #define MC_HUB_WRRET_MCDY__CREDIT_COUNT_MASK 0xfe 2860 #define MC_HUB_WRRET_MCDY__CREDIT_COUNT__SHIFT 0x1 2861 #define MC_HUB_WRRET_MCDZ__STALL_MODE_MASK 0x1 2862 #define MC_HUB_WRRET_MCDZ__STALL_MODE__SHIFT 0x0 2863 #define MC_HUB_WRRET_MCDZ__CREDIT_COUNT_MASK 0xfe 2864 #define MC_HUB_WRRET_MCDZ__CREDIT_COUNT__SHIFT 0x1 2865 #define MC_HUB_WDP_VCEU0__ENABLE_MASK 0x1 2866 #define MC_HUB_WDP_VCEU0__ENABLE__SHIFT 0x0 2867 #define MC_HUB_WDP_VCEU0__PRESCALE_MASK 0x6 2868 #define MC_HUB_WDP_VCEU0__PRESCALE__SHIFT 0x1 2869 #define MC_HUB_WDP_VCEU0__BLACKOUT_EXEMPT_MASK 0x8 2870 #define MC_HUB_WDP_VCEU0__BLACKOUT_EXEMPT__SHIFT 0x3 2871 #define MC_HUB_WDP_VCEU0__STALL_MODE_MASK 0x30 2872 #define MC_HUB_WDP_VCEU0__STALL_MODE__SHIFT 0x4 2873 #define MC_HUB_WDP_VCEU0__STALL_OVERRIDE_MASK 0x40 2874 #define MC_HUB_WDP_VCEU0__STALL_OVERRIDE__SHIFT 0x6 2875 #define MC_HUB_WDP_VCEU0__MAXBURST_MASK 0x780 2876 #define MC_HUB_WDP_VCEU0__MAXBURST__SHIFT 0x7 2877 #define MC_HUB_WDP_VCEU0__LAZY_TIMER_MASK 0x7800 2878 #define MC_HUB_WDP_VCEU0__LAZY_TIMER__SHIFT 0xb 2879 #define MC_HUB_WDP_VCEU0__STALL_OVERRIDE_WTM_MASK 0x8000 2880 #define MC_HUB_WDP_VCEU0__STALL_OVERRIDE_WTM__SHIFT 0xf 2881 #define MC_HUB_WDP_VCEU0__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 2882 #define MC_HUB_WDP_VCEU0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 2883 #define MC_HUB_WDP_XDMAM__ENABLE_MASK 0x1 2884 #define MC_HUB_WDP_XDMAM__ENABLE__SHIFT 0x0 2885 #define MC_HUB_WDP_XDMAM__PRESCALE_MASK 0x6 2886 #define MC_HUB_WDP_XDMAM__PRESCALE__SHIFT 0x1 2887 #define MC_HUB_WDP_XDMAM__BLACKOUT_EXEMPT_MASK 0x8 2888 #define MC_HUB_WDP_XDMAM__BLACKOUT_EXEMPT__SHIFT 0x3 2889 #define MC_HUB_WDP_XDMAM__STALL_MODE_MASK 0x30 2890 #define MC_HUB_WDP_XDMAM__STALL_MODE__SHIFT 0x4 2891 #define MC_HUB_WDP_XDMAM__STALL_OVERRIDE_MASK 0x40 2892 #define MC_HUB_WDP_XDMAM__STALL_OVERRIDE__SHIFT 0x6 2893 #define MC_HUB_WDP_XDMAM__MAXBURST_MASK 0x780 2894 #define MC_HUB_WDP_XDMAM__MAXBURST__SHIFT 0x7 2895 #define MC_HUB_WDP_XDMAM__LAZY_TIMER_MASK 0x7800 2896 #define MC_HUB_WDP_XDMAM__LAZY_TIMER__SHIFT 0xb 2897 #define MC_HUB_WDP_XDMAM__STALL_OVERRIDE_WTM_MASK 0x8000 2898 #define MC_HUB_WDP_XDMAM__STALL_OVERRIDE_WTM__SHIFT 0xf 2899 #define MC_HUB_WDP_XDMAM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 2900 #define MC_HUB_WDP_XDMAM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 2901 #define MC_HUB_WDP_XDMA__ENABLE_MASK 0x1 2902 #define MC_HUB_WDP_XDMA__ENABLE__SHIFT 0x0 2903 #define MC_HUB_WDP_XDMA__PRESCALE_MASK 0x6 2904 #define MC_HUB_WDP_XDMA__PRESCALE__SHIFT 0x1 2905 #define MC_HUB_WDP_XDMA__BLACKOUT_EXEMPT_MASK 0x8 2906 #define MC_HUB_WDP_XDMA__BLACKOUT_EXEMPT__SHIFT 0x3 2907 #define MC_HUB_WDP_XDMA__STALL_MODE_MASK 0x30 2908 #define MC_HUB_WDP_XDMA__STALL_MODE__SHIFT 0x4 2909 #define MC_HUB_WDP_XDMA__STALL_OVERRIDE_MASK 0x40 2910 #define MC_HUB_WDP_XDMA__STALL_OVERRIDE__SHIFT 0x6 2911 #define MC_HUB_WDP_XDMA__MAXBURST_MASK 0x780 2912 #define MC_HUB_WDP_XDMA__MAXBURST__SHIFT 0x7 2913 #define MC_HUB_WDP_XDMA__LAZY_TIMER_MASK 0x7800 2914 #define MC_HUB_WDP_XDMA__LAZY_TIMER__SHIFT 0xb 2915 #define MC_HUB_WDP_XDMA__STALL_OVERRIDE_WTM_MASK 0x8000 2916 #define MC_HUB_WDP_XDMA__STALL_OVERRIDE_WTM__SHIFT 0xf 2917 #define MC_HUB_WDP_XDMA__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 2918 #define MC_HUB_WDP_XDMA__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 2919 #define MC_HUB_RDREQ_XDMAM__ENABLE_MASK 0x1 2920 #define MC_HUB_RDREQ_XDMAM__ENABLE__SHIFT 0x0 2921 #define MC_HUB_RDREQ_XDMAM__PRESCALE_MASK 0x6 2922 #define MC_HUB_RDREQ_XDMAM__PRESCALE__SHIFT 0x1 2923 #define MC_HUB_RDREQ_XDMAM__BLACKOUT_EXEMPT_MASK 0x8 2924 #define MC_HUB_RDREQ_XDMAM__BLACKOUT_EXEMPT__SHIFT 0x3 2925 #define MC_HUB_RDREQ_XDMAM__STALL_MODE_MASK 0x30 2926 #define MC_HUB_RDREQ_XDMAM__STALL_MODE__SHIFT 0x4 2927 #define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE_MASK 0x40 2928 #define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE__SHIFT 0x6 2929 #define MC_HUB_RDREQ_XDMAM__MAXBURST_MASK 0x780 2930 #define MC_HUB_RDREQ_XDMAM__MAXBURST__SHIFT 0x7 2931 #define MC_HUB_RDREQ_XDMAM__LAZY_TIMER_MASK 0x7800 2932 #define MC_HUB_RDREQ_XDMAM__LAZY_TIMER__SHIFT 0xb 2933 #define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE_WTM_MASK 0x8000 2934 #define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE_WTM__SHIFT 0xf 2935 #define MC_HUB_RDREQ_XDMAM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 2936 #define MC_HUB_RDREQ_XDMAM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 2937 #define MC_HUB_RDREQ_ACPG__ENABLE_MASK 0x1 2938 #define MC_HUB_RDREQ_ACPG__ENABLE__SHIFT 0x0 2939 #define MC_HUB_RDREQ_ACPG__PRESCALE_MASK 0x6 2940 #define MC_HUB_RDREQ_ACPG__PRESCALE__SHIFT 0x1 2941 #define MC_HUB_RDREQ_ACPG__BLACKOUT_EXEMPT_MASK 0x8 2942 #define MC_HUB_RDREQ_ACPG__BLACKOUT_EXEMPT__SHIFT 0x3 2943 #define MC_HUB_RDREQ_ACPG__STALL_MODE_MASK 0x30 2944 #define MC_HUB_RDREQ_ACPG__STALL_MODE__SHIFT 0x4 2945 #define MC_HUB_RDREQ_ACPG__STALL_OVERRIDE_MASK 0x40 2946 #define MC_HUB_RDREQ_ACPG__STALL_OVERRIDE__SHIFT 0x6 2947 #define MC_HUB_RDREQ_ACPG__MAXBURST_MASK 0x780 2948 #define MC_HUB_RDREQ_ACPG__MAXBURST__SHIFT 0x7 2949 #define MC_HUB_RDREQ_ACPG__LAZY_TIMER_MASK 0x7800 2950 #define MC_HUB_RDREQ_ACPG__LAZY_TIMER__SHIFT 0xb 2951 #define MC_HUB_RDREQ_ACPG__STALL_OVERRIDE_WTM_MASK 0x8000 2952 #define MC_HUB_RDREQ_ACPG__STALL_OVERRIDE_WTM__SHIFT 0xf 2953 #define MC_HUB_RDREQ_ACPG__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 2954 #define MC_HUB_RDREQ_ACPG__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 2955 #define MC_HUB_RDREQ_ACPG__PRIORITY_DISABLE_MASK 0x20000 2956 #define MC_HUB_RDREQ_ACPG__PRIORITY_DISABLE__SHIFT 0x11 2957 #define MC_HUB_RDREQ_ACPG__STALL_FILTER_ENABLE_MASK 0x40000 2958 #define MC_HUB_RDREQ_ACPG__STALL_FILTER_ENABLE__SHIFT 0x12 2959 #define MC_HUB_RDREQ_ACPG__STALL_THRESHOLD_MASK 0x1f80000 2960 #define MC_HUB_RDREQ_ACPG__STALL_THRESHOLD__SHIFT 0x13 2961 #define MC_HUB_RDREQ_ACPO__ENABLE_MASK 0x1 2962 #define MC_HUB_RDREQ_ACPO__ENABLE__SHIFT 0x0 2963 #define MC_HUB_RDREQ_ACPO__PRESCALE_MASK 0x6 2964 #define MC_HUB_RDREQ_ACPO__PRESCALE__SHIFT 0x1 2965 #define MC_HUB_RDREQ_ACPO__BLACKOUT_EXEMPT_MASK 0x8 2966 #define MC_HUB_RDREQ_ACPO__BLACKOUT_EXEMPT__SHIFT 0x3 2967 #define MC_HUB_RDREQ_ACPO__STALL_MODE_MASK 0x30 2968 #define MC_HUB_RDREQ_ACPO__STALL_MODE__SHIFT 0x4 2969 #define MC_HUB_RDREQ_ACPO__STALL_OVERRIDE_MASK 0x40 2970 #define MC_HUB_RDREQ_ACPO__STALL_OVERRIDE__SHIFT 0x6 2971 #define MC_HUB_RDREQ_ACPO__MAXBURST_MASK 0x780 2972 #define MC_HUB_RDREQ_ACPO__MAXBURST__SHIFT 0x7 2973 #define MC_HUB_RDREQ_ACPO__LAZY_TIMER_MASK 0x7800 2974 #define MC_HUB_RDREQ_ACPO__LAZY_TIMER__SHIFT 0xb 2975 #define MC_HUB_RDREQ_ACPO__STALL_OVERRIDE_WTM_MASK 0x8000 2976 #define MC_HUB_RDREQ_ACPO__STALL_OVERRIDE_WTM__SHIFT 0xf 2977 #define MC_HUB_RDREQ_ACPO__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 2978 #define MC_HUB_RDREQ_ACPO__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 2979 #define MC_HUB_RDREQ_ACPO__PRIORITY_DISABLE_MASK 0x20000 2980 #define MC_HUB_RDREQ_ACPO__PRIORITY_DISABLE__SHIFT 0x11 2981 #define MC_HUB_RDREQ_ACPO__STALL_FILTER_ENABLE_MASK 0x40000 2982 #define MC_HUB_RDREQ_ACPO__STALL_FILTER_ENABLE__SHIFT 0x12 2983 #define MC_HUB_RDREQ_ACPO__STALL_THRESHOLD_MASK 0x1f80000 2984 #define MC_HUB_RDREQ_ACPO__STALL_THRESHOLD__SHIFT 0x13 2985 #define MC_HUB_RDREQ_SAMMSP__ENABLE_MASK 0x1 2986 #define MC_HUB_RDREQ_SAMMSP__ENABLE__SHIFT 0x0 2987 #define MC_HUB_RDREQ_SAMMSP__PRESCALE_MASK 0x6 2988 #define MC_HUB_RDREQ_SAMMSP__PRESCALE__SHIFT 0x1 2989 #define MC_HUB_RDREQ_SAMMSP__BLACKOUT_EXEMPT_MASK 0x8 2990 #define MC_HUB_RDREQ_SAMMSP__BLACKOUT_EXEMPT__SHIFT 0x3 2991 #define MC_HUB_RDREQ_SAMMSP__STALL_MODE_MASK 0x30 2992 #define MC_HUB_RDREQ_SAMMSP__STALL_MODE__SHIFT 0x4 2993 #define MC_HUB_RDREQ_SAMMSP__STALL_OVERRIDE_MASK 0x40 2994 #define MC_HUB_RDREQ_SAMMSP__STALL_OVERRIDE__SHIFT 0x6 2995 #define MC_HUB_RDREQ_SAMMSP__MAXBURST_MASK 0x780 2996 #define MC_HUB_RDREQ_SAMMSP__MAXBURST__SHIFT 0x7 2997 #define MC_HUB_RDREQ_SAMMSP__LAZY_TIMER_MASK 0x7800 2998 #define MC_HUB_RDREQ_SAMMSP__LAZY_TIMER__SHIFT 0xb 2999 #define MC_HUB_RDREQ_SAMMSP__STALL_OVERRIDE_WTM_MASK 0x8000 3000 #define MC_HUB_RDREQ_SAMMSP__STALL_OVERRIDE_WTM__SHIFT 0xf 3001 #define MC_HUB_RDREQ_SAMMSP__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 3002 #define MC_HUB_RDREQ_SAMMSP__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 3003 #define MC_HUB_RDREQ_VP8__ENABLE_MASK 0x1 3004 #define MC_HUB_RDREQ_VP8__ENABLE__SHIFT 0x0 3005 #define MC_HUB_RDREQ_VP8__PRESCALE_MASK 0x6 3006 #define MC_HUB_RDREQ_VP8__PRESCALE__SHIFT 0x1 3007 #define MC_HUB_RDREQ_VP8__BLACKOUT_EXEMPT_MASK 0x8 3008 #define MC_HUB_RDREQ_VP8__BLACKOUT_EXEMPT__SHIFT 0x3 3009 #define MC_HUB_RDREQ_VP8__STALL_MODE_MASK 0x30 3010 #define MC_HUB_RDREQ_VP8__STALL_MODE__SHIFT 0x4 3011 #define MC_HUB_RDREQ_VP8__STALL_OVERRIDE_MASK 0x40 3012 #define MC_HUB_RDREQ_VP8__STALL_OVERRIDE__SHIFT 0x6 3013 #define MC_HUB_RDREQ_VP8__MAXBURST_MASK 0x780 3014 #define MC_HUB_RDREQ_VP8__MAXBURST__SHIFT 0x7 3015 #define MC_HUB_RDREQ_VP8__LAZY_TIMER_MASK 0x7800 3016 #define MC_HUB_RDREQ_VP8__LAZY_TIMER__SHIFT 0xb 3017 #define MC_HUB_RDREQ_VP8__STALL_OVERRIDE_WTM_MASK 0x8000 3018 #define MC_HUB_RDREQ_VP8__STALL_OVERRIDE_WTM__SHIFT 0xf 3019 #define MC_HUB_RDREQ_VP8__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 3020 #define MC_HUB_RDREQ_VP8__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 3021 #define MC_HUB_RDREQ_VP8U__ENABLE_MASK 0x1 3022 #define MC_HUB_RDREQ_VP8U__ENABLE__SHIFT 0x0 3023 #define MC_HUB_RDREQ_VP8U__PRESCALE_MASK 0x6 3024 #define MC_HUB_RDREQ_VP8U__PRESCALE__SHIFT 0x1 3025 #define MC_HUB_RDREQ_VP8U__BLACKOUT_EXEMPT_MASK 0x8 3026 #define MC_HUB_RDREQ_VP8U__BLACKOUT_EXEMPT__SHIFT 0x3 3027 #define MC_HUB_RDREQ_VP8U__STALL_MODE_MASK 0x30 3028 #define MC_HUB_RDREQ_VP8U__STALL_MODE__SHIFT 0x4 3029 #define MC_HUB_RDREQ_VP8U__STALL_OVERRIDE_MASK 0x40 3030 #define MC_HUB_RDREQ_VP8U__STALL_OVERRIDE__SHIFT 0x6 3031 #define MC_HUB_RDREQ_VP8U__MAXBURST_MASK 0x780 3032 #define MC_HUB_RDREQ_VP8U__MAXBURST__SHIFT 0x7 3033 #define MC_HUB_RDREQ_VP8U__LAZY_TIMER_MASK 0x7800 3034 #define MC_HUB_RDREQ_VP8U__LAZY_TIMER__SHIFT 0xb 3035 #define MC_HUB_RDREQ_VP8U__STALL_OVERRIDE_WTM_MASK 0x8000 3036 #define MC_HUB_RDREQ_VP8U__STALL_OVERRIDE_WTM__SHIFT 0xf 3037 #define MC_HUB_RDREQ_VP8U__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 3038 #define MC_HUB_RDREQ_VP8U__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 3039 #define MC_HUB_WDP_ACPG__ENABLE_MASK 0x1 3040 #define MC_HUB_WDP_ACPG__ENABLE__SHIFT 0x0 3041 #define MC_HUB_WDP_ACPG__PRESCALE_MASK 0x6 3042 #define MC_HUB_WDP_ACPG__PRESCALE__SHIFT 0x1 3043 #define MC_HUB_WDP_ACPG__BLACKOUT_EXEMPT_MASK 0x8 3044 #define MC_HUB_WDP_ACPG__BLACKOUT_EXEMPT__SHIFT 0x3 3045 #define MC_HUB_WDP_ACPG__STALL_MODE_MASK 0x30 3046 #define MC_HUB_WDP_ACPG__STALL_MODE__SHIFT 0x4 3047 #define MC_HUB_WDP_ACPG__STALL_OVERRIDE_MASK 0x40 3048 #define MC_HUB_WDP_ACPG__STALL_OVERRIDE__SHIFT 0x6 3049 #define MC_HUB_WDP_ACPG__MAXBURST_MASK 0x780 3050 #define MC_HUB_WDP_ACPG__MAXBURST__SHIFT 0x7 3051 #define MC_HUB_WDP_ACPG__LAZY_TIMER_MASK 0x7800 3052 #define MC_HUB_WDP_ACPG__LAZY_TIMER__SHIFT 0xb 3053 #define MC_HUB_WDP_ACPG__STALL_OVERRIDE_WTM_MASK 0x8000 3054 #define MC_HUB_WDP_ACPG__STALL_OVERRIDE_WTM__SHIFT 0xf 3055 #define MC_HUB_WDP_ACPG__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 3056 #define MC_HUB_WDP_ACPG__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 3057 #define MC_HUB_WDP_ACPG__PRIORITY_DISABLE_MASK 0x20000 3058 #define MC_HUB_WDP_ACPG__PRIORITY_DISABLE__SHIFT 0x11 3059 #define MC_HUB_WDP_ACPG__STALL_FILTER_ENABLE_MASK 0x40000 3060 #define MC_HUB_WDP_ACPG__STALL_FILTER_ENABLE__SHIFT 0x12 3061 #define MC_HUB_WDP_ACPG__STALL_THRESHOLD_MASK 0x1f80000 3062 #define MC_HUB_WDP_ACPG__STALL_THRESHOLD__SHIFT 0x13 3063 #define MC_HUB_WDP_ACPO__ENABLE_MASK 0x1 3064 #define MC_HUB_WDP_ACPO__ENABLE__SHIFT 0x0 3065 #define MC_HUB_WDP_ACPO__PRESCALE_MASK 0x6 3066 #define MC_HUB_WDP_ACPO__PRESCALE__SHIFT 0x1 3067 #define MC_HUB_WDP_ACPO__BLACKOUT_EXEMPT_MASK 0x8 3068 #define MC_HUB_WDP_ACPO__BLACKOUT_EXEMPT__SHIFT 0x3 3069 #define MC_HUB_WDP_ACPO__STALL_MODE_MASK 0x30 3070 #define MC_HUB_WDP_ACPO__STALL_MODE__SHIFT 0x4 3071 #define MC_HUB_WDP_ACPO__STALL_OVERRIDE_MASK 0x40 3072 #define MC_HUB_WDP_ACPO__STALL_OVERRIDE__SHIFT 0x6 3073 #define MC_HUB_WDP_ACPO__MAXBURST_MASK 0x780 3074 #define MC_HUB_WDP_ACPO__MAXBURST__SHIFT 0x7 3075 #define MC_HUB_WDP_ACPO__LAZY_TIMER_MASK 0x7800 3076 #define MC_HUB_WDP_ACPO__LAZY_TIMER__SHIFT 0xb 3077 #define MC_HUB_WDP_ACPO__STALL_OVERRIDE_WTM_MASK 0x8000 3078 #define MC_HUB_WDP_ACPO__STALL_OVERRIDE_WTM__SHIFT 0xf 3079 #define MC_HUB_WDP_ACPO__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 3080 #define MC_HUB_WDP_ACPO__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 3081 #define MC_HUB_WDP_ACPO__PRIORITY_DISABLE_MASK 0x20000 3082 #define MC_HUB_WDP_ACPO__PRIORITY_DISABLE__SHIFT 0x11 3083 #define MC_HUB_WDP_ACPO__STALL_FILTER_ENABLE_MASK 0x40000 3084 #define MC_HUB_WDP_ACPO__STALL_FILTER_ENABLE__SHIFT 0x12 3085 #define MC_HUB_WDP_ACPO__STALL_THRESHOLD_MASK 0x1f80000 3086 #define MC_HUB_WDP_ACPO__STALL_THRESHOLD__SHIFT 0x13 3087 #define MC_HUB_WDP_SAMMSP__ENABLE_MASK 0x1 3088 #define MC_HUB_WDP_SAMMSP__ENABLE__SHIFT 0x0 3089 #define MC_HUB_WDP_SAMMSP__PRESCALE_MASK 0x6 3090 #define MC_HUB_WDP_SAMMSP__PRESCALE__SHIFT 0x1 3091 #define MC_HUB_WDP_SAMMSP__BLACKOUT_EXEMPT_MASK 0x8 3092 #define MC_HUB_WDP_SAMMSP__BLACKOUT_EXEMPT__SHIFT 0x3 3093 #define MC_HUB_WDP_SAMMSP__STALL_MODE_MASK 0x30 3094 #define MC_HUB_WDP_SAMMSP__STALL_MODE__SHIFT 0x4 3095 #define MC_HUB_WDP_SAMMSP__STALL_OVERRIDE_MASK 0x40 3096 #define MC_HUB_WDP_SAMMSP__STALL_OVERRIDE__SHIFT 0x6 3097 #define MC_HUB_WDP_SAMMSP__MAXBURST_MASK 0x780 3098 #define MC_HUB_WDP_SAMMSP__MAXBURST__SHIFT 0x7 3099 #define MC_HUB_WDP_SAMMSP__LAZY_TIMER_MASK 0x7800 3100 #define MC_HUB_WDP_SAMMSP__LAZY_TIMER__SHIFT 0xb 3101 #define MC_HUB_WDP_SAMMSP__STALL_OVERRIDE_WTM_MASK 0x8000 3102 #define MC_HUB_WDP_SAMMSP__STALL_OVERRIDE_WTM__SHIFT 0xf 3103 #define MC_HUB_WDP_SAMMSP__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 3104 #define MC_HUB_WDP_SAMMSP__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 3105 #define MC_HUB_WDP_VP8__ENABLE_MASK 0x1 3106 #define MC_HUB_WDP_VP8__ENABLE__SHIFT 0x0 3107 #define MC_HUB_WDP_VP8__PRESCALE_MASK 0x6 3108 #define MC_HUB_WDP_VP8__PRESCALE__SHIFT 0x1 3109 #define MC_HUB_WDP_VP8__BLACKOUT_EXEMPT_MASK 0x8 3110 #define MC_HUB_WDP_VP8__BLACKOUT_EXEMPT__SHIFT 0x3 3111 #define MC_HUB_WDP_VP8__STALL_MODE_MASK 0x30 3112 #define MC_HUB_WDP_VP8__STALL_MODE__SHIFT 0x4 3113 #define MC_HUB_WDP_VP8__STALL_OVERRIDE_MASK 0x40 3114 #define MC_HUB_WDP_VP8__STALL_OVERRIDE__SHIFT 0x6 3115 #define MC_HUB_WDP_VP8__MAXBURST_MASK 0x780 3116 #define MC_HUB_WDP_VP8__MAXBURST__SHIFT 0x7 3117 #define MC_HUB_WDP_VP8__LAZY_TIMER_MASK 0x7800 3118 #define MC_HUB_WDP_VP8__LAZY_TIMER__SHIFT 0xb 3119 #define MC_HUB_WDP_VP8__STALL_OVERRIDE_WTM_MASK 0x8000 3120 #define MC_HUB_WDP_VP8__STALL_OVERRIDE_WTM__SHIFT 0xf 3121 #define MC_HUB_WDP_VP8__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 3122 #define MC_HUB_WDP_VP8__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 3123 #define MC_HUB_WDP_VP8U__ENABLE_MASK 0x1 3124 #define MC_HUB_WDP_VP8U__ENABLE__SHIFT 0x0 3125 #define MC_HUB_WDP_VP8U__PRESCALE_MASK 0x6 3126 #define MC_HUB_WDP_VP8U__PRESCALE__SHIFT 0x1 3127 #define MC_HUB_WDP_VP8U__BLACKOUT_EXEMPT_MASK 0x8 3128 #define MC_HUB_WDP_VP8U__BLACKOUT_EXEMPT__SHIFT 0x3 3129 #define MC_HUB_WDP_VP8U__STALL_MODE_MASK 0x30 3130 #define MC_HUB_WDP_VP8U__STALL_MODE__SHIFT 0x4 3131 #define MC_HUB_WDP_VP8U__STALL_OVERRIDE_MASK 0x40 3132 #define MC_HUB_WDP_VP8U__STALL_OVERRIDE__SHIFT 0x6 3133 #define MC_HUB_WDP_VP8U__MAXBURST_MASK 0x780 3134 #define MC_HUB_WDP_VP8U__MAXBURST__SHIFT 0x7 3135 #define MC_HUB_WDP_VP8U__LAZY_TIMER_MASK 0x7800 3136 #define MC_HUB_WDP_VP8U__LAZY_TIMER__SHIFT 0xb 3137 #define MC_HUB_WDP_VP8U__STALL_OVERRIDE_WTM_MASK 0x8000 3138 #define MC_HUB_WDP_VP8U__STALL_OVERRIDE_WTM__SHIFT 0xf 3139 #define MC_HUB_WDP_VP8U__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 3140 #define MC_HUB_WDP_VP8U__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 3141 #define MC_HUB_RDREQ_ISP_SPM__ENABLE_MASK 0x1 3142 #define MC_HUB_RDREQ_ISP_SPM__ENABLE__SHIFT 0x0 3143 #define MC_HUB_RDREQ_ISP_SPM__PRESCALE_MASK 0x6 3144 #define MC_HUB_RDREQ_ISP_SPM__PRESCALE__SHIFT 0x1 3145 #define MC_HUB_RDREQ_ISP_SPM__BLACKOUT_EXEMPT_MASK 0x8 3146 #define MC_HUB_RDREQ_ISP_SPM__BLACKOUT_EXEMPT__SHIFT 0x3 3147 #define MC_HUB_RDREQ_ISP_SPM__STALL_MODE_MASK 0x30 3148 #define MC_HUB_RDREQ_ISP_SPM__STALL_MODE__SHIFT 0x4 3149 #define MC_HUB_RDREQ_ISP_SPM__STALL_OVERRIDE_MASK 0x40 3150 #define MC_HUB_RDREQ_ISP_SPM__STALL_OVERRIDE__SHIFT 0x6 3151 #define MC_HUB_RDREQ_ISP_SPM__MAXBURST_MASK 0x780 3152 #define MC_HUB_RDREQ_ISP_SPM__MAXBURST__SHIFT 0x7 3153 #define MC_HUB_RDREQ_ISP_SPM__LAZY_TIMER_MASK 0x7800 3154 #define MC_HUB_RDREQ_ISP_SPM__LAZY_TIMER__SHIFT 0xb 3155 #define MC_HUB_RDREQ_ISP_SPM__STALL_OVERRIDE_WTM_MASK 0x8000 3156 #define MC_HUB_RDREQ_ISP_SPM__STALL_OVERRIDE_WTM__SHIFT 0xf 3157 #define MC_HUB_RDREQ_ISP_SPM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 3158 #define MC_HUB_RDREQ_ISP_SPM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 3159 #define MC_HUB_RDREQ_ISP_SPM__PRIORITY_DISABLE_MASK 0x20000 3160 #define MC_HUB_RDREQ_ISP_SPM__PRIORITY_DISABLE__SHIFT 0x11 3161 #define MC_HUB_RDREQ_ISP_SPM__STALL_FILTER_ENABLE_MASK 0x40000 3162 #define MC_HUB_RDREQ_ISP_SPM__STALL_FILTER_ENABLE__SHIFT 0x12 3163 #define MC_HUB_RDREQ_ISP_SPM__STALL_THRESHOLD_MASK 0x1f80000 3164 #define MC_HUB_RDREQ_ISP_SPM__STALL_THRESHOLD__SHIFT 0x13 3165 #define MC_HUB_RDREQ_ISP_MPM__ENABLE_MASK 0x1 3166 #define MC_HUB_RDREQ_ISP_MPM__ENABLE__SHIFT 0x0 3167 #define MC_HUB_RDREQ_ISP_MPM__PRESCALE_MASK 0x6 3168 #define MC_HUB_RDREQ_ISP_MPM__PRESCALE__SHIFT 0x1 3169 #define MC_HUB_RDREQ_ISP_MPM__BLACKOUT_EXEMPT_MASK 0x8 3170 #define MC_HUB_RDREQ_ISP_MPM__BLACKOUT_EXEMPT__SHIFT 0x3 3171 #define MC_HUB_RDREQ_ISP_MPM__STALL_MODE_MASK 0x30 3172 #define MC_HUB_RDREQ_ISP_MPM__STALL_MODE__SHIFT 0x4 3173 #define MC_HUB_RDREQ_ISP_MPM__STALL_OVERRIDE_MASK 0x40 3174 #define MC_HUB_RDREQ_ISP_MPM__STALL_OVERRIDE__SHIFT 0x6 3175 #define MC_HUB_RDREQ_ISP_MPM__MAXBURST_MASK 0x780 3176 #define MC_HUB_RDREQ_ISP_MPM__MAXBURST__SHIFT 0x7 3177 #define MC_HUB_RDREQ_ISP_MPM__LAZY_TIMER_MASK 0x7800 3178 #define MC_HUB_RDREQ_ISP_MPM__LAZY_TIMER__SHIFT 0xb 3179 #define MC_HUB_RDREQ_ISP_MPM__STALL_OVERRIDE_WTM_MASK 0x8000 3180 #define MC_HUB_RDREQ_ISP_MPM__STALL_OVERRIDE_WTM__SHIFT 0xf 3181 #define MC_HUB_RDREQ_ISP_MPM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 3182 #define MC_HUB_RDREQ_ISP_MPM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 3183 #define MC_HUB_RDREQ_ISP_MPM__PRIORITY_DISABLE_MASK 0x20000 3184 #define MC_HUB_RDREQ_ISP_MPM__PRIORITY_DISABLE__SHIFT 0x11 3185 #define MC_HUB_RDREQ_ISP_MPM__STALL_FILTER_ENABLE_MASK 0x40000 3186 #define MC_HUB_RDREQ_ISP_MPM__STALL_FILTER_ENABLE__SHIFT 0x12 3187 #define MC_HUB_RDREQ_ISP_MPM__STALL_THRESHOLD_MASK 0x1f80000 3188 #define MC_HUB_RDREQ_ISP_MPM__STALL_THRESHOLD__SHIFT 0x13 3189 #define MC_HUB_RDREQ_ISP_CCPU__ENABLE_MASK 0x1 3190 #define MC_HUB_RDREQ_ISP_CCPU__ENABLE__SHIFT 0x0 3191 #define MC_HUB_RDREQ_ISP_CCPU__PRESCALE_MASK 0x6 3192 #define MC_HUB_RDREQ_ISP_CCPU__PRESCALE__SHIFT 0x1 3193 #define MC_HUB_RDREQ_ISP_CCPU__BLACKOUT_EXEMPT_MASK 0x8 3194 #define MC_HUB_RDREQ_ISP_CCPU__BLACKOUT_EXEMPT__SHIFT 0x3 3195 #define MC_HUB_RDREQ_ISP_CCPU__STALL_MODE_MASK 0x30 3196 #define MC_HUB_RDREQ_ISP_CCPU__STALL_MODE__SHIFT 0x4 3197 #define MC_HUB_RDREQ_ISP_CCPU__STALL_OVERRIDE_MASK 0x40 3198 #define MC_HUB_RDREQ_ISP_CCPU__STALL_OVERRIDE__SHIFT 0x6 3199 #define MC_HUB_RDREQ_ISP_CCPU__MAXBURST_MASK 0x780 3200 #define MC_HUB_RDREQ_ISP_CCPU__MAXBURST__SHIFT 0x7 3201 #define MC_HUB_RDREQ_ISP_CCPU__LAZY_TIMER_MASK 0x7800 3202 #define MC_HUB_RDREQ_ISP_CCPU__LAZY_TIMER__SHIFT 0xb 3203 #define MC_HUB_RDREQ_ISP_CCPU__STALL_OVERRIDE_WTM_MASK 0x8000 3204 #define MC_HUB_RDREQ_ISP_CCPU__STALL_OVERRIDE_WTM__SHIFT 0xf 3205 #define MC_HUB_RDREQ_ISP_CCPU__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 3206 #define MC_HUB_RDREQ_ISP_CCPU__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 3207 #define MC_HUB_RDREQ_ISP_CCPU__PRIORITY_DISABLE_MASK 0x20000 3208 #define MC_HUB_RDREQ_ISP_CCPU__PRIORITY_DISABLE__SHIFT 0x11 3209 #define MC_HUB_RDREQ_ISP_CCPU__STALL_FILTER_ENABLE_MASK 0x40000 3210 #define MC_HUB_RDREQ_ISP_CCPU__STALL_FILTER_ENABLE__SHIFT 0x12 3211 #define MC_HUB_RDREQ_ISP_CCPU__STALL_THRESHOLD_MASK 0x1f80000 3212 #define MC_HUB_RDREQ_ISP_CCPU__STALL_THRESHOLD__SHIFT 0x13 3213 #define MC_HUB_WDP_ISP_SPM__ENABLE_MASK 0x1 3214 #define MC_HUB_WDP_ISP_SPM__ENABLE__SHIFT 0x0 3215 #define MC_HUB_WDP_ISP_SPM__PRESCALE_MASK 0x6 3216 #define MC_HUB_WDP_ISP_SPM__PRESCALE__SHIFT 0x1 3217 #define MC_HUB_WDP_ISP_SPM__BLACKOUT_EXEMPT_MASK 0x8 3218 #define MC_HUB_WDP_ISP_SPM__BLACKOUT_EXEMPT__SHIFT 0x3 3219 #define MC_HUB_WDP_ISP_SPM__STALL_MODE_MASK 0x30 3220 #define MC_HUB_WDP_ISP_SPM__STALL_MODE__SHIFT 0x4 3221 #define MC_HUB_WDP_ISP_SPM__STALL_OVERRIDE_MASK 0x40 3222 #define MC_HUB_WDP_ISP_SPM__STALL_OVERRIDE__SHIFT 0x6 3223 #define MC_HUB_WDP_ISP_SPM__MAXBURST_MASK 0x780 3224 #define MC_HUB_WDP_ISP_SPM__MAXBURST__SHIFT 0x7 3225 #define MC_HUB_WDP_ISP_SPM__LAZY_TIMER_MASK 0x7800 3226 #define MC_HUB_WDP_ISP_SPM__LAZY_TIMER__SHIFT 0xb 3227 #define MC_HUB_WDP_ISP_SPM__STALL_OVERRIDE_WTM_MASK 0x8000 3228 #define MC_HUB_WDP_ISP_SPM__STALL_OVERRIDE_WTM__SHIFT 0xf 3229 #define MC_HUB_WDP_ISP_SPM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 3230 #define MC_HUB_WDP_ISP_SPM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 3231 #define MC_HUB_WDP_ISP_SPM__PRIORITY_DISABLE_MASK 0x20000 3232 #define MC_HUB_WDP_ISP_SPM__PRIORITY_DISABLE__SHIFT 0x11 3233 #define MC_HUB_WDP_ISP_SPM__STALL_FILTER_ENABLE_MASK 0x40000 3234 #define MC_HUB_WDP_ISP_SPM__STALL_FILTER_ENABLE__SHIFT 0x12 3235 #define MC_HUB_WDP_ISP_SPM__STALL_THRESHOLD_MASK 0x1f80000 3236 #define MC_HUB_WDP_ISP_SPM__STALL_THRESHOLD__SHIFT 0x13 3237 #define MC_HUB_WDP_ISP_MPS__ENABLE_MASK 0x1 3238 #define MC_HUB_WDP_ISP_MPS__ENABLE__SHIFT 0x0 3239 #define MC_HUB_WDP_ISP_MPS__PRESCALE_MASK 0x6 3240 #define MC_HUB_WDP_ISP_MPS__PRESCALE__SHIFT 0x1 3241 #define MC_HUB_WDP_ISP_MPS__BLACKOUT_EXEMPT_MASK 0x8 3242 #define MC_HUB_WDP_ISP_MPS__BLACKOUT_EXEMPT__SHIFT 0x3 3243 #define MC_HUB_WDP_ISP_MPS__STALL_MODE_MASK 0x30 3244 #define MC_HUB_WDP_ISP_MPS__STALL_MODE__SHIFT 0x4 3245 #define MC_HUB_WDP_ISP_MPS__STALL_OVERRIDE_MASK 0x40 3246 #define MC_HUB_WDP_ISP_MPS__STALL_OVERRIDE__SHIFT 0x6 3247 #define MC_HUB_WDP_ISP_MPS__MAXBURST_MASK 0x780 3248 #define MC_HUB_WDP_ISP_MPS__MAXBURST__SHIFT 0x7 3249 #define MC_HUB_WDP_ISP_MPS__LAZY_TIMER_MASK 0x7800 3250 #define MC_HUB_WDP_ISP_MPS__LAZY_TIMER__SHIFT 0xb 3251 #define MC_HUB_WDP_ISP_MPS__STALL_OVERRIDE_WTM_MASK 0x8000 3252 #define MC_HUB_WDP_ISP_MPS__STALL_OVERRIDE_WTM__SHIFT 0xf 3253 #define MC_HUB_WDP_ISP_MPS__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 3254 #define MC_HUB_WDP_ISP_MPS__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 3255 #define MC_HUB_WDP_ISP_MPS__PRIORITY_DISABLE_MASK 0x20000 3256 #define MC_HUB_WDP_ISP_MPS__PRIORITY_DISABLE__SHIFT 0x11 3257 #define MC_HUB_WDP_ISP_MPS__STALL_FILTER_ENABLE_MASK 0x40000 3258 #define MC_HUB_WDP_ISP_MPS__STALL_FILTER_ENABLE__SHIFT 0x12 3259 #define MC_HUB_WDP_ISP_MPS__STALL_THRESHOLD_MASK 0x1f80000 3260 #define MC_HUB_WDP_ISP_MPS__STALL_THRESHOLD__SHIFT 0x13 3261 #define MC_HUB_WDP_ISP_MPM__ENABLE_MASK 0x1 3262 #define MC_HUB_WDP_ISP_MPM__ENABLE__SHIFT 0x0 3263 #define MC_HUB_WDP_ISP_MPM__PRESCALE_MASK 0x6 3264 #define MC_HUB_WDP_ISP_MPM__PRESCALE__SHIFT 0x1 3265 #define MC_HUB_WDP_ISP_MPM__BLACKOUT_EXEMPT_MASK 0x8 3266 #define MC_HUB_WDP_ISP_MPM__BLACKOUT_EXEMPT__SHIFT 0x3 3267 #define MC_HUB_WDP_ISP_MPM__STALL_MODE_MASK 0x30 3268 #define MC_HUB_WDP_ISP_MPM__STALL_MODE__SHIFT 0x4 3269 #define MC_HUB_WDP_ISP_MPM__STALL_OVERRIDE_MASK 0x40 3270 #define MC_HUB_WDP_ISP_MPM__STALL_OVERRIDE__SHIFT 0x6 3271 #define MC_HUB_WDP_ISP_MPM__MAXBURST_MASK 0x780 3272 #define MC_HUB_WDP_ISP_MPM__MAXBURST__SHIFT 0x7 3273 #define MC_HUB_WDP_ISP_MPM__LAZY_TIMER_MASK 0x7800 3274 #define MC_HUB_WDP_ISP_MPM__LAZY_TIMER__SHIFT 0xb 3275 #define MC_HUB_WDP_ISP_MPM__STALL_OVERRIDE_WTM_MASK 0x8000 3276 #define MC_HUB_WDP_ISP_MPM__STALL_OVERRIDE_WTM__SHIFT 0xf 3277 #define MC_HUB_WDP_ISP_MPM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 3278 #define MC_HUB_WDP_ISP_MPM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 3279 #define MC_HUB_WDP_ISP_MPM__PRIORITY_DISABLE_MASK 0x20000 3280 #define MC_HUB_WDP_ISP_MPM__PRIORITY_DISABLE__SHIFT 0x11 3281 #define MC_HUB_WDP_ISP_MPM__STALL_FILTER_ENABLE_MASK 0x40000 3282 #define MC_HUB_WDP_ISP_MPM__STALL_FILTER_ENABLE__SHIFT 0x12 3283 #define MC_HUB_WDP_ISP_MPM__STALL_THRESHOLD_MASK 0x1f80000 3284 #define MC_HUB_WDP_ISP_MPM__STALL_THRESHOLD__SHIFT 0x13 3285 #define MC_HUB_WDP_ISP_CCPU__ENABLE_MASK 0x1 3286 #define MC_HUB_WDP_ISP_CCPU__ENABLE__SHIFT 0x0 3287 #define MC_HUB_WDP_ISP_CCPU__PRESCALE_MASK 0x6 3288 #define MC_HUB_WDP_ISP_CCPU__PRESCALE__SHIFT 0x1 3289 #define MC_HUB_WDP_ISP_CCPU__BLACKOUT_EXEMPT_MASK 0x8 3290 #define MC_HUB_WDP_ISP_CCPU__BLACKOUT_EXEMPT__SHIFT 0x3 3291 #define MC_HUB_WDP_ISP_CCPU__STALL_MODE_MASK 0x30 3292 #define MC_HUB_WDP_ISP_CCPU__STALL_MODE__SHIFT 0x4 3293 #define MC_HUB_WDP_ISP_CCPU__STALL_OVERRIDE_MASK 0x40 3294 #define MC_HUB_WDP_ISP_CCPU__STALL_OVERRIDE__SHIFT 0x6 3295 #define MC_HUB_WDP_ISP_CCPU__MAXBURST_MASK 0x780 3296 #define MC_HUB_WDP_ISP_CCPU__MAXBURST__SHIFT 0x7 3297 #define MC_HUB_WDP_ISP_CCPU__LAZY_TIMER_MASK 0x7800 3298 #define MC_HUB_WDP_ISP_CCPU__LAZY_TIMER__SHIFT 0xb 3299 #define MC_HUB_WDP_ISP_CCPU__STALL_OVERRIDE_WTM_MASK 0x8000 3300 #define MC_HUB_WDP_ISP_CCPU__STALL_OVERRIDE_WTM__SHIFT 0xf 3301 #define MC_HUB_WDP_ISP_CCPU__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 3302 #define MC_HUB_WDP_ISP_CCPU__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 3303 #define MC_HUB_WDP_ISP_CCPU__PRIORITY_DISABLE_MASK 0x20000 3304 #define MC_HUB_WDP_ISP_CCPU__PRIORITY_DISABLE__SHIFT 0x11 3305 #define MC_HUB_WDP_ISP_CCPU__STALL_FILTER_ENABLE_MASK 0x40000 3306 #define MC_HUB_WDP_ISP_CCPU__STALL_FILTER_ENABLE__SHIFT 0x12 3307 #define MC_HUB_WDP_ISP_CCPU__STALL_THRESHOLD_MASK 0x1f80000 3308 #define MC_HUB_WDP_ISP_CCPU__STALL_THRESHOLD__SHIFT 0x13 3309 #define MC_HUB_RDREQ_MCDS__ENABLE_MASK 0x1 3310 #define MC_HUB_RDREQ_MCDS__ENABLE__SHIFT 0x0 3311 #define MC_HUB_RDREQ_MCDS__BLACKOUT_EXEMPT_MASK 0x2 3312 #define MC_HUB_RDREQ_MCDS__BLACKOUT_EXEMPT__SHIFT 0x1 3313 #define MC_HUB_RDREQ_MCDS__BUS_MASK 0x4 3314 #define MC_HUB_RDREQ_MCDS__BUS__SHIFT 0x2 3315 #define MC_HUB_RDREQ_MCDS__MAXBURST_MASK 0x78 3316 #define MC_HUB_RDREQ_MCDS__MAXBURST__SHIFT 0x3 3317 #define MC_HUB_RDREQ_MCDS__LAZY_TIMER_MASK 0x780 3318 #define MC_HUB_RDREQ_MCDS__LAZY_TIMER__SHIFT 0x7 3319 #define MC_HUB_RDREQ_MCDS__ASK_CREDITS_MASK 0x3f800 3320 #define MC_HUB_RDREQ_MCDS__ASK_CREDITS__SHIFT 0xb 3321 #define MC_HUB_RDREQ_MCDS__DISPLAY_CREDITS_MASK 0x1fc0000 3322 #define MC_HUB_RDREQ_MCDS__DISPLAY_CREDITS__SHIFT 0x12 3323 #define MC_HUB_RDREQ_MCDS__STALL_THRESHOLD_MASK 0xfe000000 3324 #define MC_HUB_RDREQ_MCDS__STALL_THRESHOLD__SHIFT 0x19 3325 #define MC_HUB_RDREQ_MCDT__ENABLE_MASK 0x1 3326 #define MC_HUB_RDREQ_MCDT__ENABLE__SHIFT 0x0 3327 #define MC_HUB_RDREQ_MCDT__BLACKOUT_EXEMPT_MASK 0x2 3328 #define MC_HUB_RDREQ_MCDT__BLACKOUT_EXEMPT__SHIFT 0x1 3329 #define MC_HUB_RDREQ_MCDT__BUS_MASK 0x4 3330 #define MC_HUB_RDREQ_MCDT__BUS__SHIFT 0x2 3331 #define MC_HUB_RDREQ_MCDT__MAXBURST_MASK 0x78 3332 #define MC_HUB_RDREQ_MCDT__MAXBURST__SHIFT 0x3 3333 #define MC_HUB_RDREQ_MCDT__LAZY_TIMER_MASK 0x780 3334 #define MC_HUB_RDREQ_MCDT__LAZY_TIMER__SHIFT 0x7 3335 #define MC_HUB_RDREQ_MCDT__ASK_CREDITS_MASK 0x3f800 3336 #define MC_HUB_RDREQ_MCDT__ASK_CREDITS__SHIFT 0xb 3337 #define MC_HUB_RDREQ_MCDT__DISPLAY_CREDITS_MASK 0x1fc0000 3338 #define MC_HUB_RDREQ_MCDT__DISPLAY_CREDITS__SHIFT 0x12 3339 #define MC_HUB_RDREQ_MCDT__STALL_THRESHOLD_MASK 0xfe000000 3340 #define MC_HUB_RDREQ_MCDT__STALL_THRESHOLD__SHIFT 0x19 3341 #define MC_HUB_RDREQ_MCDU__ENABLE_MASK 0x1 3342 #define MC_HUB_RDREQ_MCDU__ENABLE__SHIFT 0x0 3343 #define MC_HUB_RDREQ_MCDU__BLACKOUT_EXEMPT_MASK 0x2 3344 #define MC_HUB_RDREQ_MCDU__BLACKOUT_EXEMPT__SHIFT 0x1 3345 #define MC_HUB_RDREQ_MCDU__BUS_MASK 0x4 3346 #define MC_HUB_RDREQ_MCDU__BUS__SHIFT 0x2 3347 #define MC_HUB_RDREQ_MCDU__MAXBURST_MASK 0x78 3348 #define MC_HUB_RDREQ_MCDU__MAXBURST__SHIFT 0x3 3349 #define MC_HUB_RDREQ_MCDU__LAZY_TIMER_MASK 0x780 3350 #define MC_HUB_RDREQ_MCDU__LAZY_TIMER__SHIFT 0x7 3351 #define MC_HUB_RDREQ_MCDU__ASK_CREDITS_MASK 0x3f800 3352 #define MC_HUB_RDREQ_MCDU__ASK_CREDITS__SHIFT 0xb 3353 #define MC_HUB_RDREQ_MCDU__DISPLAY_CREDITS_MASK 0x1fc0000 3354 #define MC_HUB_RDREQ_MCDU__DISPLAY_CREDITS__SHIFT 0x12 3355 #define MC_HUB_RDREQ_MCDU__STALL_THRESHOLD_MASK 0xfe000000 3356 #define MC_HUB_RDREQ_MCDU__STALL_THRESHOLD__SHIFT 0x19 3357 #define MC_HUB_RDREQ_MCDV__ENABLE_MASK 0x1 3358 #define MC_HUB_RDREQ_MCDV__ENABLE__SHIFT 0x0 3359 #define MC_HUB_RDREQ_MCDV__BLACKOUT_EXEMPT_MASK 0x2 3360 #define MC_HUB_RDREQ_MCDV__BLACKOUT_EXEMPT__SHIFT 0x1 3361 #define MC_HUB_RDREQ_MCDV__BUS_MASK 0x4 3362 #define MC_HUB_RDREQ_MCDV__BUS__SHIFT 0x2 3363 #define MC_HUB_RDREQ_MCDV__MAXBURST_MASK 0x78 3364 #define MC_HUB_RDREQ_MCDV__MAXBURST__SHIFT 0x3 3365 #define MC_HUB_RDREQ_MCDV__LAZY_TIMER_MASK 0x780 3366 #define MC_HUB_RDREQ_MCDV__LAZY_TIMER__SHIFT 0x7 3367 #define MC_HUB_RDREQ_MCDV__ASK_CREDITS_MASK 0x3f800 3368 #define MC_HUB_RDREQ_MCDV__ASK_CREDITS__SHIFT 0xb 3369 #define MC_HUB_RDREQ_MCDV__DISPLAY_CREDITS_MASK 0x1fc0000 3370 #define MC_HUB_RDREQ_MCDV__DISPLAY_CREDITS__SHIFT 0x12 3371 #define MC_HUB_RDREQ_MCDV__STALL_THRESHOLD_MASK 0xfe000000 3372 #define MC_HUB_RDREQ_MCDV__STALL_THRESHOLD__SHIFT 0x19 3373 #define MC_HUB_WDP_MCDS__ENABLE_MASK 0x1 3374 #define MC_HUB_WDP_MCDS__ENABLE__SHIFT 0x0 3375 #define MC_HUB_WDP_MCDS__BLACKOUT_EXEMPT_MASK 0x2 3376 #define MC_HUB_WDP_MCDS__BLACKOUT_EXEMPT__SHIFT 0x1 3377 #define MC_HUB_WDP_MCDS__STALL_MODE_MASK 0x4 3378 #define MC_HUB_WDP_MCDS__STALL_MODE__SHIFT 0x2 3379 #define MC_HUB_WDP_MCDS__MAXBURST_MASK 0x78 3380 #define MC_HUB_WDP_MCDS__MAXBURST__SHIFT 0x3 3381 #define MC_HUB_WDP_MCDS__ASK_CREDITS_MASK 0x1f80 3382 #define MC_HUB_WDP_MCDS__ASK_CREDITS__SHIFT 0x7 3383 #define MC_HUB_WDP_MCDS__LAZY_TIMER_MASK 0x1e000 3384 #define MC_HUB_WDP_MCDS__LAZY_TIMER__SHIFT 0xd 3385 #define MC_HUB_WDP_MCDS__STALL_THRESHOLD_MASK 0xfe0000 3386 #define MC_HUB_WDP_MCDS__STALL_THRESHOLD__SHIFT 0x11 3387 #define MC_HUB_WDP_MCDS__ASK_CREDITS_W_MASK 0x7f000000 3388 #define MC_HUB_WDP_MCDS__ASK_CREDITS_W__SHIFT 0x18 3389 #define MC_HUB_WDP_MCDT__ENABLE_MASK 0x1 3390 #define MC_HUB_WDP_MCDT__ENABLE__SHIFT 0x0 3391 #define MC_HUB_WDP_MCDT__BLACKOUT_EXEMPT_MASK 0x2 3392 #define MC_HUB_WDP_MCDT__BLACKOUT_EXEMPT__SHIFT 0x1 3393 #define MC_HUB_WDP_MCDT__STALL_MODE_MASK 0x4 3394 #define MC_HUB_WDP_MCDT__STALL_MODE__SHIFT 0x2 3395 #define MC_HUB_WDP_MCDT__MAXBURST_MASK 0x78 3396 #define MC_HUB_WDP_MCDT__MAXBURST__SHIFT 0x3 3397 #define MC_HUB_WDP_MCDT__ASK_CREDITS_MASK 0x1f80 3398 #define MC_HUB_WDP_MCDT__ASK_CREDITS__SHIFT 0x7 3399 #define MC_HUB_WDP_MCDT__LAZY_TIMER_MASK 0x1e000 3400 #define MC_HUB_WDP_MCDT__LAZY_TIMER__SHIFT 0xd 3401 #define MC_HUB_WDP_MCDT__STALL_THRESHOLD_MASK 0xfe0000 3402 #define MC_HUB_WDP_MCDT__STALL_THRESHOLD__SHIFT 0x11 3403 #define MC_HUB_WDP_MCDT__ASK_CREDITS_W_MASK 0x7f000000 3404 #define MC_HUB_WDP_MCDT__ASK_CREDITS_W__SHIFT 0x18 3405 #define MC_HUB_WDP_MCDU__ENABLE_MASK 0x1 3406 #define MC_HUB_WDP_MCDU__ENABLE__SHIFT 0x0 3407 #define MC_HUB_WDP_MCDU__BLACKOUT_EXEMPT_MASK 0x2 3408 #define MC_HUB_WDP_MCDU__BLACKOUT_EXEMPT__SHIFT 0x1 3409 #define MC_HUB_WDP_MCDU__STALL_MODE_MASK 0x4 3410 #define MC_HUB_WDP_MCDU__STALL_MODE__SHIFT 0x2 3411 #define MC_HUB_WDP_MCDU__MAXBURST_MASK 0x78 3412 #define MC_HUB_WDP_MCDU__MAXBURST__SHIFT 0x3 3413 #define MC_HUB_WDP_MCDU__ASK_CREDITS_MASK 0x1f80 3414 #define MC_HUB_WDP_MCDU__ASK_CREDITS__SHIFT 0x7 3415 #define MC_HUB_WDP_MCDU__LAZY_TIMER_MASK 0x1e000 3416 #define MC_HUB_WDP_MCDU__LAZY_TIMER__SHIFT 0xd 3417 #define MC_HUB_WDP_MCDU__STALL_THRESHOLD_MASK 0xfe0000 3418 #define MC_HUB_WDP_MCDU__STALL_THRESHOLD__SHIFT 0x11 3419 #define MC_HUB_WDP_MCDU__ASK_CREDITS_W_MASK 0x7f000000 3420 #define MC_HUB_WDP_MCDU__ASK_CREDITS_W__SHIFT 0x18 3421 #define MC_HUB_WDP_MCDV__ENABLE_MASK 0x1 3422 #define MC_HUB_WDP_MCDV__ENABLE__SHIFT 0x0 3423 #define MC_HUB_WDP_MCDV__BLACKOUT_EXEMPT_MASK 0x2 3424 #define MC_HUB_WDP_MCDV__BLACKOUT_EXEMPT__SHIFT 0x1 3425 #define MC_HUB_WDP_MCDV__STALL_MODE_MASK 0x4 3426 #define MC_HUB_WDP_MCDV__STALL_MODE__SHIFT 0x2 3427 #define MC_HUB_WDP_MCDV__MAXBURST_MASK 0x78 3428 #define MC_HUB_WDP_MCDV__MAXBURST__SHIFT 0x3 3429 #define MC_HUB_WDP_MCDV__ASK_CREDITS_MASK 0x1f80 3430 #define MC_HUB_WDP_MCDV__ASK_CREDITS__SHIFT 0x7 3431 #define MC_HUB_WDP_MCDV__LAZY_TIMER_MASK 0x1e000 3432 #define MC_HUB_WDP_MCDV__LAZY_TIMER__SHIFT 0xd 3433 #define MC_HUB_WDP_MCDV__STALL_THRESHOLD_MASK 0xfe0000 3434 #define MC_HUB_WDP_MCDV__STALL_THRESHOLD__SHIFT 0x11 3435 #define MC_HUB_WDP_MCDV__ASK_CREDITS_W_MASK 0x7f000000 3436 #define MC_HUB_WDP_MCDV__ASK_CREDITS_W__SHIFT 0x18 3437 #define MC_HUB_WRRET_MCDS__STALL_MODE_MASK 0x1 3438 #define MC_HUB_WRRET_MCDS__STALL_MODE__SHIFT 0x0 3439 #define MC_HUB_WRRET_MCDS__CREDIT_COUNT_MASK 0xfe 3440 #define MC_HUB_WRRET_MCDS__CREDIT_COUNT__SHIFT 0x1 3441 #define MC_HUB_WRRET_MCDT__STALL_MODE_MASK 0x1 3442 #define MC_HUB_WRRET_MCDT__STALL_MODE__SHIFT 0x0 3443 #define MC_HUB_WRRET_MCDT__CREDIT_COUNT_MASK 0xfe 3444 #define MC_HUB_WRRET_MCDT__CREDIT_COUNT__SHIFT 0x1 3445 #define MC_HUB_WRRET_MCDU__STALL_MODE_MASK 0x1 3446 #define MC_HUB_WRRET_MCDU__STALL_MODE__SHIFT 0x0 3447 #define MC_HUB_WRRET_MCDU__CREDIT_COUNT_MASK 0xfe 3448 #define MC_HUB_WRRET_MCDU__CREDIT_COUNT__SHIFT 0x1 3449 #define MC_HUB_WRRET_MCDV__STALL_MODE_MASK 0x1 3450 #define MC_HUB_WRRET_MCDV__STALL_MODE__SHIFT 0x0 3451 #define MC_HUB_WRRET_MCDV__CREDIT_COUNT_MASK 0xfe 3452 #define MC_HUB_WRRET_MCDV__CREDIT_COUNT__SHIFT 0x1 3453 #define MC_HUB_WDP_CREDITS_MCDW__WR_PRI_MASK 0x7f 3454 #define MC_HUB_WDP_CREDITS_MCDW__WR_PRI__SHIFT 0x0 3455 #define MC_HUB_WDP_CREDITS_MCDW__WR_PRI_STALL_THRESHOLD_MASK 0x3f80 3456 #define MC_HUB_WDP_CREDITS_MCDW__WR_PRI_STALL_THRESHOLD__SHIFT 0x7 3457 #define MC_HUB_WDP_CREDITS_MCDX__WR_PRI_MASK 0x7f 3458 #define MC_HUB_WDP_CREDITS_MCDX__WR_PRI__SHIFT 0x0 3459 #define MC_HUB_WDP_CREDITS_MCDX__WR_PRI_STALL_THRESHOLD_MASK 0x3f80 3460 #define MC_HUB_WDP_CREDITS_MCDX__WR_PRI_STALL_THRESHOLD__SHIFT 0x7 3461 #define MC_HUB_WDP_CREDITS_MCDY__WR_PRI_MASK 0x7f 3462 #define MC_HUB_WDP_CREDITS_MCDY__WR_PRI__SHIFT 0x0 3463 #define MC_HUB_WDP_CREDITS_MCDY__WR_PRI_STALL_THRESHOLD_MASK 0x3f80 3464 #define MC_HUB_WDP_CREDITS_MCDY__WR_PRI_STALL_THRESHOLD__SHIFT 0x7 3465 #define MC_HUB_WDP_CREDITS_MCDZ__WR_PRI_MASK 0x7f 3466 #define MC_HUB_WDP_CREDITS_MCDZ__WR_PRI__SHIFT 0x0 3467 #define MC_HUB_WDP_CREDITS_MCDZ__WR_PRI_STALL_THRESHOLD_MASK 0x3f80 3468 #define MC_HUB_WDP_CREDITS_MCDZ__WR_PRI_STALL_THRESHOLD__SHIFT 0x7 3469 #define MC_HUB_WDP_CREDITS_MCDS__WR_PRI_MASK 0x7f 3470 #define MC_HUB_WDP_CREDITS_MCDS__WR_PRI__SHIFT 0x0 3471 #define MC_HUB_WDP_CREDITS_MCDS__WR_PRI_STALL_THRESHOLD_MASK 0x3f80 3472 #define MC_HUB_WDP_CREDITS_MCDS__WR_PRI_STALL_THRESHOLD__SHIFT 0x7 3473 #define MC_HUB_WDP_CREDITS_MCDT__WR_PRI_MASK 0x7f 3474 #define MC_HUB_WDP_CREDITS_MCDT__WR_PRI__SHIFT 0x0 3475 #define MC_HUB_WDP_CREDITS_MCDT__WR_PRI_STALL_THRESHOLD_MASK 0x3f80 3476 #define MC_HUB_WDP_CREDITS_MCDT__WR_PRI_STALL_THRESHOLD__SHIFT 0x7 3477 #define MC_HUB_WDP_CREDITS_MCDU__WR_PRI_MASK 0x7f 3478 #define MC_HUB_WDP_CREDITS_MCDU__WR_PRI__SHIFT 0x0 3479 #define MC_HUB_WDP_CREDITS_MCDU__WR_PRI_STALL_THRESHOLD_MASK 0x3f80 3480 #define MC_HUB_WDP_CREDITS_MCDU__WR_PRI_STALL_THRESHOLD__SHIFT 0x7 3481 #define MC_HUB_WDP_CREDITS_MCDV__WR_PRI_MASK 0x7f 3482 #define MC_HUB_WDP_CREDITS_MCDV__WR_PRI__SHIFT 0x0 3483 #define MC_HUB_WDP_CREDITS_MCDV__WR_PRI_STALL_THRESHOLD_MASK 0x3f80 3484 #define MC_HUB_WDP_CREDITS_MCDV__WR_PRI_STALL_THRESHOLD__SHIFT 0x7 3485 #define MC_HUB_WDP_BP2__RDRET_MASK 0xffff 3486 #define MC_HUB_WDP_BP2__RDRET__SHIFT 0x0 3487 #define MC_HUB_RDREQ_VCE1__ENABLE_MASK 0x1 3488 #define MC_HUB_RDREQ_VCE1__ENABLE__SHIFT 0x0 3489 #define MC_HUB_RDREQ_VCE1__PRESCALE_MASK 0x6 3490 #define MC_HUB_RDREQ_VCE1__PRESCALE__SHIFT 0x1 3491 #define MC_HUB_RDREQ_VCE1__BLACKOUT_EXEMPT_MASK 0x8 3492 #define MC_HUB_RDREQ_VCE1__BLACKOUT_EXEMPT__SHIFT 0x3 3493 #define MC_HUB_RDREQ_VCE1__STALL_MODE_MASK 0x30 3494 #define MC_HUB_RDREQ_VCE1__STALL_MODE__SHIFT 0x4 3495 #define MC_HUB_RDREQ_VCE1__STALL_OVERRIDE_MASK 0x40 3496 #define MC_HUB_RDREQ_VCE1__STALL_OVERRIDE__SHIFT 0x6 3497 #define MC_HUB_RDREQ_VCE1__MAXBURST_MASK 0x780 3498 #define MC_HUB_RDREQ_VCE1__MAXBURST__SHIFT 0x7 3499 #define MC_HUB_RDREQ_VCE1__LAZY_TIMER_MASK 0x7800 3500 #define MC_HUB_RDREQ_VCE1__LAZY_TIMER__SHIFT 0xb 3501 #define MC_HUB_RDREQ_VCE1__STALL_OVERRIDE_WTM_MASK 0x8000 3502 #define MC_HUB_RDREQ_VCE1__STALL_OVERRIDE_WTM__SHIFT 0xf 3503 #define MC_HUB_RDREQ_VCE1__VM_BYPASS_MASK 0x10000 3504 #define MC_HUB_RDREQ_VCE1__VM_BYPASS__SHIFT 0x10 3505 #define MC_HUB_RDREQ_VCE1__BYPASS_AVAIL_OVERRIDE_MASK 0x20000 3506 #define MC_HUB_RDREQ_VCE1__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11 3507 #define MC_HUB_RDREQ_VCEU1__ENABLE_MASK 0x1 3508 #define MC_HUB_RDREQ_VCEU1__ENABLE__SHIFT 0x0 3509 #define MC_HUB_RDREQ_VCEU1__PRESCALE_MASK 0x6 3510 #define MC_HUB_RDREQ_VCEU1__PRESCALE__SHIFT 0x1 3511 #define MC_HUB_RDREQ_VCEU1__BLACKOUT_EXEMPT_MASK 0x8 3512 #define MC_HUB_RDREQ_VCEU1__BLACKOUT_EXEMPT__SHIFT 0x3 3513 #define MC_HUB_RDREQ_VCEU1__STALL_MODE_MASK 0x30 3514 #define MC_HUB_RDREQ_VCEU1__STALL_MODE__SHIFT 0x4 3515 #define MC_HUB_RDREQ_VCEU1__STALL_OVERRIDE_MASK 0x40 3516 #define MC_HUB_RDREQ_VCEU1__STALL_OVERRIDE__SHIFT 0x6 3517 #define MC_HUB_RDREQ_VCEU1__MAXBURST_MASK 0x780 3518 #define MC_HUB_RDREQ_VCEU1__MAXBURST__SHIFT 0x7 3519 #define MC_HUB_RDREQ_VCEU1__LAZY_TIMER_MASK 0x7800 3520 #define MC_HUB_RDREQ_VCEU1__LAZY_TIMER__SHIFT 0xb 3521 #define MC_HUB_RDREQ_VCEU1__STALL_OVERRIDE_WTM_MASK 0x8000 3522 #define MC_HUB_RDREQ_VCEU1__STALL_OVERRIDE_WTM__SHIFT 0xf 3523 #define MC_HUB_RDREQ_VCEU1__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 3524 #define MC_HUB_RDREQ_VCEU1__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 3525 #define MC_HUB_WDP_VCE1__ENABLE_MASK 0x1 3526 #define MC_HUB_WDP_VCE1__ENABLE__SHIFT 0x0 3527 #define MC_HUB_WDP_VCE1__PRESCALE_MASK 0x6 3528 #define MC_HUB_WDP_VCE1__PRESCALE__SHIFT 0x1 3529 #define MC_HUB_WDP_VCE1__BLACKOUT_EXEMPT_MASK 0x8 3530 #define MC_HUB_WDP_VCE1__BLACKOUT_EXEMPT__SHIFT 0x3 3531 #define MC_HUB_WDP_VCE1__STALL_MODE_MASK 0x30 3532 #define MC_HUB_WDP_VCE1__STALL_MODE__SHIFT 0x4 3533 #define MC_HUB_WDP_VCE1__STALL_OVERRIDE_MASK 0x40 3534 #define MC_HUB_WDP_VCE1__STALL_OVERRIDE__SHIFT 0x6 3535 #define MC_HUB_WDP_VCE1__MAXBURST_MASK 0x780 3536 #define MC_HUB_WDP_VCE1__MAXBURST__SHIFT 0x7 3537 #define MC_HUB_WDP_VCE1__LAZY_TIMER_MASK 0x7800 3538 #define MC_HUB_WDP_VCE1__LAZY_TIMER__SHIFT 0xb 3539 #define MC_HUB_WDP_VCE1__STALL_OVERRIDE_WTM_MASK 0x8000 3540 #define MC_HUB_WDP_VCE1__STALL_OVERRIDE_WTM__SHIFT 0xf 3541 #define MC_HUB_WDP_VCE1__VM_BYPASS_MASK 0x10000 3542 #define MC_HUB_WDP_VCE1__VM_BYPASS__SHIFT 0x10 3543 #define MC_HUB_WDP_VCE1__BYPASS_AVAIL_OVERRIDE_MASK 0x20000 3544 #define MC_HUB_WDP_VCE1__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11 3545 #define MC_HUB_WDP_VCEU1__ENABLE_MASK 0x1 3546 #define MC_HUB_WDP_VCEU1__ENABLE__SHIFT 0x0 3547 #define MC_HUB_WDP_VCEU1__PRESCALE_MASK 0x6 3548 #define MC_HUB_WDP_VCEU1__PRESCALE__SHIFT 0x1 3549 #define MC_HUB_WDP_VCEU1__BLACKOUT_EXEMPT_MASK 0x8 3550 #define MC_HUB_WDP_VCEU1__BLACKOUT_EXEMPT__SHIFT 0x3 3551 #define MC_HUB_WDP_VCEU1__STALL_MODE_MASK 0x30 3552 #define MC_HUB_WDP_VCEU1__STALL_MODE__SHIFT 0x4 3553 #define MC_HUB_WDP_VCEU1__STALL_OVERRIDE_MASK 0x40 3554 #define MC_HUB_WDP_VCEU1__STALL_OVERRIDE__SHIFT 0x6 3555 #define MC_HUB_WDP_VCEU1__MAXBURST_MASK 0x780 3556 #define MC_HUB_WDP_VCEU1__MAXBURST__SHIFT 0x7 3557 #define MC_HUB_WDP_VCEU1__LAZY_TIMER_MASK 0x7800 3558 #define MC_HUB_WDP_VCEU1__LAZY_TIMER__SHIFT 0xb 3559 #define MC_HUB_WDP_VCEU1__STALL_OVERRIDE_WTM_MASK 0x8000 3560 #define MC_HUB_WDP_VCEU1__STALL_OVERRIDE_WTM__SHIFT 0xf 3561 #define MC_HUB_WDP_VCEU1__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 3562 #define MC_HUB_WDP_VCEU1__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 3563 #define MC_RPB_CONF__XPB_PCIE_ORDER_MASK 0x8000 3564 #define MC_RPB_CONF__XPB_PCIE_ORDER__SHIFT 0xf 3565 #define MC_RPB_CONF__RPB_RD_PCIE_ORDER_MASK 0x10000 3566 #define MC_RPB_CONF__RPB_RD_PCIE_ORDER__SHIFT 0x10 3567 #define MC_RPB_CONF__RPB_WR_PCIE_ORDER_MASK 0x20000 3568 #define MC_RPB_CONF__RPB_WR_PCIE_ORDER__SHIFT 0x11 3569 #define MC_RPB_IF_CONF__RPB_BIF_CREDITS_MASK 0xff 3570 #define MC_RPB_IF_CONF__RPB_BIF_CREDITS__SHIFT 0x0 3571 #define MC_RPB_IF_CONF__OUTSTANDING_WRRET_ASK_MASK 0xff00 3572 #define MC_RPB_IF_CONF__OUTSTANDING_WRRET_ASK__SHIFT 0x8 3573 #define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD_MASK 0xff 3574 #define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD__SHIFT 0x0 3575 #define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD_32B_MASK 0xfff00 3576 #define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD_32B__SHIFT 0x8 3577 #define MC_RPB_DBG1__DEBUG_BITS_MASK 0xfff00000 3578 #define MC_RPB_DBG1__DEBUG_BITS__SHIFT 0x14 3579 #define MC_RPB_EFF_CNTL__WR_LAZY_TIMER_MASK 0xff 3580 #define MC_RPB_EFF_CNTL__WR_LAZY_TIMER__SHIFT 0x0 3581 #define MC_RPB_EFF_CNTL__RD_LAZY_TIMER_MASK 0xff00 3582 #define MC_RPB_EFF_CNTL__RD_LAZY_TIMER__SHIFT 0x8 3583 #define MC_RPB_ARB_CNTL__WR_SWITCH_NUM_MASK 0xff 3584 #define MC_RPB_ARB_CNTL__WR_SWITCH_NUM__SHIFT 0x0 3585 #define MC_RPB_ARB_CNTL__RD_SWITCH_NUM_MASK 0xff00 3586 #define MC_RPB_ARB_CNTL__RD_SWITCH_NUM__SHIFT 0x8 3587 #define MC_RPB_ARB_CNTL__ATC_SWITCH_NUM_MASK 0xff0000 3588 #define MC_RPB_ARB_CNTL__ATC_SWITCH_NUM__SHIFT 0x10 3589 #define MC_RPB_BIF_CNTL__ARB_SWITCH_NUM_MASK 0xff 3590 #define MC_RPB_BIF_CNTL__ARB_SWITCH_NUM__SHIFT 0x0 3591 #define MC_RPB_BIF_CNTL__XPB_SWITCH_NUM_MASK 0xff00 3592 #define MC_RPB_BIF_CNTL__XPB_SWITCH_NUM__SHIFT 0x8 3593 #define MC_RPB_WR_SWITCH_CNTL__QUEUE0_SWITCH_NUM_MASK 0xff 3594 #define MC_RPB_WR_SWITCH_CNTL__QUEUE0_SWITCH_NUM__SHIFT 0x0 3595 #define MC_RPB_WR_SWITCH_CNTL__QUEUE1_SWITCH_NUM_MASK 0xff00 3596 #define MC_RPB_WR_SWITCH_CNTL__QUEUE1_SWITCH_NUM__SHIFT 0x8 3597 #define MC_RPB_WR_SWITCH_CNTL__QUEUE2_SWITCH_NUM_MASK 0xff0000 3598 #define MC_RPB_WR_SWITCH_CNTL__QUEUE2_SWITCH_NUM__SHIFT 0x10 3599 #define MC_RPB_WR_SWITCH_CNTL__QUEUE3_SWITCH_NUM_MASK 0xff000000 3600 #define MC_RPB_WR_SWITCH_CNTL__QUEUE3_SWITCH_NUM__SHIFT 0x18 3601 #define MC_RPB_WR_COMBINE_CNTL__WC_ENABLE_MASK 0x1 3602 #define MC_RPB_WR_COMBINE_CNTL__WC_ENABLE__SHIFT 0x0 3603 #define MC_RPB_WR_COMBINE_CNTL__WC_MAX_PACKET_SIZE_MASK 0x6 3604 #define MC_RPB_WR_COMBINE_CNTL__WC_MAX_PACKET_SIZE__SHIFT 0x1 3605 #define MC_RPB_WR_COMBINE_CNTL__WC_FLUSH_TIMER_MASK 0x78 3606 #define MC_RPB_WR_COMBINE_CNTL__WC_FLUSH_TIMER__SHIFT 0x3 3607 #define MC_RPB_WR_COMBINE_CNTL__WC_ALIGN_MASK 0x80 3608 #define MC_RPB_WR_COMBINE_CNTL__WC_ALIGN__SHIFT 0x7 3609 #define MC_RPB_RD_SWITCH_CNTL__QUEUE0_SWITCH_NUM_MASK 0xff 3610 #define MC_RPB_RD_SWITCH_CNTL__QUEUE0_SWITCH_NUM__SHIFT 0x0 3611 #define MC_RPB_RD_SWITCH_CNTL__QUEUE1_SWITCH_NUM_MASK 0xff00 3612 #define MC_RPB_RD_SWITCH_CNTL__QUEUE1_SWITCH_NUM__SHIFT 0x8 3613 #define MC_RPB_RD_SWITCH_CNTL__QUEUE2_SWITCH_NUM_MASK 0xff0000 3614 #define MC_RPB_RD_SWITCH_CNTL__QUEUE2_SWITCH_NUM__SHIFT 0x10 3615 #define MC_RPB_RD_SWITCH_CNTL__QUEUE3_SWITCH_NUM_MASK 0xff000000 3616 #define MC_RPB_RD_SWITCH_CNTL__QUEUE3_SWITCH_NUM__SHIFT 0x18 3617 #define MC_RPB_CID_QUEUE_WR__CLIENT_ID_MASK 0xff 3618 #define MC_RPB_CID_QUEUE_WR__CLIENT_ID__SHIFT 0x0 3619 #define MC_RPB_CID_QUEUE_WR__UPDATE_MODE_MASK 0x100 3620 #define MC_RPB_CID_QUEUE_WR__UPDATE_MODE__SHIFT 0x8 3621 #define MC_RPB_CID_QUEUE_WR__WRITE_QUEUE_MASK 0x600 3622 #define MC_RPB_CID_QUEUE_WR__WRITE_QUEUE__SHIFT 0x9 3623 #define MC_RPB_CID_QUEUE_WR__READ_QUEUE_MASK 0x1800 3624 #define MC_RPB_CID_QUEUE_WR__READ_QUEUE__SHIFT 0xb 3625 #define MC_RPB_CID_QUEUE_WR__UPDATE_MASK 0x2000 3626 #define MC_RPB_CID_QUEUE_WR__UPDATE__SHIFT 0xd 3627 #define MC_RPB_CID_QUEUE_RD__CLIENT_ID_MASK 0xff 3628 #define MC_RPB_CID_QUEUE_RD__CLIENT_ID__SHIFT 0x0 3629 #define MC_RPB_CID_QUEUE_RD__WRITE_QUEUE_MASK 0x300 3630 #define MC_RPB_CID_QUEUE_RD__WRITE_QUEUE__SHIFT 0x8 3631 #define MC_RPB_CID_QUEUE_RD__READ_QUEUE_MASK 0xc00 3632 #define MC_RPB_CID_QUEUE_RD__READ_QUEUE__SHIFT 0xa 3633 #define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_SELECT_MASK 0x3 3634 #define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 3635 #define MC_RPB_PERF_COUNTER_CNTL__CLEAR_SELECTED_PERF_COUNTER_MASK 0x4 3636 #define MC_RPB_PERF_COUNTER_CNTL__CLEAR_SELECTED_PERF_COUNTER__SHIFT 0x2 3637 #define MC_RPB_PERF_COUNTER_CNTL__CLEAR_ALL_PERF_COUNTERS_MASK 0x8 3638 #define MC_RPB_PERF_COUNTER_CNTL__CLEAR_ALL_PERF_COUNTERS__SHIFT 0x3 3639 #define MC_RPB_PERF_COUNTER_CNTL__STOP_ON_COUNTER_SATURATION_MASK 0x10 3640 #define MC_RPB_PERF_COUNTER_CNTL__STOP_ON_COUNTER_SATURATION__SHIFT 0x4 3641 #define MC_RPB_PERF_COUNTER_CNTL__ENABLE_PERF_COUNTERS_MASK 0x1e0 3642 #define MC_RPB_PERF_COUNTER_CNTL__ENABLE_PERF_COUNTERS__SHIFT 0x5 3643 #define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_0_MASK 0x3e00 3644 #define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_0__SHIFT 0x9 3645 #define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_1_MASK 0x7c000 3646 #define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_1__SHIFT 0xe 3647 #define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_2_MASK 0xf80000 3648 #define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_2__SHIFT 0x13 3649 #define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_3_MASK 0x1f000000 3650 #define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_3__SHIFT 0x18 3651 #define MC_RPB_PERF_COUNTER_STATUS__PERFORMANCE_COUNTER_VALUE_MASK 0xffffffff 3652 #define MC_RPB_PERF_COUNTER_STATUS__PERFORMANCE_COUNTER_VALUE__SHIFT 0x0 3653 #define MC_RPB_CID_QUEUE_EX__START_MASK 0x1 3654 #define MC_RPB_CID_QUEUE_EX__START__SHIFT 0x0 3655 #define MC_RPB_CID_QUEUE_EX__OFFSET_MASK 0x3e 3656 #define MC_RPB_CID_QUEUE_EX__OFFSET__SHIFT 0x1 3657 #define MC_RPB_CID_QUEUE_EX_DATA__WRITE_ENTRIES_MASK 0xffff 3658 #define MC_RPB_CID_QUEUE_EX_DATA__WRITE_ENTRIES__SHIFT 0x0 3659 #define MC_RPB_CID_QUEUE_EX_DATA__READ_ENTRIES_MASK 0xffff0000 3660 #define MC_RPB_CID_QUEUE_EX_DATA__READ_ENTRIES__SHIFT 0x10 3661 #define MC_RPB_TCI_CNTL__TCI_ENABLE_MASK 0x1 3662 #define MC_RPB_TCI_CNTL__TCI_ENABLE__SHIFT 0x0 3663 #define MC_RPB_TCI_CNTL__TCI_POLICY_MASK 0x6 3664 #define MC_RPB_TCI_CNTL__TCI_POLICY__SHIFT 0x1 3665 #define MC_RPB_TCI_CNTL__TCI_VOL_MASK 0x8 3666 #define MC_RPB_TCI_CNTL__TCI_VOL__SHIFT 0x3 3667 #define MC_RPB_TCI_CNTL__TCI_VMID_MASK 0xf0 3668 #define MC_RPB_TCI_CNTL__TCI_VMID__SHIFT 0x4 3669 #define MC_RPB_TCI_CNTL__TCI_REQ_CREDITS_MASK 0xff00 3670 #define MC_RPB_TCI_CNTL__TCI_REQ_CREDITS__SHIFT 0x8 3671 #define MC_RPB_TCI_CNTL__TCI_MAX_WRITES_MASK 0xff0000 3672 #define MC_RPB_TCI_CNTL__TCI_MAX_WRITES__SHIFT 0x10 3673 #define MC_RPB_TCI_CNTL__TCI_MAX_READS_MASK 0xff000000 3674 #define MC_RPB_TCI_CNTL__TCI_MAX_READS__SHIFT 0x18 3675 #define MC_RPB_TCI_CNTL2__TCI_POLICY_MASK 0x1 3676 #define MC_RPB_TCI_CNTL2__TCI_POLICY__SHIFT 0x0 3677 #define MC_RPB_TCI_CNTL2__TCI_MTYPE_MASK 0x6 3678 #define MC_RPB_TCI_CNTL2__TCI_MTYPE__SHIFT 0x1 3679 #define MC_RPB_TCI_CNTL2__TCI_SNOOP_MASK 0x8 3680 #define MC_RPB_TCI_CNTL2__TCI_SNOOP__SHIFT 0x3 3681 #define MC_RPB_TCI_CNTL2__TCI_PHYSICAL_MASK 0x10 3682 #define MC_RPB_TCI_CNTL2__TCI_PHYSICAL__SHIFT 0x4 3683 #define MC_RPB_TCI_CNTL2__TCI_PERF_CNTR_EN_MASK 0x20 3684 #define MC_RPB_TCI_CNTL2__TCI_PERF_CNTR_EN__SHIFT 0x5 3685 #define MC_RPB_TCI_CNTL2__TCI_EXE_MASK 0x40 3686 #define MC_RPB_TCI_CNTL2__TCI_EXE__SHIFT 0x6 3687 #define MC_SHARED_CHMAP__CHAN0_MASK 0xf 3688 #define MC_SHARED_CHMAP__CHAN0__SHIFT 0x0 3689 #define MC_SHARED_CHMAP__CHAN1_MASK 0xf0 3690 #define MC_SHARED_CHMAP__CHAN1__SHIFT 0x4 3691 #define MC_SHARED_CHMAP__CHAN2_MASK 0xf00 3692 #define MC_SHARED_CHMAP__CHAN2__SHIFT 0x8 3693 #define MC_SHARED_CHMAP__NOOFCHAN_MASK 0xf000 3694 #define MC_SHARED_CHMAP__NOOFCHAN__SHIFT 0xc 3695 #define MC_SHARED_CHMAP__CHAN3_MASK 0xf0000 3696 #define MC_SHARED_CHMAP__CHAN3__SHIFT 0x10 3697 #define MC_SHARED_CHMAP__CHAN4_MASK 0xf00000 3698 #define MC_SHARED_CHMAP__CHAN4__SHIFT 0x14 3699 #define MC_SHARED_CHREMAP__CHAN0_MASK 0xf 3700 #define MC_SHARED_CHREMAP__CHAN0__SHIFT 0x0 3701 #define MC_SHARED_CHREMAP__CHAN1_MASK 0xf0 3702 #define MC_SHARED_CHREMAP__CHAN1__SHIFT 0x4 3703 #define MC_SHARED_CHREMAP__CHAN2_MASK 0xf00 3704 #define MC_SHARED_CHREMAP__CHAN2__SHIFT 0x8 3705 #define MC_SHARED_CHREMAP__CHAN3_MASK 0xf000 3706 #define MC_SHARED_CHREMAP__CHAN3__SHIFT 0xc 3707 #define MC_SHARED_CHREMAP__CHAN4_MASK 0xf0000 3708 #define MC_SHARED_CHREMAP__CHAN4__SHIFT 0x10 3709 #define MC_SHARED_CHREMAP__CHAN5_MASK 0xf00000 3710 #define MC_SHARED_CHREMAP__CHAN5__SHIFT 0x14 3711 #define MC_SHARED_CHREMAP__CHAN6_MASK 0xf000000 3712 #define MC_SHARED_CHREMAP__CHAN6__SHIFT 0x18 3713 #define MC_SHARED_CHREMAP__CHAN7_MASK 0xf0000000 3714 #define MC_SHARED_CHREMAP__CHAN7__SHIFT 0x1c 3715 #define MC_RD_GRP_GFX__CP_MASK 0xf 3716 #define MC_RD_GRP_GFX__CP__SHIFT 0x0 3717 #define MC_RD_GRP_GFX__SH_MASK 0xf0 3718 #define MC_RD_GRP_GFX__SH__SHIFT 0x4 3719 #define MC_RD_GRP_GFX__IA_MASK 0xf00 3720 #define MC_RD_GRP_GFX__IA__SHIFT 0x8 3721 #define MC_RD_GRP_GFX__ACPG_MASK 0xf000 3722 #define MC_RD_GRP_GFX__ACPG__SHIFT 0xc 3723 #define MC_RD_GRP_GFX__ACPO_MASK 0xf0000 3724 #define MC_RD_GRP_GFX__ACPO__SHIFT 0x10 3725 #define MC_RD_GRP_GFX__XDMAM_MASK 0xf00000 3726 #define MC_RD_GRP_GFX__XDMAM__SHIFT 0x14 3727 #define MC_RD_GRP_GFX__ISP_MASK 0xf000000 3728 #define MC_RD_GRP_GFX__ISP__SHIFT 0x18 3729 #define MC_RD_GRP_GFX__VP8_MASK 0xf0000000 3730 #define MC_RD_GRP_GFX__VP8__SHIFT 0x1c 3731 #define MC_WR_GRP_GFX__CP_MASK 0xf 3732 #define MC_WR_GRP_GFX__CP__SHIFT 0x0 3733 #define MC_WR_GRP_GFX__SH_MASK 0xf0 3734 #define MC_WR_GRP_GFX__SH__SHIFT 0x4 3735 #define MC_WR_GRP_GFX__ACPG_MASK 0xf00 3736 #define MC_WR_GRP_GFX__ACPG__SHIFT 0x8 3737 #define MC_WR_GRP_GFX__ACPO_MASK 0xf000 3738 #define MC_WR_GRP_GFX__ACPO__SHIFT 0xc 3739 #define MC_WR_GRP_GFX__ISP_MASK 0xf0000 3740 #define MC_WR_GRP_GFX__ISP__SHIFT 0x10 3741 #define MC_WR_GRP_GFX__VP8_MASK 0xf00000 3742 #define MC_WR_GRP_GFX__VP8__SHIFT 0x14 3743 #define MC_WR_GRP_GFX__XDMA_MASK 0xf000000 3744 #define MC_WR_GRP_GFX__XDMA__SHIFT 0x18 3745 #define MC_WR_GRP_GFX__XDMAM_MASK 0xf0000000 3746 #define MC_WR_GRP_GFX__XDMAM__SHIFT 0x1c 3747 #define MC_RD_GRP_SYS__RLC_MASK 0xf 3748 #define MC_RD_GRP_SYS__RLC__SHIFT 0x0 3749 #define MC_RD_GRP_SYS__VMC_MASK 0xf0 3750 #define MC_RD_GRP_SYS__VMC__SHIFT 0x4 3751 #define MC_RD_GRP_SYS__SDMA1_MASK 0xf00 3752 #define MC_RD_GRP_SYS__SDMA1__SHIFT 0x8 3753 #define MC_RD_GRP_SYS__DMIF_MASK 0xf000 3754 #define MC_RD_GRP_SYS__DMIF__SHIFT 0xc 3755 #define MC_RD_GRP_SYS__MCIF_MASK 0xf0000 3756 #define MC_RD_GRP_SYS__MCIF__SHIFT 0x10 3757 #define MC_RD_GRP_SYS__SMU_MASK 0xf00000 3758 #define MC_RD_GRP_SYS__SMU__SHIFT 0x14 3759 #define MC_RD_GRP_SYS__VCE0_MASK 0xf000000 3760 #define MC_RD_GRP_SYS__VCE0__SHIFT 0x18 3761 #define MC_RD_GRP_SYS__VCE1_MASK 0xf0000000 3762 #define MC_RD_GRP_SYS__VCE1__SHIFT 0x1c 3763 #define MC_WR_GRP_SYS__IH_MASK 0xf 3764 #define MC_WR_GRP_SYS__IH__SHIFT 0x0 3765 #define MC_WR_GRP_SYS__MCIF_MASK 0xf0 3766 #define MC_WR_GRP_SYS__MCIF__SHIFT 0x4 3767 #define MC_WR_GRP_SYS__RLC_MASK 0xf00 3768 #define MC_WR_GRP_SYS__RLC__SHIFT 0x8 3769 #define MC_WR_GRP_SYS__SAMMSP_MASK 0xf000 3770 #define MC_WR_GRP_SYS__SAMMSP__SHIFT 0xc 3771 #define MC_WR_GRP_SYS__SMU_MASK 0xf0000 3772 #define MC_WR_GRP_SYS__SMU__SHIFT 0x10 3773 #define MC_WR_GRP_SYS__SDMA1_MASK 0xf00000 3774 #define MC_WR_GRP_SYS__SDMA1__SHIFT 0x14 3775 #define MC_WR_GRP_SYS__VCE0_MASK 0xf000000 3776 #define MC_WR_GRP_SYS__VCE0__SHIFT 0x18 3777 #define MC_WR_GRP_SYS__VCE1_MASK 0xf0000000 3778 #define MC_WR_GRP_SYS__VCE1__SHIFT 0x1c 3779 #define MC_RD_GRP_OTH__UVD_EXT0_MASK 0xf 3780 #define MC_RD_GRP_OTH__UVD_EXT0__SHIFT 0x0 3781 #define MC_RD_GRP_OTH__SDMA0_MASK 0xf0 3782 #define MC_RD_GRP_OTH__SDMA0__SHIFT 0x4 3783 #define MC_RD_GRP_OTH__HDP_MASK 0xf00 3784 #define MC_RD_GRP_OTH__HDP__SHIFT 0x8 3785 #define MC_RD_GRP_OTH__SEM_MASK 0xf000 3786 #define MC_RD_GRP_OTH__SEM__SHIFT 0xc 3787 #define MC_RD_GRP_OTH__UMC_MASK 0xf0000 3788 #define MC_RD_GRP_OTH__UMC__SHIFT 0x10 3789 #define MC_RD_GRP_OTH__UVD_MASK 0xf00000 3790 #define MC_RD_GRP_OTH__UVD__SHIFT 0x14 3791 #define MC_RD_GRP_OTH__UVD_EXT1_MASK 0xf000000 3792 #define MC_RD_GRP_OTH__UVD_EXT1__SHIFT 0x18 3793 #define MC_RD_GRP_OTH__SAMMSP_MASK 0xf0000000 3794 #define MC_RD_GRP_OTH__SAMMSP__SHIFT 0x1c 3795 #define MC_WR_GRP_OTH__UVD_EXT0_MASK 0xf 3796 #define MC_WR_GRP_OTH__UVD_EXT0__SHIFT 0x0 3797 #define MC_WR_GRP_OTH__SDMA0_MASK 0xf0 3798 #define MC_WR_GRP_OTH__SDMA0__SHIFT 0x4 3799 #define MC_WR_GRP_OTH__HDP_MASK 0xf00 3800 #define MC_WR_GRP_OTH__HDP__SHIFT 0x8 3801 #define MC_WR_GRP_OTH__SEM_MASK 0xf000 3802 #define MC_WR_GRP_OTH__SEM__SHIFT 0xc 3803 #define MC_WR_GRP_OTH__UMC_MASK 0xf0000 3804 #define MC_WR_GRP_OTH__UMC__SHIFT 0x10 3805 #define MC_WR_GRP_OTH__UVD_MASK 0xf00000 3806 #define MC_WR_GRP_OTH__UVD__SHIFT 0x14 3807 #define MC_WR_GRP_OTH__XDP_MASK 0xf000000 3808 #define MC_WR_GRP_OTH__XDP__SHIFT 0x18 3809 #define MC_WR_GRP_OTH__UVD_EXT1_MASK 0xf0000000 3810 #define MC_WR_GRP_OTH__UVD_EXT1__SHIFT 0x1c 3811 #define MC_VM_FB_LOCATION__FB_BASE_MASK 0xffff 3812 #define MC_VM_FB_LOCATION__FB_BASE__SHIFT 0x0 3813 #define MC_VM_FB_LOCATION__FB_TOP_MASK 0xffff0000 3814 #define MC_VM_FB_LOCATION__FB_TOP__SHIFT 0x10 3815 #define MC_VM_AGP_TOP__AGP_TOP_MASK 0x3ffff 3816 #define MC_VM_AGP_TOP__AGP_TOP__SHIFT 0x0 3817 #define MC_VM_AGP_BOT__AGP_BOT_MASK 0x3ffff 3818 #define MC_VM_AGP_BOT__AGP_BOT__SHIFT 0x0 3819 #define MC_VM_AGP_BASE__AGP_BASE_MASK 0x3ffff 3820 #define MC_VM_AGP_BASE__AGP_BASE__SHIFT 0x0 3821 #define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff 3822 #define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0 3823 #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff 3824 #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0 3825 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff 3826 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 3827 #define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_0_MODE_MASK 0x3 3828 #define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_0_MODE__SHIFT 0x0 3829 #define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_1_MODE_MASK 0xc 3830 #define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_1_MODE__SHIFT 0x2 3831 #define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_2_MODE_MASK 0x30 3832 #define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_2_MODE__SHIFT 0x4 3833 #define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_3_MODE_MASK 0xc0 3834 #define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_3_MODE__SHIFT 0x6 3835 #define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_LOCAL_MASK 0x100 3836 #define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_LOCAL__SHIFT 0x8 3837 #define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_SYSTEM_MASK 0x200 3838 #define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_SYSTEM__SHIFT 0x9 3839 #define MC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff 3840 #define MC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0 3841 #define MC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff 3842 #define MC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0 3843 #define MC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff 3844 #define MC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0 3845 #define MC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff 3846 #define MC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0 3847 #define MC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff 3848 #define MC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0 3849 #define MC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff 3850 #define MC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0 3851 #define MC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff 3852 #define MC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0 3853 #define MC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff 3854 #define MC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0 3855 #define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x1 3856 #define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0 3857 #define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_FRAGMENT_PROCESSING_MASK 0x2 3858 #define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_FRAGMENT_PROCESSING__SHIFT 0x1 3859 #define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x18 3860 #define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3 3861 #define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x20 3862 #define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5 3863 #define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x40 3864 #define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6 3865 #define MC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK 0x780 3866 #define MC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT 0x7 3867 #define MC_VM_FB_OFFSET__FB_OFFSET_MASK 0x3ffff 3868 #define MC_VM_FB_OFFSET__FB_OFFSET__SHIFT 0x0 3869 #define MC_VM_STEERING__DEFAULT_STEERING_MASK 0x3 3870 #define MC_VM_STEERING__DEFAULT_STEERING__SHIFT 0x0 3871 #define MC_SHARED_CHREMAP2__CHAN8_MASK 0xf 3872 #define MC_SHARED_CHREMAP2__CHAN8__SHIFT 0x0 3873 #define MC_SHARED_CHREMAP2__CHAN9_MASK 0xf0 3874 #define MC_SHARED_CHREMAP2__CHAN9__SHIFT 0x4 3875 #define MC_SHARED_CHREMAP2__CHAN10_MASK 0xf00 3876 #define MC_SHARED_CHREMAP2__CHAN10__SHIFT 0x8 3877 #define MC_SHARED_CHREMAP2__CHAN11_MASK 0xf000 3878 #define MC_SHARED_CHREMAP2__CHAN11__SHIFT 0xc 3879 #define MC_SHARED_CHREMAP2__CHAN12_MASK 0xf0000 3880 #define MC_SHARED_CHREMAP2__CHAN12__SHIFT 0x10 3881 #define MC_SHARED_CHREMAP2__CHAN13_MASK 0xf00000 3882 #define MC_SHARED_CHREMAP2__CHAN13__SHIFT 0x14 3883 #define MC_SHARED_CHREMAP2__CHAN14_MASK 0xf000000 3884 #define MC_SHARED_CHREMAP2__CHAN14__SHIFT 0x18 3885 #define MC_SHARED_CHREMAP2__CHAN15_MASK 0xf0000000 3886 #define MC_SHARED_CHREMAP2__CHAN15__SHIFT 0x1c 3887 #define MC_SHARED_VF_ENABLE__VF_ENABLE_MASK 0x1 3888 #define MC_SHARED_VF_ENABLE__VF_ENABLE__SHIFT 0x0 3889 #define MC_SHARED_VIRT_RESET_REQ__VF_MASK 0xffff 3890 #define MC_SHARED_VIRT_RESET_REQ__VF__SHIFT 0x0 3891 #define MC_SHARED_VIRT_RESET_REQ__PF_MASK 0x80000000 3892 #define MC_SHARED_VIRT_RESET_REQ__PF__SHIFT 0x1f 3893 #define MC_SHARED_ACTIVE_FCN_ID__VFID_MASK 0xf 3894 #define MC_SHARED_ACTIVE_FCN_ID__VFID__SHIFT 0x0 3895 #define MC_SHARED_ACTIVE_FCN_ID__VF_MASK 0x80000000 3896 #define MC_SHARED_ACTIVE_FCN_ID__VF__SHIFT 0x1f 3897 #define MC_CONFIG_MCD__MCD0_WR_ENABLE_MASK 0x1 3898 #define MC_CONFIG_MCD__MCD0_WR_ENABLE__SHIFT 0x0 3899 #define MC_CONFIG_MCD__MCD1_WR_ENABLE_MASK 0x2 3900 #define MC_CONFIG_MCD__MCD1_WR_ENABLE__SHIFT 0x1 3901 #define MC_CONFIG_MCD__MCD2_WR_ENABLE_MASK 0x4 3902 #define MC_CONFIG_MCD__MCD2_WR_ENABLE__SHIFT 0x2 3903 #define MC_CONFIG_MCD__MCD3_WR_ENABLE_MASK 0x8 3904 #define MC_CONFIG_MCD__MCD3_WR_ENABLE__SHIFT 0x3 3905 #define MC_CONFIG_MCD__MCD4_WR_ENABLE_MASK 0x10 3906 #define MC_CONFIG_MCD__MCD4_WR_ENABLE__SHIFT 0x4 3907 #define MC_CONFIG_MCD__MCD5_WR_ENABLE_MASK 0x20 3908 #define MC_CONFIG_MCD__MCD5_WR_ENABLE__SHIFT 0x5 3909 #define MC_CONFIG_MCD__MCD6_WR_ENABLE_MASK 0x40 3910 #define MC_CONFIG_MCD__MCD6_WR_ENABLE__SHIFT 0x6 3911 #define MC_CONFIG_MCD__MCD7_WR_ENABLE_MASK 0x80 3912 #define MC_CONFIG_MCD__MCD7_WR_ENABLE__SHIFT 0x7 3913 #define MC_CONFIG_MCD__MC_RD_ENABLE_MASK 0x700 3914 #define MC_CONFIG_MCD__MC_RD_ENABLE__SHIFT 0x8 3915 #define MC_CONFIG_MCD__MC_RD_ENABLE_SUB_MASK 0x800 3916 #define MC_CONFIG_MCD__MC_RD_ENABLE_SUB__SHIFT 0xb 3917 #define MC_CONFIG_MCD__ARB0_WR_ENABLE_MASK 0x1000 3918 #define MC_CONFIG_MCD__ARB0_WR_ENABLE__SHIFT 0xc 3919 #define MC_CONFIG_MCD__ARB1_WR_ENABLE_MASK 0x2000 3920 #define MC_CONFIG_MCD__ARB1_WR_ENABLE__SHIFT 0xd 3921 #define MC_CONFIG_MCD__MCD_INDEX_MODE_ENABLE_MASK 0x80000000 3922 #define MC_CONFIG_MCD__MCD_INDEX_MODE_ENABLE__SHIFT 0x1f 3923 #define MC_CG_CONFIG_MCD__MCD0_WR_ENABLE_MASK 0x1 3924 #define MC_CG_CONFIG_MCD__MCD0_WR_ENABLE__SHIFT 0x0 3925 #define MC_CG_CONFIG_MCD__MCD1_WR_ENABLE_MASK 0x2 3926 #define MC_CG_CONFIG_MCD__MCD1_WR_ENABLE__SHIFT 0x1 3927 #define MC_CG_CONFIG_MCD__MCD2_WR_ENABLE_MASK 0x4 3928 #define MC_CG_CONFIG_MCD__MCD2_WR_ENABLE__SHIFT 0x2 3929 #define MC_CG_CONFIG_MCD__MCD3_WR_ENABLE_MASK 0x8 3930 #define MC_CG_CONFIG_MCD__MCD3_WR_ENABLE__SHIFT 0x3 3931 #define MC_CG_CONFIG_MCD__MCD4_WR_ENABLE_MASK 0x10 3932 #define MC_CG_CONFIG_MCD__MCD4_WR_ENABLE__SHIFT 0x4 3933 #define MC_CG_CONFIG_MCD__MCD5_WR_ENABLE_MASK 0x20 3934 #define MC_CG_CONFIG_MCD__MCD5_WR_ENABLE__SHIFT 0x5 3935 #define MC_CG_CONFIG_MCD__MCD6_WR_ENABLE_MASK 0x40 3936 #define MC_CG_CONFIG_MCD__MCD6_WR_ENABLE__SHIFT 0x6 3937 #define MC_CG_CONFIG_MCD__MCD7_WR_ENABLE_MASK 0x80 3938 #define MC_CG_CONFIG_MCD__MCD7_WR_ENABLE__SHIFT 0x7 3939 #define MC_CG_CONFIG_MCD__MC_RD_ENABLE_MASK 0x700 3940 #define MC_CG_CONFIG_MCD__MC_RD_ENABLE__SHIFT 0x8 3941 #define MC_CG_CONFIG_MCD__MC_RD_ENABLE_SUB_MASK 0x800 3942 #define MC_CG_CONFIG_MCD__MC_RD_ENABLE_SUB__SHIFT 0xb 3943 #define MC_CG_CONFIG_MCD__INDEX_MASK 0x1fffe000 3944 #define MC_CG_CONFIG_MCD__INDEX__SHIFT 0xd 3945 #define MC_MEM_POWER_LS__LS_SETUP_MASK 0x3f 3946 #define MC_MEM_POWER_LS__LS_SETUP__SHIFT 0x0 3947 #define MC_MEM_POWER_LS__LS_HOLD_MASK 0xfc0 3948 #define MC_MEM_POWER_LS__LS_HOLD__SHIFT 0x6 3949 #define MC_SHARED_BLACKOUT_CNTL__BLACKOUT_MODE_MASK 0x7 3950 #define MC_SHARED_BLACKOUT_CNTL__BLACKOUT_MODE__SHIFT 0x0 3951 #define MC_SHARED_BLACKOUT_CNTL__BLACKOUT_SEQ_FREE_MASK 0x8 3952 #define MC_SHARED_BLACKOUT_CNTL__BLACKOUT_SEQ_FREE__SHIFT 0x3 3953 #define MC_SHARED_BLACKOUT_CNTL__BLACKOUT_MCD_NUM_MASK 0xff0 3954 #define MC_SHARED_BLACKOUT_CNTL__BLACKOUT_MCD_NUM__SHIFT 0x4 3955 #define MC_SHARED_BLACKOUT_CNTL__FREE_TIE_HIGH_MASK 0x1000 3956 #define MC_SHARED_BLACKOUT_CNTL__FREE_TIE_HIGH__SHIFT 0xc 3957 #define MC_SHARED_BLACKOUT_CNTL__SRBM_DUMMY_READ_RETURN_MASK 0x2000 3958 #define MC_SHARED_BLACKOUT_CNTL__SRBM_DUMMY_READ_RETURN__SHIFT 0xd 3959 #define MC_VM_MB_L1_TLB0_DEBUG__INVALIDATE_L1_TLB_MASK 0x1 3960 #define MC_VM_MB_L1_TLB0_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0 3961 #define MC_VM_MB_L1_TLB0_DEBUG__SEND_FREE_AT_RTN_MASK 0x100 3962 #define MC_VM_MB_L1_TLB0_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8 3963 #define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00 3964 #define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9 3965 #define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000 3966 #define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc 3967 #define MC_VM_MB_L1_TLB0_DEBUG__L1_TLB_DEBUG_MASK 0x78000 3968 #define MC_VM_MB_L1_TLB0_DEBUG__L1_TLB_DEBUG__SHIFT 0xf 3969 #define MC_VM_MB_L1_TLB0_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000 3970 #define MC_VM_MB_L1_TLB0_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13 3971 #define MC_VM_MB_L1_TLB1_DEBUG__INVALIDATE_L1_TLB_MASK 0x1 3972 #define MC_VM_MB_L1_TLB1_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0 3973 #define MC_VM_MB_L1_TLB1_DEBUG__SEND_FREE_AT_RTN_MASK 0x100 3974 #define MC_VM_MB_L1_TLB1_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8 3975 #define MC_VM_MB_L1_TLB1_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00 3976 #define MC_VM_MB_L1_TLB1_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9 3977 #define MC_VM_MB_L1_TLB1_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000 3978 #define MC_VM_MB_L1_TLB1_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc 3979 #define MC_VM_MB_L1_TLB1_DEBUG__L1_TLB_DEBUG_MASK 0x78000 3980 #define MC_VM_MB_L1_TLB1_DEBUG__L1_TLB_DEBUG__SHIFT 0xf 3981 #define MC_VM_MB_L1_TLB1_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000 3982 #define MC_VM_MB_L1_TLB1_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13 3983 #define MC_VM_MB_L1_TLB2_DEBUG__INVALIDATE_L1_TLB_MASK 0x1 3984 #define MC_VM_MB_L1_TLB2_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0 3985 #define MC_VM_MB_L1_TLB2_DEBUG__SEND_FREE_AT_RTN_MASK 0x100 3986 #define MC_VM_MB_L1_TLB2_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8 3987 #define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00 3988 #define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9 3989 #define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000 3990 #define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc 3991 #define MC_VM_MB_L1_TLB2_DEBUG__L1_TLB_DEBUG_MASK 0x78000 3992 #define MC_VM_MB_L1_TLB2_DEBUG__L1_TLB_DEBUG__SHIFT 0xf 3993 #define MC_VM_MB_L1_TLB2_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000 3994 #define MC_VM_MB_L1_TLB2_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13 3995 #define MC_VM_MB_L1_TLB0_STATUS__BUSY_MASK 0x1 3996 #define MC_VM_MB_L1_TLB0_STATUS__BUSY__SHIFT 0x0 3997 #define MC_VM_MB_L1_TLB1_STATUS__BUSY_MASK 0x1 3998 #define MC_VM_MB_L1_TLB1_STATUS__BUSY__SHIFT 0x0 3999 #define MC_VM_MB_L1_TLB2_STATUS__BUSY_MASK 0x1 4000 #define MC_VM_MB_L1_TLB2_STATUS__BUSY__SHIFT 0x0 4001 #define MC_VM_MB_L2ARBITER_L2_CREDITS__L2_IF_CREDITS_MASK 0x3f 4002 #define MC_VM_MB_L2ARBITER_L2_CREDITS__L2_IF_CREDITS__SHIFT 0x0 4003 #define MC_VM_MB_L1_TLB3_DEBUG__INVALIDATE_L1_TLB_MASK 0x1 4004 #define MC_VM_MB_L1_TLB3_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0 4005 #define MC_VM_MB_L1_TLB3_DEBUG__SEND_FREE_AT_RTN_MASK 0x100 4006 #define MC_VM_MB_L1_TLB3_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8 4007 #define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00 4008 #define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9 4009 #define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000 4010 #define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc 4011 #define MC_VM_MB_L1_TLB3_DEBUG__L1_TLB_DEBUG_MASK 0x78000 4012 #define MC_VM_MB_L1_TLB3_DEBUG__L1_TLB_DEBUG__SHIFT 0xf 4013 #define MC_VM_MB_L1_TLB3_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000 4014 #define MC_VM_MB_L1_TLB3_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13 4015 #define MC_VM_MB_L1_TLB3_STATUS__BUSY_MASK 0x1 4016 #define MC_VM_MB_L1_TLB3_STATUS__BUSY__SHIFT 0x0 4017 #define MC_VM_MD_L1_TLB0_DEBUG__INVALIDATE_L1_TLB_MASK 0x1 4018 #define MC_VM_MD_L1_TLB0_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0 4019 #define MC_VM_MD_L1_TLB0_DEBUG__SEND_FREE_AT_RTN_MASK 0x100 4020 #define MC_VM_MD_L1_TLB0_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8 4021 #define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00 4022 #define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9 4023 #define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000 4024 #define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc 4025 #define MC_VM_MD_L1_TLB0_DEBUG__L1_TLB_DEBUG_MASK 0x78000 4026 #define MC_VM_MD_L1_TLB0_DEBUG__L1_TLB_DEBUG__SHIFT 0xf 4027 #define MC_VM_MD_L1_TLB0_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000 4028 #define MC_VM_MD_L1_TLB0_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13 4029 #define MC_VM_MD_L1_TLB1_DEBUG__INVALIDATE_L1_TLB_MASK 0x1 4030 #define MC_VM_MD_L1_TLB1_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0 4031 #define MC_VM_MD_L1_TLB1_DEBUG__SEND_FREE_AT_RTN_MASK 0x100 4032 #define MC_VM_MD_L1_TLB1_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8 4033 #define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00 4034 #define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9 4035 #define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000 4036 #define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc 4037 #define MC_VM_MD_L1_TLB1_DEBUG__L1_TLB_DEBUG_MASK 0x78000 4038 #define MC_VM_MD_L1_TLB1_DEBUG__L1_TLB_DEBUG__SHIFT 0xf 4039 #define MC_VM_MD_L1_TLB1_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000 4040 #define MC_VM_MD_L1_TLB1_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13 4041 #define MC_VM_MD_L1_TLB2_DEBUG__INVALIDATE_L1_TLB_MASK 0x1 4042 #define MC_VM_MD_L1_TLB2_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0 4043 #define MC_VM_MD_L1_TLB2_DEBUG__SEND_FREE_AT_RTN_MASK 0x100 4044 #define MC_VM_MD_L1_TLB2_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8 4045 #define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00 4046 #define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9 4047 #define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000 4048 #define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc 4049 #define MC_VM_MD_L1_TLB2_DEBUG__L1_TLB_DEBUG_MASK 0x78000 4050 #define MC_VM_MD_L1_TLB2_DEBUG__L1_TLB_DEBUG__SHIFT 0xf 4051 #define MC_VM_MD_L1_TLB2_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000 4052 #define MC_VM_MD_L1_TLB2_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13 4053 #define MC_VM_MD_L1_TLB0_STATUS__BUSY_MASK 0x1 4054 #define MC_VM_MD_L1_TLB0_STATUS__BUSY__SHIFT 0x0 4055 #define MC_VM_MD_L1_TLB1_STATUS__BUSY_MASK 0x1 4056 #define MC_VM_MD_L1_TLB1_STATUS__BUSY__SHIFT 0x0 4057 #define MC_VM_MD_L1_TLB2_STATUS__BUSY_MASK 0x1 4058 #define MC_VM_MD_L1_TLB2_STATUS__BUSY__SHIFT 0x0 4059 #define MC_VM_MD_L2ARBITER_L2_CREDITS__L2_IF_CREDITS_MASK 0x3f 4060 #define MC_VM_MD_L2ARBITER_L2_CREDITS__L2_IF_CREDITS__SHIFT 0x0 4061 #define MC_VM_MD_L1_TLB3_DEBUG__INVALIDATE_L1_TLB_MASK 0x1 4062 #define MC_VM_MD_L1_TLB3_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0 4063 #define MC_VM_MD_L1_TLB3_DEBUG__SEND_FREE_AT_RTN_MASK 0x100 4064 #define MC_VM_MD_L1_TLB3_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8 4065 #define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00 4066 #define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9 4067 #define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000 4068 #define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc 4069 #define MC_VM_MD_L1_TLB3_DEBUG__L1_TLB_DEBUG_MASK 0x78000 4070 #define MC_VM_MD_L1_TLB3_DEBUG__L1_TLB_DEBUG__SHIFT 0xf 4071 #define MC_VM_MD_L1_TLB3_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000 4072 #define MC_VM_MD_L1_TLB3_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13 4073 #define MC_VM_MD_L1_TLB3_STATUS__BUSY_MASK 0x1 4074 #define MC_VM_MD_L1_TLB3_STATUS__BUSY__SHIFT 0x0 4075 #define MC_XPB_RTR_SRC_APRTR0__BASE_ADDR_MASK 0x1ffffff 4076 #define MC_XPB_RTR_SRC_APRTR0__BASE_ADDR__SHIFT 0x0 4077 #define MC_XPB_RTR_SRC_APRTR1__BASE_ADDR_MASK 0x1ffffff 4078 #define MC_XPB_RTR_SRC_APRTR1__BASE_ADDR__SHIFT 0x0 4079 #define MC_XPB_RTR_SRC_APRTR2__BASE_ADDR_MASK 0x1ffffff 4080 #define MC_XPB_RTR_SRC_APRTR2__BASE_ADDR__SHIFT 0x0 4081 #define MC_XPB_RTR_SRC_APRTR3__BASE_ADDR_MASK 0x1ffffff 4082 #define MC_XPB_RTR_SRC_APRTR3__BASE_ADDR__SHIFT 0x0 4083 #define MC_XPB_RTR_SRC_APRTR4__BASE_ADDR_MASK 0x1ffffff 4084 #define MC_XPB_RTR_SRC_APRTR4__BASE_ADDR__SHIFT 0x0 4085 #define MC_XPB_RTR_SRC_APRTR5__BASE_ADDR_MASK 0x1ffffff 4086 #define MC_XPB_RTR_SRC_APRTR5__BASE_ADDR__SHIFT 0x0 4087 #define MC_XPB_RTR_SRC_APRTR6__BASE_ADDR_MASK 0x1ffffff 4088 #define MC_XPB_RTR_SRC_APRTR6__BASE_ADDR__SHIFT 0x0 4089 #define MC_XPB_RTR_SRC_APRTR7__BASE_ADDR_MASK 0x1ffffff 4090 #define MC_XPB_RTR_SRC_APRTR7__BASE_ADDR__SHIFT 0x0 4091 #define MC_XPB_RTR_SRC_APRTR8__BASE_ADDR_MASK 0x1ffffff 4092 #define MC_XPB_RTR_SRC_APRTR8__BASE_ADDR__SHIFT 0x0 4093 #define MC_XPB_RTR_SRC_APRTR9__BASE_ADDR_MASK 0x1ffffff 4094 #define MC_XPB_RTR_SRC_APRTR9__BASE_ADDR__SHIFT 0x0 4095 #define MC_XPB_XDMA_RTR_SRC_APRTR0__BASE_ADDR_MASK 0x1ffffff 4096 #define MC_XPB_XDMA_RTR_SRC_APRTR0__BASE_ADDR__SHIFT 0x0 4097 #define MC_XPB_XDMA_RTR_SRC_APRTR1__BASE_ADDR_MASK 0x1ffffff 4098 #define MC_XPB_XDMA_RTR_SRC_APRTR1__BASE_ADDR__SHIFT 0x0 4099 #define MC_XPB_XDMA_RTR_SRC_APRTR2__BASE_ADDR_MASK 0x1ffffff 4100 #define MC_XPB_XDMA_RTR_SRC_APRTR2__BASE_ADDR__SHIFT 0x0 4101 #define MC_XPB_XDMA_RTR_SRC_APRTR3__BASE_ADDR_MASK 0x1ffffff 4102 #define MC_XPB_XDMA_RTR_SRC_APRTR3__BASE_ADDR__SHIFT 0x0 4103 #define MC_XPB_RTR_DEST_MAP0__NMR_MASK 0x1 4104 #define MC_XPB_RTR_DEST_MAP0__NMR__SHIFT 0x0 4105 #define MC_XPB_RTR_DEST_MAP0__DEST_OFFSET_MASK 0xffffe 4106 #define MC_XPB_RTR_DEST_MAP0__DEST_OFFSET__SHIFT 0x1 4107 #define MC_XPB_RTR_DEST_MAP0__DEST_SEL_MASK 0xf00000 4108 #define MC_XPB_RTR_DEST_MAP0__DEST_SEL__SHIFT 0x14 4109 #define MC_XPB_RTR_DEST_MAP0__DEST_SEL_RPB_MASK 0x1000000 4110 #define MC_XPB_RTR_DEST_MAP0__DEST_SEL_RPB__SHIFT 0x18 4111 #define MC_XPB_RTR_DEST_MAP0__SIDE_OK_MASK 0x2000000 4112 #define MC_XPB_RTR_DEST_MAP0__SIDE_OK__SHIFT 0x19 4113 #define MC_XPB_RTR_DEST_MAP0__APRTR_SIZE_MASK 0x7c000000 4114 #define MC_XPB_RTR_DEST_MAP0__APRTR_SIZE__SHIFT 0x1a 4115 #define MC_XPB_RTR_DEST_MAP1__NMR_MASK 0x1 4116 #define MC_XPB_RTR_DEST_MAP1__NMR__SHIFT 0x0 4117 #define MC_XPB_RTR_DEST_MAP1__DEST_OFFSET_MASK 0xffffe 4118 #define MC_XPB_RTR_DEST_MAP1__DEST_OFFSET__SHIFT 0x1 4119 #define MC_XPB_RTR_DEST_MAP1__DEST_SEL_MASK 0xf00000 4120 #define MC_XPB_RTR_DEST_MAP1__DEST_SEL__SHIFT 0x14 4121 #define MC_XPB_RTR_DEST_MAP1__DEST_SEL_RPB_MASK 0x1000000 4122 #define MC_XPB_RTR_DEST_MAP1__DEST_SEL_RPB__SHIFT 0x18 4123 #define MC_XPB_RTR_DEST_MAP1__SIDE_OK_MASK 0x2000000 4124 #define MC_XPB_RTR_DEST_MAP1__SIDE_OK__SHIFT 0x19 4125 #define MC_XPB_RTR_DEST_MAP1__APRTR_SIZE_MASK 0x7c000000 4126 #define MC_XPB_RTR_DEST_MAP1__APRTR_SIZE__SHIFT 0x1a 4127 #define MC_XPB_RTR_DEST_MAP2__NMR_MASK 0x1 4128 #define MC_XPB_RTR_DEST_MAP2__NMR__SHIFT 0x0 4129 #define MC_XPB_RTR_DEST_MAP2__DEST_OFFSET_MASK 0xffffe 4130 #define MC_XPB_RTR_DEST_MAP2__DEST_OFFSET__SHIFT 0x1 4131 #define MC_XPB_RTR_DEST_MAP2__DEST_SEL_MASK 0xf00000 4132 #define MC_XPB_RTR_DEST_MAP2__DEST_SEL__SHIFT 0x14 4133 #define MC_XPB_RTR_DEST_MAP2__DEST_SEL_RPB_MASK 0x1000000 4134 #define MC_XPB_RTR_DEST_MAP2__DEST_SEL_RPB__SHIFT 0x18 4135 #define MC_XPB_RTR_DEST_MAP2__SIDE_OK_MASK 0x2000000 4136 #define MC_XPB_RTR_DEST_MAP2__SIDE_OK__SHIFT 0x19 4137 #define MC_XPB_RTR_DEST_MAP2__APRTR_SIZE_MASK 0x7c000000 4138 #define MC_XPB_RTR_DEST_MAP2__APRTR_SIZE__SHIFT 0x1a 4139 #define MC_XPB_RTR_DEST_MAP3__NMR_MASK 0x1 4140 #define MC_XPB_RTR_DEST_MAP3__NMR__SHIFT 0x0 4141 #define MC_XPB_RTR_DEST_MAP3__DEST_OFFSET_MASK 0xffffe 4142 #define MC_XPB_RTR_DEST_MAP3__DEST_OFFSET__SHIFT 0x1 4143 #define MC_XPB_RTR_DEST_MAP3__DEST_SEL_MASK 0xf00000 4144 #define MC_XPB_RTR_DEST_MAP3__DEST_SEL__SHIFT 0x14 4145 #define MC_XPB_RTR_DEST_MAP3__DEST_SEL_RPB_MASK 0x1000000 4146 #define MC_XPB_RTR_DEST_MAP3__DEST_SEL_RPB__SHIFT 0x18 4147 #define MC_XPB_RTR_DEST_MAP3__SIDE_OK_MASK 0x2000000 4148 #define MC_XPB_RTR_DEST_MAP3__SIDE_OK__SHIFT 0x19 4149 #define MC_XPB_RTR_DEST_MAP3__APRTR_SIZE_MASK 0x7c000000 4150 #define MC_XPB_RTR_DEST_MAP3__APRTR_SIZE__SHIFT 0x1a 4151 #define MC_XPB_RTR_DEST_MAP4__NMR_MASK 0x1 4152 #define MC_XPB_RTR_DEST_MAP4__NMR__SHIFT 0x0 4153 #define MC_XPB_RTR_DEST_MAP4__DEST_OFFSET_MASK 0xffffe 4154 #define MC_XPB_RTR_DEST_MAP4__DEST_OFFSET__SHIFT 0x1 4155 #define MC_XPB_RTR_DEST_MAP4__DEST_SEL_MASK 0xf00000 4156 #define MC_XPB_RTR_DEST_MAP4__DEST_SEL__SHIFT 0x14 4157 #define MC_XPB_RTR_DEST_MAP4__DEST_SEL_RPB_MASK 0x1000000 4158 #define MC_XPB_RTR_DEST_MAP4__DEST_SEL_RPB__SHIFT 0x18 4159 #define MC_XPB_RTR_DEST_MAP4__SIDE_OK_MASK 0x2000000 4160 #define MC_XPB_RTR_DEST_MAP4__SIDE_OK__SHIFT 0x19 4161 #define MC_XPB_RTR_DEST_MAP4__APRTR_SIZE_MASK 0x7c000000 4162 #define MC_XPB_RTR_DEST_MAP4__APRTR_SIZE__SHIFT 0x1a 4163 #define MC_XPB_RTR_DEST_MAP5__NMR_MASK 0x1 4164 #define MC_XPB_RTR_DEST_MAP5__NMR__SHIFT 0x0 4165 #define MC_XPB_RTR_DEST_MAP5__DEST_OFFSET_MASK 0xffffe 4166 #define MC_XPB_RTR_DEST_MAP5__DEST_OFFSET__SHIFT 0x1 4167 #define MC_XPB_RTR_DEST_MAP5__DEST_SEL_MASK 0xf00000 4168 #define MC_XPB_RTR_DEST_MAP5__DEST_SEL__SHIFT 0x14 4169 #define MC_XPB_RTR_DEST_MAP5__DEST_SEL_RPB_MASK 0x1000000 4170 #define MC_XPB_RTR_DEST_MAP5__DEST_SEL_RPB__SHIFT 0x18 4171 #define MC_XPB_RTR_DEST_MAP5__SIDE_OK_MASK 0x2000000 4172 #define MC_XPB_RTR_DEST_MAP5__SIDE_OK__SHIFT 0x19 4173 #define MC_XPB_RTR_DEST_MAP5__APRTR_SIZE_MASK 0x7c000000 4174 #define MC_XPB_RTR_DEST_MAP5__APRTR_SIZE__SHIFT 0x1a 4175 #define MC_XPB_RTR_DEST_MAP6__NMR_MASK 0x1 4176 #define MC_XPB_RTR_DEST_MAP6__NMR__SHIFT 0x0 4177 #define MC_XPB_RTR_DEST_MAP6__DEST_OFFSET_MASK 0xffffe 4178 #define MC_XPB_RTR_DEST_MAP6__DEST_OFFSET__SHIFT 0x1 4179 #define MC_XPB_RTR_DEST_MAP6__DEST_SEL_MASK 0xf00000 4180 #define MC_XPB_RTR_DEST_MAP6__DEST_SEL__SHIFT 0x14 4181 #define MC_XPB_RTR_DEST_MAP6__DEST_SEL_RPB_MASK 0x1000000 4182 #define MC_XPB_RTR_DEST_MAP6__DEST_SEL_RPB__SHIFT 0x18 4183 #define MC_XPB_RTR_DEST_MAP6__SIDE_OK_MASK 0x2000000 4184 #define MC_XPB_RTR_DEST_MAP6__SIDE_OK__SHIFT 0x19 4185 #define MC_XPB_RTR_DEST_MAP6__APRTR_SIZE_MASK 0x7c000000 4186 #define MC_XPB_RTR_DEST_MAP6__APRTR_SIZE__SHIFT 0x1a 4187 #define MC_XPB_RTR_DEST_MAP7__NMR_MASK 0x1 4188 #define MC_XPB_RTR_DEST_MAP7__NMR__SHIFT 0x0 4189 #define MC_XPB_RTR_DEST_MAP7__DEST_OFFSET_MASK 0xffffe 4190 #define MC_XPB_RTR_DEST_MAP7__DEST_OFFSET__SHIFT 0x1 4191 #define MC_XPB_RTR_DEST_MAP7__DEST_SEL_MASK 0xf00000 4192 #define MC_XPB_RTR_DEST_MAP7__DEST_SEL__SHIFT 0x14 4193 #define MC_XPB_RTR_DEST_MAP7__DEST_SEL_RPB_MASK 0x1000000 4194 #define MC_XPB_RTR_DEST_MAP7__DEST_SEL_RPB__SHIFT 0x18 4195 #define MC_XPB_RTR_DEST_MAP7__SIDE_OK_MASK 0x2000000 4196 #define MC_XPB_RTR_DEST_MAP7__SIDE_OK__SHIFT 0x19 4197 #define MC_XPB_RTR_DEST_MAP7__APRTR_SIZE_MASK 0x7c000000 4198 #define MC_XPB_RTR_DEST_MAP7__APRTR_SIZE__SHIFT 0x1a 4199 #define MC_XPB_RTR_DEST_MAP8__NMR_MASK 0x1 4200 #define MC_XPB_RTR_DEST_MAP8__NMR__SHIFT 0x0 4201 #define MC_XPB_RTR_DEST_MAP8__DEST_OFFSET_MASK 0xffffe 4202 #define MC_XPB_RTR_DEST_MAP8__DEST_OFFSET__SHIFT 0x1 4203 #define MC_XPB_RTR_DEST_MAP8__DEST_SEL_MASK 0xf00000 4204 #define MC_XPB_RTR_DEST_MAP8__DEST_SEL__SHIFT 0x14 4205 #define MC_XPB_RTR_DEST_MAP8__DEST_SEL_RPB_MASK 0x1000000 4206 #define MC_XPB_RTR_DEST_MAP8__DEST_SEL_RPB__SHIFT 0x18 4207 #define MC_XPB_RTR_DEST_MAP8__SIDE_OK_MASK 0x2000000 4208 #define MC_XPB_RTR_DEST_MAP8__SIDE_OK__SHIFT 0x19 4209 #define MC_XPB_RTR_DEST_MAP8__APRTR_SIZE_MASK 0x7c000000 4210 #define MC_XPB_RTR_DEST_MAP8__APRTR_SIZE__SHIFT 0x1a 4211 #define MC_XPB_RTR_DEST_MAP9__NMR_MASK 0x1 4212 #define MC_XPB_RTR_DEST_MAP9__NMR__SHIFT 0x0 4213 #define MC_XPB_RTR_DEST_MAP9__DEST_OFFSET_MASK 0xffffe 4214 #define MC_XPB_RTR_DEST_MAP9__DEST_OFFSET__SHIFT 0x1 4215 #define MC_XPB_RTR_DEST_MAP9__DEST_SEL_MASK 0xf00000 4216 #define MC_XPB_RTR_DEST_MAP9__DEST_SEL__SHIFT 0x14 4217 #define MC_XPB_RTR_DEST_MAP9__DEST_SEL_RPB_MASK 0x1000000 4218 #define MC_XPB_RTR_DEST_MAP9__DEST_SEL_RPB__SHIFT 0x18 4219 #define MC_XPB_RTR_DEST_MAP9__SIDE_OK_MASK 0x2000000 4220 #define MC_XPB_RTR_DEST_MAP9__SIDE_OK__SHIFT 0x19 4221 #define MC_XPB_RTR_DEST_MAP9__APRTR_SIZE_MASK 0x7c000000 4222 #define MC_XPB_RTR_DEST_MAP9__APRTR_SIZE__SHIFT 0x1a 4223 #define MC_XPB_XDMA_RTR_DEST_MAP0__NMR_MASK 0x1 4224 #define MC_XPB_XDMA_RTR_DEST_MAP0__NMR__SHIFT 0x0 4225 #define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_OFFSET_MASK 0xffffe 4226 #define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_OFFSET__SHIFT 0x1 4227 #define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_MASK 0xf00000 4228 #define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL__SHIFT 0x14 4229 #define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_RPB_MASK 0x1000000 4230 #define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_RPB__SHIFT 0x18 4231 #define MC_XPB_XDMA_RTR_DEST_MAP0__SIDE_OK_MASK 0x2000000 4232 #define MC_XPB_XDMA_RTR_DEST_MAP0__SIDE_OK__SHIFT 0x19 4233 #define MC_XPB_XDMA_RTR_DEST_MAP0__APRTR_SIZE_MASK 0x7c000000 4234 #define MC_XPB_XDMA_RTR_DEST_MAP0__APRTR_SIZE__SHIFT 0x1a 4235 #define MC_XPB_XDMA_RTR_DEST_MAP1__NMR_MASK 0x1 4236 #define MC_XPB_XDMA_RTR_DEST_MAP1__NMR__SHIFT 0x0 4237 #define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_OFFSET_MASK 0xffffe 4238 #define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_OFFSET__SHIFT 0x1 4239 #define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_MASK 0xf00000 4240 #define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL__SHIFT 0x14 4241 #define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_RPB_MASK 0x1000000 4242 #define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_RPB__SHIFT 0x18 4243 #define MC_XPB_XDMA_RTR_DEST_MAP1__SIDE_OK_MASK 0x2000000 4244 #define MC_XPB_XDMA_RTR_DEST_MAP1__SIDE_OK__SHIFT 0x19 4245 #define MC_XPB_XDMA_RTR_DEST_MAP1__APRTR_SIZE_MASK 0x7c000000 4246 #define MC_XPB_XDMA_RTR_DEST_MAP1__APRTR_SIZE__SHIFT 0x1a 4247 #define MC_XPB_XDMA_RTR_DEST_MAP2__NMR_MASK 0x1 4248 #define MC_XPB_XDMA_RTR_DEST_MAP2__NMR__SHIFT 0x0 4249 #define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_OFFSET_MASK 0xffffe 4250 #define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_OFFSET__SHIFT 0x1 4251 #define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_MASK 0xf00000 4252 #define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL__SHIFT 0x14 4253 #define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_RPB_MASK 0x1000000 4254 #define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_RPB__SHIFT 0x18 4255 #define MC_XPB_XDMA_RTR_DEST_MAP2__SIDE_OK_MASK 0x2000000 4256 #define MC_XPB_XDMA_RTR_DEST_MAP2__SIDE_OK__SHIFT 0x19 4257 #define MC_XPB_XDMA_RTR_DEST_MAP2__APRTR_SIZE_MASK 0x7c000000 4258 #define MC_XPB_XDMA_RTR_DEST_MAP2__APRTR_SIZE__SHIFT 0x1a 4259 #define MC_XPB_XDMA_RTR_DEST_MAP3__NMR_MASK 0x1 4260 #define MC_XPB_XDMA_RTR_DEST_MAP3__NMR__SHIFT 0x0 4261 #define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_OFFSET_MASK 0xffffe 4262 #define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_OFFSET__SHIFT 0x1 4263 #define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_MASK 0xf00000 4264 #define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL__SHIFT 0x14 4265 #define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_RPB_MASK 0x1000000 4266 #define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_RPB__SHIFT 0x18 4267 #define MC_XPB_XDMA_RTR_DEST_MAP3__SIDE_OK_MASK 0x2000000 4268 #define MC_XPB_XDMA_RTR_DEST_MAP3__SIDE_OK__SHIFT 0x19 4269 #define MC_XPB_XDMA_RTR_DEST_MAP3__APRTR_SIZE_MASK 0x7c000000 4270 #define MC_XPB_XDMA_RTR_DEST_MAP3__APRTR_SIZE__SHIFT 0x1a 4271 #define MC_XPB_CLG_CFG0__WCB_NUM_MASK 0xf 4272 #define MC_XPB_CLG_CFG0__WCB_NUM__SHIFT 0x0 4273 #define MC_XPB_CLG_CFG0__LB_TYPE_MASK 0x70 4274 #define MC_XPB_CLG_CFG0__LB_TYPE__SHIFT 0x4 4275 #define MC_XPB_CLG_CFG0__P2P_BAR_MASK 0x380 4276 #define MC_XPB_CLG_CFG0__P2P_BAR__SHIFT 0x7 4277 #define MC_XPB_CLG_CFG0__HOST_FLUSH_MASK 0x3c00 4278 #define MC_XPB_CLG_CFG0__HOST_FLUSH__SHIFT 0xa 4279 #define MC_XPB_CLG_CFG0__SIDE_FLUSH_MASK 0x3c000 4280 #define MC_XPB_CLG_CFG0__SIDE_FLUSH__SHIFT 0xe 4281 #define MC_XPB_CLG_CFG1__WCB_NUM_MASK 0xf 4282 #define MC_XPB_CLG_CFG1__WCB_NUM__SHIFT 0x0 4283 #define MC_XPB_CLG_CFG1__LB_TYPE_MASK 0x70 4284 #define MC_XPB_CLG_CFG1__LB_TYPE__SHIFT 0x4 4285 #define MC_XPB_CLG_CFG1__P2P_BAR_MASK 0x380 4286 #define MC_XPB_CLG_CFG1__P2P_BAR__SHIFT 0x7 4287 #define MC_XPB_CLG_CFG1__HOST_FLUSH_MASK 0x3c00 4288 #define MC_XPB_CLG_CFG1__HOST_FLUSH__SHIFT 0xa 4289 #define MC_XPB_CLG_CFG1__SIDE_FLUSH_MASK 0x3c000 4290 #define MC_XPB_CLG_CFG1__SIDE_FLUSH__SHIFT 0xe 4291 #define MC_XPB_CLG_CFG2__WCB_NUM_MASK 0xf 4292 #define MC_XPB_CLG_CFG2__WCB_NUM__SHIFT 0x0 4293 #define MC_XPB_CLG_CFG2__LB_TYPE_MASK 0x70 4294 #define MC_XPB_CLG_CFG2__LB_TYPE__SHIFT 0x4 4295 #define MC_XPB_CLG_CFG2__P2P_BAR_MASK 0x380 4296 #define MC_XPB_CLG_CFG2__P2P_BAR__SHIFT 0x7 4297 #define MC_XPB_CLG_CFG2__HOST_FLUSH_MASK 0x3c00 4298 #define MC_XPB_CLG_CFG2__HOST_FLUSH__SHIFT 0xa 4299 #define MC_XPB_CLG_CFG2__SIDE_FLUSH_MASK 0x3c000 4300 #define MC_XPB_CLG_CFG2__SIDE_FLUSH__SHIFT 0xe 4301 #define MC_XPB_CLG_CFG3__WCB_NUM_MASK 0xf 4302 #define MC_XPB_CLG_CFG3__WCB_NUM__SHIFT 0x0 4303 #define MC_XPB_CLG_CFG3__LB_TYPE_MASK 0x70 4304 #define MC_XPB_CLG_CFG3__LB_TYPE__SHIFT 0x4 4305 #define MC_XPB_CLG_CFG3__P2P_BAR_MASK 0x380 4306 #define MC_XPB_CLG_CFG3__P2P_BAR__SHIFT 0x7 4307 #define MC_XPB_CLG_CFG3__HOST_FLUSH_MASK 0x3c00 4308 #define MC_XPB_CLG_CFG3__HOST_FLUSH__SHIFT 0xa 4309 #define MC_XPB_CLG_CFG3__SIDE_FLUSH_MASK 0x3c000 4310 #define MC_XPB_CLG_CFG3__SIDE_FLUSH__SHIFT 0xe 4311 #define MC_XPB_CLG_CFG4__WCB_NUM_MASK 0xf 4312 #define MC_XPB_CLG_CFG4__WCB_NUM__SHIFT 0x0 4313 #define MC_XPB_CLG_CFG4__LB_TYPE_MASK 0x70 4314 #define MC_XPB_CLG_CFG4__LB_TYPE__SHIFT 0x4 4315 #define MC_XPB_CLG_CFG4__P2P_BAR_MASK 0x380 4316 #define MC_XPB_CLG_CFG4__P2P_BAR__SHIFT 0x7 4317 #define MC_XPB_CLG_CFG4__HOST_FLUSH_MASK 0x3c00 4318 #define MC_XPB_CLG_CFG4__HOST_FLUSH__SHIFT 0xa 4319 #define MC_XPB_CLG_CFG4__SIDE_FLUSH_MASK 0x3c000 4320 #define MC_XPB_CLG_CFG4__SIDE_FLUSH__SHIFT 0xe 4321 #define MC_XPB_CLG_CFG5__WCB_NUM_MASK 0xf 4322 #define MC_XPB_CLG_CFG5__WCB_NUM__SHIFT 0x0 4323 #define MC_XPB_CLG_CFG5__LB_TYPE_MASK 0x70 4324 #define MC_XPB_CLG_CFG5__LB_TYPE__SHIFT 0x4 4325 #define MC_XPB_CLG_CFG5__P2P_BAR_MASK 0x380 4326 #define MC_XPB_CLG_CFG5__P2P_BAR__SHIFT 0x7 4327 #define MC_XPB_CLG_CFG5__HOST_FLUSH_MASK 0x3c00 4328 #define MC_XPB_CLG_CFG5__HOST_FLUSH__SHIFT 0xa 4329 #define MC_XPB_CLG_CFG5__SIDE_FLUSH_MASK 0x3c000 4330 #define MC_XPB_CLG_CFG5__SIDE_FLUSH__SHIFT 0xe 4331 #define MC_XPB_CLG_CFG6__WCB_NUM_MASK 0xf 4332 #define MC_XPB_CLG_CFG6__WCB_NUM__SHIFT 0x0 4333 #define MC_XPB_CLG_CFG6__LB_TYPE_MASK 0x70 4334 #define MC_XPB_CLG_CFG6__LB_TYPE__SHIFT 0x4 4335 #define MC_XPB_CLG_CFG6__P2P_BAR_MASK 0x380 4336 #define MC_XPB_CLG_CFG6__P2P_BAR__SHIFT 0x7 4337 #define MC_XPB_CLG_CFG6__HOST_FLUSH_MASK 0x3c00 4338 #define MC_XPB_CLG_CFG6__HOST_FLUSH__SHIFT 0xa 4339 #define MC_XPB_CLG_CFG6__SIDE_FLUSH_MASK 0x3c000 4340 #define MC_XPB_CLG_CFG6__SIDE_FLUSH__SHIFT 0xe 4341 #define MC_XPB_CLG_CFG7__WCB_NUM_MASK 0xf 4342 #define MC_XPB_CLG_CFG7__WCB_NUM__SHIFT 0x0 4343 #define MC_XPB_CLG_CFG7__LB_TYPE_MASK 0x70 4344 #define MC_XPB_CLG_CFG7__LB_TYPE__SHIFT 0x4 4345 #define MC_XPB_CLG_CFG7__P2P_BAR_MASK 0x380 4346 #define MC_XPB_CLG_CFG7__P2P_BAR__SHIFT 0x7 4347 #define MC_XPB_CLG_CFG7__HOST_FLUSH_MASK 0x3c00 4348 #define MC_XPB_CLG_CFG7__HOST_FLUSH__SHIFT 0xa 4349 #define MC_XPB_CLG_CFG7__SIDE_FLUSH_MASK 0x3c000 4350 #define MC_XPB_CLG_CFG7__SIDE_FLUSH__SHIFT 0xe 4351 #define MC_XPB_CLG_CFG8__WCB_NUM_MASK 0xf 4352 #define MC_XPB_CLG_CFG8__WCB_NUM__SHIFT 0x0 4353 #define MC_XPB_CLG_CFG8__LB_TYPE_MASK 0x70 4354 #define MC_XPB_CLG_CFG8__LB_TYPE__SHIFT 0x4 4355 #define MC_XPB_CLG_CFG8__P2P_BAR_MASK 0x380 4356 #define MC_XPB_CLG_CFG8__P2P_BAR__SHIFT 0x7 4357 #define MC_XPB_CLG_CFG8__HOST_FLUSH_MASK 0x3c00 4358 #define MC_XPB_CLG_CFG8__HOST_FLUSH__SHIFT 0xa 4359 #define MC_XPB_CLG_CFG8__SIDE_FLUSH_MASK 0x3c000 4360 #define MC_XPB_CLG_CFG8__SIDE_FLUSH__SHIFT 0xe 4361 #define MC_XPB_CLG_CFG9__WCB_NUM_MASK 0xf 4362 #define MC_XPB_CLG_CFG9__WCB_NUM__SHIFT 0x0 4363 #define MC_XPB_CLG_CFG9__LB_TYPE_MASK 0x70 4364 #define MC_XPB_CLG_CFG9__LB_TYPE__SHIFT 0x4 4365 #define MC_XPB_CLG_CFG9__P2P_BAR_MASK 0x380 4366 #define MC_XPB_CLG_CFG9__P2P_BAR__SHIFT 0x7 4367 #define MC_XPB_CLG_CFG9__HOST_FLUSH_MASK 0x3c00 4368 #define MC_XPB_CLG_CFG9__HOST_FLUSH__SHIFT 0xa 4369 #define MC_XPB_CLG_CFG9__SIDE_FLUSH_MASK 0x3c000 4370 #define MC_XPB_CLG_CFG9__SIDE_FLUSH__SHIFT 0xe 4371 #define MC_XPB_CLG_CFG10__WCB_NUM_MASK 0xf 4372 #define MC_XPB_CLG_CFG10__WCB_NUM__SHIFT 0x0 4373 #define MC_XPB_CLG_CFG10__LB_TYPE_MASK 0x70 4374 #define MC_XPB_CLG_CFG10__LB_TYPE__SHIFT 0x4 4375 #define MC_XPB_CLG_CFG10__P2P_BAR_MASK 0x380 4376 #define MC_XPB_CLG_CFG10__P2P_BAR__SHIFT 0x7 4377 #define MC_XPB_CLG_CFG10__HOST_FLUSH_MASK 0x3c00 4378 #define MC_XPB_CLG_CFG10__HOST_FLUSH__SHIFT 0xa 4379 #define MC_XPB_CLG_CFG10__SIDE_FLUSH_MASK 0x3c000 4380 #define MC_XPB_CLG_CFG10__SIDE_FLUSH__SHIFT 0xe 4381 #define MC_XPB_CLG_CFG11__WCB_NUM_MASK 0xf 4382 #define MC_XPB_CLG_CFG11__WCB_NUM__SHIFT 0x0 4383 #define MC_XPB_CLG_CFG11__LB_TYPE_MASK 0x70 4384 #define MC_XPB_CLG_CFG11__LB_TYPE__SHIFT 0x4 4385 #define MC_XPB_CLG_CFG11__P2P_BAR_MASK 0x380 4386 #define MC_XPB_CLG_CFG11__P2P_BAR__SHIFT 0x7 4387 #define MC_XPB_CLG_CFG11__HOST_FLUSH_MASK 0x3c00 4388 #define MC_XPB_CLG_CFG11__HOST_FLUSH__SHIFT 0xa 4389 #define MC_XPB_CLG_CFG11__SIDE_FLUSH_MASK 0x3c000 4390 #define MC_XPB_CLG_CFG11__SIDE_FLUSH__SHIFT 0xe 4391 #define MC_XPB_CLG_CFG12__WCB_NUM_MASK 0xf 4392 #define MC_XPB_CLG_CFG12__WCB_NUM__SHIFT 0x0 4393 #define MC_XPB_CLG_CFG12__LB_TYPE_MASK 0x70 4394 #define MC_XPB_CLG_CFG12__LB_TYPE__SHIFT 0x4 4395 #define MC_XPB_CLG_CFG12__P2P_BAR_MASK 0x380 4396 #define MC_XPB_CLG_CFG12__P2P_BAR__SHIFT 0x7 4397 #define MC_XPB_CLG_CFG12__HOST_FLUSH_MASK 0x3c00 4398 #define MC_XPB_CLG_CFG12__HOST_FLUSH__SHIFT 0xa 4399 #define MC_XPB_CLG_CFG12__SIDE_FLUSH_MASK 0x3c000 4400 #define MC_XPB_CLG_CFG12__SIDE_FLUSH__SHIFT 0xe 4401 #define MC_XPB_CLG_CFG13__WCB_NUM_MASK 0xf 4402 #define MC_XPB_CLG_CFG13__WCB_NUM__SHIFT 0x0 4403 #define MC_XPB_CLG_CFG13__LB_TYPE_MASK 0x70 4404 #define MC_XPB_CLG_CFG13__LB_TYPE__SHIFT 0x4 4405 #define MC_XPB_CLG_CFG13__P2P_BAR_MASK 0x380 4406 #define MC_XPB_CLG_CFG13__P2P_BAR__SHIFT 0x7 4407 #define MC_XPB_CLG_CFG13__HOST_FLUSH_MASK 0x3c00 4408 #define MC_XPB_CLG_CFG13__HOST_FLUSH__SHIFT 0xa 4409 #define MC_XPB_CLG_CFG13__SIDE_FLUSH_MASK 0x3c000 4410 #define MC_XPB_CLG_CFG13__SIDE_FLUSH__SHIFT 0xe 4411 #define MC_XPB_CLG_CFG14__WCB_NUM_MASK 0xf 4412 #define MC_XPB_CLG_CFG14__WCB_NUM__SHIFT 0x0 4413 #define MC_XPB_CLG_CFG14__LB_TYPE_MASK 0x70 4414 #define MC_XPB_CLG_CFG14__LB_TYPE__SHIFT 0x4 4415 #define MC_XPB_CLG_CFG14__P2P_BAR_MASK 0x380 4416 #define MC_XPB_CLG_CFG14__P2P_BAR__SHIFT 0x7 4417 #define MC_XPB_CLG_CFG14__HOST_FLUSH_MASK 0x3c00 4418 #define MC_XPB_CLG_CFG14__HOST_FLUSH__SHIFT 0xa 4419 #define MC_XPB_CLG_CFG14__SIDE_FLUSH_MASK 0x3c000 4420 #define MC_XPB_CLG_CFG14__SIDE_FLUSH__SHIFT 0xe 4421 #define MC_XPB_CLG_CFG15__WCB_NUM_MASK 0xf 4422 #define MC_XPB_CLG_CFG15__WCB_NUM__SHIFT 0x0 4423 #define MC_XPB_CLG_CFG15__LB_TYPE_MASK 0x70 4424 #define MC_XPB_CLG_CFG15__LB_TYPE__SHIFT 0x4 4425 #define MC_XPB_CLG_CFG15__P2P_BAR_MASK 0x380 4426 #define MC_XPB_CLG_CFG15__P2P_BAR__SHIFT 0x7 4427 #define MC_XPB_CLG_CFG15__HOST_FLUSH_MASK 0x3c00 4428 #define MC_XPB_CLG_CFG15__HOST_FLUSH__SHIFT 0xa 4429 #define MC_XPB_CLG_CFG15__SIDE_FLUSH_MASK 0x3c000 4430 #define MC_XPB_CLG_CFG15__SIDE_FLUSH__SHIFT 0xe 4431 #define MC_XPB_CLG_CFG16__WCB_NUM_MASK 0xf 4432 #define MC_XPB_CLG_CFG16__WCB_NUM__SHIFT 0x0 4433 #define MC_XPB_CLG_CFG16__LB_TYPE_MASK 0x70 4434 #define MC_XPB_CLG_CFG16__LB_TYPE__SHIFT 0x4 4435 #define MC_XPB_CLG_CFG16__P2P_BAR_MASK 0x380 4436 #define MC_XPB_CLG_CFG16__P2P_BAR__SHIFT 0x7 4437 #define MC_XPB_CLG_CFG16__HOST_FLUSH_MASK 0x3c00 4438 #define MC_XPB_CLG_CFG16__HOST_FLUSH__SHIFT 0xa 4439 #define MC_XPB_CLG_CFG16__SIDE_FLUSH_MASK 0x3c000 4440 #define MC_XPB_CLG_CFG16__SIDE_FLUSH__SHIFT 0xe 4441 #define MC_XPB_CLG_CFG17__WCB_NUM_MASK 0xf 4442 #define MC_XPB_CLG_CFG17__WCB_NUM__SHIFT 0x0 4443 #define MC_XPB_CLG_CFG17__LB_TYPE_MASK 0x70 4444 #define MC_XPB_CLG_CFG17__LB_TYPE__SHIFT 0x4 4445 #define MC_XPB_CLG_CFG17__P2P_BAR_MASK 0x380 4446 #define MC_XPB_CLG_CFG17__P2P_BAR__SHIFT 0x7 4447 #define MC_XPB_CLG_CFG17__HOST_FLUSH_MASK 0x3c00 4448 #define MC_XPB_CLG_CFG17__HOST_FLUSH__SHIFT 0xa 4449 #define MC_XPB_CLG_CFG17__SIDE_FLUSH_MASK 0x3c000 4450 #define MC_XPB_CLG_CFG17__SIDE_FLUSH__SHIFT 0xe 4451 #define MC_XPB_CLG_CFG18__WCB_NUM_MASK 0xf 4452 #define MC_XPB_CLG_CFG18__WCB_NUM__SHIFT 0x0 4453 #define MC_XPB_CLG_CFG18__LB_TYPE_MASK 0x70 4454 #define MC_XPB_CLG_CFG18__LB_TYPE__SHIFT 0x4 4455 #define MC_XPB_CLG_CFG18__P2P_BAR_MASK 0x380 4456 #define MC_XPB_CLG_CFG18__P2P_BAR__SHIFT 0x7 4457 #define MC_XPB_CLG_CFG18__HOST_FLUSH_MASK 0x3c00 4458 #define MC_XPB_CLG_CFG18__HOST_FLUSH__SHIFT 0xa 4459 #define MC_XPB_CLG_CFG18__SIDE_FLUSH_MASK 0x3c000 4460 #define MC_XPB_CLG_CFG18__SIDE_FLUSH__SHIFT 0xe 4461 #define MC_XPB_CLG_CFG19__WCB_NUM_MASK 0xf 4462 #define MC_XPB_CLG_CFG19__WCB_NUM__SHIFT 0x0 4463 #define MC_XPB_CLG_CFG19__LB_TYPE_MASK 0x70 4464 #define MC_XPB_CLG_CFG19__LB_TYPE__SHIFT 0x4 4465 #define MC_XPB_CLG_CFG19__P2P_BAR_MASK 0x380 4466 #define MC_XPB_CLG_CFG19__P2P_BAR__SHIFT 0x7 4467 #define MC_XPB_CLG_CFG19__HOST_FLUSH_MASK 0x3c00 4468 #define MC_XPB_CLG_CFG19__HOST_FLUSH__SHIFT 0xa 4469 #define MC_XPB_CLG_CFG19__SIDE_FLUSH_MASK 0x3c000 4470 #define MC_XPB_CLG_CFG19__SIDE_FLUSH__SHIFT 0xe 4471 #define MC_XPB_CLG_EXTRA__CMP0_MASK 0xff 4472 #define MC_XPB_CLG_EXTRA__CMP0__SHIFT 0x0 4473 #define MC_XPB_CLG_EXTRA__MSK0_MASK 0xff00 4474 #define MC_XPB_CLG_EXTRA__MSK0__SHIFT 0x8 4475 #define MC_XPB_CLG_EXTRA__VLD0_MASK 0x10000 4476 #define MC_XPB_CLG_EXTRA__VLD0__SHIFT 0x10 4477 #define MC_XPB_CLG_EXTRA__CMP1_MASK 0x1fe0000 4478 #define MC_XPB_CLG_EXTRA__CMP1__SHIFT 0x11 4479 #define MC_XPB_CLG_EXTRA__VLD1_MASK 0x2000000 4480 #define MC_XPB_CLG_EXTRA__VLD1__SHIFT 0x19 4481 #define MC_XPB_LB_ADDR__CMP0_MASK 0x3ff 4482 #define MC_XPB_LB_ADDR__CMP0__SHIFT 0x0 4483 #define MC_XPB_LB_ADDR__MASK0_MASK 0xffc00 4484 #define MC_XPB_LB_ADDR__MASK0__SHIFT 0xa 4485 #define MC_XPB_LB_ADDR__CMP1_MASK 0x3f00000 4486 #define MC_XPB_LB_ADDR__CMP1__SHIFT 0x14 4487 #define MC_XPB_LB_ADDR__MASK1_MASK 0xfc000000 4488 #define MC_XPB_LB_ADDR__MASK1__SHIFT 0x1a 4489 #define MC_XPB_UNC_THRESH_HST__CHANGE_PREF_MASK 0x3f 4490 #define MC_XPB_UNC_THRESH_HST__CHANGE_PREF__SHIFT 0x0 4491 #define MC_XPB_UNC_THRESH_HST__STRONG_PREF_MASK 0xfc0 4492 #define MC_XPB_UNC_THRESH_HST__STRONG_PREF__SHIFT 0x6 4493 #define MC_XPB_UNC_THRESH_HST__USE_UNFULL_MASK 0x3f000 4494 #define MC_XPB_UNC_THRESH_HST__USE_UNFULL__SHIFT 0xc 4495 #define MC_XPB_UNC_THRESH_SID__CHANGE_PREF_MASK 0x3f 4496 #define MC_XPB_UNC_THRESH_SID__CHANGE_PREF__SHIFT 0x0 4497 #define MC_XPB_UNC_THRESH_SID__STRONG_PREF_MASK 0xfc0 4498 #define MC_XPB_UNC_THRESH_SID__STRONG_PREF__SHIFT 0x6 4499 #define MC_XPB_UNC_THRESH_SID__USE_UNFULL_MASK 0x3f000 4500 #define MC_XPB_UNC_THRESH_SID__USE_UNFULL__SHIFT 0xc 4501 #define MC_XPB_WCB_STS__PBUF_VLD_MASK 0xffff 4502 #define MC_XPB_WCB_STS__PBUF_VLD__SHIFT 0x0 4503 #define MC_XPB_WCB_STS__WCB_HST_DATA_BUF_CNT_MASK 0x7f0000 4504 #define MC_XPB_WCB_STS__WCB_HST_DATA_BUF_CNT__SHIFT 0x10 4505 #define MC_XPB_WCB_STS__WCB_SID_DATA_BUF_CNT_MASK 0x3f800000 4506 #define MC_XPB_WCB_STS__WCB_SID_DATA_BUF_CNT__SHIFT 0x17 4507 #define MC_XPB_WCB_CFG__TIMEOUT_MASK 0xffff 4508 #define MC_XPB_WCB_CFG__TIMEOUT__SHIFT 0x0 4509 #define MC_XPB_WCB_CFG__HST_MAX_MASK 0x30000 4510 #define MC_XPB_WCB_CFG__HST_MAX__SHIFT 0x10 4511 #define MC_XPB_WCB_CFG__SID_MAX_MASK 0xc0000 4512 #define MC_XPB_WCB_CFG__SID_MAX__SHIFT 0x12 4513 #define MC_XPB_P2P_BAR_CFG__ADDR_SIZE_MASK 0xf 4514 #define MC_XPB_P2P_BAR_CFG__ADDR_SIZE__SHIFT 0x0 4515 #define MC_XPB_P2P_BAR_CFG__SEND_BAR_MASK 0x30 4516 #define MC_XPB_P2P_BAR_CFG__SEND_BAR__SHIFT 0x4 4517 #define MC_XPB_P2P_BAR_CFG__SNOOP_MASK 0x40 4518 #define MC_XPB_P2P_BAR_CFG__SNOOP__SHIFT 0x6 4519 #define MC_XPB_P2P_BAR_CFG__SEND_DIS_MASK 0x80 4520 #define MC_XPB_P2P_BAR_CFG__SEND_DIS__SHIFT 0x7 4521 #define MC_XPB_P2P_BAR_CFG__COMPRESS_DIS_MASK 0x100 4522 #define MC_XPB_P2P_BAR_CFG__COMPRESS_DIS__SHIFT 0x8 4523 #define MC_XPB_P2P_BAR_CFG__UPDATE_DIS_MASK 0x200 4524 #define MC_XPB_P2P_BAR_CFG__UPDATE_DIS__SHIFT 0x9 4525 #define MC_XPB_P2P_BAR_CFG__REGBAR_FROM_SYSBAR_MASK 0x400 4526 #define MC_XPB_P2P_BAR_CFG__REGBAR_FROM_SYSBAR__SHIFT 0xa 4527 #define MC_XPB_P2P_BAR_CFG__RD_EN_MASK 0x800 4528 #define MC_XPB_P2P_BAR_CFG__RD_EN__SHIFT 0xb 4529 #define MC_XPB_P2P_BAR_CFG__ATC_TRANSLATED_MASK 0x1000 4530 #define MC_XPB_P2P_BAR_CFG__ATC_TRANSLATED__SHIFT 0xc 4531 #define MC_XPB_P2P_BAR0__HOST_FLUSH_MASK 0xf 4532 #define MC_XPB_P2P_BAR0__HOST_FLUSH__SHIFT 0x0 4533 #define MC_XPB_P2P_BAR0__REG_SYS_BAR_MASK 0xf0 4534 #define MC_XPB_P2P_BAR0__REG_SYS_BAR__SHIFT 0x4 4535 #define MC_XPB_P2P_BAR0__MEM_SYS_BAR_MASK 0xf00 4536 #define MC_XPB_P2P_BAR0__MEM_SYS_BAR__SHIFT 0x8 4537 #define MC_XPB_P2P_BAR0__VALID_MASK 0x1000 4538 #define MC_XPB_P2P_BAR0__VALID__SHIFT 0xc 4539 #define MC_XPB_P2P_BAR0__SEND_DIS_MASK 0x2000 4540 #define MC_XPB_P2P_BAR0__SEND_DIS__SHIFT 0xd 4541 #define MC_XPB_P2P_BAR0__COMPRESS_DIS_MASK 0x4000 4542 #define MC_XPB_P2P_BAR0__COMPRESS_DIS__SHIFT 0xe 4543 #define MC_XPB_P2P_BAR0__RESERVED_MASK 0x8000 4544 #define MC_XPB_P2P_BAR0__RESERVED__SHIFT 0xf 4545 #define MC_XPB_P2P_BAR0__ADDRESS_MASK 0xffff0000 4546 #define MC_XPB_P2P_BAR0__ADDRESS__SHIFT 0x10 4547 #define MC_XPB_P2P_BAR1__HOST_FLUSH_MASK 0xf 4548 #define MC_XPB_P2P_BAR1__HOST_FLUSH__SHIFT 0x0 4549 #define MC_XPB_P2P_BAR1__REG_SYS_BAR_MASK 0xf0 4550 #define MC_XPB_P2P_BAR1__REG_SYS_BAR__SHIFT 0x4 4551 #define MC_XPB_P2P_BAR1__MEM_SYS_BAR_MASK 0xf00 4552 #define MC_XPB_P2P_BAR1__MEM_SYS_BAR__SHIFT 0x8 4553 #define MC_XPB_P2P_BAR1__VALID_MASK 0x1000 4554 #define MC_XPB_P2P_BAR1__VALID__SHIFT 0xc 4555 #define MC_XPB_P2P_BAR1__SEND_DIS_MASK 0x2000 4556 #define MC_XPB_P2P_BAR1__SEND_DIS__SHIFT 0xd 4557 #define MC_XPB_P2P_BAR1__COMPRESS_DIS_MASK 0x4000 4558 #define MC_XPB_P2P_BAR1__COMPRESS_DIS__SHIFT 0xe 4559 #define MC_XPB_P2P_BAR1__RESERVED_MASK 0x8000 4560 #define MC_XPB_P2P_BAR1__RESERVED__SHIFT 0xf 4561 #define MC_XPB_P2P_BAR1__ADDRESS_MASK 0xffff0000 4562 #define MC_XPB_P2P_BAR1__ADDRESS__SHIFT 0x10 4563 #define MC_XPB_P2P_BAR2__HOST_FLUSH_MASK 0xf 4564 #define MC_XPB_P2P_BAR2__HOST_FLUSH__SHIFT 0x0 4565 #define MC_XPB_P2P_BAR2__REG_SYS_BAR_MASK 0xf0 4566 #define MC_XPB_P2P_BAR2__REG_SYS_BAR__SHIFT 0x4 4567 #define MC_XPB_P2P_BAR2__MEM_SYS_BAR_MASK 0xf00 4568 #define MC_XPB_P2P_BAR2__MEM_SYS_BAR__SHIFT 0x8 4569 #define MC_XPB_P2P_BAR2__VALID_MASK 0x1000 4570 #define MC_XPB_P2P_BAR2__VALID__SHIFT 0xc 4571 #define MC_XPB_P2P_BAR2__SEND_DIS_MASK 0x2000 4572 #define MC_XPB_P2P_BAR2__SEND_DIS__SHIFT 0xd 4573 #define MC_XPB_P2P_BAR2__COMPRESS_DIS_MASK 0x4000 4574 #define MC_XPB_P2P_BAR2__COMPRESS_DIS__SHIFT 0xe 4575 #define MC_XPB_P2P_BAR2__RESERVED_MASK 0x8000 4576 #define MC_XPB_P2P_BAR2__RESERVED__SHIFT 0xf 4577 #define MC_XPB_P2P_BAR2__ADDRESS_MASK 0xffff0000 4578 #define MC_XPB_P2P_BAR2__ADDRESS__SHIFT 0x10 4579 #define MC_XPB_P2P_BAR3__HOST_FLUSH_MASK 0xf 4580 #define MC_XPB_P2P_BAR3__HOST_FLUSH__SHIFT 0x0 4581 #define MC_XPB_P2P_BAR3__REG_SYS_BAR_MASK 0xf0 4582 #define MC_XPB_P2P_BAR3__REG_SYS_BAR__SHIFT 0x4 4583 #define MC_XPB_P2P_BAR3__MEM_SYS_BAR_MASK 0xf00 4584 #define MC_XPB_P2P_BAR3__MEM_SYS_BAR__SHIFT 0x8 4585 #define MC_XPB_P2P_BAR3__VALID_MASK 0x1000 4586 #define MC_XPB_P2P_BAR3__VALID__SHIFT 0xc 4587 #define MC_XPB_P2P_BAR3__SEND_DIS_MASK 0x2000 4588 #define MC_XPB_P2P_BAR3__SEND_DIS__SHIFT 0xd 4589 #define MC_XPB_P2P_BAR3__COMPRESS_DIS_MASK 0x4000 4590 #define MC_XPB_P2P_BAR3__COMPRESS_DIS__SHIFT 0xe 4591 #define MC_XPB_P2P_BAR3__RESERVED_MASK 0x8000 4592 #define MC_XPB_P2P_BAR3__RESERVED__SHIFT 0xf 4593 #define MC_XPB_P2P_BAR3__ADDRESS_MASK 0xffff0000 4594 #define MC_XPB_P2P_BAR3__ADDRESS__SHIFT 0x10 4595 #define MC_XPB_P2P_BAR4__HOST_FLUSH_MASK 0xf 4596 #define MC_XPB_P2P_BAR4__HOST_FLUSH__SHIFT 0x0 4597 #define MC_XPB_P2P_BAR4__REG_SYS_BAR_MASK 0xf0 4598 #define MC_XPB_P2P_BAR4__REG_SYS_BAR__SHIFT 0x4 4599 #define MC_XPB_P2P_BAR4__MEM_SYS_BAR_MASK 0xf00 4600 #define MC_XPB_P2P_BAR4__MEM_SYS_BAR__SHIFT 0x8 4601 #define MC_XPB_P2P_BAR4__VALID_MASK 0x1000 4602 #define MC_XPB_P2P_BAR4__VALID__SHIFT 0xc 4603 #define MC_XPB_P2P_BAR4__SEND_DIS_MASK 0x2000 4604 #define MC_XPB_P2P_BAR4__SEND_DIS__SHIFT 0xd 4605 #define MC_XPB_P2P_BAR4__COMPRESS_DIS_MASK 0x4000 4606 #define MC_XPB_P2P_BAR4__COMPRESS_DIS__SHIFT 0xe 4607 #define MC_XPB_P2P_BAR4__RESERVED_MASK 0x8000 4608 #define MC_XPB_P2P_BAR4__RESERVED__SHIFT 0xf 4609 #define MC_XPB_P2P_BAR4__ADDRESS_MASK 0xffff0000 4610 #define MC_XPB_P2P_BAR4__ADDRESS__SHIFT 0x10 4611 #define MC_XPB_P2P_BAR5__HOST_FLUSH_MASK 0xf 4612 #define MC_XPB_P2P_BAR5__HOST_FLUSH__SHIFT 0x0 4613 #define MC_XPB_P2P_BAR5__REG_SYS_BAR_MASK 0xf0 4614 #define MC_XPB_P2P_BAR5__REG_SYS_BAR__SHIFT 0x4 4615 #define MC_XPB_P2P_BAR5__MEM_SYS_BAR_MASK 0xf00 4616 #define MC_XPB_P2P_BAR5__MEM_SYS_BAR__SHIFT 0x8 4617 #define MC_XPB_P2P_BAR5__VALID_MASK 0x1000 4618 #define MC_XPB_P2P_BAR5__VALID__SHIFT 0xc 4619 #define MC_XPB_P2P_BAR5__SEND_DIS_MASK 0x2000 4620 #define MC_XPB_P2P_BAR5__SEND_DIS__SHIFT 0xd 4621 #define MC_XPB_P2P_BAR5__COMPRESS_DIS_MASK 0x4000 4622 #define MC_XPB_P2P_BAR5__COMPRESS_DIS__SHIFT 0xe 4623 #define MC_XPB_P2P_BAR5__RESERVED_MASK 0x8000 4624 #define MC_XPB_P2P_BAR5__RESERVED__SHIFT 0xf 4625 #define MC_XPB_P2P_BAR5__ADDRESS_MASK 0xffff0000 4626 #define MC_XPB_P2P_BAR5__ADDRESS__SHIFT 0x10 4627 #define MC_XPB_P2P_BAR6__HOST_FLUSH_MASK 0xf 4628 #define MC_XPB_P2P_BAR6__HOST_FLUSH__SHIFT 0x0 4629 #define MC_XPB_P2P_BAR6__REG_SYS_BAR_MASK 0xf0 4630 #define MC_XPB_P2P_BAR6__REG_SYS_BAR__SHIFT 0x4 4631 #define MC_XPB_P2P_BAR6__MEM_SYS_BAR_MASK 0xf00 4632 #define MC_XPB_P2P_BAR6__MEM_SYS_BAR__SHIFT 0x8 4633 #define MC_XPB_P2P_BAR6__VALID_MASK 0x1000 4634 #define MC_XPB_P2P_BAR6__VALID__SHIFT 0xc 4635 #define MC_XPB_P2P_BAR6__SEND_DIS_MASK 0x2000 4636 #define MC_XPB_P2P_BAR6__SEND_DIS__SHIFT 0xd 4637 #define MC_XPB_P2P_BAR6__COMPRESS_DIS_MASK 0x4000 4638 #define MC_XPB_P2P_BAR6__COMPRESS_DIS__SHIFT 0xe 4639 #define MC_XPB_P2P_BAR6__RESERVED_MASK 0x8000 4640 #define MC_XPB_P2P_BAR6__RESERVED__SHIFT 0xf 4641 #define MC_XPB_P2P_BAR6__ADDRESS_MASK 0xffff0000 4642 #define MC_XPB_P2P_BAR6__ADDRESS__SHIFT 0x10 4643 #define MC_XPB_P2P_BAR7__HOST_FLUSH_MASK 0xf 4644 #define MC_XPB_P2P_BAR7__HOST_FLUSH__SHIFT 0x0 4645 #define MC_XPB_P2P_BAR7__REG_SYS_BAR_MASK 0xf0 4646 #define MC_XPB_P2P_BAR7__REG_SYS_BAR__SHIFT 0x4 4647 #define MC_XPB_P2P_BAR7__MEM_SYS_BAR_MASK 0xf00 4648 #define MC_XPB_P2P_BAR7__MEM_SYS_BAR__SHIFT 0x8 4649 #define MC_XPB_P2P_BAR7__VALID_MASK 0x1000 4650 #define MC_XPB_P2P_BAR7__VALID__SHIFT 0xc 4651 #define MC_XPB_P2P_BAR7__SEND_DIS_MASK 0x2000 4652 #define MC_XPB_P2P_BAR7__SEND_DIS__SHIFT 0xd 4653 #define MC_XPB_P2P_BAR7__COMPRESS_DIS_MASK 0x4000 4654 #define MC_XPB_P2P_BAR7__COMPRESS_DIS__SHIFT 0xe 4655 #define MC_XPB_P2P_BAR7__RESERVED_MASK 0x8000 4656 #define MC_XPB_P2P_BAR7__RESERVED__SHIFT 0xf 4657 #define MC_XPB_P2P_BAR7__ADDRESS_MASK 0xffff0000 4658 #define MC_XPB_P2P_BAR7__ADDRESS__SHIFT 0x10 4659 #define MC_XPB_P2P_BAR_SETUP__SEL_MASK 0xff 4660 #define MC_XPB_P2P_BAR_SETUP__SEL__SHIFT 0x0 4661 #define MC_XPB_P2P_BAR_SETUP__REG_SYS_BAR_MASK 0xf00 4662 #define MC_XPB_P2P_BAR_SETUP__REG_SYS_BAR__SHIFT 0x8 4663 #define MC_XPB_P2P_BAR_SETUP__VALID_MASK 0x1000 4664 #define MC_XPB_P2P_BAR_SETUP__VALID__SHIFT 0xc 4665 #define MC_XPB_P2P_BAR_SETUP__SEND_DIS_MASK 0x2000 4666 #define MC_XPB_P2P_BAR_SETUP__SEND_DIS__SHIFT 0xd 4667 #define MC_XPB_P2P_BAR_SETUP__COMPRESS_DIS_MASK 0x4000 4668 #define MC_XPB_P2P_BAR_SETUP__COMPRESS_DIS__SHIFT 0xe 4669 #define MC_XPB_P2P_BAR_SETUP__RESERVED_MASK 0x8000 4670 #define MC_XPB_P2P_BAR_SETUP__RESERVED__SHIFT 0xf 4671 #define MC_XPB_P2P_BAR_SETUP__ADDRESS_MASK 0xffff0000 4672 #define MC_XPB_P2P_BAR_SETUP__ADDRESS__SHIFT 0x10 4673 #define MC_XPB_P2P_BAR_DEBUG__SEL_MASK 0xff 4674 #define MC_XPB_P2P_BAR_DEBUG__SEL__SHIFT 0x0 4675 #define MC_XPB_P2P_BAR_DEBUG__HOST_FLUSH_MASK 0xf00 4676 #define MC_XPB_P2P_BAR_DEBUG__HOST_FLUSH__SHIFT 0x8 4677 #define MC_XPB_P2P_BAR_DEBUG__MEM_SYS_BAR_MASK 0xf000 4678 #define MC_XPB_P2P_BAR_DEBUG__MEM_SYS_BAR__SHIFT 0xc 4679 #define MC_XPB_P2P_BAR_DELTA_ABOVE__EN_MASK 0xff 4680 #define MC_XPB_P2P_BAR_DELTA_ABOVE__EN__SHIFT 0x0 4681 #define MC_XPB_P2P_BAR_DELTA_ABOVE__DELTA_MASK 0xfffff00 4682 #define MC_XPB_P2P_BAR_DELTA_ABOVE__DELTA__SHIFT 0x8 4683 #define MC_XPB_P2P_BAR_DELTA_BELOW__EN_MASK 0xff 4684 #define MC_XPB_P2P_BAR_DELTA_BELOW__EN__SHIFT 0x0 4685 #define MC_XPB_P2P_BAR_DELTA_BELOW__DELTA_MASK 0xfffff00 4686 #define MC_XPB_P2P_BAR_DELTA_BELOW__DELTA__SHIFT 0x8 4687 #define MC_XPB_PEER_SYS_BAR0__VALID_MASK 0x1 4688 #define MC_XPB_PEER_SYS_BAR0__VALID__SHIFT 0x0 4689 #define MC_XPB_PEER_SYS_BAR0__SIDE_OK_MASK 0x2 4690 #define MC_XPB_PEER_SYS_BAR0__SIDE_OK__SHIFT 0x1 4691 #define MC_XPB_PEER_SYS_BAR0__ADDR_MASK 0x7fffffc 4692 #define MC_XPB_PEER_SYS_BAR0__ADDR__SHIFT 0x2 4693 #define MC_XPB_PEER_SYS_BAR1__VALID_MASK 0x1 4694 #define MC_XPB_PEER_SYS_BAR1__VALID__SHIFT 0x0 4695 #define MC_XPB_PEER_SYS_BAR1__SIDE_OK_MASK 0x2 4696 #define MC_XPB_PEER_SYS_BAR1__SIDE_OK__SHIFT 0x1 4697 #define MC_XPB_PEER_SYS_BAR1__ADDR_MASK 0x7fffffc 4698 #define MC_XPB_PEER_SYS_BAR1__ADDR__SHIFT 0x2 4699 #define MC_XPB_PEER_SYS_BAR2__VALID_MASK 0x1 4700 #define MC_XPB_PEER_SYS_BAR2__VALID__SHIFT 0x0 4701 #define MC_XPB_PEER_SYS_BAR2__SIDE_OK_MASK 0x2 4702 #define MC_XPB_PEER_SYS_BAR2__SIDE_OK__SHIFT 0x1 4703 #define MC_XPB_PEER_SYS_BAR2__ADDR_MASK 0x7fffffc 4704 #define MC_XPB_PEER_SYS_BAR2__ADDR__SHIFT 0x2 4705 #define MC_XPB_PEER_SYS_BAR3__VALID_MASK 0x1 4706 #define MC_XPB_PEER_SYS_BAR3__VALID__SHIFT 0x0 4707 #define MC_XPB_PEER_SYS_BAR3__SIDE_OK_MASK 0x2 4708 #define MC_XPB_PEER_SYS_BAR3__SIDE_OK__SHIFT 0x1 4709 #define MC_XPB_PEER_SYS_BAR3__ADDR_MASK 0x7fffffc 4710 #define MC_XPB_PEER_SYS_BAR3__ADDR__SHIFT 0x2 4711 #define MC_XPB_PEER_SYS_BAR4__VALID_MASK 0x1 4712 #define MC_XPB_PEER_SYS_BAR4__VALID__SHIFT 0x0 4713 #define MC_XPB_PEER_SYS_BAR4__SIDE_OK_MASK 0x2 4714 #define MC_XPB_PEER_SYS_BAR4__SIDE_OK__SHIFT 0x1 4715 #define MC_XPB_PEER_SYS_BAR4__ADDR_MASK 0x7fffffc 4716 #define MC_XPB_PEER_SYS_BAR4__ADDR__SHIFT 0x2 4717 #define MC_XPB_PEER_SYS_BAR5__VALID_MASK 0x1 4718 #define MC_XPB_PEER_SYS_BAR5__VALID__SHIFT 0x0 4719 #define MC_XPB_PEER_SYS_BAR5__SIDE_OK_MASK 0x2 4720 #define MC_XPB_PEER_SYS_BAR5__SIDE_OK__SHIFT 0x1 4721 #define MC_XPB_PEER_SYS_BAR5__ADDR_MASK 0x7fffffc 4722 #define MC_XPB_PEER_SYS_BAR5__ADDR__SHIFT 0x2 4723 #define MC_XPB_PEER_SYS_BAR6__VALID_MASK 0x1 4724 #define MC_XPB_PEER_SYS_BAR6__VALID__SHIFT 0x0 4725 #define MC_XPB_PEER_SYS_BAR6__SIDE_OK_MASK 0x2 4726 #define MC_XPB_PEER_SYS_BAR6__SIDE_OK__SHIFT 0x1 4727 #define MC_XPB_PEER_SYS_BAR6__ADDR_MASK 0x7fffffc 4728 #define MC_XPB_PEER_SYS_BAR6__ADDR__SHIFT 0x2 4729 #define MC_XPB_PEER_SYS_BAR7__VALID_MASK 0x1 4730 #define MC_XPB_PEER_SYS_BAR7__VALID__SHIFT 0x0 4731 #define MC_XPB_PEER_SYS_BAR7__SIDE_OK_MASK 0x2 4732 #define MC_XPB_PEER_SYS_BAR7__SIDE_OK__SHIFT 0x1 4733 #define MC_XPB_PEER_SYS_BAR7__ADDR_MASK 0x7fffffc 4734 #define MC_XPB_PEER_SYS_BAR7__ADDR__SHIFT 0x2 4735 #define MC_XPB_PEER_SYS_BAR8__VALID_MASK 0x1 4736 #define MC_XPB_PEER_SYS_BAR8__VALID__SHIFT 0x0 4737 #define MC_XPB_PEER_SYS_BAR8__SIDE_OK_MASK 0x2 4738 #define MC_XPB_PEER_SYS_BAR8__SIDE_OK__SHIFT 0x1 4739 #define MC_XPB_PEER_SYS_BAR8__ADDR_MASK 0x7fffffc 4740 #define MC_XPB_PEER_SYS_BAR8__ADDR__SHIFT 0x2 4741 #define MC_XPB_PEER_SYS_BAR9__VALID_MASK 0x1 4742 #define MC_XPB_PEER_SYS_BAR9__VALID__SHIFT 0x0 4743 #define MC_XPB_PEER_SYS_BAR9__SIDE_OK_MASK 0x2 4744 #define MC_XPB_PEER_SYS_BAR9__SIDE_OK__SHIFT 0x1 4745 #define MC_XPB_PEER_SYS_BAR9__ADDR_MASK 0x7fffffc 4746 #define MC_XPB_PEER_SYS_BAR9__ADDR__SHIFT 0x2 4747 #define MC_XPB_XDMA_PEER_SYS_BAR0__VALID_MASK 0x1 4748 #define MC_XPB_XDMA_PEER_SYS_BAR0__VALID__SHIFT 0x0 4749 #define MC_XPB_XDMA_PEER_SYS_BAR0__SIDE_OK_MASK 0x2 4750 #define MC_XPB_XDMA_PEER_SYS_BAR0__SIDE_OK__SHIFT 0x1 4751 #define MC_XPB_XDMA_PEER_SYS_BAR0__ADDR_MASK 0x7fffffc 4752 #define MC_XPB_XDMA_PEER_SYS_BAR0__ADDR__SHIFT 0x2 4753 #define MC_XPB_XDMA_PEER_SYS_BAR1__VALID_MASK 0x1 4754 #define MC_XPB_XDMA_PEER_SYS_BAR1__VALID__SHIFT 0x0 4755 #define MC_XPB_XDMA_PEER_SYS_BAR1__SIDE_OK_MASK 0x2 4756 #define MC_XPB_XDMA_PEER_SYS_BAR1__SIDE_OK__SHIFT 0x1 4757 #define MC_XPB_XDMA_PEER_SYS_BAR1__ADDR_MASK 0x7fffffc 4758 #define MC_XPB_XDMA_PEER_SYS_BAR1__ADDR__SHIFT 0x2 4759 #define MC_XPB_XDMA_PEER_SYS_BAR2__VALID_MASK 0x1 4760 #define MC_XPB_XDMA_PEER_SYS_BAR2__VALID__SHIFT 0x0 4761 #define MC_XPB_XDMA_PEER_SYS_BAR2__SIDE_OK_MASK 0x2 4762 #define MC_XPB_XDMA_PEER_SYS_BAR2__SIDE_OK__SHIFT 0x1 4763 #define MC_XPB_XDMA_PEER_SYS_BAR2__ADDR_MASK 0x7fffffc 4764 #define MC_XPB_XDMA_PEER_SYS_BAR2__ADDR__SHIFT 0x2 4765 #define MC_XPB_XDMA_PEER_SYS_BAR3__VALID_MASK 0x1 4766 #define MC_XPB_XDMA_PEER_SYS_BAR3__VALID__SHIFT 0x0 4767 #define MC_XPB_XDMA_PEER_SYS_BAR3__SIDE_OK_MASK 0x2 4768 #define MC_XPB_XDMA_PEER_SYS_BAR3__SIDE_OK__SHIFT 0x1 4769 #define MC_XPB_XDMA_PEER_SYS_BAR3__ADDR_MASK 0x7fffffc 4770 #define MC_XPB_XDMA_PEER_SYS_BAR3__ADDR__SHIFT 0x2 4771 #define MC_XPB_CLK_GAT__ONDLY_MASK 0x3f 4772 #define MC_XPB_CLK_GAT__ONDLY__SHIFT 0x0 4773 #define MC_XPB_CLK_GAT__OFFDLY_MASK 0xfc0 4774 #define MC_XPB_CLK_GAT__OFFDLY__SHIFT 0x6 4775 #define MC_XPB_CLK_GAT__RDYDLY_MASK 0x3f000 4776 #define MC_XPB_CLK_GAT__RDYDLY__SHIFT 0xc 4777 #define MC_XPB_CLK_GAT__ENABLE_MASK 0x40000 4778 #define MC_XPB_CLK_GAT__ENABLE__SHIFT 0x12 4779 #define MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK 0x80000 4780 #define MC_XPB_CLK_GAT__MEM_LS_ENABLE__SHIFT 0x13 4781 #define MC_XPB_INTF_CFG__RPB_WRREQ_CRD_MASK 0xff 4782 #define MC_XPB_INTF_CFG__RPB_WRREQ_CRD__SHIFT 0x0 4783 #define MC_XPB_INTF_CFG__MC_WRRET_ASK_MASK 0xff00 4784 #define MC_XPB_INTF_CFG__MC_WRRET_ASK__SHIFT 0x8 4785 #define MC_XPB_INTF_CFG__XSP_REQ_CRD_MASK 0x7f0000 4786 #define MC_XPB_INTF_CFG__XSP_REQ_CRD__SHIFT 0x10 4787 #define MC_XPB_INTF_CFG__BIF_REG_SNOOP_SEL_MASK 0x800000 4788 #define MC_XPB_INTF_CFG__BIF_REG_SNOOP_SEL__SHIFT 0x17 4789 #define MC_XPB_INTF_CFG__BIF_REG_SNOOP_VAL_MASK 0x1000000 4790 #define MC_XPB_INTF_CFG__BIF_REG_SNOOP_VAL__SHIFT 0x18 4791 #define MC_XPB_INTF_CFG__BIF_MEM_SNOOP_SEL_MASK 0x2000000 4792 #define MC_XPB_INTF_CFG__BIF_MEM_SNOOP_SEL__SHIFT 0x19 4793 #define MC_XPB_INTF_CFG__BIF_MEM_SNOOP_VAL_MASK 0x4000000 4794 #define MC_XPB_INTF_CFG__BIF_MEM_SNOOP_VAL__SHIFT 0x1a 4795 #define MC_XPB_INTF_CFG__XSP_SNOOP_SEL_MASK 0x18000000 4796 #define MC_XPB_INTF_CFG__XSP_SNOOP_SEL__SHIFT 0x1b 4797 #define MC_XPB_INTF_CFG__XSP_SNOOP_VAL_MASK 0x20000000 4798 #define MC_XPB_INTF_CFG__XSP_SNOOP_VAL__SHIFT 0x1d 4799 #define MC_XPB_INTF_CFG__XSP_ORDERING_SEL_MASK 0x40000000 4800 #define MC_XPB_INTF_CFG__XSP_ORDERING_SEL__SHIFT 0x1e 4801 #define MC_XPB_INTF_CFG__XSP_ORDERING_VAL_MASK 0x80000000 4802 #define MC_XPB_INTF_CFG__XSP_ORDERING_VAL__SHIFT 0x1f 4803 #define MC_XPB_INTF_STS__RPB_WRREQ_CRD_MASK 0xff 4804 #define MC_XPB_INTF_STS__RPB_WRREQ_CRD__SHIFT 0x0 4805 #define MC_XPB_INTF_STS__XSP_REQ_CRD_MASK 0x7f00 4806 #define MC_XPB_INTF_STS__XSP_REQ_CRD__SHIFT 0x8 4807 #define MC_XPB_INTF_STS__HOP_DATA_BUF_FULL_MASK 0x8000 4808 #define MC_XPB_INTF_STS__HOP_DATA_BUF_FULL__SHIFT 0xf 4809 #define MC_XPB_INTF_STS__HOP_ATTR_BUF_FULL_MASK 0x10000 4810 #define MC_XPB_INTF_STS__HOP_ATTR_BUF_FULL__SHIFT 0x10 4811 #define MC_XPB_INTF_STS__CNS_BUF_FULL_MASK 0x20000 4812 #define MC_XPB_INTF_STS__CNS_BUF_FULL__SHIFT 0x11 4813 #define MC_XPB_INTF_STS__CNS_BUF_BUSY_MASK 0x40000 4814 #define MC_XPB_INTF_STS__CNS_BUF_BUSY__SHIFT 0x12 4815 #define MC_XPB_INTF_STS__RPB_RDREQ_CRD_MASK 0x7f80000 4816 #define MC_XPB_INTF_STS__RPB_RDREQ_CRD__SHIFT 0x13 4817 #define MC_XPB_PIPE_STS__WCB_ANY_PBUF_MASK 0x1 4818 #define MC_XPB_PIPE_STS__WCB_ANY_PBUF__SHIFT 0x0 4819 #define MC_XPB_PIPE_STS__WCB_HST_DATA_BUF_CNT_MASK 0xfe 4820 #define MC_XPB_PIPE_STS__WCB_HST_DATA_BUF_CNT__SHIFT 0x1 4821 #define MC_XPB_PIPE_STS__WCB_SID_DATA_BUF_CNT_MASK 0x7f00 4822 #define MC_XPB_PIPE_STS__WCB_SID_DATA_BUF_CNT__SHIFT 0x8 4823 #define MC_XPB_PIPE_STS__WCB_HST_RD_PTR_BUF_FULL_MASK 0x8000 4824 #define MC_XPB_PIPE_STS__WCB_HST_RD_PTR_BUF_FULL__SHIFT 0xf 4825 #define MC_XPB_PIPE_STS__WCB_SID_RD_PTR_BUF_FULL_MASK 0x10000 4826 #define MC_XPB_PIPE_STS__WCB_SID_RD_PTR_BUF_FULL__SHIFT 0x10 4827 #define MC_XPB_PIPE_STS__WCB_HST_REQ_FIFO_FULL_MASK 0x20000 4828 #define MC_XPB_PIPE_STS__WCB_HST_REQ_FIFO_FULL__SHIFT 0x11 4829 #define MC_XPB_PIPE_STS__WCB_SID_REQ_FIFO_FULL_MASK 0x40000 4830 #define MC_XPB_PIPE_STS__WCB_SID_REQ_FIFO_FULL__SHIFT 0x12 4831 #define MC_XPB_PIPE_STS__WCB_HST_REQ_OBUF_FULL_MASK 0x80000 4832 #define MC_XPB_PIPE_STS__WCB_HST_REQ_OBUF_FULL__SHIFT 0x13 4833 #define MC_XPB_PIPE_STS__WCB_SID_REQ_OBUF_FULL_MASK 0x100000 4834 #define MC_XPB_PIPE_STS__WCB_SID_REQ_OBUF_FULL__SHIFT 0x14 4835 #define MC_XPB_PIPE_STS__WCB_HST_DATA_OBUF_FULL_MASK 0x200000 4836 #define MC_XPB_PIPE_STS__WCB_HST_DATA_OBUF_FULL__SHIFT 0x15 4837 #define MC_XPB_PIPE_STS__WCB_SID_DATA_OBUF_FULL_MASK 0x400000 4838 #define MC_XPB_PIPE_STS__WCB_SID_DATA_OBUF_FULL__SHIFT 0x16 4839 #define MC_XPB_PIPE_STS__RET_BUF_FULL_MASK 0x800000 4840 #define MC_XPB_PIPE_STS__RET_BUF_FULL__SHIFT 0x17 4841 #define MC_XPB_PIPE_STS__XPB_CLK_BUSY_BITS_MASK 0xff000000 4842 #define MC_XPB_PIPE_STS__XPB_CLK_BUSY_BITS__SHIFT 0x18 4843 #define MC_XPB_SUB_CTRL__WRREQ_BYPASS_XPB_MASK 0x1 4844 #define MC_XPB_SUB_CTRL__WRREQ_BYPASS_XPB__SHIFT 0x0 4845 #define MC_XPB_SUB_CTRL__STALL_CNS_RTR_REQ_MASK 0x2 4846 #define MC_XPB_SUB_CTRL__STALL_CNS_RTR_REQ__SHIFT 0x1 4847 #define MC_XPB_SUB_CTRL__STALL_RTR_RPB_WRREQ_MASK 0x4 4848 #define MC_XPB_SUB_CTRL__STALL_RTR_RPB_WRREQ__SHIFT 0x2 4849 #define MC_XPB_SUB_CTRL__STALL_RTR_MAP_REQ_MASK 0x8 4850 #define MC_XPB_SUB_CTRL__STALL_RTR_MAP_REQ__SHIFT 0x3 4851 #define MC_XPB_SUB_CTRL__STALL_MAP_WCB_REQ_MASK 0x10 4852 #define MC_XPB_SUB_CTRL__STALL_MAP_WCB_REQ__SHIFT 0x4 4853 #define MC_XPB_SUB_CTRL__STALL_WCB_SID_REQ_MASK 0x20 4854 #define MC_XPB_SUB_CTRL__STALL_WCB_SID_REQ__SHIFT 0x5 4855 #define MC_XPB_SUB_CTRL__STALL_MC_XSP_REQ_SEND_MASK 0x40 4856 #define MC_XPB_SUB_CTRL__STALL_MC_XSP_REQ_SEND__SHIFT 0x6 4857 #define MC_XPB_SUB_CTRL__STALL_WCB_HST_REQ_MASK 0x80 4858 #define MC_XPB_SUB_CTRL__STALL_WCB_HST_REQ__SHIFT 0x7 4859 #define MC_XPB_SUB_CTRL__STALL_HST_HOP_REQ_MASK 0x100 4860 #define MC_XPB_SUB_CTRL__STALL_HST_HOP_REQ__SHIFT 0x8 4861 #define MC_XPB_SUB_CTRL__STALL_XPB_RPB_REQ_ATTR_MASK 0x200 4862 #define MC_XPB_SUB_CTRL__STALL_XPB_RPB_REQ_ATTR__SHIFT 0x9 4863 #define MC_XPB_SUB_CTRL__RESET_CNS_MASK 0x400 4864 #define MC_XPB_SUB_CTRL__RESET_CNS__SHIFT 0xa 4865 #define MC_XPB_SUB_CTRL__RESET_RTR_MASK 0x800 4866 #define MC_XPB_SUB_CTRL__RESET_RTR__SHIFT 0xb 4867 #define MC_XPB_SUB_CTRL__RESET_RET_MASK 0x1000 4868 #define MC_XPB_SUB_CTRL__RESET_RET__SHIFT 0xc 4869 #define MC_XPB_SUB_CTRL__RESET_MAP_MASK 0x2000 4870 #define MC_XPB_SUB_CTRL__RESET_MAP__SHIFT 0xd 4871 #define MC_XPB_SUB_CTRL__RESET_WCB_MASK 0x4000 4872 #define MC_XPB_SUB_CTRL__RESET_WCB__SHIFT 0xe 4873 #define MC_XPB_SUB_CTRL__RESET_HST_MASK 0x8000 4874 #define MC_XPB_SUB_CTRL__RESET_HST__SHIFT 0xf 4875 #define MC_XPB_SUB_CTRL__RESET_HOP_MASK 0x10000 4876 #define MC_XPB_SUB_CTRL__RESET_HOP__SHIFT 0x10 4877 #define MC_XPB_SUB_CTRL__RESET_SID_MASK 0x20000 4878 #define MC_XPB_SUB_CTRL__RESET_SID__SHIFT 0x11 4879 #define MC_XPB_SUB_CTRL__RESET_SRB_MASK 0x40000 4880 #define MC_XPB_SUB_CTRL__RESET_SRB__SHIFT 0x12 4881 #define MC_XPB_SUB_CTRL__RESET_CGR_MASK 0x80000 4882 #define MC_XPB_SUB_CTRL__RESET_CGR__SHIFT 0x13 4883 #define MC_XPB_MAP_INVERT_FLUSH_NUM_LSB__ALTER_FLUSH_NUM_MASK 0xffff 4884 #define MC_XPB_MAP_INVERT_FLUSH_NUM_LSB__ALTER_FLUSH_NUM__SHIFT 0x0 4885 #define MC_XPB_PERF_KNOBS__CNS_FIFO_DEPTH_MASK 0x3f 4886 #define MC_XPB_PERF_KNOBS__CNS_FIFO_DEPTH__SHIFT 0x0 4887 #define MC_XPB_PERF_KNOBS__WCB_HST_FIFO_DEPTH_MASK 0xfc0 4888 #define MC_XPB_PERF_KNOBS__WCB_HST_FIFO_DEPTH__SHIFT 0x6 4889 #define MC_XPB_PERF_KNOBS__WCB_SID_FIFO_DEPTH_MASK 0x3f000 4890 #define MC_XPB_PERF_KNOBS__WCB_SID_FIFO_DEPTH__SHIFT 0xc 4891 #define MC_XPB_STICKY__BITS_MASK 0xffffffff 4892 #define MC_XPB_STICKY__BITS__SHIFT 0x0 4893 #define MC_XPB_STICKY_W1C__BITS_MASK 0xffffffff 4894 #define MC_XPB_STICKY_W1C__BITS__SHIFT 0x0 4895 #define MC_XPB_MISC_CFG__FIELDNAME0_MASK 0xff 4896 #define MC_XPB_MISC_CFG__FIELDNAME0__SHIFT 0x0 4897 #define MC_XPB_MISC_CFG__FIELDNAME1_MASK 0xff00 4898 #define MC_XPB_MISC_CFG__FIELDNAME1__SHIFT 0x8 4899 #define MC_XPB_MISC_CFG__FIELDNAME2_MASK 0xff0000 4900 #define MC_XPB_MISC_CFG__FIELDNAME2__SHIFT 0x10 4901 #define MC_XPB_MISC_CFG__FIELDNAME3_MASK 0x7f000000 4902 #define MC_XPB_MISC_CFG__FIELDNAME3__SHIFT 0x18 4903 #define MC_XPB_MISC_CFG__TRIGGERNAME_MASK 0x80000000 4904 #define MC_XPB_MISC_CFG__TRIGGERNAME__SHIFT 0x1f 4905 #define MC_XPB_CLG_CFG20__WCB_NUM_MASK 0xf 4906 #define MC_XPB_CLG_CFG20__WCB_NUM__SHIFT 0x0 4907 #define MC_XPB_CLG_CFG20__LB_TYPE_MASK 0x70 4908 #define MC_XPB_CLG_CFG20__LB_TYPE__SHIFT 0x4 4909 #define MC_XPB_CLG_CFG20__P2P_BAR_MASK 0x380 4910 #define MC_XPB_CLG_CFG20__P2P_BAR__SHIFT 0x7 4911 #define MC_XPB_CLG_CFG20__HOST_FLUSH_MASK 0x3c00 4912 #define MC_XPB_CLG_CFG20__HOST_FLUSH__SHIFT 0xa 4913 #define MC_XPB_CLG_CFG20__SIDE_FLUSH_MASK 0x3c000 4914 #define MC_XPB_CLG_CFG20__SIDE_FLUSH__SHIFT 0xe 4915 #define MC_XPB_CLG_CFG21__WCB_NUM_MASK 0xf 4916 #define MC_XPB_CLG_CFG21__WCB_NUM__SHIFT 0x0 4917 #define MC_XPB_CLG_CFG21__LB_TYPE_MASK 0x70 4918 #define MC_XPB_CLG_CFG21__LB_TYPE__SHIFT 0x4 4919 #define MC_XPB_CLG_CFG21__P2P_BAR_MASK 0x380 4920 #define MC_XPB_CLG_CFG21__P2P_BAR__SHIFT 0x7 4921 #define MC_XPB_CLG_CFG21__HOST_FLUSH_MASK 0x3c00 4922 #define MC_XPB_CLG_CFG21__HOST_FLUSH__SHIFT 0xa 4923 #define MC_XPB_CLG_CFG21__SIDE_FLUSH_MASK 0x3c000 4924 #define MC_XPB_CLG_CFG21__SIDE_FLUSH__SHIFT 0xe 4925 #define MC_XPB_CLG_CFG22__WCB_NUM_MASK 0xf 4926 #define MC_XPB_CLG_CFG22__WCB_NUM__SHIFT 0x0 4927 #define MC_XPB_CLG_CFG22__LB_TYPE_MASK 0x70 4928 #define MC_XPB_CLG_CFG22__LB_TYPE__SHIFT 0x4 4929 #define MC_XPB_CLG_CFG22__P2P_BAR_MASK 0x380 4930 #define MC_XPB_CLG_CFG22__P2P_BAR__SHIFT 0x7 4931 #define MC_XPB_CLG_CFG22__HOST_FLUSH_MASK 0x3c00 4932 #define MC_XPB_CLG_CFG22__HOST_FLUSH__SHIFT 0xa 4933 #define MC_XPB_CLG_CFG22__SIDE_FLUSH_MASK 0x3c000 4934 #define MC_XPB_CLG_CFG22__SIDE_FLUSH__SHIFT 0xe 4935 #define MC_XPB_CLG_CFG23__WCB_NUM_MASK 0xf 4936 #define MC_XPB_CLG_CFG23__WCB_NUM__SHIFT 0x0 4937 #define MC_XPB_CLG_CFG23__LB_TYPE_MASK 0x70 4938 #define MC_XPB_CLG_CFG23__LB_TYPE__SHIFT 0x4 4939 #define MC_XPB_CLG_CFG23__P2P_BAR_MASK 0x380 4940 #define MC_XPB_CLG_CFG23__P2P_BAR__SHIFT 0x7 4941 #define MC_XPB_CLG_CFG23__HOST_FLUSH_MASK 0x3c00 4942 #define MC_XPB_CLG_CFG23__HOST_FLUSH__SHIFT 0xa 4943 #define MC_XPB_CLG_CFG23__SIDE_FLUSH_MASK 0x3c000 4944 #define MC_XPB_CLG_CFG23__SIDE_FLUSH__SHIFT 0xe 4945 #define MC_XPB_CLG_CFG24__WCB_NUM_MASK 0xf 4946 #define MC_XPB_CLG_CFG24__WCB_NUM__SHIFT 0x0 4947 #define MC_XPB_CLG_CFG24__LB_TYPE_MASK 0x70 4948 #define MC_XPB_CLG_CFG24__LB_TYPE__SHIFT 0x4 4949 #define MC_XPB_CLG_CFG24__P2P_BAR_MASK 0x380 4950 #define MC_XPB_CLG_CFG24__P2P_BAR__SHIFT 0x7 4951 #define MC_XPB_CLG_CFG24__HOST_FLUSH_MASK 0x3c00 4952 #define MC_XPB_CLG_CFG24__HOST_FLUSH__SHIFT 0xa 4953 #define MC_XPB_CLG_CFG24__SIDE_FLUSH_MASK 0x3c000 4954 #define MC_XPB_CLG_CFG24__SIDE_FLUSH__SHIFT 0xe 4955 #define MC_XPB_CLG_CFG25__WCB_NUM_MASK 0xf 4956 #define MC_XPB_CLG_CFG25__WCB_NUM__SHIFT 0x0 4957 #define MC_XPB_CLG_CFG25__LB_TYPE_MASK 0x70 4958 #define MC_XPB_CLG_CFG25__LB_TYPE__SHIFT 0x4 4959 #define MC_XPB_CLG_CFG25__P2P_BAR_MASK 0x380 4960 #define MC_XPB_CLG_CFG25__P2P_BAR__SHIFT 0x7 4961 #define MC_XPB_CLG_CFG25__HOST_FLUSH_MASK 0x3c00 4962 #define MC_XPB_CLG_CFG25__HOST_FLUSH__SHIFT 0xa 4963 #define MC_XPB_CLG_CFG25__SIDE_FLUSH_MASK 0x3c000 4964 #define MC_XPB_CLG_CFG25__SIDE_FLUSH__SHIFT 0xe 4965 #define MC_XPB_CLG_CFG26__WCB_NUM_MASK 0xf 4966 #define MC_XPB_CLG_CFG26__WCB_NUM__SHIFT 0x0 4967 #define MC_XPB_CLG_CFG26__LB_TYPE_MASK 0x70 4968 #define MC_XPB_CLG_CFG26__LB_TYPE__SHIFT 0x4 4969 #define MC_XPB_CLG_CFG26__P2P_BAR_MASK 0x380 4970 #define MC_XPB_CLG_CFG26__P2P_BAR__SHIFT 0x7 4971 #define MC_XPB_CLG_CFG26__HOST_FLUSH_MASK 0x3c00 4972 #define MC_XPB_CLG_CFG26__HOST_FLUSH__SHIFT 0xa 4973 #define MC_XPB_CLG_CFG26__SIDE_FLUSH_MASK 0x3c000 4974 #define MC_XPB_CLG_CFG26__SIDE_FLUSH__SHIFT 0xe 4975 #define MC_XPB_CLG_CFG27__WCB_NUM_MASK 0xf 4976 #define MC_XPB_CLG_CFG27__WCB_NUM__SHIFT 0x0 4977 #define MC_XPB_CLG_CFG27__LB_TYPE_MASK 0x70 4978 #define MC_XPB_CLG_CFG27__LB_TYPE__SHIFT 0x4 4979 #define MC_XPB_CLG_CFG27__P2P_BAR_MASK 0x380 4980 #define MC_XPB_CLG_CFG27__P2P_BAR__SHIFT 0x7 4981 #define MC_XPB_CLG_CFG27__HOST_FLUSH_MASK 0x3c00 4982 #define MC_XPB_CLG_CFG27__HOST_FLUSH__SHIFT 0xa 4983 #define MC_XPB_CLG_CFG27__SIDE_FLUSH_MASK 0x3c000 4984 #define MC_XPB_CLG_CFG27__SIDE_FLUSH__SHIFT 0xe 4985 #define MC_XPB_CLG_CFG28__WCB_NUM_MASK 0xf 4986 #define MC_XPB_CLG_CFG28__WCB_NUM__SHIFT 0x0 4987 #define MC_XPB_CLG_CFG28__LB_TYPE_MASK 0x70 4988 #define MC_XPB_CLG_CFG28__LB_TYPE__SHIFT 0x4 4989 #define MC_XPB_CLG_CFG28__P2P_BAR_MASK 0x380 4990 #define MC_XPB_CLG_CFG28__P2P_BAR__SHIFT 0x7 4991 #define MC_XPB_CLG_CFG28__HOST_FLUSH_MASK 0x3c00 4992 #define MC_XPB_CLG_CFG28__HOST_FLUSH__SHIFT 0xa 4993 #define MC_XPB_CLG_CFG28__SIDE_FLUSH_MASK 0x3c000 4994 #define MC_XPB_CLG_CFG28__SIDE_FLUSH__SHIFT 0xe 4995 #define MC_XPB_CLG_CFG29__WCB_NUM_MASK 0xf 4996 #define MC_XPB_CLG_CFG29__WCB_NUM__SHIFT 0x0 4997 #define MC_XPB_CLG_CFG29__LB_TYPE_MASK 0x70 4998 #define MC_XPB_CLG_CFG29__LB_TYPE__SHIFT 0x4 4999 #define MC_XPB_CLG_CFG29__P2P_BAR_MASK 0x380 5000 #define MC_XPB_CLG_CFG29__P2P_BAR__SHIFT 0x7 5001 #define MC_XPB_CLG_CFG29__HOST_FLUSH_MASK 0x3c00 5002 #define MC_XPB_CLG_CFG29__HOST_FLUSH__SHIFT 0xa 5003 #define MC_XPB_CLG_CFG29__SIDE_FLUSH_MASK 0x3c000 5004 #define MC_XPB_CLG_CFG29__SIDE_FLUSH__SHIFT 0xe 5005 #define MC_XPB_CLG_CFG30__WCB_NUM_MASK 0xf 5006 #define MC_XPB_CLG_CFG30__WCB_NUM__SHIFT 0x0 5007 #define MC_XPB_CLG_CFG30__LB_TYPE_MASK 0x70 5008 #define MC_XPB_CLG_CFG30__LB_TYPE__SHIFT 0x4 5009 #define MC_XPB_CLG_CFG30__P2P_BAR_MASK 0x380 5010 #define MC_XPB_CLG_CFG30__P2P_BAR__SHIFT 0x7 5011 #define MC_XPB_CLG_CFG30__HOST_FLUSH_MASK 0x3c00 5012 #define MC_XPB_CLG_CFG30__HOST_FLUSH__SHIFT 0xa 5013 #define MC_XPB_CLG_CFG30__SIDE_FLUSH_MASK 0x3c000 5014 #define MC_XPB_CLG_CFG30__SIDE_FLUSH__SHIFT 0xe 5015 #define MC_XPB_CLG_CFG31__WCB_NUM_MASK 0xf 5016 #define MC_XPB_CLG_CFG31__WCB_NUM__SHIFT 0x0 5017 #define MC_XPB_CLG_CFG31__LB_TYPE_MASK 0x70 5018 #define MC_XPB_CLG_CFG31__LB_TYPE__SHIFT 0x4 5019 #define MC_XPB_CLG_CFG31__P2P_BAR_MASK 0x380 5020 #define MC_XPB_CLG_CFG31__P2P_BAR__SHIFT 0x7 5021 #define MC_XPB_CLG_CFG31__HOST_FLUSH_MASK 0x3c00 5022 #define MC_XPB_CLG_CFG31__HOST_FLUSH__SHIFT 0xa 5023 #define MC_XPB_CLG_CFG31__SIDE_FLUSH_MASK 0x3c000 5024 #define MC_XPB_CLG_CFG31__SIDE_FLUSH__SHIFT 0xe 5025 #define MC_XPB_INTF_CFG2__RPB_RDREQ_CRD_MASK 0xff 5026 #define MC_XPB_INTF_CFG2__RPB_RDREQ_CRD__SHIFT 0x0 5027 #define MC_XPB_CLG_EXTRA_RD__CMP0_MASK 0xff 5028 #define MC_XPB_CLG_EXTRA_RD__CMP0__SHIFT 0x0 5029 #define MC_XPB_CLG_EXTRA_RD__MSK0_MASK 0xff00 5030 #define MC_XPB_CLG_EXTRA_RD__MSK0__SHIFT 0x8 5031 #define MC_XPB_CLG_EXTRA_RD__VLD0_MASK 0x10000 5032 #define MC_XPB_CLG_EXTRA_RD__VLD0__SHIFT 0x10 5033 #define MC_XPB_CLG_EXTRA_RD__CMP1_MASK 0x1fe0000 5034 #define MC_XPB_CLG_EXTRA_RD__CMP1__SHIFT 0x11 5035 #define MC_XPB_CLG_EXTRA_RD__VLD1_MASK 0x2000000 5036 #define MC_XPB_CLG_EXTRA_RD__VLD1__SHIFT 0x19 5037 #define MC_XPB_CLG_CFG32__WCB_NUM_MASK 0xf 5038 #define MC_XPB_CLG_CFG32__WCB_NUM__SHIFT 0x0 5039 #define MC_XPB_CLG_CFG32__LB_TYPE_MASK 0x70 5040 #define MC_XPB_CLG_CFG32__LB_TYPE__SHIFT 0x4 5041 #define MC_XPB_CLG_CFG32__P2P_BAR_MASK 0x380 5042 #define MC_XPB_CLG_CFG32__P2P_BAR__SHIFT 0x7 5043 #define MC_XPB_CLG_CFG32__HOST_FLUSH_MASK 0x3c00 5044 #define MC_XPB_CLG_CFG32__HOST_FLUSH__SHIFT 0xa 5045 #define MC_XPB_CLG_CFG32__SIDE_FLUSH_MASK 0x3c000 5046 #define MC_XPB_CLG_CFG32__SIDE_FLUSH__SHIFT 0xe 5047 #define MC_XPB_CLG_CFG33__WCB_NUM_MASK 0xf 5048 #define MC_XPB_CLG_CFG33__WCB_NUM__SHIFT 0x0 5049 #define MC_XPB_CLG_CFG33__LB_TYPE_MASK 0x70 5050 #define MC_XPB_CLG_CFG33__LB_TYPE__SHIFT 0x4 5051 #define MC_XPB_CLG_CFG33__P2P_BAR_MASK 0x380 5052 #define MC_XPB_CLG_CFG33__P2P_BAR__SHIFT 0x7 5053 #define MC_XPB_CLG_CFG33__HOST_FLUSH_MASK 0x3c00 5054 #define MC_XPB_CLG_CFG33__HOST_FLUSH__SHIFT 0xa 5055 #define MC_XPB_CLG_CFG33__SIDE_FLUSH_MASK 0x3c000 5056 #define MC_XPB_CLG_CFG33__SIDE_FLUSH__SHIFT 0xe 5057 #define MC_XPB_CLG_CFG34__WCB_NUM_MASK 0xf 5058 #define MC_XPB_CLG_CFG34__WCB_NUM__SHIFT 0x0 5059 #define MC_XPB_CLG_CFG34__LB_TYPE_MASK 0x70 5060 #define MC_XPB_CLG_CFG34__LB_TYPE__SHIFT 0x4 5061 #define MC_XPB_CLG_CFG34__P2P_BAR_MASK 0x380 5062 #define MC_XPB_CLG_CFG34__P2P_BAR__SHIFT 0x7 5063 #define MC_XPB_CLG_CFG34__HOST_FLUSH_MASK 0x3c00 5064 #define MC_XPB_CLG_CFG34__HOST_FLUSH__SHIFT 0xa 5065 #define MC_XPB_CLG_CFG34__SIDE_FLUSH_MASK 0x3c000 5066 #define MC_XPB_CLG_CFG34__SIDE_FLUSH__SHIFT 0xe 5067 #define MC_XPB_CLG_CFG35__WCB_NUM_MASK 0xf 5068 #define MC_XPB_CLG_CFG35__WCB_NUM__SHIFT 0x0 5069 #define MC_XPB_CLG_CFG35__LB_TYPE_MASK 0x70 5070 #define MC_XPB_CLG_CFG35__LB_TYPE__SHIFT 0x4 5071 #define MC_XPB_CLG_CFG35__P2P_BAR_MASK 0x380 5072 #define MC_XPB_CLG_CFG35__P2P_BAR__SHIFT 0x7 5073 #define MC_XPB_CLG_CFG35__HOST_FLUSH_MASK 0x3c00 5074 #define MC_XPB_CLG_CFG35__HOST_FLUSH__SHIFT 0xa 5075 #define MC_XPB_CLG_CFG35__SIDE_FLUSH_MASK 0x3c000 5076 #define MC_XPB_CLG_CFG35__SIDE_FLUSH__SHIFT 0xe 5077 #define MC_XPB_CLG_CFG36__WCB_NUM_MASK 0xf 5078 #define MC_XPB_CLG_CFG36__WCB_NUM__SHIFT 0x0 5079 #define MC_XPB_CLG_CFG36__LB_TYPE_MASK 0x70 5080 #define MC_XPB_CLG_CFG36__LB_TYPE__SHIFT 0x4 5081 #define MC_XPB_CLG_CFG36__P2P_BAR_MASK 0x380 5082 #define MC_XPB_CLG_CFG36__P2P_BAR__SHIFT 0x7 5083 #define MC_XPB_CLG_CFG36__HOST_FLUSH_MASK 0x3c00 5084 #define MC_XPB_CLG_CFG36__HOST_FLUSH__SHIFT 0xa 5085 #define MC_XPB_CLG_CFG36__SIDE_FLUSH_MASK 0x3c000 5086 #define MC_XPB_CLG_CFG36__SIDE_FLUSH__SHIFT 0xe 5087 #define MC_XBAR_ADDR_DEC__NO_DIV_BY_3_MASK 0x1 5088 #define MC_XBAR_ADDR_DEC__NO_DIV_BY_3__SHIFT 0x0 5089 #define MC_XBAR_ADDR_DEC__GECC_MASK 0x2 5090 #define MC_XBAR_ADDR_DEC__GECC__SHIFT 0x1 5091 #define MC_XBAR_ADDR_DEC__RB_SPLIT_MASK 0x4 5092 #define MC_XBAR_ADDR_DEC__RB_SPLIT__SHIFT 0x2 5093 #define MC_XBAR_ADDR_DEC__RB_SPLIT_COLHI_MASK 0x8 5094 #define MC_XBAR_ADDR_DEC__RB_SPLIT_COLHI__SHIFT 0x3 5095 #define MC_XBAR_REMOTE__WRREQ_EN_GOQ_MASK 0x1 5096 #define MC_XBAR_REMOTE__WRREQ_EN_GOQ__SHIFT 0x0 5097 #define MC_XBAR_REMOTE__RDREQ_EN_GOQ_MASK 0x2 5098 #define MC_XBAR_REMOTE__RDREQ_EN_GOQ__SHIFT 0x1 5099 #define MC_XBAR_WRREQ_CREDIT__OUT0_MASK 0xff 5100 #define MC_XBAR_WRREQ_CREDIT__OUT0__SHIFT 0x0 5101 #define MC_XBAR_WRREQ_CREDIT__OUT1_MASK 0xff00 5102 #define MC_XBAR_WRREQ_CREDIT__OUT1__SHIFT 0x8 5103 #define MC_XBAR_WRREQ_CREDIT__OUT2_MASK 0xff0000 5104 #define MC_XBAR_WRREQ_CREDIT__OUT2__SHIFT 0x10 5105 #define MC_XBAR_WRREQ_CREDIT__OUT3_MASK 0xff000000 5106 #define MC_XBAR_WRREQ_CREDIT__OUT3__SHIFT 0x18 5107 #define MC_XBAR_RDREQ_CREDIT__OUT0_MASK 0xff 5108 #define MC_XBAR_RDREQ_CREDIT__OUT0__SHIFT 0x0 5109 #define MC_XBAR_RDREQ_CREDIT__OUT1_MASK 0xff00 5110 #define MC_XBAR_RDREQ_CREDIT__OUT1__SHIFT 0x8 5111 #define MC_XBAR_RDREQ_CREDIT__OUT2_MASK 0xff0000 5112 #define MC_XBAR_RDREQ_CREDIT__OUT2__SHIFT 0x10 5113 #define MC_XBAR_RDREQ_CREDIT__OUT3_MASK 0xff000000 5114 #define MC_XBAR_RDREQ_CREDIT__OUT3__SHIFT 0x18 5115 #define MC_XBAR_RDREQ_PRI_CREDIT__OUT0_MASK 0xff 5116 #define MC_XBAR_RDREQ_PRI_CREDIT__OUT0__SHIFT 0x0 5117 #define MC_XBAR_RDREQ_PRI_CREDIT__OUT1_MASK 0xff00 5118 #define MC_XBAR_RDREQ_PRI_CREDIT__OUT1__SHIFT 0x8 5119 #define MC_XBAR_RDREQ_PRI_CREDIT__OUT2_MASK 0xff0000 5120 #define MC_XBAR_RDREQ_PRI_CREDIT__OUT2__SHIFT 0x10 5121 #define MC_XBAR_RDREQ_PRI_CREDIT__OUT3_MASK 0xff000000 5122 #define MC_XBAR_RDREQ_PRI_CREDIT__OUT3__SHIFT 0x18 5123 #define MC_XBAR_WRRET_CREDIT1__OUT0_MASK 0xff 5124 #define MC_XBAR_WRRET_CREDIT1__OUT0__SHIFT 0x0 5125 #define MC_XBAR_WRRET_CREDIT1__OUT1_MASK 0xff00 5126 #define MC_XBAR_WRRET_CREDIT1__OUT1__SHIFT 0x8 5127 #define MC_XBAR_WRRET_CREDIT1__OUT2_MASK 0xff0000 5128 #define MC_XBAR_WRRET_CREDIT1__OUT2__SHIFT 0x10 5129 #define MC_XBAR_WRRET_CREDIT1__OUT3_MASK 0xff000000 5130 #define MC_XBAR_WRRET_CREDIT1__OUT3__SHIFT 0x18 5131 #define MC_XBAR_WRRET_CREDIT2__OUT4_MASK 0xff 5132 #define MC_XBAR_WRRET_CREDIT2__OUT4__SHIFT 0x0 5133 #define MC_XBAR_WRRET_CREDIT2__OUT5_MASK 0xff00 5134 #define MC_XBAR_WRRET_CREDIT2__OUT5__SHIFT 0x8 5135 #define MC_XBAR_RDRET_CREDIT1__OUT0_MASK 0xff 5136 #define MC_XBAR_RDRET_CREDIT1__OUT0__SHIFT 0x0 5137 #define MC_XBAR_RDRET_CREDIT1__OUT1_MASK 0xff00 5138 #define MC_XBAR_RDRET_CREDIT1__OUT1__SHIFT 0x8 5139 #define MC_XBAR_RDRET_CREDIT1__OUT2_MASK 0xff0000 5140 #define MC_XBAR_RDRET_CREDIT1__OUT2__SHIFT 0x10 5141 #define MC_XBAR_RDRET_CREDIT1__OUT3_MASK 0xff000000 5142 #define MC_XBAR_RDRET_CREDIT1__OUT3__SHIFT 0x18 5143 #define MC_XBAR_RDRET_CREDIT2__OUT4_MASK 0xff 5144 #define MC_XBAR_RDRET_CREDIT2__OUT4__SHIFT 0x0 5145 #define MC_XBAR_RDRET_CREDIT2__OUT5_MASK 0xff00 5146 #define MC_XBAR_RDRET_CREDIT2__OUT5__SHIFT 0x8 5147 #define MC_XBAR_RDRET_CREDIT2__HUB_LP_RDRET_SKID_MASK 0xff0000 5148 #define MC_XBAR_RDRET_CREDIT2__HUB_LP_RDRET_SKID__SHIFT 0x10 5149 #define MC_XBAR_RDRET_PRI_CREDIT1__OUT0_MASK 0xff 5150 #define MC_XBAR_RDRET_PRI_CREDIT1__OUT0__SHIFT 0x0 5151 #define MC_XBAR_RDRET_PRI_CREDIT1__OUT1_MASK 0xff00 5152 #define MC_XBAR_RDRET_PRI_CREDIT1__OUT1__SHIFT 0x8 5153 #define MC_XBAR_RDRET_PRI_CREDIT1__OUT2_MASK 0xff0000 5154 #define MC_XBAR_RDRET_PRI_CREDIT1__OUT2__SHIFT 0x10 5155 #define MC_XBAR_RDRET_PRI_CREDIT1__OUT3_MASK 0xff000000 5156 #define MC_XBAR_RDRET_PRI_CREDIT1__OUT3__SHIFT 0x18 5157 #define MC_XBAR_RDRET_PRI_CREDIT2__OUT4_MASK 0xff 5158 #define MC_XBAR_RDRET_PRI_CREDIT2__OUT4__SHIFT 0x0 5159 #define MC_XBAR_RDRET_PRI_CREDIT2__OUT5_MASK 0xff00 5160 #define MC_XBAR_RDRET_PRI_CREDIT2__OUT5__SHIFT 0x8 5161 #define MC_XBAR_CHTRIREMAP__CH0_MASK 0x3 5162 #define MC_XBAR_CHTRIREMAP__CH0__SHIFT 0x0 5163 #define MC_XBAR_CHTRIREMAP__CH1_MASK 0xc 5164 #define MC_XBAR_CHTRIREMAP__CH1__SHIFT 0x2 5165 #define MC_XBAR_CHTRIREMAP__CH2_MASK 0x30 5166 #define MC_XBAR_CHTRIREMAP__CH2__SHIFT 0x4 5167 #define MC_XBAR_TWOCHAN__DISABLE_ONEPORT_MASK 0x1 5168 #define MC_XBAR_TWOCHAN__DISABLE_ONEPORT__SHIFT 0x0 5169 #define MC_XBAR_TWOCHAN__CH0_MASK 0x6 5170 #define MC_XBAR_TWOCHAN__CH0__SHIFT 0x1 5171 #define MC_XBAR_TWOCHAN__CH1_MASK 0x18 5172 #define MC_XBAR_TWOCHAN__CH1__SHIFT 0x3 5173 #define MC_XBAR_ARB__HUBRD_HIGHEST_MASK 0x1 5174 #define MC_XBAR_ARB__HUBRD_HIGHEST__SHIFT 0x0 5175 #define MC_XBAR_ARB__DISABLE_HUB_STALL_HIGHEST_MASK 0x2 5176 #define MC_XBAR_ARB__DISABLE_HUB_STALL_HIGHEST__SHIFT 0x1 5177 #define MC_XBAR_ARB__BREAK_BURST_CID_CHANGE_MASK 0x4 5178 #define MC_XBAR_ARB__BREAK_BURST_CID_CHANGE__SHIFT 0x2 5179 #define MC_XBAR_ARB__ACP_RDRET_URG_MASK 0x8 5180 #define MC_XBAR_ARB__ACP_RDRET_URG__SHIFT 0x3 5181 #define MC_XBAR_ARB__HDP_RDRET_URG_MASK 0x10 5182 #define MC_XBAR_ARB__HDP_RDRET_URG__SHIFT 0x4 5183 #define MC_XBAR_ARB_MAX_BURST__RD_PORT0_MASK 0xf 5184 #define MC_XBAR_ARB_MAX_BURST__RD_PORT0__SHIFT 0x0 5185 #define MC_XBAR_ARB_MAX_BURST__RD_PORT1_MASK 0xf0 5186 #define MC_XBAR_ARB_MAX_BURST__RD_PORT1__SHIFT 0x4 5187 #define MC_XBAR_ARB_MAX_BURST__RD_PORT2_MASK 0xf00 5188 #define MC_XBAR_ARB_MAX_BURST__RD_PORT2__SHIFT 0x8 5189 #define MC_XBAR_ARB_MAX_BURST__RD_PORT3_MASK 0xf000 5190 #define MC_XBAR_ARB_MAX_BURST__RD_PORT3__SHIFT 0xc 5191 #define MC_XBAR_ARB_MAX_BURST__WR_PORT0_MASK 0xf0000 5192 #define MC_XBAR_ARB_MAX_BURST__WR_PORT0__SHIFT 0x10 5193 #define MC_XBAR_ARB_MAX_BURST__WR_PORT1_MASK 0xf00000 5194 #define MC_XBAR_ARB_MAX_BURST__WR_PORT1__SHIFT 0x14 5195 #define MC_XBAR_ARB_MAX_BURST__WR_PORT2_MASK 0xf000000 5196 #define MC_XBAR_ARB_MAX_BURST__WR_PORT2__SHIFT 0x18 5197 #define MC_XBAR_ARB_MAX_BURST__WR_PORT3_MASK 0xf0000000 5198 #define MC_XBAR_ARB_MAX_BURST__WR_PORT3__SHIFT 0x1c 5199 #define MC_XBAR_FIFO_MON_CNTL0__START_THRESH_MASK 0xfff 5200 #define MC_XBAR_FIFO_MON_CNTL0__START_THRESH__SHIFT 0x0 5201 #define MC_XBAR_FIFO_MON_CNTL0__STOP_THRESH_MASK 0xfff000 5202 #define MC_XBAR_FIFO_MON_CNTL0__STOP_THRESH__SHIFT 0xc 5203 #define MC_XBAR_FIFO_MON_CNTL0__START_MODE_MASK 0x3000000 5204 #define MC_XBAR_FIFO_MON_CNTL0__START_MODE__SHIFT 0x18 5205 #define MC_XBAR_FIFO_MON_CNTL0__STOP_MODE_MASK 0xc000000 5206 #define MC_XBAR_FIFO_MON_CNTL0__STOP_MODE__SHIFT 0x1a 5207 #define MC_XBAR_FIFO_MON_CNTL0__ALLOW_WRAP_MASK 0x10000000 5208 #define MC_XBAR_FIFO_MON_CNTL0__ALLOW_WRAP__SHIFT 0x1c 5209 #define MC_XBAR_FIFO_MON_CNTL1__THRESH_CNTR_ID_MASK 0xff 5210 #define MC_XBAR_FIFO_MON_CNTL1__THRESH_CNTR_ID__SHIFT 0x0 5211 #define MC_XBAR_FIFO_MON_CNTL1__START_TRIG_ID_MASK 0xff00 5212 #define MC_XBAR_FIFO_MON_CNTL1__START_TRIG_ID__SHIFT 0x8 5213 #define MC_XBAR_FIFO_MON_CNTL1__STOP_TRIG_ID_MASK 0xff0000 5214 #define MC_XBAR_FIFO_MON_CNTL1__STOP_TRIG_ID__SHIFT 0x10 5215 #define MC_XBAR_FIFO_MON_CNTL2__MON0_ID_MASK 0xff 5216 #define MC_XBAR_FIFO_MON_CNTL2__MON0_ID__SHIFT 0x0 5217 #define MC_XBAR_FIFO_MON_CNTL2__MON1_ID_MASK 0xff00 5218 #define MC_XBAR_FIFO_MON_CNTL2__MON1_ID__SHIFT 0x8 5219 #define MC_XBAR_FIFO_MON_CNTL2__MON2_ID_MASK 0xff0000 5220 #define MC_XBAR_FIFO_MON_CNTL2__MON2_ID__SHIFT 0x10 5221 #define MC_XBAR_FIFO_MON_CNTL2__MON3_ID_MASK 0xff000000 5222 #define MC_XBAR_FIFO_MON_CNTL2__MON3_ID__SHIFT 0x18 5223 #define MC_XBAR_FIFO_MON_RSLT0__COUNT_MASK 0xffffffff 5224 #define MC_XBAR_FIFO_MON_RSLT0__COUNT__SHIFT 0x0 5225 #define MC_XBAR_FIFO_MON_RSLT1__COUNT_MASK 0xffffffff 5226 #define MC_XBAR_FIFO_MON_RSLT1__COUNT__SHIFT 0x0 5227 #define MC_XBAR_FIFO_MON_RSLT2__COUNT_MASK 0xffffffff 5228 #define MC_XBAR_FIFO_MON_RSLT2__COUNT__SHIFT 0x0 5229 #define MC_XBAR_FIFO_MON_RSLT3__COUNT_MASK 0xffffffff 5230 #define MC_XBAR_FIFO_MON_RSLT3__COUNT__SHIFT 0x0 5231 #define MC_XBAR_FIFO_MON_MAX_THSH__MON0_MASK 0xff 5232 #define MC_XBAR_FIFO_MON_MAX_THSH__MON0__SHIFT 0x0 5233 #define MC_XBAR_FIFO_MON_MAX_THSH__MON1_MASK 0xff00 5234 #define MC_XBAR_FIFO_MON_MAX_THSH__MON1__SHIFT 0x8 5235 #define MC_XBAR_FIFO_MON_MAX_THSH__MON2_MASK 0xff0000 5236 #define MC_XBAR_FIFO_MON_MAX_THSH__MON2__SHIFT 0x10 5237 #define MC_XBAR_FIFO_MON_MAX_THSH__MON3_MASK 0xff000000 5238 #define MC_XBAR_FIFO_MON_MAX_THSH__MON3__SHIFT 0x18 5239 #define MC_XBAR_SPARE0__BIT_MASK 0xffffffff 5240 #define MC_XBAR_SPARE0__BIT__SHIFT 0x0 5241 #define MC_XBAR_SPARE1__BIT_MASK 0xffffffff 5242 #define MC_XBAR_SPARE1__BIT__SHIFT 0x0 5243 #define MC_CITF_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff 5244 #define MC_CITF_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 5245 #define MC_HUB_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff 5246 #define MC_HUB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 5247 #define MC_RPB_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff 5248 #define MC_RPB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 5249 #define MC_MCBVM_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff 5250 #define MC_MCBVM_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 5251 #define MC_MCDVM_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff 5252 #define MC_MCDVM_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 5253 #define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff 5254 #define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 5255 #define MC_ARB_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff 5256 #define MC_ARB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 5257 #define ATC_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff 5258 #define ATC_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 5259 #define MC_CITF_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff 5260 #define MC_CITF_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 5261 #define MC_CITF_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000 5262 #define MC_CITF_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 5263 #define MC_HUB_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff 5264 #define MC_HUB_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 5265 #define MC_HUB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000 5266 #define MC_HUB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 5267 #define MC_MCBVM_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff 5268 #define MC_MCBVM_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 5269 #define MC_MCBVM_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000 5270 #define MC_MCBVM_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 5271 #define MC_MCDVM_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff 5272 #define MC_MCDVM_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 5273 #define MC_MCDVM_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000 5274 #define MC_MCDVM_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 5275 #define MC_RPB_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff 5276 #define MC_RPB_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 5277 #define MC_RPB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000 5278 #define MC_RPB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 5279 #define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff 5280 #define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 5281 #define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000 5282 #define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 5283 #define MC_ARB_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff 5284 #define MC_ARB_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 5285 #define MC_ARB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000 5286 #define MC_ARB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 5287 #define ATC_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff 5288 #define ATC_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 5289 #define ATC_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000 5290 #define ATC_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 5291 #define MC_CITF_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff 5292 #define MC_CITF_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 5293 #define MC_CITF_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00 5294 #define MC_CITF_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 5295 #define MC_CITF_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000 5296 #define MC_CITF_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 5297 #define MC_CITF_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000 5298 #define MC_CITF_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 5299 #define MC_CITF_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000 5300 #define MC_CITF_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 5301 #define MC_CITF_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff 5302 #define MC_CITF_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 5303 #define MC_CITF_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00 5304 #define MC_CITF_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 5305 #define MC_CITF_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000 5306 #define MC_CITF_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 5307 #define MC_CITF_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000 5308 #define MC_CITF_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 5309 #define MC_CITF_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000 5310 #define MC_CITF_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 5311 #define MC_CITF_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff 5312 #define MC_CITF_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 5313 #define MC_CITF_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00 5314 #define MC_CITF_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 5315 #define MC_CITF_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000 5316 #define MC_CITF_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 5317 #define MC_CITF_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000 5318 #define MC_CITF_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c 5319 #define MC_CITF_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000 5320 #define MC_CITF_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 5321 #define MC_CITF_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff 5322 #define MC_CITF_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 5323 #define MC_CITF_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00 5324 #define MC_CITF_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 5325 #define MC_CITF_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000 5326 #define MC_CITF_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 5327 #define MC_CITF_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000 5328 #define MC_CITF_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c 5329 #define MC_CITF_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000 5330 #define MC_CITF_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d 5331 #define MC_HUB_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff 5332 #define MC_HUB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 5333 #define MC_HUB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00 5334 #define MC_HUB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 5335 #define MC_HUB_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000 5336 #define MC_HUB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 5337 #define MC_HUB_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000 5338 #define MC_HUB_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 5339 #define MC_HUB_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000 5340 #define MC_HUB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 5341 #define MC_HUB_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff 5342 #define MC_HUB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 5343 #define MC_HUB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00 5344 #define MC_HUB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 5345 #define MC_HUB_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000 5346 #define MC_HUB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 5347 #define MC_HUB_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000 5348 #define MC_HUB_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 5349 #define MC_HUB_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000 5350 #define MC_HUB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 5351 #define MC_HUB_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff 5352 #define MC_HUB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 5353 #define MC_HUB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00 5354 #define MC_HUB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 5355 #define MC_HUB_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000 5356 #define MC_HUB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 5357 #define MC_HUB_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000 5358 #define MC_HUB_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c 5359 #define MC_HUB_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000 5360 #define MC_HUB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 5361 #define MC_HUB_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff 5362 #define MC_HUB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 5363 #define MC_HUB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00 5364 #define MC_HUB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 5365 #define MC_HUB_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000 5366 #define MC_HUB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 5367 #define MC_HUB_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000 5368 #define MC_HUB_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c 5369 #define MC_HUB_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000 5370 #define MC_HUB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d 5371 #define MC_RPB_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff 5372 #define MC_RPB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 5373 #define MC_RPB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00 5374 #define MC_RPB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 5375 #define MC_RPB_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000 5376 #define MC_RPB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 5377 #define MC_RPB_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000 5378 #define MC_RPB_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 5379 #define MC_RPB_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000 5380 #define MC_RPB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 5381 #define MC_RPB_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff 5382 #define MC_RPB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 5383 #define MC_RPB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00 5384 #define MC_RPB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 5385 #define MC_RPB_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000 5386 #define MC_RPB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 5387 #define MC_RPB_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000 5388 #define MC_RPB_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 5389 #define MC_RPB_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000 5390 #define MC_RPB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 5391 #define MC_RPB_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff 5392 #define MC_RPB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 5393 #define MC_RPB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00 5394 #define MC_RPB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 5395 #define MC_RPB_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000 5396 #define MC_RPB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 5397 #define MC_RPB_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000 5398 #define MC_RPB_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c 5399 #define MC_RPB_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000 5400 #define MC_RPB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 5401 #define MC_RPB_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff 5402 #define MC_RPB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 5403 #define MC_RPB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00 5404 #define MC_RPB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 5405 #define MC_RPB_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000 5406 #define MC_RPB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 5407 #define MC_RPB_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000 5408 #define MC_RPB_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c 5409 #define MC_RPB_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000 5410 #define MC_RPB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d 5411 #define MC_ARB_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff 5412 #define MC_ARB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 5413 #define MC_ARB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00 5414 #define MC_ARB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 5415 #define MC_ARB_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000 5416 #define MC_ARB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 5417 #define MC_ARB_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000 5418 #define MC_ARB_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 5419 #define MC_ARB_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000 5420 #define MC_ARB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 5421 #define MC_ARB_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff 5422 #define MC_ARB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 5423 #define MC_ARB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00 5424 #define MC_ARB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 5425 #define MC_ARB_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000 5426 #define MC_ARB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 5427 #define MC_ARB_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000 5428 #define MC_ARB_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 5429 #define MC_ARB_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000 5430 #define MC_ARB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 5431 #define MC_ARB_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff 5432 #define MC_ARB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 5433 #define MC_ARB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00 5434 #define MC_ARB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 5435 #define MC_ARB_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000 5436 #define MC_ARB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 5437 #define MC_ARB_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000 5438 #define MC_ARB_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c 5439 #define MC_ARB_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000 5440 #define MC_ARB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 5441 #define MC_ARB_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff 5442 #define MC_ARB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 5443 #define MC_ARB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00 5444 #define MC_ARB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 5445 #define MC_ARB_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000 5446 #define MC_ARB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 5447 #define MC_ARB_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000 5448 #define MC_ARB_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c 5449 #define MC_ARB_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000 5450 #define MC_ARB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d 5451 #define MC_MCBVM_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff 5452 #define MC_MCBVM_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 5453 #define MC_MCBVM_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00 5454 #define MC_MCBVM_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 5455 #define MC_MCBVM_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000 5456 #define MC_MCBVM_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 5457 #define MC_MCBVM_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000 5458 #define MC_MCBVM_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 5459 #define MC_MCBVM_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000 5460 #define MC_MCBVM_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 5461 #define MC_MCBVM_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff 5462 #define MC_MCBVM_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 5463 #define MC_MCBVM_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00 5464 #define MC_MCBVM_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 5465 #define MC_MCBVM_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000 5466 #define MC_MCBVM_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 5467 #define MC_MCBVM_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000 5468 #define MC_MCBVM_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 5469 #define MC_MCBVM_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000 5470 #define MC_MCBVM_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 5471 #define MC_MCBVM_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff 5472 #define MC_MCBVM_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 5473 #define MC_MCBVM_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00 5474 #define MC_MCBVM_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 5475 #define MC_MCBVM_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000 5476 #define MC_MCBVM_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 5477 #define MC_MCBVM_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000 5478 #define MC_MCBVM_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c 5479 #define MC_MCBVM_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000 5480 #define MC_MCBVM_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 5481 #define MC_MCBVM_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff 5482 #define MC_MCBVM_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 5483 #define MC_MCBVM_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00 5484 #define MC_MCBVM_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 5485 #define MC_MCBVM_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000 5486 #define MC_MCBVM_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 5487 #define MC_MCBVM_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000 5488 #define MC_MCBVM_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c 5489 #define MC_MCBVM_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000 5490 #define MC_MCBVM_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d 5491 #define MC_MCDVM_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff 5492 #define MC_MCDVM_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 5493 #define MC_MCDVM_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00 5494 #define MC_MCDVM_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 5495 #define MC_MCDVM_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000 5496 #define MC_MCDVM_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 5497 #define MC_MCDVM_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000 5498 #define MC_MCDVM_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 5499 #define MC_MCDVM_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000 5500 #define MC_MCDVM_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 5501 #define MC_MCDVM_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff 5502 #define MC_MCDVM_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 5503 #define MC_MCDVM_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00 5504 #define MC_MCDVM_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 5505 #define MC_MCDVM_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000 5506 #define MC_MCDVM_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 5507 #define MC_MCDVM_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000 5508 #define MC_MCDVM_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 5509 #define MC_MCDVM_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000 5510 #define MC_MCDVM_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 5511 #define MC_MCDVM_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff 5512 #define MC_MCDVM_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 5513 #define MC_MCDVM_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00 5514 #define MC_MCDVM_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 5515 #define MC_MCDVM_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000 5516 #define MC_MCDVM_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 5517 #define MC_MCDVM_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000 5518 #define MC_MCDVM_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c 5519 #define MC_MCDVM_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000 5520 #define MC_MCDVM_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 5521 #define MC_MCDVM_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff 5522 #define MC_MCDVM_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 5523 #define MC_MCDVM_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00 5524 #define MC_MCDVM_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 5525 #define MC_MCDVM_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000 5526 #define MC_MCDVM_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 5527 #define MC_MCDVM_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000 5528 #define MC_MCDVM_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c 5529 #define MC_MCDVM_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000 5530 #define MC_MCDVM_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d 5531 #define ATC_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff 5532 #define ATC_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 5533 #define ATC_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00 5534 #define ATC_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 5535 #define ATC_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000 5536 #define ATC_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 5537 #define ATC_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000 5538 #define ATC_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 5539 #define ATC_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000 5540 #define ATC_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 5541 #define ATC_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff 5542 #define ATC_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 5543 #define ATC_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00 5544 #define ATC_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 5545 #define ATC_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000 5546 #define ATC_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 5547 #define ATC_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000 5548 #define ATC_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 5549 #define ATC_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000 5550 #define ATC_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 5551 #define ATC_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff 5552 #define ATC_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 5553 #define ATC_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00 5554 #define ATC_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 5555 #define ATC_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000 5556 #define ATC_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 5557 #define ATC_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000 5558 #define ATC_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c 5559 #define ATC_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000 5560 #define ATC_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 5561 #define ATC_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff 5562 #define ATC_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 5563 #define ATC_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00 5564 #define ATC_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 5565 #define ATC_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000 5566 #define ATC_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 5567 #define ATC_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000 5568 #define ATC_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c 5569 #define ATC_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000 5570 #define ATC_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d 5571 #define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff 5572 #define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 5573 #define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00 5574 #define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 5575 #define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000 5576 #define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 5577 #define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000 5578 #define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 5579 #define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000 5580 #define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 5581 #define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff 5582 #define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 5583 #define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00 5584 #define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 5585 #define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000 5586 #define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 5587 #define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000 5588 #define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 5589 #define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000 5590 #define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 5591 #define MC_CITF_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf 5592 #define MC_CITF_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 5593 #define MC_CITF_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00 5594 #define MC_CITF_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 5595 #define MC_CITF_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000 5596 #define MC_CITF_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 5597 #define MC_CITF_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000 5598 #define MC_CITF_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 5599 #define MC_CITF_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000 5600 #define MC_CITF_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 5601 #define MC_CITF_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000 5602 #define MC_CITF_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 5603 #define MC_HUB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf 5604 #define MC_HUB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 5605 #define MC_HUB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00 5606 #define MC_HUB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 5607 #define MC_HUB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000 5608 #define MC_HUB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 5609 #define MC_HUB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000 5610 #define MC_HUB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 5611 #define MC_HUB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000 5612 #define MC_HUB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 5613 #define MC_HUB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000 5614 #define MC_HUB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 5615 #define MC_RPB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf 5616 #define MC_RPB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 5617 #define MC_RPB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00 5618 #define MC_RPB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 5619 #define MC_RPB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000 5620 #define MC_RPB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 5621 #define MC_RPB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000 5622 #define MC_RPB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 5623 #define MC_RPB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000 5624 #define MC_RPB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 5625 #define MC_RPB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000 5626 #define MC_RPB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 5627 #define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf 5628 #define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 5629 #define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00 5630 #define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 5631 #define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000 5632 #define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 5633 #define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000 5634 #define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 5635 #define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000 5636 #define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 5637 #define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000 5638 #define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 5639 #define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf 5640 #define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 5641 #define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00 5642 #define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 5643 #define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000 5644 #define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 5645 #define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000 5646 #define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 5647 #define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000 5648 #define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 5649 #define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000 5650 #define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 5651 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf 5652 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 5653 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00 5654 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 5655 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000 5656 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 5657 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000 5658 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 5659 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000 5660 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 5661 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000 5662 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 5663 #define MC_ARB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf 5664 #define MC_ARB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 5665 #define MC_ARB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00 5666 #define MC_ARB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 5667 #define MC_ARB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000 5668 #define MC_ARB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 5669 #define MC_ARB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000 5670 #define MC_ARB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 5671 #define MC_ARB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000 5672 #define MC_ARB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 5673 #define MC_ARB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000 5674 #define MC_ARB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 5675 #define ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf 5676 #define ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 5677 #define ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00 5678 #define ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 5679 #define ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000 5680 #define ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 5681 #define ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000 5682 #define ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 5683 #define ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000 5684 #define ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 5685 #define ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000 5686 #define ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 5687 #define CHUB_ATC_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff 5688 #define CHUB_ATC_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 5689 #define CHUB_ATC_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff 5690 #define CHUB_ATC_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 5691 #define CHUB_ATC_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000 5692 #define CHUB_ATC_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 5693 #define CHUB_ATC_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff 5694 #define CHUB_ATC_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 5695 #define CHUB_ATC_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00 5696 #define CHUB_ATC_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 5697 #define CHUB_ATC_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000 5698 #define CHUB_ATC_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 5699 #define CHUB_ATC_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000 5700 #define CHUB_ATC_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 5701 #define CHUB_ATC_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000 5702 #define CHUB_ATC_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 5703 #define CHUB_ATC_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff 5704 #define CHUB_ATC_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 5705 #define CHUB_ATC_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00 5706 #define CHUB_ATC_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 5707 #define CHUB_ATC_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000 5708 #define CHUB_ATC_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 5709 #define CHUB_ATC_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000 5710 #define CHUB_ATC_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 5711 #define CHUB_ATC_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000 5712 #define CHUB_ATC_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 5713 #define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf 5714 #define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 5715 #define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00 5716 #define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 5717 #define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000 5718 #define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 5719 #define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000 5720 #define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 5721 #define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000 5722 #define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 5723 #define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000 5724 #define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 5725 #define MC_GRUB_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff 5726 #define MC_GRUB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 5727 #define MC_GRUB_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff 5728 #define MC_GRUB_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 5729 #define MC_GRUB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000 5730 #define MC_GRUB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 5731 #define MC_GRUB_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff 5732 #define MC_GRUB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 5733 #define MC_GRUB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00 5734 #define MC_GRUB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 5735 #define MC_GRUB_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000 5736 #define MC_GRUB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 5737 #define MC_GRUB_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000 5738 #define MC_GRUB_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 5739 #define MC_GRUB_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000 5740 #define MC_GRUB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 5741 #define MC_GRUB_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff 5742 #define MC_GRUB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 5743 #define MC_GRUB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00 5744 #define MC_GRUB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 5745 #define MC_GRUB_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000 5746 #define MC_GRUB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 5747 #define MC_GRUB_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000 5748 #define MC_GRUB_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 5749 #define MC_GRUB_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000 5750 #define MC_GRUB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 5751 #define MC_GRUB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf 5752 #define MC_GRUB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 5753 #define MC_GRUB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00 5754 #define MC_GRUB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 5755 #define MC_GRUB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000 5756 #define MC_GRUB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 5757 #define MC_GRUB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000 5758 #define MC_GRUB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 5759 #define MC_GRUB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000 5760 #define MC_GRUB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 5761 #define MC_GRUB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000 5762 #define MC_GRUB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 5763 #define ATC_VM_APERTURE0_LOW_ADDR__VIRTUAL_PAGE_NUMBER_MASK 0xfffffff 5764 #define ATC_VM_APERTURE0_LOW_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT 0x0 5765 #define ATC_VM_APERTURE1_LOW_ADDR__VIRTUAL_PAGE_NUMBER_MASK 0xfffffff 5766 #define ATC_VM_APERTURE1_LOW_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT 0x0 5767 #define ATC_VM_APERTURE0_HIGH_ADDR__VIRTUAL_PAGE_NUMBER_MASK 0xfffffff 5768 #define ATC_VM_APERTURE0_HIGH_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT 0x0 5769 #define ATC_VM_APERTURE1_HIGH_ADDR__VIRTUAL_PAGE_NUMBER_MASK 0xfffffff 5770 #define ATC_VM_APERTURE1_HIGH_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT 0x0 5771 #define ATC_VM_APERTURE0_CNTL__ATS_ACCESS_MODE_MASK 0x3 5772 #define ATC_VM_APERTURE0_CNTL__ATS_ACCESS_MODE__SHIFT 0x0 5773 #define ATC_VM_APERTURE1_CNTL__ATS_ACCESS_MODE_MASK 0x3 5774 #define ATC_VM_APERTURE1_CNTL__ATS_ACCESS_MODE__SHIFT 0x0 5775 #define ATC_VM_APERTURE0_CNTL2__VMIDS_USING_RANGE_MASK 0xffff 5776 #define ATC_VM_APERTURE0_CNTL2__VMIDS_USING_RANGE__SHIFT 0x0 5777 #define ATC_VM_APERTURE1_CNTL2__VMIDS_USING_RANGE_MASK 0xffff 5778 #define ATC_VM_APERTURE1_CNTL2__VMIDS_USING_RANGE__SHIFT 0x0 5779 #define ATC_ATS_CNTL__DISABLE_ATC_MASK 0x1 5780 #define ATC_ATS_CNTL__DISABLE_ATC__SHIFT 0x0 5781 #define ATC_ATS_CNTL__DISABLE_PRI_MASK 0x2 5782 #define ATC_ATS_CNTL__DISABLE_PRI__SHIFT 0x1 5783 #define ATC_ATS_CNTL__DISABLE_PASID_MASK 0x4 5784 #define ATC_ATS_CNTL__DISABLE_PASID__SHIFT 0x2 5785 #define ATC_ATS_CNTL__CREDITS_ATS_RPB_MASK 0x3f00 5786 #define ATC_ATS_CNTL__CREDITS_ATS_RPB__SHIFT 0x8 5787 #define ATC_ATS_CNTL__DEBUG_ECO_MASK 0xf0000 5788 #define ATC_ATS_CNTL__DEBUG_ECO__SHIFT 0x10 5789 #define ATC_ATS_DEBUG__INVALIDATE_ALL_MASK 0x1 5790 #define ATC_ATS_DEBUG__INVALIDATE_ALL__SHIFT 0x0 5791 #define ATC_ATS_DEBUG__IDENT_RETURN_MASK 0x2 5792 #define ATC_ATS_DEBUG__IDENT_RETURN__SHIFT 0x1 5793 #define ATC_ATS_DEBUG__ADDRESS_TRANSLATION_REQUEST_WRITE_PERMS_MASK 0x4 5794 #define ATC_ATS_DEBUG__ADDRESS_TRANSLATION_REQUEST_WRITE_PERMS__SHIFT 0x2 5795 #define ATC_ATS_DEBUG__PAGE_REQUESTS_USE_RELAXED_ORDERING_MASK 0x20 5796 #define ATC_ATS_DEBUG__PAGE_REQUESTS_USE_RELAXED_ORDERING__SHIFT 0x5 5797 #define ATC_ATS_DEBUG__PRIV_BIT_MASK 0x40 5798 #define ATC_ATS_DEBUG__PRIV_BIT__SHIFT 0x6 5799 #define ATC_ATS_DEBUG__EXE_BIT_MASK 0x80 5800 #define ATC_ATS_DEBUG__EXE_BIT__SHIFT 0x7 5801 #define ATC_ATS_DEBUG__PAGE_REQUEST_PERMS_MASK 0x100 5802 #define ATC_ATS_DEBUG__PAGE_REQUEST_PERMS__SHIFT 0x8 5803 #define ATC_ATS_DEBUG__UNTRANSLATED_ONLY_REQUESTS_CARRY_SIZE_MASK 0x200 5804 #define ATC_ATS_DEBUG__UNTRANSLATED_ONLY_REQUESTS_CARRY_SIZE__SHIFT 0x9 5805 #define ATC_ATS_DEBUG__NUM_REQUESTS_AT_ERR_MASK 0x3c00 5806 #define ATC_ATS_DEBUG__NUM_REQUESTS_AT_ERR__SHIFT 0xa 5807 #define ATC_ATS_DEBUG__DISALLOW_ERR_TO_DONE_MASK 0x4000 5808 #define ATC_ATS_DEBUG__DISALLOW_ERR_TO_DONE__SHIFT 0xe 5809 #define ATC_ATS_DEBUG__IGNORE_FED_MASK 0x8000 5810 #define ATC_ATS_DEBUG__IGNORE_FED__SHIFT 0xf 5811 #define ATC_ATS_DEBUG__INVALIDATION_REQUESTS_DISALLOWED_WHEN_ATC_IS_DISABLED_MASK 0x10000 5812 #define ATC_ATS_DEBUG__INVALIDATION_REQUESTS_DISALLOWED_WHEN_ATC_IS_DISABLED__SHIFT 0x10 5813 #define ATC_ATS_DEBUG__DEBUG_BUS_SELECT_MASK 0x20000 5814 #define ATC_ATS_DEBUG__DEBUG_BUS_SELECT__SHIFT 0x11 5815 #define ATC_ATS_DEBUG__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x40000 5816 #define ATC_ATS_DEBUG__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x12 5817 #define ATC_ATS_DEBUG__DISABLE_VMID0_PASID_MAPPING_MASK 0x80000 5818 #define ATC_ATS_DEBUG__DISABLE_VMID0_PASID_MAPPING__SHIFT 0x13 5819 #define ATC_ATS_DEBUG__DISABLE_INVALIDATION_ON_WORLD_SWITCH_MASK 0x100000 5820 #define ATC_ATS_DEBUG__DISABLE_INVALIDATION_ON_WORLD_SWITCH__SHIFT 0x14 5821 #define ATC_ATS_DEBUG__ENABLE_INVALIDATION_ON_VIRTUALIZATION_ENTRY_AND_EXIT_MASK 0x200000 5822 #define ATC_ATS_DEBUG__ENABLE_INVALIDATION_ON_VIRTUALIZATION_ENTRY_AND_EXIT__SHIFT 0x15 5823 #define ATC_ATS_FAULT_DEBUG__CREDITS_ATS_IH_MASK 0x1f 5824 #define ATC_ATS_FAULT_DEBUG__CREDITS_ATS_IH__SHIFT 0x0 5825 #define ATC_ATS_FAULT_DEBUG__ALLOW_SUBSEQUENT_FAULT_STATUS_ADDR_UPDATES_MASK 0x100 5826 #define ATC_ATS_FAULT_DEBUG__ALLOW_SUBSEQUENT_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x8 5827 #define ATC_ATS_FAULT_DEBUG__CLEAR_FAULT_STATUS_ADDR_MASK 0x10000 5828 #define ATC_ATS_FAULT_DEBUG__CLEAR_FAULT_STATUS_ADDR__SHIFT 0x10 5829 #define ATC_ATS_STATUS__BUSY_MASK 0x1 5830 #define ATC_ATS_STATUS__BUSY__SHIFT 0x0 5831 #define ATC_ATS_STATUS__CRASHED_MASK 0x2 5832 #define ATC_ATS_STATUS__CRASHED__SHIFT 0x1 5833 #define ATC_ATS_STATUS__DEADLOCK_DETECTION_MASK 0x4 5834 #define ATC_ATS_STATUS__DEADLOCK_DETECTION__SHIFT 0x2 5835 #define ATC_ATS_FAULT_CNTL__FAULT_REGISTER_LOG_MASK 0x1ff 5836 #define ATC_ATS_FAULT_CNTL__FAULT_REGISTER_LOG__SHIFT 0x0 5837 #define ATC_ATS_FAULT_CNTL__FAULT_INTERRUPT_TABLE_MASK 0x7fc00 5838 #define ATC_ATS_FAULT_CNTL__FAULT_INTERRUPT_TABLE__SHIFT 0xa 5839 #define ATC_ATS_FAULT_CNTL__FAULT_CRASH_TABLE_MASK 0x1ff00000 5840 #define ATC_ATS_FAULT_CNTL__FAULT_CRASH_TABLE__SHIFT 0x14 5841 #define ATC_ATS_FAULT_STATUS_INFO__FAULT_TYPE_MASK 0x1ff 5842 #define ATC_ATS_FAULT_STATUS_INFO__FAULT_TYPE__SHIFT 0x0 5843 #define ATC_ATS_FAULT_STATUS_INFO__VMID_MASK 0x7c00 5844 #define ATC_ATS_FAULT_STATUS_INFO__VMID__SHIFT 0xa 5845 #define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO_MASK 0x8000 5846 #define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO__SHIFT 0xf 5847 #define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO2_MASK 0x10000 5848 #define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO2__SHIFT 0x10 5849 #define ATC_ATS_FAULT_STATUS_INFO__INVALIDATION_MASK 0x20000 5850 #define ATC_ATS_FAULT_STATUS_INFO__INVALIDATION__SHIFT 0x11 5851 #define ATC_ATS_FAULT_STATUS_INFO__PAGE_REQUEST_MASK 0x40000 5852 #define ATC_ATS_FAULT_STATUS_INFO__PAGE_REQUEST__SHIFT 0x12 5853 #define ATC_ATS_FAULT_STATUS_INFO__STATUS_MASK 0xf80000 5854 #define ATC_ATS_FAULT_STATUS_INFO__STATUS__SHIFT 0x13 5855 #define ATC_ATS_FAULT_STATUS_INFO__PAGE_ADDR_HIGH_MASK 0xf000000 5856 #define ATC_ATS_FAULT_STATUS_INFO__PAGE_ADDR_HIGH__SHIFT 0x18 5857 #define ATC_ATS_FAULT_STATUS_ADDR__PAGE_ADDR_MASK 0xffffffff 5858 #define ATC_ATS_FAULT_STATUS_ADDR__PAGE_ADDR__SHIFT 0x0 5859 #define ATC_ATS_DEFAULT_PAGE_LOW__DEFAULT_PAGE_MASK 0xfffffff 5860 #define ATC_ATS_DEFAULT_PAGE_LOW__DEFAULT_PAGE__SHIFT 0x0 5861 #define ATC_ATS_DEFAULT_PAGE_CNTL__SEND_DEFAULT_PAGE_MASK 0x1 5862 #define ATC_ATS_DEFAULT_PAGE_CNTL__SEND_DEFAULT_PAGE__SHIFT 0x0 5863 #define ATC_ATS_FAULT_STATUS_INFO2__VF_MASK 0x1 5864 #define ATC_ATS_FAULT_STATUS_INFO2__VF__SHIFT 0x0 5865 #define ATC_ATS_FAULT_STATUS_INFO2__VFID_MASK 0x3e 5866 #define ATC_ATS_FAULT_STATUS_INFO2__VFID__SHIFT 0x1 5867 #define ATC_ATS_FAULT_STATUS_INFO2__L1_ID_MASK 0x1fe00 5868 #define ATC_ATS_FAULT_STATUS_INFO2__L1_ID__SHIFT 0x9 5869 #define ATC_MISC_CG__OFFDLY_MASK 0xfc0 5870 #define ATC_MISC_CG__OFFDLY__SHIFT 0x6 5871 #define ATC_MISC_CG__ENABLE_MASK 0x40000 5872 #define ATC_MISC_CG__ENABLE__SHIFT 0x12 5873 #define ATC_MISC_CG__MEM_LS_ENABLE_MASK 0x80000 5874 #define ATC_MISC_CG__MEM_LS_ENABLE__SHIFT 0x13 5875 #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS_MASK 0x3 5876 #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS__SHIFT 0x0 5877 #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS_MASK 0x30 5878 #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS__SHIFT 0x4 5879 #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x100 5880 #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0x8 5881 #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x200 5882 #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0x9 5883 #define ATC_L2_CNTL2__BANK_SELECT_MASK 0x3f 5884 #define ATC_L2_CNTL2__BANK_SELECT__SHIFT 0x0 5885 #define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE_MASK 0xc0 5886 #define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE__SHIFT 0x6 5887 #define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x100 5888 #define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x8 5889 #define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS_MASK 0xe00 5890 #define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS__SHIFT 0x9 5891 #define ATC_L2_CNTL2__L2_CACHE_VMID_MODE_MASK 0x7000 5892 #define ATC_L2_CNTL2__L2_CACHE_VMID_MODE__SHIFT 0xc 5893 #define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x1f8000 5894 #define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0xf 5895 #define ATC_L2_DEBUG__CREDITS_L2_ATS_MASK 0x3f 5896 #define ATC_L2_DEBUG__CREDITS_L2_ATS__SHIFT 0x0 5897 #define ATC_L2_DEBUG__L2_MEM_SELECT_MASK 0x80 5898 #define ATC_L2_DEBUG__L2_MEM_SELECT__SHIFT 0x7 5899 #define ATC_L2_DEBUG__CACHE_INDEX_MASK 0xfff00 5900 #define ATC_L2_DEBUG__CACHE_INDEX__SHIFT 0x8 5901 #define ATC_L2_DEBUG__CACHE_SELECT_MASK 0x1000000 5902 #define ATC_L2_DEBUG__CACHE_SELECT__SHIFT 0x18 5903 #define ATC_L2_DEBUG__CACHE_BANK_SELECT_MASK 0x2000000 5904 #define ATC_L2_DEBUG__CACHE_BANK_SELECT__SHIFT 0x19 5905 #define ATC_L2_DEBUG__CACHE_WAY_SELECT_MASK 0x8000000 5906 #define ATC_L2_DEBUG__CACHE_WAY_SELECT__SHIFT 0x1b 5907 #define ATC_L2_DEBUG__CACHE_READ_MASK 0x20000000 5908 #define ATC_L2_DEBUG__CACHE_READ__SHIFT 0x1d 5909 #define ATC_L2_DEBUG__CACHE_INJECT_SOFT_PARITY_ERROR_MASK 0x40000000 5910 #define ATC_L2_DEBUG__CACHE_INJECT_SOFT_PARITY_ERROR__SHIFT 0x1e 5911 #define ATC_L2_DEBUG__CACHE_INJECT_HARD_PARITY_ERROR_MASK 0x80000000 5912 #define ATC_L2_DEBUG__CACHE_INJECT_HARD_PARITY_ERROR__SHIFT 0x1f 5913 #define ATC_L2_DEBUG2__EFFECTIVE_CACHE_SIZE_MASK 0x1f 5914 #define ATC_L2_DEBUG2__EFFECTIVE_CACHE_SIZE__SHIFT 0x0 5915 #define ATC_L2_DEBUG2__EFFECTIVE_WORK_QUEUE_SIZE_MASK 0xe0 5916 #define ATC_L2_DEBUG2__EFFECTIVE_WORK_QUEUE_SIZE__SHIFT 0x5 5917 #define ATC_L2_DEBUG2__FORCE_CACHE_MISS_MASK 0x100 5918 #define ATC_L2_DEBUG2__FORCE_CACHE_MISS__SHIFT 0x8 5919 #define ATC_L2_DEBUG2__INVALIDATE_ALL_MASK 0x200 5920 #define ATC_L2_DEBUG2__INVALIDATE_ALL__SHIFT 0x9 5921 #define ATC_L2_DEBUG2__DISABLE_2M_CACHE_MASK 0x400 5922 #define ATC_L2_DEBUG2__DISABLE_2M_CACHE__SHIFT 0xa 5923 #define ATC_L2_DEBUG2__DISABLE_CACHING_SPECULATIVE_RETURNS_MASK 0x800 5924 #define ATC_L2_DEBUG2__DISABLE_CACHING_SPECULATIVE_RETURNS__SHIFT 0xb 5925 #define ATC_L2_DEBUG2__DISABLE_CACHING_FAULT_RETURNS_MASK 0x4000 5926 #define ATC_L2_DEBUG2__DISABLE_CACHING_FAULT_RETURNS__SHIFT 0xe 5927 #define ATC_L2_DEBUG2__DEBUG_BUS_SELECT_MASK 0x18000 5928 #define ATC_L2_DEBUG2__DEBUG_BUS_SELECT__SHIFT 0xf 5929 #define ATC_L2_DEBUG2__DEBUG_ECO_MASK 0x60000 5930 #define ATC_L2_DEBUG2__DEBUG_ECO__SHIFT 0x11 5931 #define ATC_L2_DEBUG2__EFFECTIVE_2M_CACHE_SIZE_MASK 0x780000 5932 #define ATC_L2_DEBUG2__EFFECTIVE_2M_CACHE_SIZE__SHIFT 0x13 5933 #define ATC_L2_DEBUG2__CACHE_PARITY_ERROR_INTERRUPT_THRESHOLD_MASK 0x7f800000 5934 #define ATC_L2_DEBUG2__CACHE_PARITY_ERROR_INTERRUPT_THRESHOLD__SHIFT 0x17 5935 #define ATC_L2_DEBUG2__CLEAR_PARITY_ERROR_INFO_MASK 0x80000000 5936 #define ATC_L2_DEBUG2__CLEAR_PARITY_ERROR_INFO__SHIFT 0x1f 5937 #define ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID_MASK 0x1 5938 #define ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID__SHIFT 0x0 5939 #define ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID_MASK 0x2 5940 #define ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID__SHIFT 0x1 5941 #define ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES_MASK 0x1fffffc 5942 #define ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES__SHIFT 0x2 5943 #define ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH_MASK 0x1e000000 5944 #define ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH__SHIFT 0x19 5945 #define ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW_MASK 0xffffffff 5946 #define ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW__SHIFT 0x0 5947 #define ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS_LOW_MASK 0xfffffff 5948 #define ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS_LOW__SHIFT 0x0 5949 #define ATC_L1_CNTL__DONT_NEED_ATS_BEHAVIOR_MASK 0x3 5950 #define ATC_L1_CNTL__DONT_NEED_ATS_BEHAVIOR__SHIFT 0x0 5951 #define ATC_L1_CNTL__NEED_ATS_BEHAVIOR_MASK 0x4 5952 #define ATC_L1_CNTL__NEED_ATS_BEHAVIOR__SHIFT 0x2 5953 #define ATC_L1_CNTL__NEED_ATS_SNOOP_DEFAULT_MASK 0x10 5954 #define ATC_L1_CNTL__NEED_ATS_SNOOP_DEFAULT__SHIFT 0x4 5955 #define ATC_L1_ADDRESS_OFFSET__LOGICAL_ADDRESS_MASK 0xffffffff 5956 #define ATC_L1_ADDRESS_OFFSET__LOGICAL_ADDRESS__SHIFT 0x0 5957 #define ATC_L1RD_DEBUG_TLB__DISABLE_FRAGMENTS_MASK 0x1 5958 #define ATC_L1RD_DEBUG_TLB__DISABLE_FRAGMENTS__SHIFT 0x0 5959 #define ATC_L1RD_DEBUG_TLB__DISABLE_INVALIDATE_BY_ADDRESS_RANGE_MASK 0x2 5960 #define ATC_L1RD_DEBUG_TLB__DISABLE_INVALIDATE_BY_ADDRESS_RANGE__SHIFT 0x1 5961 #define ATC_L1RD_DEBUG_TLB__EFFECTIVE_CAM_SIZE_MASK 0xf0 5962 #define ATC_L1RD_DEBUG_TLB__EFFECTIVE_CAM_SIZE__SHIFT 0x4 5963 #define ATC_L1RD_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE_MASK 0x700 5964 #define ATC_L1RD_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE__SHIFT 0x8 5965 #define ATC_L1RD_DEBUG_TLB__CREDITS_L1_L2_MASK 0x3f000 5966 #define ATC_L1RD_DEBUG_TLB__CREDITS_L1_L2__SHIFT 0xc 5967 #define ATC_L1RD_DEBUG_TLB__CREDITS_L1_RPB_MASK 0xff00000 5968 #define ATC_L1RD_DEBUG_TLB__CREDITS_L1_RPB__SHIFT 0x14 5969 #define ATC_L1RD_DEBUG_TLB__DEBUG_ECO_MASK 0x30000000 5970 #define ATC_L1RD_DEBUG_TLB__DEBUG_ECO__SHIFT 0x1c 5971 #define ATC_L1RD_DEBUG_TLB__INVALIDATE_ALL_MASK 0x40000000 5972 #define ATC_L1RD_DEBUG_TLB__INVALIDATE_ALL__SHIFT 0x1e 5973 #define ATC_L1RD_DEBUG_TLB__DISABLE_CACHING_FAULT_RETURNS_MASK 0x80000000 5974 #define ATC_L1RD_DEBUG_TLB__DISABLE_CACHING_FAULT_RETURNS__SHIFT 0x1f 5975 #define ATC_L1WR_DEBUG_TLB__DISABLE_FRAGMENTS_MASK 0x1 5976 #define ATC_L1WR_DEBUG_TLB__DISABLE_FRAGMENTS__SHIFT 0x0 5977 #define ATC_L1WR_DEBUG_TLB__DISABLE_INVALIDATE_BY_ADDRESS_RANGE_MASK 0x2 5978 #define ATC_L1WR_DEBUG_TLB__DISABLE_INVALIDATE_BY_ADDRESS_RANGE__SHIFT 0x1 5979 #define ATC_L1WR_DEBUG_TLB__EFFECTIVE_CAM_SIZE_MASK 0xf0 5980 #define ATC_L1WR_DEBUG_TLB__EFFECTIVE_CAM_SIZE__SHIFT 0x4 5981 #define ATC_L1WR_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE_MASK 0x700 5982 #define ATC_L1WR_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE__SHIFT 0x8 5983 #define ATC_L1WR_DEBUG_TLB__CREDITS_L1_L2_MASK 0x3f000 5984 #define ATC_L1WR_DEBUG_TLB__CREDITS_L1_L2__SHIFT 0xc 5985 #define ATC_L1WR_DEBUG_TLB__CREDITS_L1_RPB_MASK 0xff00000 5986 #define ATC_L1WR_DEBUG_TLB__CREDITS_L1_RPB__SHIFT 0x14 5987 #define ATC_L1WR_DEBUG_TLB__DEBUG_ECO_MASK 0x30000000 5988 #define ATC_L1WR_DEBUG_TLB__DEBUG_ECO__SHIFT 0x1c 5989 #define ATC_L1WR_DEBUG_TLB__INVALIDATE_ALL_MASK 0x40000000 5990 #define ATC_L1WR_DEBUG_TLB__INVALIDATE_ALL__SHIFT 0x1e 5991 #define ATC_L1WR_DEBUG_TLB__DISABLE_CACHING_FAULT_RETURNS_MASK 0x80000000 5992 #define ATC_L1WR_DEBUG_TLB__DISABLE_CACHING_FAULT_RETURNS__SHIFT 0x1f 5993 #define ATC_L1RD_STATUS__BUSY_MASK 0x1 5994 #define ATC_L1RD_STATUS__BUSY__SHIFT 0x0 5995 #define ATC_L1RD_STATUS__DEADLOCK_DETECTION_MASK 0x2 5996 #define ATC_L1RD_STATUS__DEADLOCK_DETECTION__SHIFT 0x1 5997 #define ATC_L1RD_STATUS__BAD_NEED_ATS_MASK 0x100 5998 #define ATC_L1RD_STATUS__BAD_NEED_ATS__SHIFT 0x8 5999 #define ATC_L1RD_STATUS__CAM_PARITY_ERRORS_MASK 0x1f000 6000 #define ATC_L1RD_STATUS__CAM_PARITY_ERRORS__SHIFT 0xc 6001 #define ATC_L1RD_STATUS__CAM_INDEX_MASK 0x3e0000 6002 #define ATC_L1RD_STATUS__CAM_INDEX__SHIFT 0x11 6003 #define ATC_L1WR_STATUS__BUSY_MASK 0x1 6004 #define ATC_L1WR_STATUS__BUSY__SHIFT 0x0 6005 #define ATC_L1WR_STATUS__DEADLOCK_DETECTION_MASK 0x2 6006 #define ATC_L1WR_STATUS__DEADLOCK_DETECTION__SHIFT 0x1 6007 #define ATC_L1WR_STATUS__BAD_NEED_ATS_MASK 0x100 6008 #define ATC_L1WR_STATUS__BAD_NEED_ATS__SHIFT 0x8 6009 #define ATC_L1WR_STATUS__CAM_PARITY_ERRORS_MASK 0x1f000 6010 #define ATC_L1WR_STATUS__CAM_PARITY_ERRORS__SHIFT 0xc 6011 #define ATC_L1WR_STATUS__CAM_INDEX_MASK 0x3e0000 6012 #define ATC_L1WR_STATUS__CAM_INDEX__SHIFT 0x11 6013 #define ATC_L1RD_DEBUG2_TLB__XNACK_RETRY_PERIOD_MASK 0xfff 6014 #define ATC_L1RD_DEBUG2_TLB__XNACK_RETRY_PERIOD__SHIFT 0x0 6015 #define ATC_L1RD_DEBUG2_TLB__XNACK_RETRY_MODE_MASK 0xc000 6016 #define ATC_L1RD_DEBUG2_TLB__XNACK_RETRY_MODE__SHIFT 0xe 6017 #define ATC_L1RD_DEBUG2_TLB__INJECT_SOFT_PARITY_ERROR_MASK 0x10000 6018 #define ATC_L1RD_DEBUG2_TLB__INJECT_SOFT_PARITY_ERROR__SHIFT 0x10 6019 #define ATC_L1RD_DEBUG2_TLB__INJECT_HARD_PARITY_ERROR_MASK 0x20000 6020 #define ATC_L1RD_DEBUG2_TLB__INJECT_HARD_PARITY_ERROR__SHIFT 0x11 6021 #define ATC_L1RD_DEBUG2_TLB__CLEAR_CAM_PARITY_ERROR_MASK 0x40000 6022 #define ATC_L1RD_DEBUG2_TLB__CLEAR_CAM_PARITY_ERROR__SHIFT 0x12 6023 #define ATC_L1RD_DEBUG2_TLB__CAM_INDEX_MASK 0xf80000 6024 #define ATC_L1RD_DEBUG2_TLB__CAM_INDEX__SHIFT 0x13 6025 #define ATC_L1WR_DEBUG2_TLB__XNACK_RETRY_PERIOD_MASK 0xfff 6026 #define ATC_L1WR_DEBUG2_TLB__XNACK_RETRY_PERIOD__SHIFT 0x0 6027 #define ATC_L1WR_DEBUG2_TLB__XNACK_RETRY_MODE_MASK 0xc000 6028 #define ATC_L1WR_DEBUG2_TLB__XNACK_RETRY_MODE__SHIFT 0xe 6029 #define ATC_L1WR_DEBUG2_TLB__INJECT_SOFT_PARITY_ERROR_MASK 0x10000 6030 #define ATC_L1WR_DEBUG2_TLB__INJECT_SOFT_PARITY_ERROR__SHIFT 0x10 6031 #define ATC_L1WR_DEBUG2_TLB__INJECT_HARD_PARITY_ERROR_MASK 0x20000 6032 #define ATC_L1WR_DEBUG2_TLB__INJECT_HARD_PARITY_ERROR__SHIFT 0x11 6033 #define ATC_L1WR_DEBUG2_TLB__CLEAR_CAM_PARITY_ERROR_MASK 0x40000 6034 #define ATC_L1WR_DEBUG2_TLB__CLEAR_CAM_PARITY_ERROR__SHIFT 0x12 6035 #define ATC_L1WR_DEBUG2_TLB__CAM_INDEX_MASK 0xf80000 6036 #define ATC_L1WR_DEBUG2_TLB__CAM_INDEX__SHIFT 0x13 6037 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID0_REMAPPING_FINISHED_MASK 0x1 6038 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID0_REMAPPING_FINISHED__SHIFT 0x0 6039 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID1_REMAPPING_FINISHED_MASK 0x2 6040 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID1_REMAPPING_FINISHED__SHIFT 0x1 6041 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID2_REMAPPING_FINISHED_MASK 0x4 6042 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID2_REMAPPING_FINISHED__SHIFT 0x2 6043 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID3_REMAPPING_FINISHED_MASK 0x8 6044 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID3_REMAPPING_FINISHED__SHIFT 0x3 6045 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID4_REMAPPING_FINISHED_MASK 0x10 6046 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID4_REMAPPING_FINISHED__SHIFT 0x4 6047 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID5_REMAPPING_FINISHED_MASK 0x20 6048 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID5_REMAPPING_FINISHED__SHIFT 0x5 6049 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID6_REMAPPING_FINISHED_MASK 0x40 6050 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID6_REMAPPING_FINISHED__SHIFT 0x6 6051 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID7_REMAPPING_FINISHED_MASK 0x80 6052 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID7_REMAPPING_FINISHED__SHIFT 0x7 6053 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID8_REMAPPING_FINISHED_MASK 0x100 6054 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID8_REMAPPING_FINISHED__SHIFT 0x8 6055 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID9_REMAPPING_FINISHED_MASK 0x200 6056 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID9_REMAPPING_FINISHED__SHIFT 0x9 6057 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID10_REMAPPING_FINISHED_MASK 0x400 6058 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID10_REMAPPING_FINISHED__SHIFT 0xa 6059 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID11_REMAPPING_FINISHED_MASK 0x800 6060 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID11_REMAPPING_FINISHED__SHIFT 0xb 6061 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID12_REMAPPING_FINISHED_MASK 0x1000 6062 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID12_REMAPPING_FINISHED__SHIFT 0xc 6063 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID13_REMAPPING_FINISHED_MASK 0x2000 6064 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID13_REMAPPING_FINISHED__SHIFT 0xd 6065 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID14_REMAPPING_FINISHED_MASK 0x4000 6066 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID14_REMAPPING_FINISHED__SHIFT 0xe 6067 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID15_REMAPPING_FINISHED_MASK 0x8000 6068 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID15_REMAPPING_FINISHED__SHIFT 0xf 6069 #define ATC_VMID0_PASID_MAPPING__PASID_MASK 0xffff 6070 #define ATC_VMID0_PASID_MAPPING__PASID__SHIFT 0x0 6071 #define ATC_VMID0_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000 6072 #define ATC_VMID0_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 6073 #define ATC_VMID0_PASID_MAPPING__VALID_MASK 0x80000000 6074 #define ATC_VMID0_PASID_MAPPING__VALID__SHIFT 0x1f 6075 #define ATC_VMID1_PASID_MAPPING__PASID_MASK 0xffff 6076 #define ATC_VMID1_PASID_MAPPING__PASID__SHIFT 0x0 6077 #define ATC_VMID1_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000 6078 #define ATC_VMID1_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 6079 #define ATC_VMID1_PASID_MAPPING__VALID_MASK 0x80000000 6080 #define ATC_VMID1_PASID_MAPPING__VALID__SHIFT 0x1f 6081 #define ATC_VMID2_PASID_MAPPING__PASID_MASK 0xffff 6082 #define ATC_VMID2_PASID_MAPPING__PASID__SHIFT 0x0 6083 #define ATC_VMID2_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000 6084 #define ATC_VMID2_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 6085 #define ATC_VMID2_PASID_MAPPING__VALID_MASK 0x80000000 6086 #define ATC_VMID2_PASID_MAPPING__VALID__SHIFT 0x1f 6087 #define ATC_VMID3_PASID_MAPPING__PASID_MASK 0xffff 6088 #define ATC_VMID3_PASID_MAPPING__PASID__SHIFT 0x0 6089 #define ATC_VMID3_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000 6090 #define ATC_VMID3_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 6091 #define ATC_VMID3_PASID_MAPPING__VALID_MASK 0x80000000 6092 #define ATC_VMID3_PASID_MAPPING__VALID__SHIFT 0x1f 6093 #define ATC_VMID4_PASID_MAPPING__PASID_MASK 0xffff 6094 #define ATC_VMID4_PASID_MAPPING__PASID__SHIFT 0x0 6095 #define ATC_VMID4_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000 6096 #define ATC_VMID4_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 6097 #define ATC_VMID4_PASID_MAPPING__VALID_MASK 0x80000000 6098 #define ATC_VMID4_PASID_MAPPING__VALID__SHIFT 0x1f 6099 #define ATC_VMID5_PASID_MAPPING__PASID_MASK 0xffff 6100 #define ATC_VMID5_PASID_MAPPING__PASID__SHIFT 0x0 6101 #define ATC_VMID5_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000 6102 #define ATC_VMID5_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 6103 #define ATC_VMID5_PASID_MAPPING__VALID_MASK 0x80000000 6104 #define ATC_VMID5_PASID_MAPPING__VALID__SHIFT 0x1f 6105 #define ATC_VMID6_PASID_MAPPING__PASID_MASK 0xffff 6106 #define ATC_VMID6_PASID_MAPPING__PASID__SHIFT 0x0 6107 #define ATC_VMID6_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000 6108 #define ATC_VMID6_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 6109 #define ATC_VMID6_PASID_MAPPING__VALID_MASK 0x80000000 6110 #define ATC_VMID6_PASID_MAPPING__VALID__SHIFT 0x1f 6111 #define ATC_VMID7_PASID_MAPPING__PASID_MASK 0xffff 6112 #define ATC_VMID7_PASID_MAPPING__PASID__SHIFT 0x0 6113 #define ATC_VMID7_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000 6114 #define ATC_VMID7_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 6115 #define ATC_VMID7_PASID_MAPPING__VALID_MASK 0x80000000 6116 #define ATC_VMID7_PASID_MAPPING__VALID__SHIFT 0x1f 6117 #define ATC_VMID8_PASID_MAPPING__PASID_MASK 0xffff 6118 #define ATC_VMID8_PASID_MAPPING__PASID__SHIFT 0x0 6119 #define ATC_VMID8_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000 6120 #define ATC_VMID8_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 6121 #define ATC_VMID8_PASID_MAPPING__VALID_MASK 0x80000000 6122 #define ATC_VMID8_PASID_MAPPING__VALID__SHIFT 0x1f 6123 #define ATC_VMID9_PASID_MAPPING__PASID_MASK 0xffff 6124 #define ATC_VMID9_PASID_MAPPING__PASID__SHIFT 0x0 6125 #define ATC_VMID9_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000 6126 #define ATC_VMID9_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 6127 #define ATC_VMID9_PASID_MAPPING__VALID_MASK 0x80000000 6128 #define ATC_VMID9_PASID_MAPPING__VALID__SHIFT 0x1f 6129 #define ATC_VMID10_PASID_MAPPING__PASID_MASK 0xffff 6130 #define ATC_VMID10_PASID_MAPPING__PASID__SHIFT 0x0 6131 #define ATC_VMID10_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000 6132 #define ATC_VMID10_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 6133 #define ATC_VMID10_PASID_MAPPING__VALID_MASK 0x80000000 6134 #define ATC_VMID10_PASID_MAPPING__VALID__SHIFT 0x1f 6135 #define ATC_VMID11_PASID_MAPPING__PASID_MASK 0xffff 6136 #define ATC_VMID11_PASID_MAPPING__PASID__SHIFT 0x0 6137 #define ATC_VMID11_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000 6138 #define ATC_VMID11_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 6139 #define ATC_VMID11_PASID_MAPPING__VALID_MASK 0x80000000 6140 #define ATC_VMID11_PASID_MAPPING__VALID__SHIFT 0x1f 6141 #define ATC_VMID12_PASID_MAPPING__PASID_MASK 0xffff 6142 #define ATC_VMID12_PASID_MAPPING__PASID__SHIFT 0x0 6143 #define ATC_VMID12_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000 6144 #define ATC_VMID12_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 6145 #define ATC_VMID12_PASID_MAPPING__VALID_MASK 0x80000000 6146 #define ATC_VMID12_PASID_MAPPING__VALID__SHIFT 0x1f 6147 #define ATC_VMID13_PASID_MAPPING__PASID_MASK 0xffff 6148 #define ATC_VMID13_PASID_MAPPING__PASID__SHIFT 0x0 6149 #define ATC_VMID13_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000 6150 #define ATC_VMID13_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 6151 #define ATC_VMID13_PASID_MAPPING__VALID_MASK 0x80000000 6152 #define ATC_VMID13_PASID_MAPPING__VALID__SHIFT 0x1f 6153 #define ATC_VMID14_PASID_MAPPING__PASID_MASK 0xffff 6154 #define ATC_VMID14_PASID_MAPPING__PASID__SHIFT 0x0 6155 #define ATC_VMID14_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000 6156 #define ATC_VMID14_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 6157 #define ATC_VMID14_PASID_MAPPING__VALID_MASK 0x80000000 6158 #define ATC_VMID14_PASID_MAPPING__VALID__SHIFT 0x1f 6159 #define ATC_VMID15_PASID_MAPPING__PASID_MASK 0xffff 6160 #define ATC_VMID15_PASID_MAPPING__PASID__SHIFT 0x0 6161 #define ATC_VMID15_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000 6162 #define ATC_VMID15_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 6163 #define ATC_VMID15_PASID_MAPPING__VALID_MASK 0x80000000 6164 #define ATC_VMID15_PASID_MAPPING__VALID__SHIFT 0x1f 6165 #define ATC_ATS_VMID_STATUS__VMID0_OUTSTANDING_MASK 0x1 6166 #define ATC_ATS_VMID_STATUS__VMID0_OUTSTANDING__SHIFT 0x0 6167 #define ATC_ATS_VMID_STATUS__VMID1_OUTSTANDING_MASK 0x2 6168 #define ATC_ATS_VMID_STATUS__VMID1_OUTSTANDING__SHIFT 0x1 6169 #define ATC_ATS_VMID_STATUS__VMID2_OUTSTANDING_MASK 0x4 6170 #define ATC_ATS_VMID_STATUS__VMID2_OUTSTANDING__SHIFT 0x2 6171 #define ATC_ATS_VMID_STATUS__VMID3_OUTSTANDING_MASK 0x8 6172 #define ATC_ATS_VMID_STATUS__VMID3_OUTSTANDING__SHIFT 0x3 6173 #define ATC_ATS_VMID_STATUS__VMID4_OUTSTANDING_MASK 0x10 6174 #define ATC_ATS_VMID_STATUS__VMID4_OUTSTANDING__SHIFT 0x4 6175 #define ATC_ATS_VMID_STATUS__VMID5_OUTSTANDING_MASK 0x20 6176 #define ATC_ATS_VMID_STATUS__VMID5_OUTSTANDING__SHIFT 0x5 6177 #define ATC_ATS_VMID_STATUS__VMID6_OUTSTANDING_MASK 0x40 6178 #define ATC_ATS_VMID_STATUS__VMID6_OUTSTANDING__SHIFT 0x6 6179 #define ATC_ATS_VMID_STATUS__VMID7_OUTSTANDING_MASK 0x80 6180 #define ATC_ATS_VMID_STATUS__VMID7_OUTSTANDING__SHIFT 0x7 6181 #define ATC_ATS_VMID_STATUS__VMID8_OUTSTANDING_MASK 0x100 6182 #define ATC_ATS_VMID_STATUS__VMID8_OUTSTANDING__SHIFT 0x8 6183 #define ATC_ATS_VMID_STATUS__VMID9_OUTSTANDING_MASK 0x200 6184 #define ATC_ATS_VMID_STATUS__VMID9_OUTSTANDING__SHIFT 0x9 6185 #define ATC_ATS_VMID_STATUS__VMID10_OUTSTANDING_MASK 0x400 6186 #define ATC_ATS_VMID_STATUS__VMID10_OUTSTANDING__SHIFT 0xa 6187 #define ATC_ATS_VMID_STATUS__VMID11_OUTSTANDING_MASK 0x800 6188 #define ATC_ATS_VMID_STATUS__VMID11_OUTSTANDING__SHIFT 0xb 6189 #define ATC_ATS_VMID_STATUS__VMID12_OUTSTANDING_MASK 0x1000 6190 #define ATC_ATS_VMID_STATUS__VMID12_OUTSTANDING__SHIFT 0xc 6191 #define ATC_ATS_VMID_STATUS__VMID13_OUTSTANDING_MASK 0x2000 6192 #define ATC_ATS_VMID_STATUS__VMID13_OUTSTANDING__SHIFT 0xd 6193 #define ATC_ATS_VMID_STATUS__VMID14_OUTSTANDING_MASK 0x4000 6194 #define ATC_ATS_VMID_STATUS__VMID14_OUTSTANDING__SHIFT 0xe 6195 #define ATC_ATS_VMID_STATUS__VMID15_OUTSTANDING_MASK 0x8000 6196 #define ATC_ATS_VMID_STATUS__VMID15_OUTSTANDING__SHIFT 0xf 6197 #define ATC_ATS_SMU_STATUS__VDDGFX_POWERED_DOWN_MASK 0x1 6198 #define ATC_ATS_SMU_STATUS__VDDGFX_POWERED_DOWN__SHIFT 0x0 6199 #define ATC_L2_CNTL3__ENABLE_HW_L2_CACHE_ADDRESS_MODES_SWITCHING_MASK 0x7f 6200 #define ATC_L2_CNTL3__ENABLE_HW_L2_CACHE_ADDRESS_MODES_SWITCHING__SHIFT 0x0 6201 #define ATC_L2_CNTL3__ENABLE_FREE_COUNTER_MASK 0x80 6202 #define ATC_L2_CNTL3__ENABLE_FREE_COUNTER__SHIFT 0x7 6203 #define ATC_L2_CNTL3__L2_CACHE_EVICTION_THRESHOLD_MASK 0x1f00 6204 #define ATC_L2_CNTL3__L2_CACHE_EVICTION_THRESHOLD__SHIFT 0x8 6205 #define ATC_L2_CNTL3__DISABLE_CLEAR_CACHE_EVICTION_COUNTER_ON_INVALIDATION_MASK 0x2000 6206 #define ATC_L2_CNTL3__DISABLE_CLEAR_CACHE_EVICTION_COUNTER_ON_INVALIDATION__SHIFT 0xd 6207 #define ATC_L2_CNTL3__L2_DELAY_SEND_INVALIDATION_REQUEST_MASK 0x1c000 6208 #define ATC_L2_CNTL3__L2_DELAY_SEND_INVALIDATION_REQUEST__SHIFT 0xe 6209 #define ATC_L2_STATUS__BUSY_MASK 0x1 6210 #define ATC_L2_STATUS__BUSY__SHIFT 0x0 6211 #define ATC_L2_STATUS__PARITY_ERROR_INFO_MASK 0x3ffffffe 6212 #define ATC_L2_STATUS__PARITY_ERROR_INFO__SHIFT 0x1 6213 #define ATC_L2_STATUS2__CACHE_ADDRESS_MODE_MASK 0x7 6214 #define ATC_L2_STATUS2__CACHE_ADDRESS_MODE__SHIFT 0x0 6215 #define ATC_L2_STATUS2__PARITY_ERROR_INFO_MASK 0x7f8 6216 #define ATC_L2_STATUS2__PARITY_ERROR_INFO__SHIFT 0x3 6217 #define GMCON_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x3ff 6218 #define GMCON_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0 6219 #define GMCON_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xffffffff 6220 #define GMCON_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0 6221 #define GMCON_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP_MASK 0x1 6222 #define GMCON_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP__SHIFT 0x0 6223 #define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x2 6224 #define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x1 6225 #define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0xffc 6226 #define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x2 6227 #define GMCON_RENG_EXECUTE__RENG_EXECUTE_DSP_END_PTR_MASK 0x3ff000 6228 #define GMCON_RENG_EXECUTE__RENG_EXECUTE_DSP_END_PTR__SHIFT 0xc 6229 #define GMCON_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0xffc00000 6230 #define GMCON_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0x16 6231 #define GMCON_MISC__RENG_EXECUTE_NOW_MODE_MASK 0x400 6232 #define GMCON_MISC__RENG_EXECUTE_NOW_MODE__SHIFT 0xa 6233 #define GMCON_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x800 6234 #define GMCON_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0xb 6235 #define GMCON_MISC__RENG_SRBM_CREDITS_MCD_MASK 0xf000 6236 #define GMCON_MISC__RENG_SRBM_CREDITS_MCD__SHIFT 0xc 6237 #define GMCON_MISC__STCTRL_STUTTER_EN_MASK 0x10000 6238 #define GMCON_MISC__STCTRL_STUTTER_EN__SHIFT 0x10 6239 #define GMCON_MISC__STCTRL_GMC_IDLE_THRESHOLD_MASK 0x60000 6240 #define GMCON_MISC__STCTRL_GMC_IDLE_THRESHOLD__SHIFT 0x11 6241 #define GMCON_MISC__STCTRL_SRBM_IDLE_THRESHOLD_MASK 0x180000 6242 #define GMCON_MISC__STCTRL_SRBM_IDLE_THRESHOLD__SHIFT 0x13 6243 #define GMCON_MISC__STCTRL_IGNORE_PRE_SR_MASK 0x200000 6244 #define GMCON_MISC__STCTRL_IGNORE_PRE_SR__SHIFT 0x15 6245 #define GMCON_MISC__STCTRL_IGNORE_ALLOW_STOP_MASK 0x400000 6246 #define GMCON_MISC__STCTRL_IGNORE_ALLOW_STOP__SHIFT 0x16 6247 #define GMCON_MISC__STCTRL_IGNORE_SR_COMMIT_MASK 0x800000 6248 #define GMCON_MISC__STCTRL_IGNORE_SR_COMMIT__SHIFT 0x17 6249 #define GMCON_MISC__STCTRL_IGNORE_PROTECTION_FAULT_MASK 0x1000000 6250 #define GMCON_MISC__STCTRL_IGNORE_PROTECTION_FAULT__SHIFT 0x18 6251 #define GMCON_MISC__STCTRL_DISABLE_ALLOW_SR_MASK 0x2000000 6252 #define GMCON_MISC__STCTRL_DISABLE_ALLOW_SR__SHIFT 0x19 6253 #define GMCON_MISC__STCTRL_DISABLE_GMC_OFFLINE_MASK 0x4000000 6254 #define GMCON_MISC__STCTRL_DISABLE_GMC_OFFLINE__SHIFT 0x1a 6255 #define GMCON_MISC__CRITICAL_REGS_LOCK_MASK 0x8000000 6256 #define GMCON_MISC__CRITICAL_REGS_LOCK__SHIFT 0x1b 6257 #define GMCON_MISC__ALLOW_DEEP_SLEEP_MODE_MASK 0x70000000 6258 #define GMCON_MISC__ALLOW_DEEP_SLEEP_MODE__SHIFT 0x1c 6259 #define GMCON_MISC__STCTRL_FORCE_ALLOW_SR_MASK 0x80000000 6260 #define GMCON_MISC__STCTRL_FORCE_ALLOW_SR__SHIFT 0x1f 6261 #define GMCON_MISC2__GMCON_MISC2_RESERVED0_MASK 0x3f 6262 #define GMCON_MISC2__GMCON_MISC2_RESERVED0__SHIFT 0x0 6263 #define GMCON_MISC2__STCTRL_NONDISP_IDLE_THRESHOLD_MASK 0x7c0 6264 #define GMCON_MISC2__STCTRL_NONDISP_IDLE_THRESHOLD__SHIFT 0x6 6265 #define GMCON_MISC2__RENG_SR_HOLD_THRESHOLD_MASK 0x1f800 6266 #define GMCON_MISC2__RENG_SR_HOLD_THRESHOLD__SHIFT 0xb 6267 #define GMCON_MISC2__GMCON_MISC2_RESERVED1_MASK 0x1ffe0000 6268 #define GMCON_MISC2__GMCON_MISC2_RESERVED1__SHIFT 0x11 6269 #define GMCON_MISC2__STCTRL_IGNORE_ARB_BUSY_MASK 0x20000000 6270 #define GMCON_MISC2__STCTRL_IGNORE_ARB_BUSY__SHIFT 0x1d 6271 #define GMCON_MISC2__STCTRL_EXTEND_GMC_OFFLINE_MASK 0x40000000 6272 #define GMCON_MISC2__STCTRL_EXTEND_GMC_OFFLINE__SHIFT 0x1e 6273 #define GMCON_MISC2__STCTRL_TIMER_PULSE_OVERRIDE_MASK 0x80000000 6274 #define GMCON_MISC2__STCTRL_TIMER_PULSE_OVERRIDE__SHIFT 0x1f 6275 #define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE0_MASK 0xffff 6276 #define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE0__SHIFT 0x0 6277 #define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT0_MASK 0xffff0000 6278 #define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT0__SHIFT 0x10 6279 #define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE1_MASK 0xffff 6280 #define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE1__SHIFT 0x0 6281 #define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT1_MASK 0xffff0000 6282 #define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT1__SHIFT 0x10 6283 #define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE2_MASK 0xffff 6284 #define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE2__SHIFT 0x0 6285 #define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT2_MASK 0xffff0000 6286 #define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT2__SHIFT 0x10 6287 #define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK 0xffff 6288 #define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 6289 #define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xffff0000 6290 #define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 6291 #define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK 0xffff 6292 #define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT 0x0 6293 #define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK 0xffff0000 6294 #define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT 0x10 6295 #define GMCON_PERF_MON_CNTL0__START_THRESH_MASK 0xfff 6296 #define GMCON_PERF_MON_CNTL0__START_THRESH__SHIFT 0x0 6297 #define GMCON_PERF_MON_CNTL0__STOP_THRESH_MASK 0xfff000 6298 #define GMCON_PERF_MON_CNTL0__STOP_THRESH__SHIFT 0xc 6299 #define GMCON_PERF_MON_CNTL0__START_MODE_MASK 0x3000000 6300 #define GMCON_PERF_MON_CNTL0__START_MODE__SHIFT 0x18 6301 #define GMCON_PERF_MON_CNTL0__STOP_MODE_MASK 0xc000000 6302 #define GMCON_PERF_MON_CNTL0__STOP_MODE__SHIFT 0x1a 6303 #define GMCON_PERF_MON_CNTL0__ALLOW_WRAP_MASK 0x10000000 6304 #define GMCON_PERF_MON_CNTL0__ALLOW_WRAP__SHIFT 0x1c 6305 #define GMCON_PERF_MON_CNTL0__THRESH_CNTR_ID_EXT_MASK 0x20000000 6306 #define GMCON_PERF_MON_CNTL0__THRESH_CNTR_ID_EXT__SHIFT 0x1d 6307 #define GMCON_PERF_MON_CNTL0__START_TRIG_ID_EXT_MASK 0x40000000 6308 #define GMCON_PERF_MON_CNTL0__START_TRIG_ID_EXT__SHIFT 0x1e 6309 #define GMCON_PERF_MON_CNTL0__STOP_TRIG_ID_EXT_MASK 0x80000000 6310 #define GMCON_PERF_MON_CNTL0__STOP_TRIG_ID_EXT__SHIFT 0x1f 6311 #define GMCON_PERF_MON_CNTL1__THRESH_CNTR_ID_MASK 0x3f 6312 #define GMCON_PERF_MON_CNTL1__THRESH_CNTR_ID__SHIFT 0x0 6313 #define GMCON_PERF_MON_CNTL1__START_TRIG_ID_MASK 0xfc0 6314 #define GMCON_PERF_MON_CNTL1__START_TRIG_ID__SHIFT 0x6 6315 #define GMCON_PERF_MON_CNTL1__STOP_TRIG_ID_MASK 0x3f000 6316 #define GMCON_PERF_MON_CNTL1__STOP_TRIG_ID__SHIFT 0xc 6317 #define GMCON_PERF_MON_CNTL1__MON0_ID_MASK 0x1fc0000 6318 #define GMCON_PERF_MON_CNTL1__MON0_ID__SHIFT 0x12 6319 #define GMCON_PERF_MON_CNTL1__MON1_ID_MASK 0xfe000000 6320 #define GMCON_PERF_MON_CNTL1__MON1_ID__SHIFT 0x19 6321 #define GMCON_PERF_MON_RSLT0__COUNT_MASK 0xffffffff 6322 #define GMCON_PERF_MON_RSLT0__COUNT__SHIFT 0x0 6323 #define GMCON_PERF_MON_RSLT1__COUNT_MASK 0xffffffff 6324 #define GMCON_PERF_MON_RSLT1__COUNT__SHIFT 0x0 6325 #define GMCON_PGFSM_CONFIG__FSM_ADDR_MASK 0xff 6326 #define GMCON_PGFSM_CONFIG__FSM_ADDR__SHIFT 0x0 6327 #define GMCON_PGFSM_CONFIG__POWER_DOWN_MASK 0x100 6328 #define GMCON_PGFSM_CONFIG__POWER_DOWN__SHIFT 0x8 6329 #define GMCON_PGFSM_CONFIG__POWER_UP_MASK 0x200 6330 #define GMCON_PGFSM_CONFIG__POWER_UP__SHIFT 0x9 6331 #define GMCON_PGFSM_CONFIG__P1_SELECT_MASK 0x400 6332 #define GMCON_PGFSM_CONFIG__P1_SELECT__SHIFT 0xa 6333 #define GMCON_PGFSM_CONFIG__P2_SELECT_MASK 0x800 6334 #define GMCON_PGFSM_CONFIG__P2_SELECT__SHIFT 0xb 6335 #define GMCON_PGFSM_CONFIG__WRITE_MASK 0x1000 6336 #define GMCON_PGFSM_CONFIG__WRITE__SHIFT 0xc 6337 #define GMCON_PGFSM_CONFIG__READ_MASK 0x2000 6338 #define GMCON_PGFSM_CONFIG__READ__SHIFT 0xd 6339 #define GMCON_PGFSM_CONFIG__RSRVD_MASK 0x7ffc000 6340 #define GMCON_PGFSM_CONFIG__RSRVD__SHIFT 0xe 6341 #define GMCON_PGFSM_CONFIG__SRBM_OVERRIDE_MASK 0x8000000 6342 #define GMCON_PGFSM_CONFIG__SRBM_OVERRIDE__SHIFT 0x1b 6343 #define GMCON_PGFSM_CONFIG__REG_ADDR_MASK 0xf0000000 6344 #define GMCON_PGFSM_CONFIG__REG_ADDR__SHIFT 0x1c 6345 #define GMCON_PGFSM_WRITE__WRITE_VALUE_MASK 0xffffffff 6346 #define GMCON_PGFSM_WRITE__WRITE_VALUE__SHIFT 0x0 6347 #define GMCON_PGFSM_READ__READ_VALUE_MASK 0xffffff 6348 #define GMCON_PGFSM_READ__READ_VALUE__SHIFT 0x0 6349 #define GMCON_PGFSM_READ__PGFSM_SELECT_MASK 0xf000000 6350 #define GMCON_PGFSM_READ__PGFSM_SELECT__SHIFT 0x18 6351 #define GMCON_PGFSM_READ__SERDES_MASTER_BUSY_MASK 0x10000000 6352 #define GMCON_PGFSM_READ__SERDES_MASTER_BUSY__SHIFT 0x1c 6353 #define GMCON_MISC3__RENG_DISABLE_MCC_MASK 0xff 6354 #define GMCON_MISC3__RENG_DISABLE_MCC__SHIFT 0x0 6355 #define GMCON_MISC3__RENG_DISABLE_MCD_MASK 0xff00 6356 #define GMCON_MISC3__RENG_DISABLE_MCD__SHIFT 0x8 6357 #define GMCON_MISC3__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0xfff0000 6358 #define GMCON_MISC3__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0x10 6359 #define GMCON_MISC3__STCTRL_IGNORE_ALLOW_STUTTER_MASK 0x10000000 6360 #define GMCON_MISC3__STCTRL_IGNORE_ALLOW_STUTTER__SHIFT 0x1c 6361 #define GMCON_MISC3__RENG_MEM_LS_ENABLE_MASK 0x20000000 6362 #define GMCON_MISC3__RENG_MEM_LS_ENABLE__SHIFT 0x1d 6363 #define GMCON_MISC3__STCTRL_EXCLUDE_NONMEM_CLIENTS_MASK 0x40000000 6364 #define GMCON_MISC3__STCTRL_EXCLUDE_NONMEM_CLIENTS__SHIFT 0x1e 6365 #define GMCON_MASK__STCTRL_BUSY_MASK_ACP_RD_MASK 0x1 6366 #define GMCON_MASK__STCTRL_BUSY_MASK_ACP_RD__SHIFT 0x0 6367 #define GMCON_MASK__STCTRL_BUSY_MASK_ACP_WR_MASK 0x2 6368 #define GMCON_MASK__STCTRL_BUSY_MASK_ACP_WR__SHIFT 0x1 6369 #define GMCON_MASK__STCTRL_BUSY_MASK_VCE_RD_MASK 0x4 6370 #define GMCON_MASK__STCTRL_BUSY_MASK_VCE_RD__SHIFT 0x2 6371 #define GMCON_MASK__STCTRL_BUSY_MASK_VCE_WR_MASK 0x8 6372 #define GMCON_MASK__STCTRL_BUSY_MASK_VCE_WR__SHIFT 0x3 6373 #define GMCON_MASK__STCTRL_SR_HANDSHAKE_MASK_MASK 0xff0 6374 #define GMCON_MASK__STCTRL_SR_HANDSHAKE_MASK__SHIFT 0x4 6375 #define GMCON_LPT_TARGET__STCTRL_LPT_TARGET_MASK 0xffffffff 6376 #define GMCON_LPT_TARGET__STCTRL_LPT_TARGET__SHIFT 0x0 6377 #define GMCON_DEBUG__GFX_STALL_MASK 0x1 6378 #define GMCON_DEBUG__GFX_STALL__SHIFT 0x0 6379 #define GMCON_DEBUG__GFX_CLEAR_MASK 0x2 6380 #define GMCON_DEBUG__GFX_CLEAR__SHIFT 0x1 6381 #define GMCON_DEBUG__GMCON_DEBUG_RESERVED0_MASK 0x4 6382 #define GMCON_DEBUG__GMCON_DEBUG_RESERVED0__SHIFT 0x2 6383 #define GMCON_DEBUG__SR_COMMIT_STATE_MASK 0x8 6384 #define GMCON_DEBUG__SR_COMMIT_STATE__SHIFT 0x3 6385 #define GMCON_DEBUG__STCTRL_ST_MASK 0xf0 6386 #define GMCON_DEBUG__STCTRL_ST__SHIFT 0x4 6387 #define GMCON_DEBUG__MISC_FLAGS_MASK 0xffffff00 6388 #define GMCON_DEBUG__MISC_FLAGS__SHIFT 0x8 6389 #define VM_L2_CNTL__ENABLE_L2_CACHE_MASK 0x1 6390 #define VM_L2_CNTL__ENABLE_L2_CACHE__SHIFT 0x0 6391 #define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK 0x2 6392 #define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT 0x1 6393 #define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK 0xc 6394 #define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT 0x2 6395 #define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK 0x30 6396 #define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT 0x4 6397 #define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK 0x100 6398 #define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT 0x8 6399 #define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x200 6400 #define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x9 6401 #define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x400 6402 #define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xa 6403 #define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x800 6404 #define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb 6405 #define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK 0x7000 6406 #define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT 0xc 6407 #define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x38000 6408 #define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0xf 6409 #define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK 0x40000 6410 #define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT 0x12 6411 #define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK 0x180000 6412 #define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT 0x13 6413 #define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK 0x3e00000 6414 #define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT 0x15 6415 #define VM_L2_CNTL__L2_CACHE_4K_SWAP_TAG_INDEX_LSBS_MASK 0xc000000 6416 #define VM_L2_CNTL__L2_CACHE_4K_SWAP_TAG_INDEX_LSBS__SHIFT 0x1a 6417 #define VM_L2_CNTL__L2_CACHE_BIGK_SWAP_TAG_INDEX_LSBS_MASK 0x70000000 6418 #define VM_L2_CNTL__L2_CACHE_BIGK_SWAP_TAG_INDEX_LSBS__SHIFT 0x1c 6419 #define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK 0x1 6420 #define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT 0x0 6421 #define VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK 0x2 6422 #define VM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT 0x1 6423 #define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x200000 6424 #define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x15 6425 #define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK 0x400000 6426 #define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT 0x16 6427 #define VM_L2_CNTL2__L2_CACHE_BIGK_VMID_MODE_MASK 0x3800000 6428 #define VM_L2_CNTL2__L2_CACHE_BIGK_VMID_MODE__SHIFT 0x17 6429 #define VM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK 0xc000000 6430 #define VM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT 0x1a 6431 #define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK 0x70000000 6432 #define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT 0x1c 6433 #define VM_L2_CNTL3__BANK_SELECT_MASK 0x3f 6434 #define VM_L2_CNTL3__BANK_SELECT__SHIFT 0x0 6435 #define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK 0xc0 6436 #define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT 0x6 6437 #define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x1f00 6438 #define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x8 6439 #define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0xf8000 6440 #define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0xf 6441 #define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK 0x100000 6442 #define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT 0x14 6443 #define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 0xe00000 6444 #define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 0x15 6445 #define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 0xf000000 6446 #define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT 0x18 6447 #define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK 0x10000000 6448 #define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT 0x1c 6449 #define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK 0x20000000 6450 #define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT 0x1d 6451 #define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK 0x40000000 6452 #define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT 0x1e 6453 #define VM_L2_STATUS__L2_BUSY_MASK 0x1 6454 #define VM_L2_STATUS__L2_BUSY__SHIFT 0x0 6455 #define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK 0x1fffe 6456 #define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT 0x1 6457 #define VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK 0x1 6458 #define VM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT 0x0 6459 #define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x6 6460 #define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 6461 #define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x8 6462 #define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x3 6463 #define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x10 6464 #define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4 6465 #define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x40 6466 #define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x6 6467 #define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x80 6468 #define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7 6469 #define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x200 6470 #define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 6471 #define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x400 6472 #define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 6473 #define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x800 6474 #define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0xb 6475 #define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x1000 6476 #define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc 6477 #define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x2000 6478 #define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd 6479 #define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x4000 6480 #define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0xe 6481 #define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x8000 6482 #define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 6483 #define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x10000 6484 #define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 6485 #define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x20000 6486 #define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x11 6487 #define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x40000 6488 #define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 6489 #define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x80000 6490 #define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 6491 #define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x100000 6492 #define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x14 6493 #define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x200000 6494 #define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 6495 #define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x400000 6496 #define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 6497 #define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x800000 6498 #define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x17 6499 #define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0xf000000 6500 #define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x18 6501 #define VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK 0x1 6502 #define VM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT 0x0 6503 #define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK 0x6 6504 #define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 6505 #define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x8 6506 #define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x3 6507 #define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x10 6508 #define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4 6509 #define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x40 6510 #define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x6 6511 #define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x80 6512 #define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7 6513 #define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x200 6514 #define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 6515 #define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x400 6516 #define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 6517 #define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x800 6518 #define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0xb 6519 #define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x1000 6520 #define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc 6521 #define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x2000 6522 #define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd 6523 #define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x4000 6524 #define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0xe 6525 #define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x8000 6526 #define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 6527 #define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x10000 6528 #define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 6529 #define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x20000 6530 #define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x11 6531 #define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x40000 6532 #define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 6533 #define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x80000 6534 #define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 6535 #define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x100000 6536 #define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x14 6537 #define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x200000 6538 #define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 6539 #define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x400000 6540 #define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 6541 #define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x800000 6542 #define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x17 6543 #define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0xf000000 6544 #define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x18 6545 #define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK 0x1 6546 #define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT 0x0 6547 #define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK 0x2 6548 #define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT 0x1 6549 #define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MASK_MASK 0xc 6550 #define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MASK__SHIFT 0x2 6551 #define VM_DUMMY_PAGE_FAULT_ADDR__DUMMY_PAGE_ADDR_MASK 0xfffffff 6552 #define VM_DUMMY_PAGE_FAULT_ADDR__DUMMY_PAGE_ADDR__SHIFT 0x0 6553 #define VM_CONTEXT0_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x1 6554 #define VM_CONTEXT0_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0 6555 #define VM_CONTEXT0_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT_MASK 0x2 6556 #define VM_CONTEXT0_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT__SHIFT 0x1 6557 #define VM_CONTEXT0_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT_MASK 0x4 6558 #define VM_CONTEXT0_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT__SHIFT 0x2 6559 #define VM_CONTEXT0_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x8 6560 #define VM_CONTEXT0_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x3 6561 #define VM_CONTEXT0_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE_MASK 0x10 6562 #define VM_CONTEXT0_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE__SHIFT 0x4 6563 #define VM_CONTEXT1_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x1 6564 #define VM_CONTEXT1_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0 6565 #define VM_CONTEXT1_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT_MASK 0x2 6566 #define VM_CONTEXT1_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT__SHIFT 0x1 6567 #define VM_CONTEXT1_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT_MASK 0x4 6568 #define VM_CONTEXT1_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT__SHIFT 0x2 6569 #define VM_CONTEXT1_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x8 6570 #define VM_CONTEXT1_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x3 6571 #define VM_CONTEXT1_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE_MASK 0x10 6572 #define VM_CONTEXT1_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE__SHIFT 0x4 6573 #define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff 6574 #define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 6575 #define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff 6576 #define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 6577 #define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff 6578 #define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 6579 #define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff 6580 #define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 6581 #define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff 6582 #define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 6583 #define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff 6584 #define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 6585 #define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff 6586 #define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 6587 #define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff 6588 #define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 6589 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_0_MASK 0x1 6590 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_0__SHIFT 0x0 6591 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_1_MASK 0x2 6592 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_1__SHIFT 0x1 6593 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_2_MASK 0x4 6594 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_2__SHIFT 0x2 6595 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_3_MASK 0x8 6596 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_3__SHIFT 0x3 6597 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_4_MASK 0x10 6598 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_4__SHIFT 0x4 6599 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_5_MASK 0x20 6600 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_5__SHIFT 0x5 6601 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_6_MASK 0x40 6602 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_6__SHIFT 0x6 6603 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_7_MASK 0x80 6604 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_7__SHIFT 0x7 6605 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_8_MASK 0x100 6606 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_8__SHIFT 0x8 6607 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_9_MASK 0x200 6608 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_9__SHIFT 0x9 6609 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_10_MASK 0x400 6610 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_10__SHIFT 0xa 6611 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_11_MASK 0x800 6612 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_11__SHIFT 0xb 6613 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_12_MASK 0x1000 6614 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_12__SHIFT 0xc 6615 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_13_MASK 0x2000 6616 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_13__SHIFT 0xd 6617 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_14_MASK 0x4000 6618 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_14__SHIFT 0xe 6619 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_15_MASK 0x8000 6620 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_15__SHIFT 0xf 6621 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_0_MASK 0x1 6622 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_0__SHIFT 0x0 6623 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_1_MASK 0x2 6624 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_1__SHIFT 0x1 6625 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_2_MASK 0x4 6626 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_2__SHIFT 0x2 6627 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_3_MASK 0x8 6628 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_3__SHIFT 0x3 6629 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_4_MASK 0x10 6630 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_4__SHIFT 0x4 6631 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_5_MASK 0x20 6632 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_5__SHIFT 0x5 6633 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_6_MASK 0x40 6634 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_6__SHIFT 0x6 6635 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_7_MASK 0x80 6636 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_7__SHIFT 0x7 6637 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_8_MASK 0x100 6638 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_8__SHIFT 0x8 6639 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_9_MASK 0x200 6640 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_9__SHIFT 0x9 6641 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_10_MASK 0x400 6642 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_10__SHIFT 0xa 6643 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_11_MASK 0x800 6644 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_11__SHIFT 0xb 6645 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_12_MASK 0x1000 6646 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_12__SHIFT 0xc 6647 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_13_MASK 0x2000 6648 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_13__SHIFT 0xd 6649 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_14_MASK 0x4000 6650 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_14__SHIFT 0xe 6651 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_15_MASK 0x8000 6652 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_15__SHIFT 0xf 6653 #define VM_PRT_APERTURE0_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff 6654 #define VM_PRT_APERTURE0_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0 6655 #define VM_PRT_APERTURE1_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff 6656 #define VM_PRT_APERTURE1_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0 6657 #define VM_PRT_APERTURE2_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff 6658 #define VM_PRT_APERTURE2_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0 6659 #define VM_PRT_APERTURE3_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff 6660 #define VM_PRT_APERTURE3_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0 6661 #define VM_PRT_APERTURE0_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff 6662 #define VM_PRT_APERTURE0_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0 6663 #define VM_PRT_APERTURE1_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff 6664 #define VM_PRT_APERTURE1_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0 6665 #define VM_PRT_APERTURE2_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff 6666 #define VM_PRT_APERTURE2_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0 6667 #define VM_PRT_APERTURE3_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff 6668 #define VM_PRT_APERTURE3_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0 6669 #define VM_PRT_CNTL__CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS_MASK 0x1 6670 #define VM_PRT_CNTL__CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS__SHIFT 0x0 6671 #define VM_PRT_CNTL__TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS_MASK 0x2 6672 #define VM_PRT_CNTL__TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS__SHIFT 0x1 6673 #define VM_PRT_CNTL__L2_CACHE_STORE_INVALID_ENTRIES_MASK 0x4 6674 #define VM_PRT_CNTL__L2_CACHE_STORE_INVALID_ENTRIES__SHIFT 0x2 6675 #define VM_PRT_CNTL__L1_TLB_STORE_INVALID_ENTRIES_MASK 0x8 6676 #define VM_PRT_CNTL__L1_TLB_STORE_INVALID_ENTRIES__SHIFT 0x3 6677 #define VM_PRT_CNTL__CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS_MASK 0x10 6678 #define VM_PRT_CNTL__CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS__SHIFT 0x4 6679 #define VM_PRT_CNTL__TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS_MASK 0x20 6680 #define VM_PRT_CNTL__TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS__SHIFT 0x5 6681 #define VM_PRT_CNTL__MASK_PDE0_FAULT_MASK 0x40 6682 #define VM_PRT_CNTL__MASK_PDE0_FAULT__SHIFT 0x6 6683 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK 0x1 6684 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT 0x0 6685 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK 0x2 6686 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT 0x1 6687 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK 0x4 6688 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT 0x2 6689 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK 0x8 6690 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT 0x3 6691 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK 0x10 6692 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT 0x4 6693 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK 0x20 6694 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT 0x5 6695 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK 0x40 6696 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT 0x6 6697 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK 0x80 6698 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT 0x7 6699 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK 0x100 6700 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT 0x8 6701 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK 0x200 6702 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT 0x9 6703 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK 0x400 6704 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT 0xa 6705 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK 0x800 6706 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT 0xb 6707 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK 0x1000 6708 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT 0xc 6709 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK 0x2000 6710 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT 0xd 6711 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK 0x4000 6712 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT 0xe 6713 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK 0x8000 6714 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT 0xf 6715 #define VM_CONTEXT0_PROTECTION_FAULT_STATUS__PROTECTIONS_MASK 0xff 6716 #define VM_CONTEXT0_PROTECTION_FAULT_STATUS__PROTECTIONS__SHIFT 0x0 6717 #define VM_CONTEXT0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID_MASK 0x1ff000 6718 #define VM_CONTEXT0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID__SHIFT 0xc 6719 #define VM_CONTEXT0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW_MASK 0x1000000 6720 #define VM_CONTEXT0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW__SHIFT 0x18 6721 #define VM_CONTEXT0_PROTECTION_FAULT_STATUS__VMID_MASK 0x1e000000 6722 #define VM_CONTEXT0_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x19 6723 #define VM_CONTEXT0_PROTECTION_FAULT_STATUS__ATOMIC_MASK 0x20000000 6724 #define VM_CONTEXT0_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT 0x1d 6725 #define VM_CONTEXT1_PROTECTION_FAULT_STATUS__PROTECTIONS_MASK 0xff 6726 #define VM_CONTEXT1_PROTECTION_FAULT_STATUS__PROTECTIONS__SHIFT 0x0 6727 #define VM_CONTEXT1_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID_MASK 0x1ff000 6728 #define VM_CONTEXT1_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID__SHIFT 0xc 6729 #define VM_CONTEXT1_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW_MASK 0x1000000 6730 #define VM_CONTEXT1_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW__SHIFT 0x18 6731 #define VM_CONTEXT1_PROTECTION_FAULT_STATUS__VMID_MASK 0x1e000000 6732 #define VM_CONTEXT1_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x19 6733 #define VM_CONTEXT1_PROTECTION_FAULT_STATUS__ATOMIC_MASK 0x20000000 6734 #define VM_CONTEXT1_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT 0x1d 6735 #define VM_CONTEXT0_PROTECTION_FAULT_MCCLIENT__NAME_MASK 0xffffffff 6736 #define VM_CONTEXT0_PROTECTION_FAULT_MCCLIENT__NAME__SHIFT 0x0 6737 #define VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT__NAME_MASK 0xffffffff 6738 #define VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT__NAME__SHIFT 0x0 6739 #define VM_CONTEXT0_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR_MASK 0xfffffff 6740 #define VM_CONTEXT0_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR__SHIFT 0x0 6741 #define VM_CONTEXT1_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR_MASK 0xfffffff 6742 #define VM_CONTEXT1_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR__SHIFT 0x0 6743 #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR__PHYSICAL_PAGE_ADDR_MASK 0xfffffff 6744 #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR__PHYSICAL_PAGE_ADDR__SHIFT 0x0 6745 #define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR__PHYSICAL_PAGE_ADDR_MASK 0xfffffff 6746 #define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR__PHYSICAL_PAGE_ADDR__SHIFT 0x0 6747 #define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_MASK 0x1ff 6748 #define VM_FAULT_CLIENT_ID__MEMORY_CLIENT__SHIFT 0x0 6749 #define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_MASK_MASK 0x3fe00 6750 #define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_MASK__SHIFT 0x9 6751 #define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_ID_MSB_MASK 0x40000 6752 #define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_ID_MSB__SHIFT 0x12 6753 #define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_ID_MASK_MSB_MASK 0x80000 6754 #define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_ID_MASK_MSB__SHIFT 0x13 6755 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff 6756 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 6757 #define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff 6758 #define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 6759 #define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff 6760 #define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 6761 #define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff 6762 #define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 6763 #define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff 6764 #define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 6765 #define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff 6766 #define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 6767 #define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff 6768 #define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 6769 #define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff 6770 #define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 6771 #define VM_CONTEXT0_PAGE_TABLE_START_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff 6772 #define VM_CONTEXT0_PAGE_TABLE_START_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0 6773 #define VM_CONTEXT1_PAGE_TABLE_START_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff 6774 #define VM_CONTEXT1_PAGE_TABLE_START_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0 6775 #define VM_CONTEXT0_PAGE_TABLE_END_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff 6776 #define VM_CONTEXT0_PAGE_TABLE_END_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0 6777 #define VM_CONTEXT1_PAGE_TABLE_END_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff 6778 #define VM_CONTEXT1_PAGE_TABLE_END_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0 6779 #define VM_DEBUG__FLAGS_MASK 0xffffffff 6780 #define VM_DEBUG__FLAGS__SHIFT 0x0 6781 #define VM_L2_CG__OFFDLY_MASK 0xfc0 6782 #define VM_L2_CG__OFFDLY__SHIFT 0x6 6783 #define VM_L2_CG__ENABLE_MASK 0x40000 6784 #define VM_L2_CG__ENABLE__SHIFT 0x12 6785 #define VM_L2_CG__MEM_LS_ENABLE_MASK 0x80000 6786 #define VM_L2_CG__MEM_LS_ENABLE__SHIFT 0x13 6787 #define VM_L2_CG__OVERRIDE_MASK 0x100000 6788 #define VM_L2_CG__OVERRIDE__SHIFT 0x14 6789 #define VM_L2_BANK_SELECT_MASKA__BANK_SELECT_MASK_MASK 0xfffffff 6790 #define VM_L2_BANK_SELECT_MASKA__BANK_SELECT_MASK__SHIFT 0x0 6791 #define VM_L2_BANK_SELECT_MASKB__BANK_SELECT_MASK_MASK 0x7f 6792 #define VM_L2_BANK_SELECT_MASKB__BANK_SELECT_MASK__SHIFT 0x0 6793 #define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff 6794 #define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0 6795 #define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff 6796 #define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0 6797 #define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET__PHYSICAL_PAGE_OFFSET_MASK 0xfffffff 6798 #define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET__PHYSICAL_PAGE_OFFSET__SHIFT 0x0 6799 #define VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK 0x3f 6800 #define VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT 0x0 6801 #define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL_MASK 0x40 6802 #define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL__SHIFT 0x6 6803 #define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED_MASK 0x80 6804 #define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED__SHIFT 0x7 6805 #define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP_MASK 0x100 6806 #define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP__SHIFT 0x8 6807 #define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL_MASK 0x200 6808 #define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL__SHIFT 0x9 6809 #define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED_MASK 0x400 6810 #define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED__SHIFT 0xa 6811 #define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP_MASK 0x800 6812 #define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP__SHIFT 0xb 6813 #define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL_MASK 0x1000 6814 #define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL__SHIFT 0xc 6815 #define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED_MASK 0x2000 6816 #define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED__SHIFT 0xd 6817 #define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP_MASK 0x4000 6818 #define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP__SHIFT 0xe 6819 #define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL_MASK 0x8000 6820 #define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL__SHIFT 0xf 6821 #define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED_MASK 0x10000 6822 #define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED__SHIFT 0x10 6823 #define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP_MASK 0x20000 6824 #define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP__SHIFT 0x11 6825 #define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID_MASK 0x1ff 6826 #define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID__SHIFT 0x0 6827 #define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID_MASK 0x7fc00 6828 #define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa 6829 #define VM_L2_BANK_SELECT_RESERVED_CID__ENABLE_MASK 0x100000 6830 #define VM_L2_BANK_SELECT_RESERVED_CID__ENABLE__SHIFT 0x14 6831 #define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x1000000 6832 #define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18 6833 #define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x2000000 6834 #define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19 6835 #define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE_MASK 0xffff 6836 #define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE__SHIFT 0x0 6837 #define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET_MASK 0xffff0000 6838 #define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET__SHIFT 0x10 6839 #define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE_MASK 0xffff 6840 #define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE__SHIFT 0x0 6841 #define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET_MASK 0xffff0000 6842 #define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET__SHIFT 0x10 6843 #define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE_MASK 0xffff 6844 #define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE__SHIFT 0x0 6845 #define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET_MASK 0xffff0000 6846 #define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET__SHIFT 0x10 6847 #define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE_MASK 0xffff 6848 #define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE__SHIFT 0x0 6849 #define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET_MASK 0xffff0000 6850 #define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET__SHIFT 0x10 6851 #define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE_MASK 0xffff 6852 #define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE__SHIFT 0x0 6853 #define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET_MASK 0xffff0000 6854 #define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET__SHIFT 0x10 6855 #define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE_MASK 0xffff 6856 #define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE__SHIFT 0x0 6857 #define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET_MASK 0xffff0000 6858 #define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET__SHIFT 0x10 6859 #define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE_MASK 0xffff 6860 #define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE__SHIFT 0x0 6861 #define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET_MASK 0xffff0000 6862 #define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET__SHIFT 0x10 6863 #define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE_MASK 0xffff 6864 #define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE__SHIFT 0x0 6865 #define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET_MASK 0xffff0000 6866 #define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET__SHIFT 0x10 6867 #define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE_MASK 0xffff 6868 #define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE__SHIFT 0x0 6869 #define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET_MASK 0xffff0000 6870 #define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET__SHIFT 0x10 6871 #define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE_MASK 0xffff 6872 #define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE__SHIFT 0x0 6873 #define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET_MASK 0xffff0000 6874 #define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET__SHIFT 0x10 6875 #define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE_MASK 0xffff 6876 #define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE__SHIFT 0x0 6877 #define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET_MASK 0xffff0000 6878 #define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET__SHIFT 0x10 6879 #define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE_MASK 0xffff 6880 #define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE__SHIFT 0x0 6881 #define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET_MASK 0xffff0000 6882 #define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET__SHIFT 0x10 6883 #define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE_MASK 0xffff 6884 #define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE__SHIFT 0x0 6885 #define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET_MASK 0xffff0000 6886 #define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET__SHIFT 0x10 6887 #define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE_MASK 0xffff 6888 #define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE__SHIFT 0x0 6889 #define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET_MASK 0xffff0000 6890 #define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET__SHIFT 0x10 6891 #define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE_MASK 0xffff 6892 #define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE__SHIFT 0x0 6893 #define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET_MASK 0xffff0000 6894 #define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET__SHIFT 0x10 6895 #define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE_MASK 0xffff 6896 #define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE__SHIFT 0x0 6897 #define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET_MASK 0xffff0000 6898 #define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET__SHIFT 0x10 6899 #define MC_VM_NB_MMIOBASE__MMIOBASE_MASK 0xffffffff 6900 #define MC_VM_NB_MMIOBASE__MMIOBASE__SHIFT 0x0 6901 #define MC_VM_NB_MMIOLIMIT__MMIOLIMIT_MASK 0xffffffff 6902 #define MC_VM_NB_MMIOLIMIT__MMIOLIMIT__SHIFT 0x0 6903 #define MC_VM_NB_PCI_CTRL__MMIOENABLE_MASK 0x800000 6904 #define MC_VM_NB_PCI_CTRL__MMIOENABLE__SHIFT 0x17 6905 #define MC_VM_NB_PCI_ARB__VGA_HOLE_MASK 0x8 6906 #define MC_VM_NB_PCI_ARB__VGA_HOLE__SHIFT 0x3 6907 #define MC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_MASK 0xff800000 6908 #define MC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM__SHIFT 0x17 6909 #define MC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE_MASK 0x1 6910 #define MC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE__SHIFT 0x0 6911 #define MC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2_MASK 0xff800000 6912 #define MC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2__SHIFT 0x17 6913 #define MC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2_MASK 0xff 6914 #define MC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2__SHIFT 0x0 6915 #define MC_VM_NB_TOP_OF_DRAM3__TOM3_LIMIT_MASK 0x3fffffff 6916 #define MC_VM_NB_TOP_OF_DRAM3__TOM3_LIMIT__SHIFT 0x0 6917 #define MC_VM_NB_TOP_OF_DRAM3__TOM3_ENABLE_MASK 0x80000000 6918 #define MC_VM_NB_TOP_OF_DRAM3__TOM3_ENABLE__SHIFT 0x1f 6919 #define MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0_MASK 0xfffff000 6920 #define MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0__SHIFT 0xc 6921 #define MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1_MASK 0xfffff000 6922 #define MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1__SHIFT 0xc 6923 #define MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2_MASK 0xfffff000 6924 #define MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2__SHIFT 0xc 6925 #define MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3_MASK 0xfffff000 6926 #define MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3__SHIFT 0xc 6927 #define MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0_MASK 0xfffff 6928 #define MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0__SHIFT 0x0 6929 #define MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1_MASK 0xfffff 6930 #define MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1__SHIFT 0x0 6931 #define MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2_MASK 0xfffff 6932 #define MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2__SHIFT 0x0 6933 #define MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3_MASK 0xfffff 6934 #define MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3__SHIFT 0x0 6935 #define MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0_MASK 0x1 6936 #define MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0__SHIFT 0x0 6937 #define MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0_MASK 0x2 6938 #define MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0__SHIFT 0x1 6939 #define MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0_MASK 0xfffff000 6940 #define MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0__SHIFT 0xc 6941 #define MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1_MASK 0x1 6942 #define MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1__SHIFT 0x0 6943 #define MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1_MASK 0x2 6944 #define MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1__SHIFT 0x1 6945 #define MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1_MASK 0xfffff000 6946 #define MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1__SHIFT 0xc 6947 #define MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2_MASK 0x1 6948 #define MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2__SHIFT 0x0 6949 #define MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2_MASK 0x2 6950 #define MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2__SHIFT 0x1 6951 #define MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2_MASK 0xfffff000 6952 #define MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2__SHIFT 0xc 6953 #define MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3_MASK 0x1 6954 #define MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3__SHIFT 0x0 6955 #define MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3_MASK 0x2 6956 #define MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3__SHIFT 0x1 6957 #define MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3_MASK 0xfffff000 6958 #define MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3__SHIFT 0xc 6959 #define MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0_MASK 0xfffff 6960 #define MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0__SHIFT 0x0 6961 #define MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1_MASK 0xfffff 6962 #define MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1__SHIFT 0x0 6963 #define MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2_MASK 0xfffff 6964 #define MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2__SHIFT 0x0 6965 #define MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3_MASK 0xfffff 6966 #define MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3__SHIFT 0x0 6967 #define MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0_MASK 0xfffff000 6968 #define MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0__SHIFT 0xc 6969 #define MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1_MASK 0xfffff000 6970 #define MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1__SHIFT 0xc 6971 #define MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2_MASK 0xfffff000 6972 #define MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2__SHIFT 0xc 6973 #define MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3_MASK 0xfffff000 6974 #define MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3__SHIFT 0xc 6975 #define MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0_MASK 0xfffff 6976 #define MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0__SHIFT 0x0 6977 #define MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1_MASK 0xfffff 6978 #define MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1__SHIFT 0x0 6979 #define MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2_MASK 0xfffff 6980 #define MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2__SHIFT 0x0 6981 #define MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3_MASK 0xfffff 6982 #define MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3__SHIFT 0x0 6983 #define MC_VM_MARC_CNTL__ENABLE_ALL_CLIENTS_MASK 0x1 6984 #define MC_VM_MARC_CNTL__ENABLE_ALL_CLIENTS__SHIFT 0x0 6985 #define MC_ARB_HARSH_EN_RD__TX_PRI_MASK 0xff 6986 #define MC_ARB_HARSH_EN_RD__TX_PRI__SHIFT 0x0 6987 #define MC_ARB_HARSH_EN_RD__BW_PRI_MASK 0xff00 6988 #define MC_ARB_HARSH_EN_RD__BW_PRI__SHIFT 0x8 6989 #define MC_ARB_HARSH_EN_RD__FIX_PRI_MASK 0xff0000 6990 #define MC_ARB_HARSH_EN_RD__FIX_PRI__SHIFT 0x10 6991 #define MC_ARB_HARSH_EN_RD__ST_PRI_MASK 0xff000000 6992 #define MC_ARB_HARSH_EN_RD__ST_PRI__SHIFT 0x18 6993 #define MC_ARB_HARSH_EN_WR__TX_PRI_MASK 0xff 6994 #define MC_ARB_HARSH_EN_WR__TX_PRI__SHIFT 0x0 6995 #define MC_ARB_HARSH_EN_WR__BW_PRI_MASK 0xff00 6996 #define MC_ARB_HARSH_EN_WR__BW_PRI__SHIFT 0x8 6997 #define MC_ARB_HARSH_EN_WR__FIX_PRI_MASK 0xff0000 6998 #define MC_ARB_HARSH_EN_WR__FIX_PRI__SHIFT 0x10 6999 #define MC_ARB_HARSH_EN_WR__ST_PRI_MASK 0xff000000 7000 #define MC_ARB_HARSH_EN_WR__ST_PRI__SHIFT 0x18 7001 #define MC_ARB_HARSH_TX_HI0_RD__GROUP0_MASK 0xff 7002 #define MC_ARB_HARSH_TX_HI0_RD__GROUP0__SHIFT 0x0 7003 #define MC_ARB_HARSH_TX_HI0_RD__GROUP1_MASK 0xff00 7004 #define MC_ARB_HARSH_TX_HI0_RD__GROUP1__SHIFT 0x8 7005 #define MC_ARB_HARSH_TX_HI0_RD__GROUP2_MASK 0xff0000 7006 #define MC_ARB_HARSH_TX_HI0_RD__GROUP2__SHIFT 0x10 7007 #define MC_ARB_HARSH_TX_HI0_RD__GROUP3_MASK 0xff000000 7008 #define MC_ARB_HARSH_TX_HI0_RD__GROUP3__SHIFT 0x18 7009 #define MC_ARB_HARSH_TX_HI0_WR__GROUP0_MASK 0xff 7010 #define MC_ARB_HARSH_TX_HI0_WR__GROUP0__SHIFT 0x0 7011 #define MC_ARB_HARSH_TX_HI0_WR__GROUP1_MASK 0xff00 7012 #define MC_ARB_HARSH_TX_HI0_WR__GROUP1__SHIFT 0x8 7013 #define MC_ARB_HARSH_TX_HI0_WR__GROUP2_MASK 0xff0000 7014 #define MC_ARB_HARSH_TX_HI0_WR__GROUP2__SHIFT 0x10 7015 #define MC_ARB_HARSH_TX_HI0_WR__GROUP3_MASK 0xff000000 7016 #define MC_ARB_HARSH_TX_HI0_WR__GROUP3__SHIFT 0x18 7017 #define MC_ARB_HARSH_TX_HI1_RD__GROUP4_MASK 0xff 7018 #define MC_ARB_HARSH_TX_HI1_RD__GROUP4__SHIFT 0x0 7019 #define MC_ARB_HARSH_TX_HI1_RD__GROUP5_MASK 0xff00 7020 #define MC_ARB_HARSH_TX_HI1_RD__GROUP5__SHIFT 0x8 7021 #define MC_ARB_HARSH_TX_HI1_RD__GROUP6_MASK 0xff0000 7022 #define MC_ARB_HARSH_TX_HI1_RD__GROUP6__SHIFT 0x10 7023 #define MC_ARB_HARSH_TX_HI1_RD__GROUP7_MASK 0xff000000 7024 #define MC_ARB_HARSH_TX_HI1_RD__GROUP7__SHIFT 0x18 7025 #define MC_ARB_HARSH_TX_HI1_WR__GROUP4_MASK 0xff 7026 #define MC_ARB_HARSH_TX_HI1_WR__GROUP4__SHIFT 0x0 7027 #define MC_ARB_HARSH_TX_HI1_WR__GROUP5_MASK 0xff00 7028 #define MC_ARB_HARSH_TX_HI1_WR__GROUP5__SHIFT 0x8 7029 #define MC_ARB_HARSH_TX_HI1_WR__GROUP6_MASK 0xff0000 7030 #define MC_ARB_HARSH_TX_HI1_WR__GROUP6__SHIFT 0x10 7031 #define MC_ARB_HARSH_TX_HI1_WR__GROUP7_MASK 0xff000000 7032 #define MC_ARB_HARSH_TX_HI1_WR__GROUP7__SHIFT 0x18 7033 #define MC_ARB_HARSH_TX_LO0_RD__GROUP0_MASK 0xff 7034 #define MC_ARB_HARSH_TX_LO0_RD__GROUP0__SHIFT 0x0 7035 #define MC_ARB_HARSH_TX_LO0_RD__GROUP1_MASK 0xff00 7036 #define MC_ARB_HARSH_TX_LO0_RD__GROUP1__SHIFT 0x8 7037 #define MC_ARB_HARSH_TX_LO0_RD__GROUP2_MASK 0xff0000 7038 #define MC_ARB_HARSH_TX_LO0_RD__GROUP2__SHIFT 0x10 7039 #define MC_ARB_HARSH_TX_LO0_RD__GROUP3_MASK 0xff000000 7040 #define MC_ARB_HARSH_TX_LO0_RD__GROUP3__SHIFT 0x18 7041 #define MC_ARB_HARSH_TX_LO0_WR__GROUP0_MASK 0xff 7042 #define MC_ARB_HARSH_TX_LO0_WR__GROUP0__SHIFT 0x0 7043 #define MC_ARB_HARSH_TX_LO0_WR__GROUP1_MASK 0xff00 7044 #define MC_ARB_HARSH_TX_LO0_WR__GROUP1__SHIFT 0x8 7045 #define MC_ARB_HARSH_TX_LO0_WR__GROUP2_MASK 0xff0000 7046 #define MC_ARB_HARSH_TX_LO0_WR__GROUP2__SHIFT 0x10 7047 #define MC_ARB_HARSH_TX_LO0_WR__GROUP3_MASK 0xff000000 7048 #define MC_ARB_HARSH_TX_LO0_WR__GROUP3__SHIFT 0x18 7049 #define MC_ARB_HARSH_TX_LO1_RD__GROUP4_MASK 0xff 7050 #define MC_ARB_HARSH_TX_LO1_RD__GROUP4__SHIFT 0x0 7051 #define MC_ARB_HARSH_TX_LO1_RD__GROUP5_MASK 0xff00 7052 #define MC_ARB_HARSH_TX_LO1_RD__GROUP5__SHIFT 0x8 7053 #define MC_ARB_HARSH_TX_LO1_RD__GROUP6_MASK 0xff0000 7054 #define MC_ARB_HARSH_TX_LO1_RD__GROUP6__SHIFT 0x10 7055 #define MC_ARB_HARSH_TX_LO1_RD__GROUP7_MASK 0xff000000 7056 #define MC_ARB_HARSH_TX_LO1_RD__GROUP7__SHIFT 0x18 7057 #define MC_ARB_HARSH_TX_LO1_WR__GROUP4_MASK 0xff 7058 #define MC_ARB_HARSH_TX_LO1_WR__GROUP4__SHIFT 0x0 7059 #define MC_ARB_HARSH_TX_LO1_WR__GROUP5_MASK 0xff00 7060 #define MC_ARB_HARSH_TX_LO1_WR__GROUP5__SHIFT 0x8 7061 #define MC_ARB_HARSH_TX_LO1_WR__GROUP6_MASK 0xff0000 7062 #define MC_ARB_HARSH_TX_LO1_WR__GROUP6__SHIFT 0x10 7063 #define MC_ARB_HARSH_TX_LO1_WR__GROUP7_MASK 0xff000000 7064 #define MC_ARB_HARSH_TX_LO1_WR__GROUP7__SHIFT 0x18 7065 #define MC_ARB_HARSH_BWPERIOD0_RD__GROUP0_MASK 0xff 7066 #define MC_ARB_HARSH_BWPERIOD0_RD__GROUP0__SHIFT 0x0 7067 #define MC_ARB_HARSH_BWPERIOD0_RD__GROUP1_MASK 0xff00 7068 #define MC_ARB_HARSH_BWPERIOD0_RD__GROUP1__SHIFT 0x8 7069 #define MC_ARB_HARSH_BWPERIOD0_RD__GROUP2_MASK 0xff0000 7070 #define MC_ARB_HARSH_BWPERIOD0_RD__GROUP2__SHIFT 0x10 7071 #define MC_ARB_HARSH_BWPERIOD0_RD__GROUP3_MASK 0xff000000 7072 #define MC_ARB_HARSH_BWPERIOD0_RD__GROUP3__SHIFT 0x18 7073 #define MC_ARB_HARSH_BWPERIOD0_WR__GROUP0_MASK 0xff 7074 #define MC_ARB_HARSH_BWPERIOD0_WR__GROUP0__SHIFT 0x0 7075 #define MC_ARB_HARSH_BWPERIOD0_WR__GROUP1_MASK 0xff00 7076 #define MC_ARB_HARSH_BWPERIOD0_WR__GROUP1__SHIFT 0x8 7077 #define MC_ARB_HARSH_BWPERIOD0_WR__GROUP2_MASK 0xff0000 7078 #define MC_ARB_HARSH_BWPERIOD0_WR__GROUP2__SHIFT 0x10 7079 #define MC_ARB_HARSH_BWPERIOD0_WR__GROUP3_MASK 0xff000000 7080 #define MC_ARB_HARSH_BWPERIOD0_WR__GROUP3__SHIFT 0x18 7081 #define MC_ARB_HARSH_BWPERIOD1_RD__GROUP4_MASK 0xff 7082 #define MC_ARB_HARSH_BWPERIOD1_RD__GROUP4__SHIFT 0x0 7083 #define MC_ARB_HARSH_BWPERIOD1_RD__GROUP5_MASK 0xff00 7084 #define MC_ARB_HARSH_BWPERIOD1_RD__GROUP5__SHIFT 0x8 7085 #define MC_ARB_HARSH_BWPERIOD1_RD__GROUP6_MASK 0xff0000 7086 #define MC_ARB_HARSH_BWPERIOD1_RD__GROUP6__SHIFT 0x10 7087 #define MC_ARB_HARSH_BWPERIOD1_RD__GROUP7_MASK 0xff000000 7088 #define MC_ARB_HARSH_BWPERIOD1_RD__GROUP7__SHIFT 0x18 7089 #define MC_ARB_HARSH_BWPERIOD1_WR__GROUP4_MASK 0xff 7090 #define MC_ARB_HARSH_BWPERIOD1_WR__GROUP4__SHIFT 0x0 7091 #define MC_ARB_HARSH_BWPERIOD1_WR__GROUP5_MASK 0xff00 7092 #define MC_ARB_HARSH_BWPERIOD1_WR__GROUP5__SHIFT 0x8 7093 #define MC_ARB_HARSH_BWPERIOD1_WR__GROUP6_MASK 0xff0000 7094 #define MC_ARB_HARSH_BWPERIOD1_WR__GROUP6__SHIFT 0x10 7095 #define MC_ARB_HARSH_BWPERIOD1_WR__GROUP7_MASK 0xff000000 7096 #define MC_ARB_HARSH_BWPERIOD1_WR__GROUP7__SHIFT 0x18 7097 #define MC_ARB_HARSH_BWCNT0_RD__GROUP0_MASK 0xff 7098 #define MC_ARB_HARSH_BWCNT0_RD__GROUP0__SHIFT 0x0 7099 #define MC_ARB_HARSH_BWCNT0_RD__GROUP1_MASK 0xff00 7100 #define MC_ARB_HARSH_BWCNT0_RD__GROUP1__SHIFT 0x8 7101 #define MC_ARB_HARSH_BWCNT0_RD__GROUP2_MASK 0xff0000 7102 #define MC_ARB_HARSH_BWCNT0_RD__GROUP2__SHIFT 0x10 7103 #define MC_ARB_HARSH_BWCNT0_RD__GROUP3_MASK 0xff000000 7104 #define MC_ARB_HARSH_BWCNT0_RD__GROUP3__SHIFT 0x18 7105 #define MC_ARB_HARSH_BWCNT0_WR__GROUP0_MASK 0xff 7106 #define MC_ARB_HARSH_BWCNT0_WR__GROUP0__SHIFT 0x0 7107 #define MC_ARB_HARSH_BWCNT0_WR__GROUP1_MASK 0xff00 7108 #define MC_ARB_HARSH_BWCNT0_WR__GROUP1__SHIFT 0x8 7109 #define MC_ARB_HARSH_BWCNT0_WR__GROUP2_MASK 0xff0000 7110 #define MC_ARB_HARSH_BWCNT0_WR__GROUP2__SHIFT 0x10 7111 #define MC_ARB_HARSH_BWCNT0_WR__GROUP3_MASK 0xff000000 7112 #define MC_ARB_HARSH_BWCNT0_WR__GROUP3__SHIFT 0x18 7113 #define MC_ARB_HARSH_BWCNT1_RD__GROUP4_MASK 0xff 7114 #define MC_ARB_HARSH_BWCNT1_RD__GROUP4__SHIFT 0x0 7115 #define MC_ARB_HARSH_BWCNT1_RD__GROUP5_MASK 0xff00 7116 #define MC_ARB_HARSH_BWCNT1_RD__GROUP5__SHIFT 0x8 7117 #define MC_ARB_HARSH_BWCNT1_RD__GROUP6_MASK 0xff0000 7118 #define MC_ARB_HARSH_BWCNT1_RD__GROUP6__SHIFT 0x10 7119 #define MC_ARB_HARSH_BWCNT1_RD__GROUP7_MASK 0xff000000 7120 #define MC_ARB_HARSH_BWCNT1_RD__GROUP7__SHIFT 0x18 7121 #define MC_ARB_HARSH_BWCNT1_WR__GROUP4_MASK 0xff 7122 #define MC_ARB_HARSH_BWCNT1_WR__GROUP4__SHIFT 0x0 7123 #define MC_ARB_HARSH_BWCNT1_WR__GROUP5_MASK 0xff00 7124 #define MC_ARB_HARSH_BWCNT1_WR__GROUP5__SHIFT 0x8 7125 #define MC_ARB_HARSH_BWCNT1_WR__GROUP6_MASK 0xff0000 7126 #define MC_ARB_HARSH_BWCNT1_WR__GROUP6__SHIFT 0x10 7127 #define MC_ARB_HARSH_BWCNT1_WR__GROUP7_MASK 0xff000000 7128 #define MC_ARB_HARSH_BWCNT1_WR__GROUP7__SHIFT 0x18 7129 #define MC_ARB_HARSH_SAT0_RD__GROUP0_MASK 0xff 7130 #define MC_ARB_HARSH_SAT0_RD__GROUP0__SHIFT 0x0 7131 #define MC_ARB_HARSH_SAT0_RD__GROUP1_MASK 0xff00 7132 #define MC_ARB_HARSH_SAT0_RD__GROUP1__SHIFT 0x8 7133 #define MC_ARB_HARSH_SAT0_RD__GROUP2_MASK 0xff0000 7134 #define MC_ARB_HARSH_SAT0_RD__GROUP2__SHIFT 0x10 7135 #define MC_ARB_HARSH_SAT0_RD__GROUP3_MASK 0xff000000 7136 #define MC_ARB_HARSH_SAT0_RD__GROUP3__SHIFT 0x18 7137 #define MC_ARB_HARSH_SAT0_WR__GROUP0_MASK 0xff 7138 #define MC_ARB_HARSH_SAT0_WR__GROUP0__SHIFT 0x0 7139 #define MC_ARB_HARSH_SAT0_WR__GROUP1_MASK 0xff00 7140 #define MC_ARB_HARSH_SAT0_WR__GROUP1__SHIFT 0x8 7141 #define MC_ARB_HARSH_SAT0_WR__GROUP2_MASK 0xff0000 7142 #define MC_ARB_HARSH_SAT0_WR__GROUP2__SHIFT 0x10 7143 #define MC_ARB_HARSH_SAT0_WR__GROUP3_MASK 0xff000000 7144 #define MC_ARB_HARSH_SAT0_WR__GROUP3__SHIFT 0x18 7145 #define MC_ARB_HARSH_SAT1_RD__GROUP4_MASK 0xff 7146 #define MC_ARB_HARSH_SAT1_RD__GROUP4__SHIFT 0x0 7147 #define MC_ARB_HARSH_SAT1_RD__GROUP5_MASK 0xff00 7148 #define MC_ARB_HARSH_SAT1_RD__GROUP5__SHIFT 0x8 7149 #define MC_ARB_HARSH_SAT1_RD__GROUP6_MASK 0xff0000 7150 #define MC_ARB_HARSH_SAT1_RD__GROUP6__SHIFT 0x10 7151 #define MC_ARB_HARSH_SAT1_RD__GROUP7_MASK 0xff000000 7152 #define MC_ARB_HARSH_SAT1_RD__GROUP7__SHIFT 0x18 7153 #define MC_ARB_HARSH_SAT1_WR__GROUP4_MASK 0xff 7154 #define MC_ARB_HARSH_SAT1_WR__GROUP4__SHIFT 0x0 7155 #define MC_ARB_HARSH_SAT1_WR__GROUP5_MASK 0xff00 7156 #define MC_ARB_HARSH_SAT1_WR__GROUP5__SHIFT 0x8 7157 #define MC_ARB_HARSH_SAT1_WR__GROUP6_MASK 0xff0000 7158 #define MC_ARB_HARSH_SAT1_WR__GROUP6__SHIFT 0x10 7159 #define MC_ARB_HARSH_SAT1_WR__GROUP7_MASK 0xff000000 7160 #define MC_ARB_HARSH_SAT1_WR__GROUP7__SHIFT 0x18 7161 #define MC_ARB_HARSH_CTL_RD__FORCE_HIGHEST_MASK 0xff 7162 #define MC_ARB_HARSH_CTL_RD__FORCE_HIGHEST__SHIFT 0x0 7163 #define MC_ARB_HARSH_CTL_RD__HARSH_RR_MASK 0x100 7164 #define MC_ARB_HARSH_CTL_RD__HARSH_RR__SHIFT 0x8 7165 #define MC_ARB_HARSH_CTL_RD__BANK_AGE_ONLY_MASK 0x200 7166 #define MC_ARB_HARSH_CTL_RD__BANK_AGE_ONLY__SHIFT 0x9 7167 #define MC_ARB_HARSH_CTL_RD__USE_LEGACY_HARSH_MASK 0x400 7168 #define MC_ARB_HARSH_CTL_RD__USE_LEGACY_HARSH__SHIFT 0xa 7169 #define MC_ARB_HARSH_CTL_RD__BWCNT_CATCHUP_MASK 0x800 7170 #define MC_ARB_HARSH_CTL_RD__BWCNT_CATCHUP__SHIFT 0xb 7171 #define MC_ARB_HARSH_CTL_RD__ST_MODE_MASK 0x3000 7172 #define MC_ARB_HARSH_CTL_RD__ST_MODE__SHIFT 0xc 7173 #define MC_ARB_HARSH_CTL_RD__FORCE_STALL_MASK 0x3fc000 7174 #define MC_ARB_HARSH_CTL_RD__FORCE_STALL__SHIFT 0xe 7175 #define MC_ARB_HARSH_CTL_RD__PERF_MON_SEL_MASK 0x1c00000 7176 #define MC_ARB_HARSH_CTL_RD__PERF_MON_SEL__SHIFT 0x16 7177 #define MC_ARB_HARSH_CTL_WR__FORCE_HIGHEST_MASK 0xff 7178 #define MC_ARB_HARSH_CTL_WR__FORCE_HIGHEST__SHIFT 0x0 7179 #define MC_ARB_HARSH_CTL_WR__HARSH_RR_MASK 0x100 7180 #define MC_ARB_HARSH_CTL_WR__HARSH_RR__SHIFT 0x8 7181 #define MC_ARB_HARSH_CTL_WR__BANK_AGE_ONLY_MASK 0x200 7182 #define MC_ARB_HARSH_CTL_WR__BANK_AGE_ONLY__SHIFT 0x9 7183 #define MC_ARB_HARSH_CTL_WR__USE_LEGACY_HARSH_MASK 0x400 7184 #define MC_ARB_HARSH_CTL_WR__USE_LEGACY_HARSH__SHIFT 0xa 7185 #define MC_ARB_HARSH_CTL_WR__BWCNT_CATCHUP_MASK 0x800 7186 #define MC_ARB_HARSH_CTL_WR__BWCNT_CATCHUP__SHIFT 0xb 7187 #define MC_ARB_HARSH_CTL_WR__ST_MODE_MASK 0x3000 7188 #define MC_ARB_HARSH_CTL_WR__ST_MODE__SHIFT 0xc 7189 #define MC_ARB_HARSH_CTL_WR__FORCE_STALL_MASK 0x3fc000 7190 #define MC_ARB_HARSH_CTL_WR__FORCE_STALL__SHIFT 0xe 7191 #define MC_ARB_HARSH_CTL_WR__PERF_MON_SEL_MASK 0x1c00000 7192 #define MC_ARB_HARSH_CTL_WR__PERF_MON_SEL__SHIFT 0x16 7193 #define MC_ARB_GRUB_PRIORITY1_RD__CB0_MASK 0x3 7194 #define MC_ARB_GRUB_PRIORITY1_RD__CB0__SHIFT 0x0 7195 #define MC_ARB_GRUB_PRIORITY1_RD__CBCMASK0_MASK 0xc 7196 #define MC_ARB_GRUB_PRIORITY1_RD__CBCMASK0__SHIFT 0x2 7197 #define MC_ARB_GRUB_PRIORITY1_RD__CBFMASK0_MASK 0x30 7198 #define MC_ARB_GRUB_PRIORITY1_RD__CBFMASK0__SHIFT 0x4 7199 #define MC_ARB_GRUB_PRIORITY1_RD__DB0_MASK 0xc0 7200 #define MC_ARB_GRUB_PRIORITY1_RD__DB0__SHIFT 0x6 7201 #define MC_ARB_GRUB_PRIORITY1_RD__DBHTILE0_MASK 0x300 7202 #define MC_ARB_GRUB_PRIORITY1_RD__DBHTILE0__SHIFT 0x8 7203 #define MC_ARB_GRUB_PRIORITY1_RD__DBSTEN0_MASK 0xc00 7204 #define MC_ARB_GRUB_PRIORITY1_RD__DBSTEN0__SHIFT 0xa 7205 #define MC_ARB_GRUB_PRIORITY1_RD__TC0_MASK 0x3000 7206 #define MC_ARB_GRUB_PRIORITY1_RD__TC0__SHIFT 0xc 7207 #define MC_ARB_GRUB_PRIORITY1_RD__ACPG_MASK 0xc000 7208 #define MC_ARB_GRUB_PRIORITY1_RD__ACPG__SHIFT 0xe 7209 #define MC_ARB_GRUB_PRIORITY1_RD__ACPO_MASK 0x30000 7210 #define MC_ARB_GRUB_PRIORITY1_RD__ACPO__SHIFT 0x10 7211 #define MC_ARB_GRUB_PRIORITY1_RD__DMIF_MASK 0xc0000 7212 #define MC_ARB_GRUB_PRIORITY1_RD__DMIF__SHIFT 0x12 7213 #define MC_ARB_GRUB_PRIORITY1_RD__DMIF_EXT0_MASK 0x300000 7214 #define MC_ARB_GRUB_PRIORITY1_RD__DMIF_EXT0__SHIFT 0x14 7215 #define MC_ARB_GRUB_PRIORITY1_RD__DMIF_EXT1_MASK 0xc00000 7216 #define MC_ARB_GRUB_PRIORITY1_RD__DMIF_EXT1__SHIFT 0x16 7217 #define MC_ARB_GRUB_PRIORITY1_RD__DMIF_TW_MASK 0x3000000 7218 #define MC_ARB_GRUB_PRIORITY1_RD__DMIF_TW__SHIFT 0x18 7219 #define MC_ARB_GRUB_PRIORITY1_RD__MCIF_MASK 0xc000000 7220 #define MC_ARB_GRUB_PRIORITY1_RD__MCIF__SHIFT 0x1a 7221 #define MC_ARB_GRUB_PRIORITY1_RD__RLC_MASK 0x30000000 7222 #define MC_ARB_GRUB_PRIORITY1_RD__RLC__SHIFT 0x1c 7223 #define MC_ARB_GRUB_PRIORITY1_RD__VMC_MASK 0xc0000000 7224 #define MC_ARB_GRUB_PRIORITY1_RD__VMC__SHIFT 0x1e 7225 #define MC_ARB_GRUB_PRIORITY1_WR__CB0_MASK 0x3 7226 #define MC_ARB_GRUB_PRIORITY1_WR__CB0__SHIFT 0x0 7227 #define MC_ARB_GRUB_PRIORITY1_WR__CBCMASK0_MASK 0xc 7228 #define MC_ARB_GRUB_PRIORITY1_WR__CBCMASK0__SHIFT 0x2 7229 #define MC_ARB_GRUB_PRIORITY1_WR__CBFMASK0_MASK 0x30 7230 #define MC_ARB_GRUB_PRIORITY1_WR__CBFMASK0__SHIFT 0x4 7231 #define MC_ARB_GRUB_PRIORITY1_WR__CBIMMED0_MASK 0xc0 7232 #define MC_ARB_GRUB_PRIORITY1_WR__CBIMMED0__SHIFT 0x6 7233 #define MC_ARB_GRUB_PRIORITY1_WR__DB0_MASK 0x300 7234 #define MC_ARB_GRUB_PRIORITY1_WR__DB0__SHIFT 0x8 7235 #define MC_ARB_GRUB_PRIORITY1_WR__DBHTILE0_MASK 0xc00 7236 #define MC_ARB_GRUB_PRIORITY1_WR__DBHTILE0__SHIFT 0xa 7237 #define MC_ARB_GRUB_PRIORITY1_WR__DBSTEN0_MASK 0x3000 7238 #define MC_ARB_GRUB_PRIORITY1_WR__DBSTEN0__SHIFT 0xc 7239 #define MC_ARB_GRUB_PRIORITY1_WR__TC0_MASK 0xc000 7240 #define MC_ARB_GRUB_PRIORITY1_WR__TC0__SHIFT 0xe 7241 #define MC_ARB_GRUB_PRIORITY1_WR__SH_MASK 0x30000 7242 #define MC_ARB_GRUB_PRIORITY1_WR__SH__SHIFT 0x10 7243 #define MC_ARB_GRUB_PRIORITY1_WR__ACPG_MASK 0xc0000 7244 #define MC_ARB_GRUB_PRIORITY1_WR__ACPG__SHIFT 0x12 7245 #define MC_ARB_GRUB_PRIORITY1_WR__ACPO_MASK 0x300000 7246 #define MC_ARB_GRUB_PRIORITY1_WR__ACPO__SHIFT 0x14 7247 #define MC_ARB_GRUB_PRIORITY1_WR__MCIF_MASK 0xc00000 7248 #define MC_ARB_GRUB_PRIORITY1_WR__MCIF__SHIFT 0x16 7249 #define MC_ARB_GRUB_PRIORITY1_WR__RLC_MASK 0x3000000 7250 #define MC_ARB_GRUB_PRIORITY1_WR__RLC__SHIFT 0x18 7251 #define MC_ARB_GRUB_PRIORITY1_WR__SDMA1_MASK 0xc000000 7252 #define MC_ARB_GRUB_PRIORITY1_WR__SDMA1__SHIFT 0x1a 7253 #define MC_ARB_GRUB_PRIORITY1_WR__SMU_MASK 0x30000000 7254 #define MC_ARB_GRUB_PRIORITY1_WR__SMU__SHIFT 0x1c 7255 #define MC_ARB_GRUB_PRIORITY1_WR__VCE0_MASK 0xc0000000 7256 #define MC_ARB_GRUB_PRIORITY1_WR__VCE0__SHIFT 0x1e 7257 #define MC_ARB_GRUB_PRIORITY2_RD__SDMA1_MASK 0x3 7258 #define MC_ARB_GRUB_PRIORITY2_RD__SDMA1__SHIFT 0x0 7259 #define MC_ARB_GRUB_PRIORITY2_RD__SMU_MASK 0xc 7260 #define MC_ARB_GRUB_PRIORITY2_RD__SMU__SHIFT 0x2 7261 #define MC_ARB_GRUB_PRIORITY2_RD__VCE0_MASK 0x30 7262 #define MC_ARB_GRUB_PRIORITY2_RD__VCE0__SHIFT 0x4 7263 #define MC_ARB_GRUB_PRIORITY2_RD__VCE1_MASK 0xc0 7264 #define MC_ARB_GRUB_PRIORITY2_RD__VCE1__SHIFT 0x6 7265 #define MC_ARB_GRUB_PRIORITY2_RD__XDMAM_MASK 0x300 7266 #define MC_ARB_GRUB_PRIORITY2_RD__XDMAM__SHIFT 0x8 7267 #define MC_ARB_GRUB_PRIORITY2_RD__SDMA0_MASK 0xc00 7268 #define MC_ARB_GRUB_PRIORITY2_RD__SDMA0__SHIFT 0xa 7269 #define MC_ARB_GRUB_PRIORITY2_RD__HDP_MASK 0x3000 7270 #define MC_ARB_GRUB_PRIORITY2_RD__HDP__SHIFT 0xc 7271 #define MC_ARB_GRUB_PRIORITY2_RD__UMC_MASK 0xc000 7272 #define MC_ARB_GRUB_PRIORITY2_RD__UMC__SHIFT 0xe 7273 #define MC_ARB_GRUB_PRIORITY2_RD__UVD_MASK 0x30000 7274 #define MC_ARB_GRUB_PRIORITY2_RD__UVD__SHIFT 0x10 7275 #define MC_ARB_GRUB_PRIORITY2_RD__UVD_EXT0_MASK 0xc0000 7276 #define MC_ARB_GRUB_PRIORITY2_RD__UVD_EXT0__SHIFT 0x12 7277 #define MC_ARB_GRUB_PRIORITY2_RD__UVD_EXT1_MASK 0x300000 7278 #define MC_ARB_GRUB_PRIORITY2_RD__UVD_EXT1__SHIFT 0x14 7279 #define MC_ARB_GRUB_PRIORITY2_RD__SEM_MASK 0xc00000 7280 #define MC_ARB_GRUB_PRIORITY2_RD__SEM__SHIFT 0x16 7281 #define MC_ARB_GRUB_PRIORITY2_RD__SAMMSP_MASK 0x3000000 7282 #define MC_ARB_GRUB_PRIORITY2_RD__SAMMSP__SHIFT 0x18 7283 #define MC_ARB_GRUB_PRIORITY2_RD__VP8_MASK 0xc000000 7284 #define MC_ARB_GRUB_PRIORITY2_RD__VP8__SHIFT 0x1a 7285 #define MC_ARB_GRUB_PRIORITY2_RD__ISP_MASK 0x30000000 7286 #define MC_ARB_GRUB_PRIORITY2_RD__ISP__SHIFT 0x1c 7287 #define MC_ARB_GRUB_PRIORITY2_RD__RSV2_MASK 0xc0000000 7288 #define MC_ARB_GRUB_PRIORITY2_RD__RSV2__SHIFT 0x1e 7289 #define MC_ARB_GRUB_PRIORITY2_WR__VCE1_MASK 0x3 7290 #define MC_ARB_GRUB_PRIORITY2_WR__VCE1__SHIFT 0x0 7291 #define MC_ARB_GRUB_PRIORITY2_WR__SAMMSP_MASK 0xc 7292 #define MC_ARB_GRUB_PRIORITY2_WR__SAMMSP__SHIFT 0x2 7293 #define MC_ARB_GRUB_PRIORITY2_WR__XDMA_MASK 0x30 7294 #define MC_ARB_GRUB_PRIORITY2_WR__XDMA__SHIFT 0x4 7295 #define MC_ARB_GRUB_PRIORITY2_WR__XDMAM_MASK 0xc0 7296 #define MC_ARB_GRUB_PRIORITY2_WR__XDMAM__SHIFT 0x6 7297 #define MC_ARB_GRUB_PRIORITY2_WR__SDMA0_MASK 0x300 7298 #define MC_ARB_GRUB_PRIORITY2_WR__SDMA0__SHIFT 0x8 7299 #define MC_ARB_GRUB_PRIORITY2_WR__HDP_MASK 0xc00 7300 #define MC_ARB_GRUB_PRIORITY2_WR__HDP__SHIFT 0xa 7301 #define MC_ARB_GRUB_PRIORITY2_WR__UMC_MASK 0x3000 7302 #define MC_ARB_GRUB_PRIORITY2_WR__UMC__SHIFT 0xc 7303 #define MC_ARB_GRUB_PRIORITY2_WR__UVD_MASK 0xc000 7304 #define MC_ARB_GRUB_PRIORITY2_WR__UVD__SHIFT 0xe 7305 #define MC_ARB_GRUB_PRIORITY2_WR__UVD_EXT0_MASK 0x30000 7306 #define MC_ARB_GRUB_PRIORITY2_WR__UVD_EXT0__SHIFT 0x10 7307 #define MC_ARB_GRUB_PRIORITY2_WR__UVD_EXT1_MASK 0xc0000 7308 #define MC_ARB_GRUB_PRIORITY2_WR__UVD_EXT1__SHIFT 0x12 7309 #define MC_ARB_GRUB_PRIORITY2_WR__XDP_MASK 0x300000 7310 #define MC_ARB_GRUB_PRIORITY2_WR__XDP__SHIFT 0x14 7311 #define MC_ARB_GRUB_PRIORITY2_WR__SEM_MASK 0xc00000 7312 #define MC_ARB_GRUB_PRIORITY2_WR__SEM__SHIFT 0x16 7313 #define MC_ARB_GRUB_PRIORITY2_WR__IH_MASK 0x3000000 7314 #define MC_ARB_GRUB_PRIORITY2_WR__IH__SHIFT 0x18 7315 #define MC_ARB_GRUB_PRIORITY2_WR__VP8_MASK 0xc000000 7316 #define MC_ARB_GRUB_PRIORITY2_WR__VP8__SHIFT 0x1a 7317 #define MC_ARB_GRUB_PRIORITY2_WR__ISP_MASK 0x30000000 7318 #define MC_ARB_GRUB_PRIORITY2_WR__ISP__SHIFT 0x1c 7319 #define MC_ARB_GRUB_PRIORITY2_WR__VIN0_MASK 0xc0000000 7320 #define MC_ARB_GRUB_PRIORITY2_WR__VIN0__SHIFT 0x1e 7321 #define MC_FUS_DRAM0_CS0_BASE__CSENABLE_MASK 0x1 7322 #define MC_FUS_DRAM0_CS0_BASE__CSENABLE__SHIFT 0x0 7323 #define MC_FUS_DRAM0_CS0_BASE__BASEADDR21_11_MASK 0xffe0 7324 #define MC_FUS_DRAM0_CS0_BASE__BASEADDR21_11__SHIFT 0x5 7325 #define MC_FUS_DRAM0_CS0_BASE__BASEADDR38_27_MASK 0x7ff80000 7326 #define MC_FUS_DRAM0_CS0_BASE__BASEADDR38_27__SHIFT 0x13 7327 #define MC_FUS_DRAM1_CS0_BASE__CSENABLE_MASK 0x1 7328 #define MC_FUS_DRAM1_CS0_BASE__CSENABLE__SHIFT 0x0 7329 #define MC_FUS_DRAM1_CS0_BASE__BASEADDR21_11_MASK 0xffe0 7330 #define MC_FUS_DRAM1_CS0_BASE__BASEADDR21_11__SHIFT 0x5 7331 #define MC_FUS_DRAM1_CS0_BASE__BASEADDR38_27_MASK 0x7ff80000 7332 #define MC_FUS_DRAM1_CS0_BASE__BASEADDR38_27__SHIFT 0x13 7333 #define MC_FUS_DRAM0_CS1_BASE__CSENABLE_MASK 0x1 7334 #define MC_FUS_DRAM0_CS1_BASE__CSENABLE__SHIFT 0x0 7335 #define MC_FUS_DRAM0_CS1_BASE__BASEADDR21_11_MASK 0xffe0 7336 #define MC_FUS_DRAM0_CS1_BASE__BASEADDR21_11__SHIFT 0x5 7337 #define MC_FUS_DRAM0_CS1_BASE__BASEADDR38_27_MASK 0x7ff80000 7338 #define MC_FUS_DRAM0_CS1_BASE__BASEADDR38_27__SHIFT 0x13 7339 #define MC_FUS_DRAM1_CS1_BASE__CSENABLE_MASK 0x1 7340 #define MC_FUS_DRAM1_CS1_BASE__CSENABLE__SHIFT 0x0 7341 #define MC_FUS_DRAM1_CS1_BASE__BASEADDR21_11_MASK 0xffe0 7342 #define MC_FUS_DRAM1_CS1_BASE__BASEADDR21_11__SHIFT 0x5 7343 #define MC_FUS_DRAM1_CS1_BASE__BASEADDR38_27_MASK 0x7ff80000 7344 #define MC_FUS_DRAM1_CS1_BASE__BASEADDR38_27__SHIFT 0x13 7345 #define MC_FUS_DRAM0_CS2_BASE__CSENABLE_MASK 0x1 7346 #define MC_FUS_DRAM0_CS2_BASE__CSENABLE__SHIFT 0x0 7347 #define MC_FUS_DRAM0_CS2_BASE__BASEADDR21_11_MASK 0xffe0 7348 #define MC_FUS_DRAM0_CS2_BASE__BASEADDR21_11__SHIFT 0x5 7349 #define MC_FUS_DRAM0_CS2_BASE__BASEADDR38_27_MASK 0x7ff80000 7350 #define MC_FUS_DRAM0_CS2_BASE__BASEADDR38_27__SHIFT 0x13 7351 #define MC_FUS_DRAM1_CS2_BASE__CSENABLE_MASK 0x1 7352 #define MC_FUS_DRAM1_CS2_BASE__CSENABLE__SHIFT 0x0 7353 #define MC_FUS_DRAM1_CS2_BASE__BASEADDR21_11_MASK 0xffe0 7354 #define MC_FUS_DRAM1_CS2_BASE__BASEADDR21_11__SHIFT 0x5 7355 #define MC_FUS_DRAM1_CS2_BASE__BASEADDR38_27_MASK 0x7ff80000 7356 #define MC_FUS_DRAM1_CS2_BASE__BASEADDR38_27__SHIFT 0x13 7357 #define MC_FUS_DRAM0_CS3_BASE__CSENABLE_MASK 0x1 7358 #define MC_FUS_DRAM0_CS3_BASE__CSENABLE__SHIFT 0x0 7359 #define MC_FUS_DRAM0_CS3_BASE__BASEADDR21_11_MASK 0xffe0 7360 #define MC_FUS_DRAM0_CS3_BASE__BASEADDR21_11__SHIFT 0x5 7361 #define MC_FUS_DRAM0_CS3_BASE__BASEADDR38_27_MASK 0x7ff80000 7362 #define MC_FUS_DRAM0_CS3_BASE__BASEADDR38_27__SHIFT 0x13 7363 #define MC_FUS_DRAM1_CS3_BASE__CSENABLE_MASK 0x1 7364 #define MC_FUS_DRAM1_CS3_BASE__CSENABLE__SHIFT 0x0 7365 #define MC_FUS_DRAM1_CS3_BASE__BASEADDR21_11_MASK 0xffe0 7366 #define MC_FUS_DRAM1_CS3_BASE__BASEADDR21_11__SHIFT 0x5 7367 #define MC_FUS_DRAM1_CS3_BASE__BASEADDR38_27_MASK 0x7ff80000 7368 #define MC_FUS_DRAM1_CS3_BASE__BASEADDR38_27__SHIFT 0x13 7369 #define MC_FUS_DRAM0_BANK_ADDR_MAPPING__DIMM0ADDRMAP_MASK 0xf 7370 #define MC_FUS_DRAM0_BANK_ADDR_MAPPING__DIMM0ADDRMAP__SHIFT 0x0 7371 #define MC_FUS_DRAM0_BANK_ADDR_MAPPING__DIMM1ADDRMAP_MASK 0xf0 7372 #define MC_FUS_DRAM0_BANK_ADDR_MAPPING__DIMM1ADDRMAP__SHIFT 0x4 7373 #define MC_FUS_DRAM0_BANK_ADDR_MAPPING__BANKSWIZZLEMODE_MASK 0x100 7374 #define MC_FUS_DRAM0_BANK_ADDR_MAPPING__BANKSWIZZLEMODE__SHIFT 0x8 7375 #define MC_FUS_DRAM0_BANK_ADDR_MAPPING__BANKSWAP_MASK 0x200 7376 #define MC_FUS_DRAM0_BANK_ADDR_MAPPING__BANKSWAP__SHIFT 0x9 7377 #define MC_FUS_DRAM1_BANK_ADDR_MAPPING__DIMM0ADDRMAP_MASK 0xf 7378 #define MC_FUS_DRAM1_BANK_ADDR_MAPPING__DIMM0ADDRMAP__SHIFT 0x0 7379 #define MC_FUS_DRAM1_BANK_ADDR_MAPPING__DIMM1ADDRMAP_MASK 0xf0 7380 #define MC_FUS_DRAM1_BANK_ADDR_MAPPING__DIMM1ADDRMAP__SHIFT 0x4 7381 #define MC_FUS_DRAM1_BANK_ADDR_MAPPING__BANKSWIZZLEMODE_MASK 0x100 7382 #define MC_FUS_DRAM1_BANK_ADDR_MAPPING__BANKSWIZZLEMODE__SHIFT 0x8 7383 #define MC_FUS_DRAM1_BANK_ADDR_MAPPING__BANKSWAP_MASK 0x200 7384 #define MC_FUS_DRAM1_BANK_ADDR_MAPPING__BANKSWAP__SHIFT 0x9 7385 #define MC_FUS_DRAM0_CTL_BASE__DCTSEL_MASK 0x7 7386 #define MC_FUS_DRAM0_CTL_BASE__DCTSEL__SHIFT 0x0 7387 #define MC_FUS_DRAM0_CTL_BASE__DCTINTLVEN_MASK 0x78 7388 #define MC_FUS_DRAM0_CTL_BASE__DCTINTLVEN__SHIFT 0x3 7389 #define MC_FUS_DRAM0_CTL_BASE__DCTBASEADDR_MASK 0xfffff80 7390 #define MC_FUS_DRAM0_CTL_BASE__DCTBASEADDR__SHIFT 0x7 7391 #define MC_FUS_DRAM0_CTL_BASE__DCTOFFSETEN_MASK 0x10000000 7392 #define MC_FUS_DRAM0_CTL_BASE__DCTOFFSETEN__SHIFT 0x1c 7393 #define MC_FUS_DRAM1_CTL_BASE__DCTSEL_MASK 0x7 7394 #define MC_FUS_DRAM1_CTL_BASE__DCTSEL__SHIFT 0x0 7395 #define MC_FUS_DRAM1_CTL_BASE__DCTINTLVEN_MASK 0x78 7396 #define MC_FUS_DRAM1_CTL_BASE__DCTINTLVEN__SHIFT 0x3 7397 #define MC_FUS_DRAM1_CTL_BASE__DCTBASEADDR_MASK 0xfffff80 7398 #define MC_FUS_DRAM1_CTL_BASE__DCTBASEADDR__SHIFT 0x7 7399 #define MC_FUS_DRAM1_CTL_BASE__DCTOFFSETEN_MASK 0x10000000 7400 #define MC_FUS_DRAM1_CTL_BASE__DCTOFFSETEN__SHIFT 0x1c 7401 #define MC_FUS_DRAM0_CTL_LIMIT__DCTLIMITADDR_MASK 0x1fffff 7402 #define MC_FUS_DRAM0_CTL_LIMIT__DCTLIMITADDR__SHIFT 0x0 7403 #define MC_FUS_DRAM0_CTL_LIMIT__DRAMHOLEVALID_MASK 0x200000 7404 #define MC_FUS_DRAM0_CTL_LIMIT__DRAMHOLEVALID__SHIFT 0x15 7405 #define MC_FUS_DRAM1_CTL_LIMIT__DCTLIMITADDR_MASK 0x1fffff 7406 #define MC_FUS_DRAM1_CTL_LIMIT__DCTLIMITADDR__SHIFT 0x0 7407 #define MC_FUS_DRAM1_CTL_LIMIT__DRAMHOLEVALID_MASK 0x200000 7408 #define MC_FUS_DRAM1_CTL_LIMIT__DRAMHOLEVALID__SHIFT 0x15 7409 #define MC_FUS_DRAM_CTL_HIGH_01__DCTHIGHADDROFF0_MASK 0xfff 7410 #define MC_FUS_DRAM_CTL_HIGH_01__DCTHIGHADDROFF0__SHIFT 0x0 7411 #define MC_FUS_DRAM_CTL_HIGH_01__DCTHIGHADDROFF1_MASK 0xfff000 7412 #define MC_FUS_DRAM_CTL_HIGH_01__DCTHIGHADDROFF1__SHIFT 0xc 7413 #define MC_FUS_DRAM_CTL_HIGH_23__DCTHIGHADDROFF2_MASK 0xfff 7414 #define MC_FUS_DRAM_CTL_HIGH_23__DCTHIGHADDROFF2__SHIFT 0x0 7415 #define MC_FUS_DRAM_CTL_HIGH_23__DCTHIGHADDROFF3_MASK 0xfff000 7416 #define MC_FUS_DRAM_CTL_HIGH_23__DCTHIGHADDROFF3__SHIFT 0xc 7417 #define MC_FUS_DRAM_MODE__DCTSELINTLVADDR_MASK 0x7 7418 #define MC_FUS_DRAM_MODE__DCTSELINTLVADDR__SHIFT 0x0 7419 #define MC_FUS_DRAM_MODE__DRAMTYPE_MASK 0x38 7420 #define MC_FUS_DRAM_MODE__DRAMTYPE__SHIFT 0x3 7421 #define MC_FUS_DRAM_MODE__DRAMHOLEOFFSET_MASK 0x7fc0 7422 #define MC_FUS_DRAM_MODE__DRAMHOLEOFFSET__SHIFT 0x6 7423 #define MC_FUS_DRAM_MODE__DDR3LPX32_MASK 0x8000 7424 #define MC_FUS_DRAM_MODE__DDR3LPX32__SHIFT 0xf 7425 #define MC_FUS_DRAM_MODE__BANKGROUPSWAP_MASK 0x10000 7426 #define MC_FUS_DRAM_MODE__BANKGROUPSWAP__SHIFT 0x10 7427 #define MC_FUS_DRAM_APER_BASE__BASE_MASK 0xfffff 7428 #define MC_FUS_DRAM_APER_BASE__BASE__SHIFT 0x0 7429 #define MC_FUS_DRAM_APER_TOP__TOP_MASK 0xfffff 7430 #define MC_FUS_DRAM_APER_TOP__TOP__SHIFT 0x0 7431 #define MC_FUS_DRAM_APER_DEF__DEF_MASK 0xfffffff 7432 #define MC_FUS_DRAM_APER_DEF__DEF__SHIFT 0x0 7433 #define MC_FUS_DRAM_APER_DEF__LOCK_MC_FUS_DRAM_REGS_MASK 0x10000000 7434 #define MC_FUS_DRAM_APER_DEF__LOCK_MC_FUS_DRAM_REGS__SHIFT 0x1c 7435 #define MC_FUS_ARB_GARLIC_ISOC_PRI__DMIF_RD_TOKURG_EN_MASK 0x1 7436 #define MC_FUS_ARB_GARLIC_ISOC_PRI__DMIF_RD_TOKURG_EN__SHIFT 0x0 7437 #define MC_FUS_ARB_GARLIC_ISOC_PRI__UVD_RD_TOKURG_EN_MASK 0x2 7438 #define MC_FUS_ARB_GARLIC_ISOC_PRI__UVD_RD_TOKURG_EN__SHIFT 0x1 7439 #define MC_FUS_ARB_GARLIC_ISOC_PRI__VCE_RD_TOKURG_EN_MASK 0x4 7440 #define MC_FUS_ARB_GARLIC_ISOC_PRI__VCE_RD_TOKURG_EN__SHIFT 0x2 7441 #define MC_FUS_ARB_GARLIC_ISOC_PRI__ACP_RD_TOKURG_EN_MASK 0x8 7442 #define MC_FUS_ARB_GARLIC_ISOC_PRI__ACP_RD_TOKURG_EN__SHIFT 0x3 7443 #define MC_FUS_ARB_GARLIC_ISOC_PRI__DMIF_RD_PRIURG_EN_MASK 0x10 7444 #define MC_FUS_ARB_GARLIC_ISOC_PRI__DMIF_RD_PRIURG_EN__SHIFT 0x4 7445 #define MC_FUS_ARB_GARLIC_ISOC_PRI__UVD_RD_PRIURG_EN_MASK 0x20 7446 #define MC_FUS_ARB_GARLIC_ISOC_PRI__UVD_RD_PRIURG_EN__SHIFT 0x5 7447 #define MC_FUS_ARB_GARLIC_ISOC_PRI__VCE_RD_PRIURG_EN_MASK 0x40 7448 #define MC_FUS_ARB_GARLIC_ISOC_PRI__VCE_RD_PRIURG_EN__SHIFT 0x6 7449 #define MC_FUS_ARB_GARLIC_ISOC_PRI__ACP_RD_PRIURG_EN_MASK 0x80 7450 #define MC_FUS_ARB_GARLIC_ISOC_PRI__ACP_RD_PRIURG_EN__SHIFT 0x7 7451 #define MC_FUS_ARB_GARLIC_ISOC_PRI__DMIF_RD_ISOC_EN_MASK 0x100 7452 #define MC_FUS_ARB_GARLIC_ISOC_PRI__DMIF_RD_ISOC_EN__SHIFT 0x8 7453 #define MC_FUS_ARB_GARLIC_ISOC_PRI__UVD_RD_ISOC_EN_MASK 0x200 7454 #define MC_FUS_ARB_GARLIC_ISOC_PRI__UVD_RD_ISOC_EN__SHIFT 0x9 7455 #define MC_FUS_ARB_GARLIC_ISOC_PRI__VCE_RD_ISOC_EN_MASK 0x400 7456 #define MC_FUS_ARB_GARLIC_ISOC_PRI__VCE_RD_ISOC_EN__SHIFT 0xa 7457 #define MC_FUS_ARB_GARLIC_ISOC_PRI__MCIF_RD_ISOC_EN_MASK 0x800 7458 #define MC_FUS_ARB_GARLIC_ISOC_PRI__MCIF_RD_ISOC_EN__SHIFT 0xb 7459 #define MC_FUS_ARB_GARLIC_ISOC_PRI__UMC_RD_ISOC_EN_MASK 0x1000 7460 #define MC_FUS_ARB_GARLIC_ISOC_PRI__UMC_RD_ISOC_EN__SHIFT 0xc 7461 #define MC_FUS_ARB_GARLIC_ISOC_PRI__VCEU_RD_ISOC_EN_MASK 0x2000 7462 #define MC_FUS_ARB_GARLIC_ISOC_PRI__VCEU_RD_ISOC_EN__SHIFT 0xd 7463 #define MC_FUS_ARB_GARLIC_ISOC_PRI__ACP_RD_ISOC_EN_MASK 0x4000 7464 #define MC_FUS_ARB_GARLIC_ISOC_PRI__ACP_RD_ISOC_EN__SHIFT 0xe 7465 #define MC_FUS_ARB_GARLIC_ISOC_PRI__REQPRI_OVERRIDE_EN_MASK 0x8000 7466 #define MC_FUS_ARB_GARLIC_ISOC_PRI__REQPRI_OVERRIDE_EN__SHIFT 0xf 7467 #define MC_FUS_ARB_GARLIC_ISOC_PRI__REQPRI_OVERRIDE_VAL_MASK 0x30000 7468 #define MC_FUS_ARB_GARLIC_ISOC_PRI__REQPRI_OVERRIDE_VAL__SHIFT 0x10 7469 #define MC_FUS_ARB_GARLIC_ISOC_PRI__PRIPRMTE_OVERRIDE_EN_MASK 0x40000 7470 #define MC_FUS_ARB_GARLIC_ISOC_PRI__PRIPRMTE_OVERRIDE_EN__SHIFT 0x12 7471 #define MC_FUS_ARB_GARLIC_ISOC_PRI__TOKURG_OVERRIDE_EN_MASK 0x80000 7472 #define MC_FUS_ARB_GARLIC_ISOC_PRI__TOKURG_OVERRIDE_EN__SHIFT 0x13 7473 #define MC_FUS_ARB_GARLIC_ISOC_PRI__PRIURG_OVERRIDE_EN_MASK 0x100000 7474 #define MC_FUS_ARB_GARLIC_ISOC_PRI__PRIURG_OVERRIDE_EN__SHIFT 0x14 7475 #define MC_FUS_ARB_GARLIC_ISOC_PRI__PRIPRMTE_OVERRIDE_VAL_MASK 0x200000 7476 #define MC_FUS_ARB_GARLIC_ISOC_PRI__PRIPRMTE_OVERRIDE_VAL__SHIFT 0x15 7477 #define MC_FUS_ARB_GARLIC_ISOC_PRI__TOKURG_OVERRIDE_VAL_MASK 0x400000 7478 #define MC_FUS_ARB_GARLIC_ISOC_PRI__TOKURG_OVERRIDE_VAL__SHIFT 0x16 7479 #define MC_FUS_ARB_GARLIC_ISOC_PRI__PRIURG_OVERRIDE_VAL_MASK 0x800000 7480 #define MC_FUS_ARB_GARLIC_ISOC_PRI__PRIURG_OVERRIDE_VAL__SHIFT 0x17 7481 #define MC_FUS_ARB_GARLIC_ISOC_PRI__GARLIC_REQ_CREDITS_MASK 0x1f000000 7482 #define MC_FUS_ARB_GARLIC_ISOC_PRI__GARLIC_REQ_CREDITS__SHIFT 0x18 7483 #define MC_FUS_ARB_GARLIC_ISOC_PRI__MM_REL_LATE_MASK 0x20000000 7484 #define MC_FUS_ARB_GARLIC_ISOC_PRI__MM_REL_LATE__SHIFT 0x1d 7485 #define MC_FUS_ARB_GARLIC_CNTL__RX_RDRESP_FIFO_PTR_INIT_VALUE_MASK 0xff 7486 #define MC_FUS_ARB_GARLIC_CNTL__RX_RDRESP_FIFO_PTR_INIT_VALUE__SHIFT 0x0 7487 #define MC_FUS_ARB_GARLIC_CNTL__RX_WRRESP_FIFO_PTR_INIT_VALUE_MASK 0x7f00 7488 #define MC_FUS_ARB_GARLIC_CNTL__RX_WRRESP_FIFO_PTR_INIT_VALUE__SHIFT 0x8 7489 #define MC_FUS_ARB_GARLIC_CNTL__EN_64_BYTE_WRITE_MASK 0x8000 7490 #define MC_FUS_ARB_GARLIC_CNTL__EN_64_BYTE_WRITE__SHIFT 0xf 7491 #define MC_FUS_ARB_GARLIC_CNTL__EDC_RESPONSE_ENABLE_MASK 0x10000 7492 #define MC_FUS_ARB_GARLIC_CNTL__EDC_RESPONSE_ENABLE__SHIFT 0x10 7493 #define MC_FUS_ARB_GARLIC_CNTL__OUTSTANDING_RDRESP_LIMIT_MASK 0x3fe0000 7494 #define MC_FUS_ARB_GARLIC_CNTL__OUTSTANDING_RDRESP_LIMIT__SHIFT 0x11 7495 #define MC_FUS_ARB_GARLIC_CNTL__OUTSTANDING_WRRESP_LIMIT_MASK 0xfc000000 7496 #define MC_FUS_ARB_GARLIC_CNTL__OUTSTANDING_WRRESP_LIMIT__SHIFT 0x1a 7497 #define MC_FUS_ARB_GARLIC_WR_PRI__CB_WR_PRI_MASK 0x3 7498 #define MC_FUS_ARB_GARLIC_WR_PRI__CB_WR_PRI__SHIFT 0x0 7499 #define MC_FUS_ARB_GARLIC_WR_PRI__DB_WR_PRI_MASK 0xc 7500 #define MC_FUS_ARB_GARLIC_WR_PRI__DB_WR_PRI__SHIFT 0x2 7501 #define MC_FUS_ARB_GARLIC_WR_PRI__TC_WR_PRI_MASK 0x30 7502 #define MC_FUS_ARB_GARLIC_WR_PRI__TC_WR_PRI__SHIFT 0x4 7503 #define MC_FUS_ARB_GARLIC_WR_PRI__CP_WR_PRI_MASK 0xc0 7504 #define MC_FUS_ARB_GARLIC_WR_PRI__CP_WR_PRI__SHIFT 0x6 7505 #define MC_FUS_ARB_GARLIC_WR_PRI__HDP_WR_PRI_MASK 0x300 7506 #define MC_FUS_ARB_GARLIC_WR_PRI__HDP_WR_PRI__SHIFT 0x8 7507 #define MC_FUS_ARB_GARLIC_WR_PRI__XDP_WR_PRI_MASK 0xc00 7508 #define MC_FUS_ARB_GARLIC_WR_PRI__XDP_WR_PRI__SHIFT 0xa 7509 #define MC_FUS_ARB_GARLIC_WR_PRI__UMC_WR_PRI_MASK 0x3000 7510 #define MC_FUS_ARB_GARLIC_WR_PRI__UMC_WR_PRI__SHIFT 0xc 7511 #define MC_FUS_ARB_GARLIC_WR_PRI__UVD_WR_PRI_MASK 0xc000 7512 #define MC_FUS_ARB_GARLIC_WR_PRI__UVD_WR_PRI__SHIFT 0xe 7513 #define MC_FUS_ARB_GARLIC_WR_PRI__RLC_WR_PRI_MASK 0x30000 7514 #define MC_FUS_ARB_GARLIC_WR_PRI__RLC_WR_PRI__SHIFT 0x10 7515 #define MC_FUS_ARB_GARLIC_WR_PRI__IH_WR_PRI_MASK 0xc0000 7516 #define MC_FUS_ARB_GARLIC_WR_PRI__IH_WR_PRI__SHIFT 0x12 7517 #define MC_FUS_ARB_GARLIC_WR_PRI__SDMA_WR_PRI_MASK 0x300000 7518 #define MC_FUS_ARB_GARLIC_WR_PRI__SDMA_WR_PRI__SHIFT 0x14 7519 #define MC_FUS_ARB_GARLIC_WR_PRI__SEM_WR_PRI_MASK 0xc00000 7520 #define MC_FUS_ARB_GARLIC_WR_PRI__SEM_WR_PRI__SHIFT 0x16 7521 #define MC_FUS_ARB_GARLIC_WR_PRI__SH_WR_PRI_MASK 0x3000000 7522 #define MC_FUS_ARB_GARLIC_WR_PRI__SH_WR_PRI__SHIFT 0x18 7523 #define MC_FUS_ARB_GARLIC_WR_PRI__MCIF_WR_PRI_MASK 0xc000000 7524 #define MC_FUS_ARB_GARLIC_WR_PRI__MCIF_WR_PRI__SHIFT 0x1a 7525 #define MC_FUS_ARB_GARLIC_WR_PRI__VCE_WR_PRI_MASK 0x30000000 7526 #define MC_FUS_ARB_GARLIC_WR_PRI__VCE_WR_PRI__SHIFT 0x1c 7527 #define MC_FUS_ARB_GARLIC_WR_PRI__VCEU_WR_PRI_MASK 0xc0000000 7528 #define MC_FUS_ARB_GARLIC_WR_PRI__VCEU_WR_PRI__SHIFT 0x1e 7529 #define MC_FUS_ARB_GARLIC_WR_PRI2__SMU_WR_PRI_MASK 0x3 7530 #define MC_FUS_ARB_GARLIC_WR_PRI2__SMU_WR_PRI__SHIFT 0x0 7531 #define MC_FUS_ARB_GARLIC_WR_PRI2__SAM_WR_PRI_MASK 0xc 7532 #define MC_FUS_ARB_GARLIC_WR_PRI2__SAM_WR_PRI__SHIFT 0x2 7533 #define MC_FUS_ARB_GARLIC_WR_PRI2__ACP_WR_PRI_MASK 0x30 7534 #define MC_FUS_ARB_GARLIC_WR_PRI2__ACP_WR_PRI__SHIFT 0x4 7535 #define MC_CG_DATAPORT__DATA_FIELD_MASK 0xffffffff 7536 #define MC_CG_DATAPORT__DATA_FIELD__SHIFT 0x0 7537 #define MC_GRUB_PROBE_MAP__ADDR0_TO_TC_MAP_MASK 0x3 7538 #define MC_GRUB_PROBE_MAP__ADDR0_TO_TC_MAP__SHIFT 0x0 7539 #define MC_GRUB_PROBE_MAP__ADDR1_TO_TC_MAP_MASK 0xc 7540 #define MC_GRUB_PROBE_MAP__ADDR1_TO_TC_MAP__SHIFT 0x2 7541 #define MC_GRUB_PROBE_MAP__ADDR2_TO_TC_MAP_MASK 0x30 7542 #define MC_GRUB_PROBE_MAP__ADDR2_TO_TC_MAP__SHIFT 0x4 7543 #define MC_GRUB_PROBE_MAP__ADDR3_TO_TC_MAP_MASK 0xc0 7544 #define MC_GRUB_PROBE_MAP__ADDR3_TO_TC_MAP__SHIFT 0x6 7545 #define MC_GRUB_PROBE_MAP__ADDR0_TO_GRUB_MAP_MASK 0x100 7546 #define MC_GRUB_PROBE_MAP__ADDR0_TO_GRUB_MAP__SHIFT 0x8 7547 #define MC_GRUB_PROBE_MAP__ADDR1_TO_GRUB_MAP_MASK 0x200 7548 #define MC_GRUB_PROBE_MAP__ADDR1_TO_GRUB_MAP__SHIFT 0x9 7549 #define MC_GRUB_PROBE_MAP__ADDR2_TO_GRUB_MAP_MASK 0x400 7550 #define MC_GRUB_PROBE_MAP__ADDR2_TO_GRUB_MAP__SHIFT 0xa 7551 #define MC_GRUB_PROBE_MAP__ADDR3_TO_GRUB_MAP_MASK 0x800 7552 #define MC_GRUB_PROBE_MAP__ADDR3_TO_GRUB_MAP__SHIFT 0xb 7553 #define MC_GRUB_POST_PROBE_DELAY__REQ_TO_RSP_DELAY_MASK 0x1f 7554 #define MC_GRUB_POST_PROBE_DELAY__REQ_TO_RSP_DELAY__SHIFT 0x0 7555 #define MC_GRUB_POST_PROBE_DELAY__REQLCL_TO_RET_DELAY_MASK 0x1f00 7556 #define MC_GRUB_POST_PROBE_DELAY__REQLCL_TO_RET_DELAY__SHIFT 0x8 7557 #define MC_GRUB_POST_PROBE_DELAY__REQREM_TO_RET_DELAY_MASK 0x1f0000 7558 #define MC_GRUB_POST_PROBE_DELAY__REQREM_TO_RET_DELAY__SHIFT 0x10 7559 #define MC_GRUB_PROBE_CREDITS__CREDITS_LIMIT_LO_MASK 0x3f 7560 #define MC_GRUB_PROBE_CREDITS__CREDITS_LIMIT_LO__SHIFT 0x0 7561 #define MC_GRUB_PROBE_CREDITS__CREDITS_LIMIT_HI_MASK 0x3f00 7562 #define MC_GRUB_PROBE_CREDITS__CREDITS_LIMIT_HI__SHIFT 0x8 7563 #define MC_GRUB_PROBE_CREDITS__INTPRB_FIFO_LEVEL_MASK 0x8000 7564 #define MC_GRUB_PROBE_CREDITS__INTPRB_FIFO_LEVEL__SHIFT 0xf 7565 #define MC_GRUB_PROBE_CREDITS__INTPRB_TIMEOUT_THRESH_MASK 0x70000 7566 #define MC_GRUB_PROBE_CREDITS__INTPRB_TIMEOUT_THRESH__SHIFT 0x10 7567 #define MC_GRUB_PROBE_CREDITS__MEM_TIMEOUT_THRESH_MASK 0x700000 7568 #define MC_GRUB_PROBE_CREDITS__MEM_TIMEOUT_THRESH__SHIFT 0x14 7569 #define MC_GRUB_FEATURES__WR_COMBINE_OFF_MASK 0x1 7570 #define MC_GRUB_FEATURES__WR_COMBINE_OFF__SHIFT 0x0 7571 #define MC_GRUB_FEATURES__SCLK_CG_DISABLE_MASK 0x2 7572 #define MC_GRUB_FEATURES__SCLK_CG_DISABLE__SHIFT 0x1 7573 #define MC_GRUB_FEATURES__PRB_FILTER_DISABLE_MASK 0x4 7574 #define MC_GRUB_FEATURES__PRB_FILTER_DISABLE__SHIFT 0x2 7575 #define MC_GRUB_FEATURES__ARB_NRT_STACK_DISABLE_MASK 0x8 7576 #define MC_GRUB_FEATURES__ARB_NRT_STACK_DISABLE__SHIFT 0x3 7577 #define MC_GRUB_FEATURES__ARB_FIXED_PRIORITY_MASK 0x10 7578 #define MC_GRUB_FEATURES__ARB_FIXED_PRIORITY__SHIFT 0x4 7579 #define MC_GRUB_FEATURES__PRIORITY_UPDATE_DISABLE_MASK 0x20 7580 #define MC_GRUB_FEATURES__PRIORITY_UPDATE_DISABLE__SHIFT 0x5 7581 #define MC_GRUB_FEATURES__RT_BYPASS_OFF_MASK 0x40 7582 #define MC_GRUB_FEATURES__RT_BYPASS_OFF__SHIFT 0x6 7583 #define MC_GRUB_FEATURES__SYNC_ON_ERROR_DISABLE_MASK 0x80 7584 #define MC_GRUB_FEATURES__SYNC_ON_ERROR_DISABLE__SHIFT 0x7 7585 #define MC_GRUB_FEATURES__SYNC_REFLECT_DISABLE_MASK 0x100 7586 #define MC_GRUB_FEATURES__SYNC_REFLECT_DISABLE__SHIFT 0x8 7587 #define MC_GRUB_FEATURES__ARB_STALL_EN_MASK 0x400 7588 #define MC_GRUB_FEATURES__ARB_STALL_EN__SHIFT 0xa 7589 #define MC_GRUB_FEATURES__CREDIT_STALL_EN_MASK 0x800 7590 #define MC_GRUB_FEATURES__CREDIT_STALL_EN__SHIFT 0xb 7591 #define MC_GRUB_FEATURES__ARB_STALL_SET_SEL_MASK 0x3000 7592 #define MC_GRUB_FEATURES__ARB_STALL_SET_SEL__SHIFT 0xc 7593 #define MC_GRUB_FEATURES__ARB_STALL_CLR_SEL_MASK 0xc000 7594 #define MC_GRUB_FEATURES__ARB_STALL_CLR_SEL__SHIFT 0xe 7595 #define MC_GRUB_FEATURES__CREDIT_STALL_SET_SEL_MASK 0x30000 7596 #define MC_GRUB_FEATURES__CREDIT_STALL_SET_SEL__SHIFT 0x10 7597 #define MC_GRUB_FEATURES__CREDIT_STALL_CLR_SEL_MASK 0xc0000 7598 #define MC_GRUB_FEATURES__CREDIT_STALL_CLR_SEL__SHIFT 0x12 7599 #define MC_GRUB_FEATURES__WR_REORDER_OFF_MASK 0x100000 7600 #define MC_GRUB_FEATURES__WR_REORDER_OFF__SHIFT 0x14 7601 #define MC_GRUB_TX_CREDITS__SRCTAG_LIMIT_MASK 0x3f 7602 #define MC_GRUB_TX_CREDITS__SRCTAG_LIMIT__SHIFT 0x0 7603 #define MC_GRUB_TX_CREDITS__SRCTAG_RT_RESERVE_MASK 0xf00 7604 #define MC_GRUB_TX_CREDITS__SRCTAG_RT_RESERVE__SHIFT 0x8 7605 #define MC_GRUB_TX_CREDITS__NPC_RT_RESERVE_MASK 0xf000 7606 #define MC_GRUB_TX_CREDITS__NPC_RT_RESERVE__SHIFT 0xc 7607 #define MC_GRUB_TX_CREDITS__NPD_RT_RESERVE_MASK 0xf0000 7608 #define MC_GRUB_TX_CREDITS__NPD_RT_RESERVE__SHIFT 0x10 7609 #define MC_GRUB_TX_CREDITS__TX_FIFO_DEPTH_MASK 0x1f00000 7610 #define MC_GRUB_TX_CREDITS__TX_FIFO_DEPTH__SHIFT 0x14 7611 #define MC_GRUB_TCB_INDEX__INDEX_MASK 0x7f 7612 #define MC_GRUB_TCB_INDEX__INDEX__SHIFT 0x0 7613 #define MC_GRUB_TCB_INDEX__TCB0_WR_EN_MASK 0x100 7614 #define MC_GRUB_TCB_INDEX__TCB0_WR_EN__SHIFT 0x8 7615 #define MC_GRUB_TCB_INDEX__TCB1_WR_EN_MASK 0x200 7616 #define MC_GRUB_TCB_INDEX__TCB1_WR_EN__SHIFT 0x9 7617 #define MC_GRUB_TCB_INDEX__RD_EN_MASK 0x400 7618 #define MC_GRUB_TCB_INDEX__RD_EN__SHIFT 0xa 7619 #define MC_GRUB_TCB_INDEX__TCB_SEL_MASK 0x800 7620 #define MC_GRUB_TCB_INDEX__TCB_SEL__SHIFT 0xb 7621 #define MC_GRUB_TCB_DATA_LO__DATA_MASK 0xffffffff 7622 #define MC_GRUB_TCB_DATA_LO__DATA__SHIFT 0x0 7623 #define MC_GRUB_TCB_DATA_HI__DATA_MASK 0xffffffff 7624 #define MC_GRUB_TCB_DATA_HI__DATA__SHIFT 0x0 7625 #define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE_MASK 0x1 7626 #define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE__SHIFT 0x0 7627 #define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_DUALSIZE_REQ_MASK 0x2 7628 #define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_DUALSIZE_REQ__SHIFT 0x1 7629 #define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN_MASK 0x10 7630 #define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN__SHIFT 0x4 7631 #define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK_MASK 0x20 7632 #define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK__SHIFT 0x5 7633 #define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN_MASK 0x40 7634 #define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN__SHIFT 0x6 7635 #define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK_MASK 0xf00 7636 #define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK__SHIFT 0x8 7637 #define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_P_VMID_MASK 0xf0000 7638 #define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_P_VMID__SHIFT 0x10 7639 #define MCIF_WB_BUFMGR_CUR_LINE_R__MCIF_WB_BUFMGR_CUR_LINE_R_MASK 0x1fff 7640 #define MCIF_WB_BUFMGR_CUR_LINE_R__MCIF_WB_BUFMGR_CUR_LINE_R__SHIFT 0x0 7641 #define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_VCE_INT_STATUS_MASK 0x1 7642 #define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_VCE_INT_STATUS__SHIFT 0x0 7643 #define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS_MASK 0x2 7644 #define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS__SHIFT 0x1 7645 #define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF_MASK 0x70 7646 #define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF__SHIFT 0x4 7647 #define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS_MASK 0x80 7648 #define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS__SHIFT 0x7 7649 #define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG_MASK 0xf00 7650 #define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG__SHIFT 0x8 7651 #define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L_MASK 0x1fff000 7652 #define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L__SHIFT 0xc 7653 #define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF_MASK 0x70000000 7654 #define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF__SHIFT 0x1c 7655 #define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH_MASK 0xff00 7656 #define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH__SHIFT 0x8 7657 #define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH_MASK 0xff000000 7658 #define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH__SHIFT 0x18 7659 #define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE_MASK 0x1 7660 #define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE__SHIFT 0x0 7661 #define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED_MASK 0x2 7662 #define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED__SHIFT 0x1 7663 #define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED_MASK 0x4 7664 #define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED__SHIFT 0x2 7665 #define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW_MASK 0x8 7666 #define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW__SHIFT 0x3 7667 #define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE_MASK 0x10 7668 #define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE__SHIFT 0x4 7669 #define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE_MASK 0xe0 7670 #define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE__SHIFT 0x5 7671 #define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG_MASK 0xf00 7672 #define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG__SHIFT 0x8 7673 #define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF_MASK 0x7000 7674 #define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF__SHIFT 0xc 7675 #define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FIELD_MASK 0x8000 7676 #define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FIELD__SHIFT 0xf 7677 #define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L_MASK 0x1fff0000 7678 #define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L__SHIFT 0x10 7679 #define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_LONG_LINE_ERROR_MASK 0x20000000 7680 #define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_LONG_LINE_ERROR__SHIFT 0x1d 7681 #define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SHORT_LINE_ERROR_MASK 0x40000000 7682 #define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SHORT_LINE_ERROR__SHIFT 0x1e 7683 #define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FRAME_LENGTH_ERROR_MASK 0x80000000 7684 #define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FRAME_LENGTH_ERROR__SHIFT 0x1f 7685 #define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_CUR_LINE_R_MASK 0x1fff 7686 #define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_CUR_LINE_R__SHIFT 0x0 7687 #define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT_MASK 0x2000 7688 #define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT__SHIFT 0xd 7689 #define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH_MASK 0x4000 7690 #define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH__SHIFT 0xe 7691 #define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE_MASK 0x1 7692 #define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE__SHIFT 0x0 7693 #define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED_MASK 0x2 7694 #define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED__SHIFT 0x1 7695 #define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED_MASK 0x4 7696 #define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED__SHIFT 0x2 7697 #define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW_MASK 0x8 7698 #define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW__SHIFT 0x3 7699 #define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE_MASK 0x10 7700 #define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE__SHIFT 0x4 7701 #define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE_MASK 0xe0 7702 #define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE__SHIFT 0x5 7703 #define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG_MASK 0xf00 7704 #define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG__SHIFT 0x8 7705 #define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF_MASK 0x7000 7706 #define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF__SHIFT 0xc 7707 #define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FIELD_MASK 0x8000 7708 #define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FIELD__SHIFT 0xf 7709 #define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L_MASK 0x1fff0000 7710 #define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L__SHIFT 0x10 7711 #define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_LONG_LINE_ERROR_MASK 0x20000000 7712 #define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_LONG_LINE_ERROR__SHIFT 0x1d 7713 #define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SHORT_LINE_ERROR_MASK 0x40000000 7714 #define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SHORT_LINE_ERROR__SHIFT 0x1e 7715 #define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FRAME_LENGTH_ERROR_MASK 0x80000000 7716 #define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FRAME_LENGTH_ERROR__SHIFT 0x1f 7717 #define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_CUR_LINE_R_MASK 0x1fff 7718 #define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_CUR_LINE_R__SHIFT 0x0 7719 #define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT_MASK 0x2000 7720 #define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT__SHIFT 0xd 7721 #define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH_MASK 0x4000 7722 #define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH__SHIFT 0xe 7723 #define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE_MASK 0x1 7724 #define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE__SHIFT 0x0 7725 #define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED_MASK 0x2 7726 #define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED__SHIFT 0x1 7727 #define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED_MASK 0x4 7728 #define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED__SHIFT 0x2 7729 #define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW_MASK 0x8 7730 #define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW__SHIFT 0x3 7731 #define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE_MASK 0x10 7732 #define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE__SHIFT 0x4 7733 #define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE_MASK 0xe0 7734 #define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE__SHIFT 0x5 7735 #define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG_MASK 0xf00 7736 #define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG__SHIFT 0x8 7737 #define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF_MASK 0x7000 7738 #define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF__SHIFT 0xc 7739 #define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FIELD_MASK 0x8000 7740 #define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FIELD__SHIFT 0xf 7741 #define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L_MASK 0x1fff0000 7742 #define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L__SHIFT 0x10 7743 #define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_LONG_LINE_ERROR_MASK 0x20000000 7744 #define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_LONG_LINE_ERROR__SHIFT 0x1d 7745 #define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SHORT_LINE_ERROR_MASK 0x40000000 7746 #define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SHORT_LINE_ERROR__SHIFT 0x1e 7747 #define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FRAME_LENGTH_ERROR_MASK 0x80000000 7748 #define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FRAME_LENGTH_ERROR__SHIFT 0x1f 7749 #define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_CUR_LINE_R_MASK 0x1fff 7750 #define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_CUR_LINE_R__SHIFT 0x0 7751 #define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT_MASK 0x2000 7752 #define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT__SHIFT 0xd 7753 #define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH_MASK 0x4000 7754 #define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH__SHIFT 0xe 7755 #define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE_MASK 0x1 7756 #define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE__SHIFT 0x0 7757 #define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED_MASK 0x2 7758 #define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED__SHIFT 0x1 7759 #define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED_MASK 0x4 7760 #define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED__SHIFT 0x2 7761 #define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW_MASK 0x8 7762 #define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW__SHIFT 0x3 7763 #define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE_MASK 0x10 7764 #define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE__SHIFT 0x4 7765 #define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE_MASK 0xe0 7766 #define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE__SHIFT 0x5 7767 #define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG_MASK 0xf00 7768 #define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG__SHIFT 0x8 7769 #define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF_MASK 0x7000 7770 #define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF__SHIFT 0xc 7771 #define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FIELD_MASK 0x8000 7772 #define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FIELD__SHIFT 0xf 7773 #define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L_MASK 0x1fff0000 7774 #define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L__SHIFT 0x10 7775 #define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_LONG_LINE_ERROR_MASK 0x20000000 7776 #define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_LONG_LINE_ERROR__SHIFT 0x1d 7777 #define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SHORT_LINE_ERROR_MASK 0x40000000 7778 #define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SHORT_LINE_ERROR__SHIFT 0x1e 7779 #define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FRAME_LENGTH_ERROR_MASK 0x80000000 7780 #define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FRAME_LENGTH_ERROR__SHIFT 0x1f 7781 #define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_CUR_LINE_R_MASK 0x1fff 7782 #define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_CUR_LINE_R__SHIFT 0x0 7783 #define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT_MASK 0x2000 7784 #define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT__SHIFT 0xd 7785 #define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH_MASK 0x4000 7786 #define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH__SHIFT 0xe 7787 #define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE_MASK 0x3 7788 #define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE__SHIFT 0x0 7789 #define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL_MASK 0xfc000000 7790 #define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL__SHIFT 0x1a 7791 #define MCIF_WB_URGENCY_WATERMARK__MCIF_WB_CLIENT0_URGENCY_WATERMARK_MASK 0xffff 7792 #define MCIF_WB_URGENCY_WATERMARK__MCIF_WB_CLIENT0_URGENCY_WATERMARK__SHIFT 0x0 7793 #define MCIF_WB_URGENCY_WATERMARK__MCIF_WB_CLIENT1_URGENCY_WATERMARK_MASK 0xffff0000 7794 #define MCIF_WB_URGENCY_WATERMARK__MCIF_WB_CLIENT1_URGENCY_WATERMARK__SHIFT 0x10 7795 #define MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_INDEX_MASK 0xff 7796 #define MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_INDEX__SHIFT 0x0 7797 #define MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_WRITE_EN_MASK 0x100 7798 #define MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_WRITE_EN__SHIFT 0x8 7799 #define MCIF_WB_TEST_DEBUG_DATA__MCIF_WB_TEST_DEBUG_DATA_MASK 0xffffffff 7800 #define MCIF_WB_TEST_DEBUG_DATA__MCIF_WB_TEST_DEBUG_DATA__SHIFT 0x0 7801 #define MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y_MASK 0xffffffff 7802 #define MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y__SHIFT 0x0 7803 #define MCIF_WB_BUF_1_ADDR_Y_OFFSET__MCIF_WB_BUF_1_ADDR_Y_OFFSET_MASK 0x3ffff 7804 #define MCIF_WB_BUF_1_ADDR_Y_OFFSET__MCIF_WB_BUF_1_ADDR_Y_OFFSET__SHIFT 0x0 7805 #define MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C_MASK 0xffffffff 7806 #define MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C__SHIFT 0x0 7807 #define MCIF_WB_BUF_1_ADDR_C_OFFSET__MCIF_WB_BUF_1_ADDR_C_OFFSET_MASK 0x3ffff 7808 #define MCIF_WB_BUF_1_ADDR_C_OFFSET__MCIF_WB_BUF_1_ADDR_C_OFFSET__SHIFT 0x0 7809 #define MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y_MASK 0xffffffff 7810 #define MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y__SHIFT 0x0 7811 #define MCIF_WB_BUF_2_ADDR_Y_OFFSET__MCIF_WB_BUF_2_ADDR_Y_OFFSET_MASK 0x3ffff 7812 #define MCIF_WB_BUF_2_ADDR_Y_OFFSET__MCIF_WB_BUF_2_ADDR_Y_OFFSET__SHIFT 0x0 7813 #define MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C_MASK 0xffffffff 7814 #define MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C__SHIFT 0x0 7815 #define MCIF_WB_BUF_2_ADDR_C_OFFSET__MCIF_WB_BUF_2_ADDR_C_OFFSET_MASK 0x3ffff 7816 #define MCIF_WB_BUF_2_ADDR_C_OFFSET__MCIF_WB_BUF_2_ADDR_C_OFFSET__SHIFT 0x0 7817 #define MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y_MASK 0xffffffff 7818 #define MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y__SHIFT 0x0 7819 #define MCIF_WB_BUF_3_ADDR_Y_OFFSET__MCIF_WB_BUF_3_ADDR_Y_OFFSET_MASK 0x3ffff 7820 #define MCIF_WB_BUF_3_ADDR_Y_OFFSET__MCIF_WB_BUF_3_ADDR_Y_OFFSET__SHIFT 0x0 7821 #define MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C_MASK 0xffffffff 7822 #define MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C__SHIFT 0x0 7823 #define MCIF_WB_BUF_3_ADDR_C_OFFSET__MCIF_WB_BUF_3_ADDR_C_OFFSET_MASK 0x3ffff 7824 #define MCIF_WB_BUF_3_ADDR_C_OFFSET__MCIF_WB_BUF_3_ADDR_C_OFFSET__SHIFT 0x0 7825 #define MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y_MASK 0xffffffff 7826 #define MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y__SHIFT 0x0 7827 #define MCIF_WB_BUF_4_ADDR_Y_OFFSET__MCIF_WB_BUF_4_ADDR_Y_OFFSET_MASK 0x3ffff 7828 #define MCIF_WB_BUF_4_ADDR_Y_OFFSET__MCIF_WB_BUF_4_ADDR_Y_OFFSET__SHIFT 0x0 7829 #define MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C_MASK 0xffffffff 7830 #define MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C__SHIFT 0x0 7831 #define MCIF_WB_BUF_4_ADDR_C_OFFSET__MCIF_WB_BUF_4_ADDR_C_OFFSET_MASK 0x3ffff 7832 #define MCIF_WB_BUF_4_ADDR_C_OFFSET__MCIF_WB_BUF_4_ADDR_C_OFFSET__SHIFT 0x0 7833 #define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE_MASK 0x1 7834 #define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE__SHIFT 0x0 7835 #define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_EN_MASK 0x10 7836 #define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_EN__SHIFT 0x4 7837 #define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_ACK_MASK 0x20 7838 #define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_ACK__SHIFT 0x5 7839 #define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_SLICE_INT_EN_MASK 0x40 7840 #define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_SLICE_INT_EN__SHIFT 0x6 7841 #define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_MASK 0xf00 7842 #define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK__SHIFT 0x8 7843 #define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE_MASK 0x1fff0000 7844 #define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE__SHIFT 0x10 7845 #define MCIF_WB_HVVMID_CONTROL__MCIF_WB_DEFAULT_VMID_MASK 0xf00 7846 #define MCIF_WB_HVVMID_CONTROL__MCIF_WB_DEFAULT_VMID__SHIFT 0x8 7847 #define MCIF_WB_HVVMID_CONTROL__MCIF_WB_ALLOWED_VMID_MASK_MASK 0xffff0000 7848 #define MCIF_WB_HVVMID_CONTROL__MCIF_WB_ALLOWED_VMID_MASK__SHIFT 0x10 7849 7850 #endif /* GMC_8_2_SH_MASK_H */ 7851